Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of reducing noise. According to one embodiment, a semiconductor device includes a first switching element provided with a first electrode and a second electrode, a second switching element provided with a third electrode and a fourth electrode, a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first capacitor including a first dielectric layer; a third wiring layer connected to the first wiring layer and to which a first voltage is applied; a fourth wiring layer connected to the second wiring layer and to which a second voltage is applied; and a fifth wiring layer connected to the second and fourth electrodes and to which a third voltage is applied. The first capacitor is disposed between the first and second switching elements. The third electrode is disposed facing the first electrode. The fourth electrode is disposed facing the second electrode and is connected in series with the second electrode.

Description

[0001] Reference to relevant applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-082673 (filed on May 21, 2024). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] A semiconductor device for power conversion and control is known. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device capable of reducing noise.

[0006] In a semiconductor device according to an embodiment, the device includes: a first switching element having a first electrode and a second electrode disposed on its front side; a second switching element having a third electrode and a fourth electrode disposed on its front side; a first capacitor including a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer disposed between the first wiring layer and the second wiring layer; a substrate having the first switching element, the second switching element, and the first capacitor internally mounted thereon; a third wiring layer connected to the first wiring layer and subjected to a first voltage; a fourth wiring layer connected to the second wiring layer and subjected to a second voltage higher than the first voltage; and a fifth wiring layer connected to the second electrode and the fourth electrode and subjected to a third voltage in a range between the first voltage and the second voltage. The first capacitor is disposed between the first switching element and the second switching element. The third electrode is disposed opposite to the first electrode in a first direction. The fourth electrode is disposed opposite to the second electrode in a first direction and is connected in series with the second electrode. Attached Figure Description

[0007] Figure 1 This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a circuit diagram illustrating an application example of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a circuit diagram illustrating an example of the structure of each switching element in the semiconductor device of the first embodiment.

[0010] Figure 4 This is a perspective view showing an example of the structure of the semiconductor device according to the first embodiment.

[0011] Figure 5This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device according to the first embodiment.

[0012] Figure 6 This is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the first embodiment.

[0013] Figure 7 This is an example of a planar structure of a semiconductor device according to the first embodiment. Figure 5 and Figure 6 A top view showing the position of line aa.

[0014] Figure 8 This is an example of a planar structure of a semiconductor device according to the first embodiment. Figure 5 and Figure 6 The top view showing the position of the bb line.

[0015] Figure 9 This is an example of a planar structure of a semiconductor device according to the first embodiment. Figure 5 and Figure 6 The top view showing the position of the cc line.

[0016] Figure 10 This is an example of a planar structure of a semiconductor device according to the first embodiment. Figure 5 and Figure 6 A top view showing the position of the dd line.

[0017] Figure 11 This is a diagram showing the high-frequency current path of the semiconductor device according to the first embodiment.

[0018] Figure 12 This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to the second embodiment.

[0019] Figure 13 This is a circuit diagram illustrating an example of the structure of each switching element in the semiconductor device of the second embodiment.

[0020] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device according to the second embodiment.

[0021] Figure 15 This is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the second embodiment.

[0022] Figure 16 This is an example of a planar structure of a semiconductor device according to the second embodiment. Figure 14 and 15 A top view showing the position of line aa.

[0023] Figure 17 This is an example of a planar structure of a semiconductor device according to the second embodiment. Figure 14 and 15 The top view showing the position of the bb line.

[0024] Figure 18 This is an example of a planar structure of a semiconductor device according to the second embodiment. Figure 14 and 15 A top view showing the position of the cc line.

[0025] Figure 19 This is an example of a planar structure of a semiconductor device according to the second embodiment. Figure 14 and 15 A top view showing the position of the dd line.

[0026] Figure 20 This is a diagram showing the high-frequency current path and the magnetic flux generated by the high-frequency current in the semiconductor device of the second embodiment.

[0027] Figure 21 This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to the third embodiment.

[0028] Figure 22 This is a circuit diagram illustrating an example of the structure of each switching element in the semiconductor device according to the third embodiment.

[0029] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device according to the third embodiment.

[0030] Figure 24 This is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the third embodiment.

[0031] Figure 25 This is a diagram showing the high-frequency current path of the semiconductor device in the third embodiment.

[0032] Figure 26 This is a circuit diagram illustrating an example of the circuit structure of the semiconductor device according to the fourth embodiment.

[0033] Figure 27 This is a circuit diagram illustrating an example of the structure of each switching element in the semiconductor device according to the fourth embodiment.

[0034] Figure 28 This is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device according to the fourth embodiment.

[0035] Figure 29 This is a cross-sectional view showing another example of the cross-sectional structure of the semiconductor device according to the fourth embodiment.

[0036] Figure 30 This is a diagram showing the high-frequency current path and the magnetic flux generated by the high-frequency current in the semiconductor device of the fourth embodiment. Detailed Implementation

[0037] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings may not be identical to the actual dimensions and scale. Furthermore, in the following description, constituent elements having substantially the same function and structure are given the same reference numerals, and sometimes repeated descriptions are omitted. When elements having the same structure are specifically distinguished from each other, sometimes different words or numbers are appended to the end of the same reference numeral. Moreover, unless explicitly or obviously excluded, the entire description of one embodiment also applies to the description of other embodiments.

[0038] 1. First Embodiment

[0039] The semiconductor device of the first embodiment will be described below. Hereinafter, an example will be given of a semiconductor device that performs power conversion and control by alternately driving two switching elements. The semiconductor device of this embodiment is applicable, for example, to AC-DC converters, DC-AC converters, and DC-DC converters.

[0040] 1.1 Circuit Structure of Semiconductor Devices

[0041] use Figure 1 Explain the circuit structure of a semiconductor device. Figure 1 This is a circuit diagram illustrating an example of the circuit structure of a semiconductor device.

[0042] Semiconductor device 1 is, for example, a power module. Semiconductor device 1 includes control terminals T1 and T2, drive circuits 11 and 12, input / output terminals T3, T4 and T5, switching elements 13 and 14, and capacitor 15.

[0043] Control terminal T1 is the terminal where the control signal IH1 is input from the outside. The control signal IH1 is a signal used to control the operation of the drive circuit 11. The control signal IH1 is, for example, a high ("H") level signal or a low ("L") level signal.

[0044] Control terminal T2 is the terminal where the control signal IL1 is input from the outside. The control signal IL1 is a signal used to control the operation of the drive circuit 12. The control signal IL1 is, for example, a "H" level signal or a "L" level signal.

[0045] The drive circuit 11 is a circuit that drives the switching element 13. The drive circuit 11 is connected to the control terminal T1 and the switching element 13. The drive circuit 11 turns the switching element 13 on or off based on the control signal IH1.

[0046] The drive circuit 11 turns on the switch element 13 according to the turn-on request signal for the switch element 13 based on the control signal IH1. Conversely, the drive circuit 11 turns off the switch element 13 according to the turn-off request signal for the switch element 13 based on the control signal IH1.

[0047] The drive circuit 12 is a circuit that drives the switching element 14. The drive circuit 12 is connected to the control terminal T2 and the switching element 14. The drive circuit 12 turns the switching element 14 on or off based on the control signal IL1.

[0048] The drive circuit 12 turns on the switch element 14 according to the turn-on request signal of the control signal IL1. Conversely, the drive circuit 12 turns off the switch element 14 according to the turn-off request signal of the control signal IL1.

[0049] Control signals IH1 and IL1 are controlled to alternately turn switching elements 13 and 14 on or off. Consequently, drive circuits 11 and 12 cause switching elements 13 and 14 to alternately turn on or off. In other words, when one of switching elements 13 and 14 is on, the other is off.

[0050] Input / output terminals T3 to T5 are either input or output terminals. Input / output terminal T3 is connected to node N1. Input / output terminal T4 is connected to node N2. Input / output terminal T5 is connected to node N3. Voltage VDC- is the DC voltage applied to node N3, i.e., input / output terminal T5. Voltage VDC- is, for example, the ground voltage GND. Voltage VDC+ is the DC voltage applied to node N2, i.e., input / output terminal T4. Voltage VDC+ is a voltage higher than voltage VDC-. Voltage VSW is the voltage applied to node N1, i.e., input / output terminal T3. Voltage VSW switches between voltage VDC- and voltage VDC+. Voltage VSW sometimes exceeds voltage VDC+ due to surges caused by parasitic inductance of the wiring when switching elements 13 and 14. Under steady-state conditions, voltage VSW is a voltage in the range above voltage VDC- and below voltage VDC+.

[0051] Switching element 13 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 13 is connected to drive circuit 11. The second terminal of switching element 13 is connected to node N2. The third terminal of switching element 13 is connected to node N1. Switching element 14 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 14 is connected to drive circuit 12. The second terminal of switching element 14 is connected to node N1. The third terminal of switching element 14 is connected to node N3. Switching elements 13 and 14 include at least one of, for example, an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a p-channel MOSFET, a GaN (Gallium Nitride) transistor, a SiC (Silicon Carbide) transistor, an IGBT (Insulated Gate Bipolar Transistor), and a JFET (Junction Field Effect Transistor). Furthermore, switching elements 13 and 14 are normally off switching elements.

[0052] One electrode of capacitor 15 is connected to node N2. The other electrode of capacitor 15 is connected to node N3. In other words, capacitor 15 is connected across the two ends of the series-connected switching elements 13 and 14. Thus, capacitor 15 functions as a buffer capacitor to reduce surges that may occur due to parasitic inductance in the wiring when switching elements 13 and 14 are switched on or off.

[0053] The input and output terminals T3 to T5 become input terminals or output terminals through the structure of the circuit (not shown) connected to the input and output terminals T3 to T5.

[0054] For example, in the case where a synchronous rectification boost converter is constructed from a semiconductor device 1 and a circuit connected to input / output terminals T3 to T5, input / output terminal T3 is an input terminal, and input / output terminals T4 and T5 are output terminals.

[0055] Figure 2 This is a circuit diagram illustrating an application example of semiconductor device 1 (synchronous rectification boost converter). For example... Figure 2 As shown, the synchronous rectification boost converter includes a semiconductor device 1, terminals Tin and Tout, a coil L1, and capacitors C1 and C2.

[0056] Terminal Tin is connected to node N61. Input voltage Vin is applied to terminal Tin.

[0057] Terminal Tout is connected to node N62. Output voltage Vout is output from terminal Tout.

[0058] One end of coil L1 is connected to node N61. The other end of coil L1 is connected to input / output terminal T3.

[0059] One electrode of capacitor C1 is connected to node N61. The other electrode of capacitor C1 is grounded.

[0060] Input / output terminal T4 is connected to node N62.

[0061] One electrode of capacitor C2 is connected to node N62. The other electrode of capacitor C2 is grounded.

[0062] Input / output terminal T5 is grounded.

[0063] When switching element 13 is in the off state and switching element 14 is in the on state, since input / output terminal T3 is grounded through switching element 14, current flows from terminal Tin to coil L1, input / output terminal T3, switching element 14, and input / output terminal T5. At this time, magnetic energy is stored in coil L1.

[0064] Subsequently, when switch element 13 is in the ON state and switch element 14 is in the OFF state, current flows from input / output terminal T3 through switch element 13 to input / output terminal T4 due to the release of magnetic energy by coil L1. As a result, the voltage at node N62 rises because charge is stored in capacitor C2. This rising voltage is output as voltage Vout from terminal Tout.

[0065] Furthermore, for example, when the semiconductor device 1 and the circuit connected to the input / output terminals T3 to T5 constitute a half-bridge converter, a full-bridge converter, a half-bridge LLC converter, or a phase-full-bridge converter, input / output terminal T3 becomes an output terminal, and input / output terminals T4 and T5 become input terminals. Even when the semiconductor device 1 and the circuit connected to the input / output terminals T3 to T5 constitute a DC-AC inverter, input / output terminal T3 also becomes an output terminal, and input / output terminals T4 and T5 become input terminals.

[0066] The following is an example of the case where switching elements 13 and 14 are n-channel MOSFETs.

[0067] Figure 3 This is a circuit diagram illustrating an example of the structure of each switching element in semiconductor device 1.

[0068] like Figure 3 As shown, switching element 13 is transistor TR1. Switching element 14 is transistor TR2. Transistors TR1 and TR2 are n-channel MOSFETs. Furthermore, transistors TR1 and TR2 are normally off transistors.

[0069] The gate electrode (control electrode) of switching element 13 is connected to drive circuit 11. The drain electrode of switching element 13 is connected to node N2. The source electrode of switching element 13 is connected to node N1. The gate electrode (control electrode) of switching element 14 is connected to drive circuit 12. The drain electrode of switching element 14 is connected to node N1. The source electrode of switching element 14 is connected to node N3. The source electrode of switching element 13 and the drain electrode of switching element 14 are connected in series.

[0070] 1.2 Semiconductor Device Structure

[0071] The structure of semiconductor device 1 will be described.

[0072] Figure 4 This is a perspective view showing an example of the structure of semiconductor device 1. For example... Figure 4 As shown, the semiconductor device 1 includes drive circuits 11 and 12, switching elements 13 and 14, and a substrate 20 with a built-in capacitor 15. That is, the substrate 20 is a component-integrated substrate. The substrate 20 is, for example, a glass epoxy board. Furthermore, in Figure 4 The diagrams of control terminals T1 and T2 are omitted.

[0073] Hereinafter, the surface parallel to the surface of substrate 20 will be designated as the XY plane. The directions that intersect each other perpendicularly within the XY plane will be designated as the X direction and the Y direction. The direction intersecting the XY plane will be designated as the Z direction. The direction in the Z direction from substrate 20 toward the wiring layer 30 (described later) will be called the upward direction, and the direction from substrate 20 toward the wiring layers 21, 22, and 23 (described later) will be called the downward direction. Furthermore, the upper surface of substrate 20 will be labeled as the "front surface of substrate 20," and the lower surface of substrate 20 will be labeled as the "back surface of substrate 20."

[0074] Wiring layers 21 to 23 are provided on the back side of substrate 20. Wiring layers 21 to 23 are arranged separately from each other in the X direction. Wiring layer 21 corresponds to input / output terminal T4. A voltage VDC+ is applied to wiring layer 21. Wiring layer 22 corresponds to input / output terminal T5. A voltage VDC- is applied to wiring layer 22. Wiring layer 23 corresponds to input / output terminal T3. A voltage VSW is applied to wiring layer 23. Hereinafter, the surface of wiring layer 22 that contacts substrate 20 will be labeled as "front side of wiring layer 22", and the surface of wiring layer 23 that contacts substrate 20 will be labeled as "front side of wiring layer 23".

[0075] A switching element 14 is disposed above the wiring layer 22. The switching element 14 and the wiring layer 22 are connected via a plurality of through holes 41.

[0076] Wiring layers 24, 25, and 28 are provided above the switching element 14. Wiring layers 24 and 25 are arranged separately from each other in the Y direction. Wiring layers 25 and 28 are arranged separately from each other in the X direction. Wiring layer 24 and switching element 14 are connected via through-hole 41. Wiring layer 25 and switching element 14 are connected via multiple through-holes 41. Wiring layer 28 and switching element 14 are connected via multiple through-holes 41.

[0077] A drive circuit 12 is disposed below the wiring layer 24. The drive circuit 12 and the switching element 14 are arranged separately from each other in the X direction. The drive circuit 12 and the wiring layer 24 are connected via a through-hole 41. Alternatively, the drive circuit 12 may not be built into the substrate 20.

[0078] A dielectric layer 51 is disposed above the wiring layer 25. A wiring layer 26 is disposed above the dielectric layer 51. The wiring layer 25, the dielectric layer 51, and the wiring layer 26 constitute a capacitor 15. The capacitor 15 is disposed between the switching element 13 and the switching element 14.

[0079] A wiring layer 29 is disposed above wiring layer 28. Wiring layers 29 and 26 are configured separately from each other in the X direction. Wiring layers 29 and 28 are connected via a plurality of vias 41.

[0080] A switching element 13 is disposed above wiring layers 26 and 29. The switching element 13 and wiring layer 26 are connected via a plurality of through holes 41. The switching element 13 and wiring layer 29 are connected via a plurality of through holes 41.

[0081] A wiring layer 27 is provided below the switching element 13. The wiring layer 27 and the switching element 13 are connected via a through-hole 41.

[0082] A drive circuit 11 is disposed above the wiring layer 27. The drive circuit 11 and the switching element 13 are arranged separately from each other in the X direction. The drive circuit 11 and the wiring layer 27 are connected via a through-hole 41. Alternatively, the drive circuit 11 may not be built into the substrate 20.

[0083] A wiring layer 30 is provided on the front side of the substrate 20. Wiring layer 30 and wiring layer 21 are connected via a plurality of vias 41. Wiring layer 30 and wiring layer 26 are connected via a plurality of vias 41. Wiring layer 30 and switching element 13 are connected via a plurality of vias 41.

[0084] Wiring layers 21-30 are made of conductive material. Wiring layers 21-30 may contain, for example, copper (copper foil). Via 41 is made of conductive material. Via 41 may contain, for example, copper (copper plating). Dielectric layer 51 may contain, for example, silicon or barium titanate. Dielectric layer 51 may contain, for example, nitride.

[0085] Figure 5 This is an example of a cross-sectional structure representing semiconductor device 1, along... Figure 4 A sectional view along line II.

[0086] like Figure 5 As shown, the switching element 13 has a surface S1 and a surface S2 opposite to surface S1. Hereinafter, surface S1 will be labeled "front side of switching element 13", and surface S2 will be labeled "back side of switching element 13". A drain electrode DE1 and a source electrode SE1 are provided on the front side of the switching element 13. A plurality of through holes 41 are provided between the switching element 13 and the wiring layer 30.

[0087] The switching element 14 has a surface S3 and a surface S4 opposite to surface S3. Hereinafter, surface S3 will be labeled as the "front side of the switching element 14" and surface S4 will be labeled as the "back side of the switching element 14". A source electrode SE2 and a drain electrode DE2 are provided on the front side of the switching element 14. A plurality of through holes 41 are provided between the switching element 14 and the wiring layer 22.

[0088] A wiring layer 25 is disposed above the switching element 14. Multiple vias 41 are provided between the end of the lower surface of the wiring layer 25 on the switching element 14 side and the source electrode SE2 of the switching element 14. In other words, the end of the lower surface of the wiring layer 25 on the switching element 14 side is connected to the multiple vias 41. The source electrode SE2 of the switching element 14 is connected to the multiple vias 41. That is, the wiring layer 25 is connected to the source electrode SE2 of the switching element 14 via the multiple vias 41. Multiple vias 41 are provided between the wiring layer 25 and the wiring layer 22. The wiring layer 25 functions as wiring to provide voltage VDC-. Additionally, the wiring layer 25 functions as another electrode of the capacitor 15. Hereinafter, the lower surface of the wiring layer 25 will also be referred to as the "front surface of the wiring layer 25".

[0089] The dielectric layer 51 is disposed above the wiring layer 25.

[0090] Wiring layer 26 is disposed above dielectric layer 51 and below switching element 13. Multiple vias 41 are provided between the end of the upper surface of wiring layer 26 on the switching element 13 side and the drain electrode DE1 of switching element 13. In other words, the end of the upper surface of wiring layer 26 on the switching element 13 side is connected to multiple vias 41. The drain electrode DE1 of switching element 13 is connected to multiple vias 41. That is, wiring layer 26 is connected to the drain electrode DE1 of switching element 13 via multiple vias 41. Multiple vias 41 are provided between wiring layer 26 and wiring layer 30. Wiring layer 26 functions as wiring to provide voltage VDC+. Additionally, wiring layer 26 functions as one electrode of capacitor 15. Hereinafter, the upper surface of wiring layer 26 will also be referred to as "front side of wiring layer 26".

[0091] Wiring layer 28 is disposed above switching element 14. Wiring layer 28 is disposed on the same layer as wiring layer 25. Multiple vias 41 are provided between the end of the lower surface of wiring layer 28 on the switching element 14 side and the drain electrode DE2 of switching element 14. In other words, the end of the lower surface of wiring layer 28 on the switching element 14 side is connected to multiple vias 41. The drain electrode DE2 of switching element 14 is connected to multiple vias 41. Multiple vias 41 are provided between wiring layer 28 and wiring layer 23. Wiring layer 28 functions as wiring to provide voltage VSW.

[0092] Wiring layer 29 is disposed above wiring layer 28 and below switching element 13. Wiring layer 29 is disposed on the same layer as wiring layer 26. A plurality of vias 41 are provided between wiring layer 29 and wiring layer 28. A plurality of vias 41 are provided between the end of the upper surface of wiring layer 29 on the switching element 13 side and the source electrode SE1 of the switching element 13. In other words, the end of the upper surface of wiring layer 29 on the switching element 13 side is connected to a plurality of vias 41. The source electrode SE1 of the switching element 13 is connected to a plurality of vias 41. Wiring layer 29 functions as wiring to provide voltage VSW.

[0093] Multiple vias 41 are provided between wiring layer 21 and wiring layer 30. Wiring layer 30 functions as wiring to provide voltage VDC+.

[0094] Wiring layer 21 is connected to wiring layer 26 via multiple vias 41, wiring layer 30, and multiple vias 41. Wiring layer 22 is connected to wiring layer 25 via multiple vias 41. Wiring layer 23 is connected to the source electrode SE1 of switching element 13 via multiple vias 41, wiring layer 28, wiring layer 29, and multiple vias 41. Furthermore, wiring layer 23 is connected to the drain electrode DE2 of switching element 14 via multiple vias 41, wiring layer 28, and multiple vias 41.

[0095] Figure 6 This is an example of a cross-sectional structure representing semiconductor device 1, along... Figure 4 A sectional view along line II-II.

[0096] like Figure 6 As shown, a gate electrode GE1 is provided on the front side of the switching element 13. A gate electrode GE2 is provided on the front side of the switching element 14.

[0097] Wiring layer 24 is disposed above switching element 14. A through-hole 41 is provided between the end of the lower surface of wiring layer 24 on the switching element 14 side and the gate electrode GE2 of switching element 14. A through-hole 41 is provided between the end of the lower surface of wiring layer 24 on the opposite side of switching element 14 and drive circuit 12.

[0098] Wiring layer 27 is disposed below switching element 13. A through-hole 41 is provided between the end of the upper surface of wiring layer 27 on the switching element 13 side and the gate electrode GE1 of switching element 13. A through-hole 41 is provided between the end of the upper surface of wiring layer 27 on the opposite side of switching element 13 and drive circuit 11.

[0099] Figure 7 This is an example of a planar structure representing semiconductor device 1, from Figure 5 and Figure 6 The top view showing the position of line aa from below.

[0100] like Figure 7 As shown, multiple vias 41 are provided on the wiring layer 21. The wiring layer 21 functions as an external connection terminal for voltage VDC+.

[0101] Multiple through-holes 41 are provided above the wiring layer 22. The wiring layer 22 functions as an external connection terminal for voltage VDC-. A switching element 14 is provided above the wiring layer 22. Additionally, Figure 7 The back side of the switching element 14 is shown. Multiple through-holes 41 provided between the wiring layer 22 and the switching element 14 are for dissipating heat from the switching element 14. In other words, the wiring layer 22 also functions as a heat dissipation surface for the switching element 14.

[0102] Multiple vias 41 are provided on the wiring layer 23. The wiring layer 23 functions as an external connection terminal for voltage VSW.

[0103] Figure 8 This is an example of a planar structure representing semiconductor device 1, from Figure 5 and Figure 6 The top view showing the position of the bb line from below.

[0104] like Figure 8 As shown, a switching element 14 is disposed above the wiring layer 22. Figure 8 The front side of the switching element 14 is shown. A drain electrode DE2, a source electrode SE2, and two gate electrodes GE2 are provided on the front side of the switching element 14.

[0105] The drain electrode DE2 is disposed at the end of the wiring layer 23 side of the front side of the switching element 14. The source electrode SE2 and two gate electrodes GE2 are disposed at the end of the wiring layer 21 side of the front side of the switching element 14. In other words, the drain electrode DE2, the source electrode SE2, and the two gate electrodes GE2 are separately configured in the X direction.

[0106] Two gate electrodes GE2 are disposed at both ends of the front side of the switching element 14 in the Y direction. A source electrode SE2 is disposed between the two gate electrodes GE2 in the Y direction. In other words, the source electrode SE2 and the two gate electrodes GE2 are arranged in the Y direction in the order of gate electrode GE2, source electrode SE2, and gate electrode GE2, and are configured separately from each other. In addition, there can be one gate electrode GE2 or more than three gate electrodes.

[0107] A drive circuit 12 is disposed above the wiring layer 22. A wiring layer 24 is disposed above the drive circuit 12 and the switching element 14. A through-hole 41 is disposed between the wiring layer 24 and the drive circuit 12. A through-hole 41 is disposed between the wiring layer 24 and the switching element 14.

[0108] A dielectric layer 51 is provided above the wiring layer 22 and above the switching element 14. Multiple vias 41 are provided below the dielectric layer 51 and above the wiring layer 22. More specifically, multiple vias 41 are provided below the dielectric layer 51 and above the source electrode SE2 on the front side of the switching element 14.

[0109] A wiring layer 28 is provided above the wiring layer 23 and above the switching element 14. A plurality of through holes 41 are provided on the wiring layer 28.

[0110] Figure 9 This is an example of a planar structure representing semiconductor device 1, from Figure 5 and Figure 6 The top view showing the position of the cc line from below.

[0111] like Figure 9 As shown, a wiring layer 26 is provided above the wiring layer 22. A plurality of through holes 41 are provided on the wiring layer 26.

[0112] A wiring layer 29 is provided above the wiring layer 23. A plurality of through holes 41 are provided below the wiring layer 29.

[0113] A switching element 13 is provided above wiring layers 26 and 29. Figure 9 The front side of the switching element 13 is shown. A drain electrode DE1, a source electrode SE1, and two gate electrodes GE1 are provided on the front side of the switching element 13.

[0114] The drain electrode DE1 is disposed at the end of the wiring layer 21 side of the front side of the switching element 13. The source electrode SE1 and two gate electrodes GE1 are disposed at the end of the wiring layer 23 side of the front side of the switching element 13. In other words, the drain electrode DE1 is separately disposed from the source electrode SE1 and the two gate electrodes GE1 in the X direction.

[0115] Two gate electrodes GE1 are disposed at both ends of the front side of the switching element 13 in the Y direction. A source electrode SE1 is disposed between the two gate electrodes GE1 in the Y direction. In other words, the source electrode SE1 and the two gate electrodes GE1 are arranged in the Y direction in the order of gate electrode GE1, source electrode SE1, gate electrode GE1, and are configured separately from each other. In addition, there may be one gate electrode GE1 or more than three gate electrodes.

[0116] A plurality of vias 41 are provided between the switching element 13 and the wiring layer 26. More specifically, a plurality of vias 41 are provided between the drain electrode DE1 on the front side of the switching element 13 and the wiring layer 26. A plurality of vias 41 are provided between the switching element 13 and the wiring layer 29. More specifically, a plurality of vias 41 are provided between the source electrode SE1 on the front side of the switching element 13 and the wiring layer 29.

[0117] A drive circuit 11 is disposed above the wiring layer 23. A wiring layer 27 is disposed below the drive circuit 11 and the switching element 13. A through-hole 41 is disposed between the wiring layer 27 and the drive circuit 11. A through-hole 41 is disposed between the wiring layer 27 and the switching element 13.

[0118] Figure 10 This is an example of a planar structure representing semiconductor device 1, from Figure 5 and Figure 6 The top view showing the position of the dd line from below.

[0119] like Figure 10 As shown, multiple vias 41 are provided between wiring layer 30 and wiring layer 21. Multiple vias 41 are also provided between wiring layer 30 and wiring layer 26. Wiring layer 30 functions as wiring to provide voltage VDC+. A z-switch element 13 is provided below wiring layer 30. Figure 10 The back side of the switching element 13 is shown. Multiple through-holes 41 disposed between the wiring layer 30 and the switching element 13 are used to dissipate heat from the switching element 13. In other words, the wiring layer 30 also functions as a heat dissipation surface for the switching element 13.

[0120] The semiconductor device 1 according to this embodiment can reduce noise.

[0121] In a power module with a structure in which buffer capacitors are arranged at both ends of two series-connected switching elements, a high-frequency current flows through the loop formed by the buffer capacitors and the two switching elements when the two switching elements are switched on or off. This high-frequency current can become a source of noise. The longer the wiring connecting the buffer capacitors and the two switching elements, the longer the loop path and the greater the parasitic inductance of the loop. Therefore, to reduce noise caused by high-frequency current, it is preferable to make the loop path shorter.

[0122] Figure 11 This is a diagram showing the high-frequency current path of semiconductor device 1.

[0123] like Figure 11 As shown, the high-frequency current path RT1 of semiconductor device 1 is a path from wiring layer 26 through via 41 above wiring layer 26, drain electrode DE1, source electrode SE1, via 41 below source electrode SE1, wiring layer 29, via 41 below wiring layer 29, wiring layer 28, via 41 below wiring layer 28, drain electrode DE2, source electrode SE2, and via 41 above source electrode SE2 to wiring layer 25.

[0124] The semiconductor device 1 of this embodiment includes: a switching element 13 having a drain electrode DE1 and a source electrode SE1 disposed on the front side, a switching element 14 having a source electrode SE2 and a drain electrode DE2 disposed on the front side, and a substrate 20 having a built-in capacitor 15.

[0125] The capacitor 15 includes a wiring layer 25 connected to the source electrode SE2, a wiring layer 26 connected to the drain electrode DE1, and a dielectric layer 51 disposed between the wiring layers 25 and 26. The capacitor 15 is formed between the layer where the switching element 13 is disposed and the layer where the switching element 14 is disposed. The source electrode SE2 is disposed opposite to the drain electrode DE1 in the Z direction. The drain electrode DE2 is disposed opposite to the source electrode SE1 in the Z direction. Furthermore, the drain electrode DE2 and the source electrode SE1 are connected in series.

[0126] Due to the aforementioned structure, in this embodiment, compared to the case where capacitor 15 is not formed between switching elements 13 and 14, and drain electrode DE1 and source electrode SE2 are not opposite each other, and source electrode SE1 and drain electrode DE2 are not opposite each other, the path between wiring layer 26 and drain electrode DE1 is shorter. The paths between source electrode SE1 and drain electrode DE2, and between source electrode SE2 and wiring layer 25, are also shorter. Therefore, compared to the case where capacitor 15 is not formed between switching elements 13 and 14, and drain electrode DE1 and source electrode SE2 are not opposite each other, the high-frequency current path RT1 is shortened. Therefore, the parasitic inductance of the loop formed by capacitor 15 and switching elements 13 and 14 can be reduced. Therefore, according to this embodiment, noise can be reduced. Furthermore, by reducing noise, power conversion efficiency can be improved.

[0127] Drain electrode DE1 and source electrode SE1 are arranged opposite each other in the X direction. Source electrode SE2 and drain electrode DE2 are also arranged opposite each other in the X direction. Therefore, in this embodiment, the paths between drain electrode DE1 and source electrode SE1, and between drain electrode DE2 and source electrode SE2, are relatively short. Consequently, the high-frequency current path RT1 becomes relatively short.

[0128] The thickness of dielectric layer 51 is thinner than the thickness of switching element 13. Furthermore, the thickness of dielectric layer 51 is thinner than the thickness of switching element 14. That is, the thickness of capacitor 15 is relatively thin. Therefore, in this embodiment, the paths between wiring layer 26 and drain electrode DE1, between source electrode SE2 and wiring layer 25, and between source electrode SE1 and drain electrode DE2 are relatively short. Moreover, the thicknesses of switching elements 13 and 14 are independent of the high-frequency current path RT1. Thus, the high-frequency current path RT1 becomes relatively short.

[0129] The dielectric layer 51 comprises, for example, silicon or barium titanate. That is, the capacitor 15 is, for example, a silicon capacitor or a barium titanate capacitor. Thin capacitors, such as silicon capacitors or barium titanate capacitors, can be formed between the layer containing the switching element 13 and the layer containing the switching element 14 within the substrate 20. This allows for a thinner capacitor 15. Therefore, in this embodiment, the paths between the wiring layer 26 and the drain electrode DE1, the path between the source electrode SE2 and the wiring layer 25, and the path between the source electrode SE1 and the drain electrode DE2 are relatively short. Consequently, the high-frequency current path RT1 becomes relatively short.

[0130] The front area of ​​wiring layer 26 is larger than the front area of ​​switching element 13. The front area of ​​wiring layer 25 is larger than the front area of ​​switching element 14. Therefore, the capacitance of capacitor 15 is relatively large.

[0131] Wiring layer 26 protrudes further into wiring layer 21 than switching element 13 in the X direction. Wiring layer 25 protrudes further into wiring layer 21 than switching element 14 in the X direction. Therefore, the areas of switching element 13 and switching element 14 are relatively large. Consequently, the capacitance of capacitor 15 is relatively large.

[0132] The back side of the switching element 13 is connected to the wiring layer 30 via a plurality of vias 41. Thus, heat from the switching element 13 is dissipated to the outside of the semiconductor device 1 through the vias 41 and the wiring layer 30. The back side of the switching element 14 is connected to the wiring layer 22 via a plurality of vias 41. Thus, heat from the switching element 14 is dissipated to the outside of the semiconductor device 1 through the vias 41 and the wiring layer 22.

[0133] The area of ​​the front side of wiring layer 23 is smaller than that of the front side of wiring layer 22. This is because wiring layer 22 functions as a heat dissipation surface for the switching element 14, so wiring layer 23 does not necessarily need to function as a heat dissipation surface. Wiring layer 23 is connected to wiring layers 28 and 29 included in the high-frequency current path RT1, and therefore may become a noise source. However, because the area of ​​the front side of wiring layer 23 is smaller, the noise source can be reduced.

[0134] Furthermore, when switching elements 13 and 14 are GaN transistors, the switching operation of switching elements 13 and 14 can be accelerated.

[0135] 2. Second Implementation Method

[0136] The semiconductor device according to the second embodiment will be described. The semiconductor device 1A of the second embodiment includes two semiconductor devices 1 and has a structure in which the two semiconductor devices 1 share an input / output terminal T3. Hereinafter, the differences from the first embodiment will be described.

[0137] 2.1 Circuit Structure of Semiconductor Devices

[0138] use Figure 12 Explain the circuit structure of semiconductor device 1A. Figure 12 This is a circuit diagram illustrating an example of the circuit structure of semiconductor device 1A.

[0139] Semiconductor device 1A includes control terminals T1 and T2, drive circuits 11 and 12, input / output terminals T3 to T5, switching elements 13 and 14, capacitor 15, control terminals T6 and T7, drive circuits 61 and 62, input / output terminals T8 and T9, switching elements 63 and 64, and capacitor 65.

[0140] Control terminals T1 and T2, drive circuits 11 and 12, input / output terminals T4 and T5, switching elements 13 and 14, and capacitor 15 are the same as those shown in the first embodiment. Figure 1 same.

[0141] Control terminal T6 is the terminal through which control signal IH2 is input from the outside. Control signal IH2 is a signal used to control the operation of drive circuit 61. Control signal IH2 is, for example, a "H" level signal or a "L" level signal.

[0142] Control terminal T7 is the terminal through which the control signal IL2 is input from the outside. The control signal IL2 is a signal used to control the operation of the drive circuit 62. The control signal IL2 is, for example, a "H" level signal or a "L" level signal.

[0143] The drive circuit 61 is a circuit that drives the switching element 63. The drive circuit 61 is connected to the control terminal T6 and the switching element 63. The drive circuit 61 turns the switching element 63 on or off based on the control signal IH2.

[0144] The drive circuit 62 is a circuit that drives the switching element 64. The drive circuit 62 is connected to the control terminal T7 and the switching element 64. The drive circuit 62 turns the switching element 64 on or off based on the control signal IL2.

[0145] Control signal IH2 is the same as control signal IH1. Control signal IL2 is the same as control signal IL1. Therefore, drive circuit 61 operates synchronously with drive circuit 11. Drive circuit 62 operates synchronously with drive circuit 12. Thus, drive circuits 11, 12, 61, and 62 cause switching elements 13 and 63, and switching elements 14 and 64 to alternately turn on or off. In other words, when one of switching elements 13 and 63, or switching elements 14 and 64 is in the on state, the other is in the off state.

[0146] Input / output terminals T3, T8, and T9 are either input or output terminals. Input / output terminal T3 is connected to nodes N1 and N4. Input / output terminal T8 is connected to node N5. Input / output terminal T9 is connected to node N6. A voltage VSW is applied to node N4, i.e., input / output terminal T3. A voltage VDC+ is applied to node N5, i.e., input / output terminal T8. A voltage VDC- is applied to node N6, i.e., input / output terminal T9.

[0147] Switching element 63 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 63 is connected to drive circuit 61. The second terminal of switching element 63 is connected to node N5. The third terminal of switching element 63 is connected to node N4. Switching element 64 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 64 is connected to drive circuit 62. The second terminal of switching element 64 is connected to node N4. The third terminal of switching element 64 is connected to node N6. Switching elements 63 and 64 include at least one of, for example, an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT, and a JFET.

[0148] One electrode of capacitor 65 is connected to node N5. The other electrode of capacitor 65 is connected to node N6. In other words, capacitor 65 is connected to both ends of the series-connected switching elements 63 and 64. Thus, capacitor 65 functions as a buffer capacitor.

[0149] Alternatively, in semiconductor device 1A, drive circuits 61 and 62, and control terminals T6 and T7 may not be included, and drive circuits 11 and 12, and control terminals T1 and T2 may be shared. In this case, the control electrode of switching element 63 is connected to drive circuit 11. The control electrode of switching element 64 is connected to drive circuit 12.

[0150] The input / output terminals T3, T8, and T9, through the structure of the circuit (not shown) connected to the input / output terminals T3, T8, and T9, are the same as in the first embodiment, and thus become input terminals or output terminals.

[0151] The following is an example of the case where switching elements 63 and 64 are n-channel MOSFETs.

[0152] Figure 13 This is a circuit diagram illustrating an example of the structure of each switching element in semiconductor device 1.

[0153] like Figure 13 As shown, switching element 63 is transistor TR3. Switching element 64 is transistor TR4. Transistors TR3 and TR4 are n-channel MOSFETs. Furthermore, transistors TR3 and TR4 are normally off transistors.

[0154] The gate electrode (control electrode) of switching element 63 is connected to drive circuit 61. The drain electrode of switching element 63 is connected to node N5. The source electrode of switching element 63 is connected to node N4. The gate electrode (control electrode) of switching element 64 is connected to drive circuit 62. The drain electrode of switching element 64 is connected to node N4. The source electrode of switching element 64 is connected to node N6. The source electrode of switching element 63 and the drain electrode of switching element 64 are connected in series.

[0155] 2.2 Structure of Semiconductor Devices

[0156] The structure of semiconductor device 1A will be described. Semiconductor device 1A has a structure that combines two semiconductor devices 1. Figure 14 This is an example of a cross-sectional structure of semiconductor device 1A, shown along the same path as in the first embodiment. Figure 4 A cross-sectional view of the same line as line II.

[0157] like Figure 14 As shown, in semiconductor device 1A, the structure on the left side of the X-axis, using a line (hereinafter referred to as "AA line") extending along the Z-direction from the center of the front side of wiring layer 23 as a boundary, has the same structure as semiconductor device 1, while the structure on the right side of the X-axis has the structure after rotating semiconductor device 1 180 degrees around the AA line as a rotation axis. Wiring layer 71 corresponds to wiring layer 21. Wiring layer 72 corresponds to wiring layer 22. Switching element 63 corresponds to switching element 13. Switching element 64 corresponds to switching element 14. Wiring layer 74 corresponds to wiring layer 25. Dielectric layer 81 corresponds to dielectric layer 51. Wiring layer 75 corresponds to wiring layer 26. Capacitor 65 corresponds to capacitor 15.

[0158] Wiring layers 71 and 72 are provided on the back side of substrate 20. Wiring layers 23, 71, and 72 are arranged separately from each other in the X direction. Wiring layer 71 corresponds to input / output terminal T8. A voltage VDC+ is applied to wiring layer 71. Wiring layer 72 corresponds to input / output terminal T9. A voltage VDC- is applied to wiring layer 72.

[0159] The switching element 63 has a surface S5 and a surface S6 opposite to surface S5. Hereinafter, surface S5 will be labeled as the "front side of the switching element 63" and surface S6 will be labeled as the "back side of the switching element 63". A drain electrode DE3 and a source electrode SE3 are provided on the front side of the switching element 63. A plurality of through holes 41 are provided between the switching element 63 and the wiring layer 30.

[0160] The switching element 64 has a surface S7 and a surface S8 opposite to surface S7. Hereinafter, surface S7 will be labeled as the "front side of the switching element 64" and surface S8 will be labeled as the "back side of the switching element 64". A source electrode SE4 and a drain electrode DE4 are provided on the front side of the switching element 64. A plurality of through holes 41 are provided between the switching element 64 and the wiring layer 72.

[0161] A wiring layer 74 is disposed above the switching element 64. Multiple vias 41 are provided between the end of the lower surface of the wiring layer 74 on the switching element 64 side and the source electrode SE4 of the switching element 64. In other words, the end of the lower surface of the wiring layer 74 on the switching element 64 side is connected to the multiple vias 41. The source electrode SE4 of the switching element 64 is connected to the multiple vias 41. That is, the wiring layer 74 is connected to the source electrode SE4 of the switching element 64 via the multiple vias 41. Multiple vias 41 are provided between the wiring layer 74 and the wiring layer 72. The wiring layer 74 functions as wiring to provide voltage VDC-. Additionally, the wiring layer 74 functions as another electrode of the capacitor 65.

[0162] The dielectric layer 81 is disposed above the wiring layer 74.

[0163] A wiring layer 75 is disposed above the dielectric layer 81 and below the switching element 63. A plurality of vias 41 are provided between the end of the upper surface of the wiring layer 75 on the switching element 63 side and the drain electrode DE3 of the switching element 63. In other words, the end of the upper surface of the wiring layer 75 on the switching element 63 side is connected to the plurality of vias 41. The drain electrode DE3 of the switching element 63 is connected to the plurality of vias 41. That is, the wiring layer 75 is connected to the drain electrode DE3 of the switching element 63 via the plurality of vias 41. A plurality of vias 41 are provided between the wiring layer 75 and the wiring layer 30. The wiring layer 75 functions as wiring to provide voltage VDC+. Additionally, the wiring layer 75 functions as one electrode of the capacitor 65.

[0164] Multiple through-holes 41 are provided between wiring layer 71 and wiring layer 30.

[0165] Wiring layer 71 is connected to wiring layer 75 via multiple vias 41, wiring layer 30, and multiple vias 41. Wiring layer 72 is connected to wiring layer 74 via multiple vias 41. Wiring layer 23 is connected to the source electrode SE3 of switching element 63 via multiple vias 41, wiring layer 28, wiring layer 29, and multiple vias 41. Furthermore, wiring layer 23 is connected to the drain electrode DE4 of switching element 64 via multiple vias 41, wiring layer 28, and multiple vias 41.

[0166] Figure 15 This is an example of a cross-sectional structure of semiconductor device 1, shown along the same path as in the first embodiment. Figure 4 A cross-sectional view of the same line as line II-II.

[0167] like Figure 15 As shown, in semiconductor device 1A, along with... Figure 4 The cross-sectional structure of the same line as line II-II, with line AA as the boundary, differs between the structure on the left side along the X-axis and the structure on the right side along the X-axis.

[0168] A gate electrode GE3 is disposed on the front side of the switching element 63. A gate electrode GE4 is disposed on the front side of the switching element 64.

[0169] Figure 16 This is an example of a planar structure representing semiconductor device 1, from Figure 14 and Figure 15 The top view showing the position of line aa from below.

[0170] like Figure 16 As shown, multiple vias 41 are provided on the wiring layer 71. The wiring layer 71 functions as an external connection terminal for voltage VDC+.

[0171] Multiple through-holes 41 are provided above the wiring layer 72. The wiring layer 72 functions as an external connection terminal for voltage VDC-. A switching element 64 is provided above the wiring layer 72. Additionally, Figure 16 The back side of the switching element 64 is shown. Multiple through-holes 41 provided between the wiring layer 72 and the switching element 64 are for dissipating heat from the switching element 64. In other words, the wiring layer 72 also functions as a heat dissipation surface for the switching element 64.

[0172] Figure 17 This is an example of a planar structure representing semiconductor device 1, from Figure 14 and Figure 15 The top view showing the position of the bb line from below.

[0173] like Figure 17 As shown, a switching element 64 is disposed above the wiring layer 72. Additionally, Figure 17 The front side of the switching element 64 is shown. A drain electrode DE4, a source electrode SE4, and two gate electrodes GE4 are provided on the front side of the switching element 64.

[0174] The drain electrode DE4 is disposed at the end of the wiring layer 23 side of the front side of the switching element 64. The source electrode SE4 and the two gate electrodes GE4 are disposed at the end of the wiring layer 71 side of the front side of the switching element 64. In other words, the drain electrode DE4 is separately configured from the source electrode SE4 and the two gate electrodes GE4 in the X direction.

[0175] Two gate electrodes GE4 are disposed at both ends of the front side of the switching element 64 in the Y direction. A source electrode SE4 is disposed between the two gate electrodes GE4 in the Y direction. In other words, the source electrode SE4 and the two gate electrodes GE4 are arranged separately from each other in the Y direction in the order of gate electrode GE4, source electrode SE4, gate electrode GE4. In addition, there may be one gate electrode GE4 or more than three gate electrodes GE4.

[0176] A drive circuit 62 is disposed above the wiring layer 72. The drive circuit 62 corresponds to the drive circuit 12. A wiring layer 73 is disposed above the drive circuit 62 and the switching element 64. The wiring layer 73 corresponds to the wiring layer 24. A through-hole 41 is disposed between the wiring layer 73 and the drive circuit 62. A through-hole 41 is disposed between the wiring layer 73 and the switching element 64.

[0177] A dielectric layer 81 is provided above the wiring layer 72 and above the switching element 64. A plurality of vias 41 are provided below the dielectric layer 81 and above the wiring layer 72. More specifically, a plurality of vias 41 are provided below the dielectric layer 81 and above the source electrode SE4 on the front side of the switching element 64.

[0178] A wiring layer 28 is provided above the wiring layer 23 and above the switching element 64. A plurality of through holes 41 are provided on the wiring layer 28.

[0179] Figure 18 This is an example of a planar structure representing semiconductor device 1, from Figure 14 and Figure 15 The top view showing the position of the cc line from below.

[0180] like Figure 18 As shown, a wiring layer 75 is provided above the wiring layer 72. A plurality of through holes 41 are provided above the wiring layer 75.

[0181] A wiring layer 29 is provided above the wiring layer 23. A plurality of through holes 41 are provided below the wiring layer 29.

[0182] A switching element 63 is disposed above wiring layers 75 and 29. Additionally, Figure 18 The front side of the switching element 63 is shown. A drain electrode DE3, a source electrode SE3, and two gate electrodes GE3 are provided on the front side of the switching element 63.

[0183] The drain electrode DE3 is disposed at the end of the wiring layer 71 side on the front side of the switching element 63. The source electrode SE3 and two gate electrodes GE3 are disposed at the end of the wiring layer 23 side on the front side of the switching element 63. In other words, the drain electrode DE3, the source electrode SE3, and the two gate electrodes GE3 are separately configured in the X direction.

[0184] Two gate electrodes GE3 are disposed at both ends of the front side of the switching element 63 in the Y direction. A source electrode SE3 is disposed between the two gate electrodes GE3 in the Y direction. In other words, the source electrode SE3 and the two gate electrodes GE3 are arranged in the Y direction in the order of gate electrode GE3, source electrode SE3, and gate electrode GE3, and are configured separately from each other. Furthermore, there can be one or more gate electrodes GE3.

[0185] A plurality of vias 41 are provided between the switching element 63 and the wiring layer 75. More specifically, a plurality of vias 41 are provided between the drain electrode DE3 on the front side of the switching element 63 and the wiring layer 75. A plurality of vias 41 are provided between the switching element 63 and the wiring layer 29. More specifically, a plurality of vias 41 are provided between the source electrode SE3 on the front side of the switching element 63 and the wiring layer 29.

[0186] A drive circuit 61 is disposed above the wiring layer 23. The drive circuit 61 corresponds to the drive circuit 11. A wiring layer 76 is disposed below the drive circuit 61 and the switching element 63. The wiring layer 76 corresponds to the wiring layer 27. A through-hole 41 is disposed between the wiring layer 76 and the drive circuit 61. A through-hole 41 is disposed between the wiring layer 76 and the switching element 63.

[0187] Figure 19 This is an example of a planar structure representing semiconductor device 1, from Figure 14 and Figure 15 The top view showing the position of the dd line from below.

[0188] like Figure 19 As shown, a plurality of through-holes 41 are provided between wiring layer 30 and wiring layer 71. A plurality of through-holes 41 are also provided between wiring layer 30 and wiring layer 75. A switching element 63 is provided below wiring layer 30. Furthermore, Figure 19 The back side of the switching element 63 is shown. Multiple through-holes 41 are provided between the wiring layer 30 and the switching element 63 to dissipate heat from the switching element 63. In other words, the wiring layer 30 also functions as a heat dissipation surface for the switching element 63.

[0189] The semiconductor device 1A according to this embodiment can reduce noise.

[0190] Figure 20 This is a diagram showing the high-frequency current path of semiconductor device 1A and the magnetic flux generated by the high-frequency current.

[0191] like Figure 20 As shown, the high-frequency current path of semiconductor device 1A includes the path shown in the first embodiment. Figure 11 The path (hereinafter, marked as "first path RT1").

[0192] Furthermore, the semiconductor device 1A includes a path (hereinafter referred to as "second path RT2") from the wiring layer 75 through the via 41 above the wiring layer 75, the drain electrode DE3, the via 41 below the source electrode SE3, the wiring layer 29, the via 41 below the wiring layer 29, the wiring layer 28, the via 41 below the wiring layer 28, the drain electrode DE4, the source electrode SE4, and the via 41 above the source electrode SE4 to the wiring layer 74.

[0193] The semiconductor device 1A of this embodiment includes the semiconductor device 1 shown in the first embodiment.

[0194] The substrate 20 has a built-in switching element 63 with a drain electrode DE3 and a source electrode SE3 on the front side, a switching element 64 with a source electrode SE4 and a drain electrode DE4 on the front side, and a capacitor 65.

[0195] The capacitor 65 includes a wiring layer 74 connected to the source electrode SE4, a wiring layer 75 connected to the drain electrode DE3, and a dielectric layer 81 disposed between the wiring layers 74 and 75. The capacitor 65 is formed between the layer where the switching element 63 is disposed and the layer where the switching element 64 is disposed. The source electrode SE4 is disposed opposite to the drain electrode DE3 in the Z direction. The drain electrode DE4 is disposed opposite to the source electrode SE3 in the Z direction. Furthermore, the drain electrode DE4 and the source electrode SE3 are connected in series.

[0196] Because of the above-described structure, in this embodiment, the high-frequency current path is shortened in both the first path RT1 and the second path RT2, similar to the first embodiment. Therefore, this embodiment achieves the same effect as the first embodiment.

[0197] Additionally, wiring layer 25 is connected to wiring layer 22, which provides voltage VDC-. Wiring layer 26 is connected to wiring layer 21, which provides voltage VDC+. Source electrode SE1 and drain electrode DE2 are connected to wiring layer 23, which provides voltage VSW in the range above VDC- and below VDC+. Wiring layer 74 is connected to wiring layer 72, which provides voltage VDC-. Wiring layer 75 is connected to wiring layer 71, which provides voltage VDC+. Source electrode SE3 and drain electrode DE4 are connected to wiring layer 23.

[0198] Switching elements 63 and 64 and capacitor 65 (wiring layers 74 and 75 and dielectric layer 81) are positioned such that switching elements 13 and 14 and capacitor 15 (wiring layers 25 and 26 and dielectric layer 51) are rotated 180 degrees about the AA line as the rotation axis. Wiring layers 71 and 72 are positioned such that wiring layers 21 and 22 are rotated 180 degrees about the AA line as the rotation axis.

[0199] Because of the above structure, such as Figure 20 As shown, in this embodiment, the direction of the magnetic flux Φ1 generated by the high-frequency current flowing through the first path RT1 (from the front of the paper towards the depth) is opposite to the direction of the magnetic flux Φ2 generated by the high-frequency current flowing through the second path RT2 (from the depth of the paper towards the front). Therefore, the magnetic fluxes generated in the two paths RT1 and RT2 respectively cancel each other out. Thus, noise emitted to the outside due to the generation of magnetic flux can be suppressed. Therefore, according to this embodiment, noise can be reduced. In addition, by reducing noise, power conversion efficiency can be improved.

[0200] 3. Third Implementation Method

[0201] The semiconductor device according to the third embodiment will be described. The semiconductor device 1B according to the third embodiment has the following structure: the switching elements 13 and 14 of the semiconductor device 1 are replaced with normally-on switching elements, and normally-on switching elements and a drive circuit for realizing pseudo-normal on / off (hereinafter referred to as "QN-off drive circuit") are added to the semiconductor device 1. Hereinafter, the differences from the first embodiment will be described.

[0202] 3.1 Circuit Structure of Semiconductor Devices

[0203] use Figure 21 Explain the circuit structure of semiconductor device 1B. Figure 21 This is a circuit diagram illustrating an example of the circuit structure of semiconductor device 1B.

[0204] Semiconductor device 1B includes control terminals T1 and T2, drive circuits 11 and 12, input / output terminals T3 to T5, switching elements 13 and 14, and capacitor 15. Furthermore, semiconductor device 1B includes control terminals T10 and T11, QN-off drive circuits 91 and 92, and switching elements 93 and 94.

[0205] Control terminals T1 and T2, input / output terminals T3 to T5, and capacitor 15 are the same as those shown in the first embodiment. Figure 1 same.

[0206] The third terminal of switching element 13 is connected to node N7. The third terminal of switching element 14 is connected to node N8. Switching elements 13 and 14 include at least one of, for example, an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT, and a JFET. Furthermore, switching elements 13 and 14 are normally-on switching elements.

[0207] Control terminal T10 is the terminal for inputting control signal IH3 from the outside. Control signal IH3 is a signal used to control the operation of QN-off drive circuit 91. Control signal IH3 is, for example, a "H" level signal or a "L" level signal.

[0208] Control terminal T11 is the terminal for inputting control signal IL3 from the outside. Control signal IL3 is a signal used to control the operation of QN-off drive circuit 92. Control signal IL3 is, for example, a "H" level signal or a "L" level signal.

[0209] The QN-off drive circuit 91 is a circuit that drives the switching element 93. The QN-off drive circuit 91 is connected to the control terminal T10 and the switching element 93. The QN-off drive circuit 91 turns the switching element 93 on or off based on the control signal IH3.

[0210] The QN-off drive circuit 92 is a circuit that drives the switching element 94. The QN-off drive circuit 92 is connected to the control terminal T11 and the switching element 94. The QN-off drive circuit 92 turns the switching element 94 on or off based on the control signal IL3.

[0211] The drive circuit 11 turns on the switch element 13 according to the turn-on request signal for the switch element 13 based on the control signal IH1. Conversely, the drive circuit 11 turns off the switch element 13 according to the turn-off request signal for the switch element 13 based on the control signal IH1.

[0212] The drive circuit 12 turns on the switch element 14 according to the turn-on request signal for the switch element 14 based on the control signal IL1. Conversely, the drive circuit 12 turns off the switch element 14 according to the turn-off request signal for the switch element 14 based on the control signal IL1.

[0213] However, when the power supply to the entire system including semiconductor device 1B is turned on or off, when the power supply is in an unpredictable state, the switching elements 13 and 14 may sometimes be turned on unintentionally.

[0214] Therefore, when the power supply is in an unpredictable state, control signals IH3 and IL3 are controlled to disconnect switching elements 93 and 94. Consequently, the switching elements on the high side (including switching elements 13 and 93) and the switching elements on the low side (including switching elements 14 and 94) are both disconnected. Conversely, when the power supply is in a stable state, control signals IH3 and IL3 are controlled to turn on switching elements 93 and 94. Control signals IH1 and IL1 are controlled to alternately turn switching elements 13 and 14 on or off. Consequently, the switching elements on the high side (including switching elements 13 and 93) and the switching elements on the low side (including switching elements 14 and 94) are alternately turned on or off. In this way, a "pseudo-normally off" state is achieved. Thus, power conversion and control are performed by alternately driving the switching elements on the high side and the low side.

[0215] Switching element 93 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 93 is connected to QN-off drive circuit 91. The second terminal of switching element 93 is connected to node N7. The third terminal of switching element 93 is connected to node N1. Switching element 94 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 94 is connected to QN-off drive circuit 92. The second terminal of switching element 94 is connected to node N8. The third terminal of switching element 94 is connected to node N3. Switching elements 93 and 94 comprise at least one of, for example, an n-channel MOSFET and a p-channel MOSFET. Furthermore, switching elements 93 and 94 are normally off switching elements.

[0216] Below, as an example, we will explain the case where switching elements 13 and 14 are n-channel MOSFETs and switching elements 93 and 94 are p-channel MOSFETs.

[0217] Figure 22 This is a circuit diagram illustrating an example of the structure of each switching element in semiconductor device 1B.

[0218] like Figure 22 As shown, switching element 13 is transistor TR1. Switching element 14 is transistor TR2. Transistors TR1 and TR2 are n-channel MOSFETs. Furthermore, transistors TR1 and TR2 are normally-on transistors.

[0219] The source electrode of switching element 13 is connected to node N7. The source electrode of switching element 14 is connected to node N8.

[0220] Switching element 93 is transistor TR5. Switching element 94 is transistor TR6. Transistors TR5 and TR6 are p-channel MOSFETs. Furthermore, transistors TR5 and TR6 are normally off transistors.

[0221] The gate electrode (control electrode) of switching element 93 is connected to QN-off drive circuit 91. The drain electrode of switching element 93 is connected to node N1. The source electrode of switching element 93 is connected to node N7. The gate electrode (control electrode) of switching element 94 is connected to QN-off drive circuit 92. The drain electrode of switching element 94 is connected to node N3. The source electrode of switching element 94 is connected to node N8.

[0222] The source electrode of switching element 13 and the source electrode of switching element 93 are connected in series. The drain of switching element 93 and the drain of switching element 14 are connected in series. The source electrode of switching element 14 and the source electrode of switching element 94 are connected in series.

[0223] 3.2 Semiconductor Device Structure

[0224] The structure of semiconductor device 1B will be described. Semiconductor device 1B has a structure in which a switching element 93 is disposed between the wiring layer 29 of semiconductor device 1 and the switching element 13, and a QN-off drive circuit 91 connected to the switching element 93 is provided. Additionally, semiconductor device 1B has a structure in which a switching element 94 is disposed between the wiring layer 25 of semiconductor device 1 and the switching element 14, and a QN-off drive circuit 92 connected to the switching element 94 is provided. Figure 23 This is an example of a cross-sectional structure of semiconductor device 1B, shown along the same path as in the first embodiment. Figure 4 A cross-sectional view of the same line as line II.

[0225] A switching element 93 is disposed above wiring layer 29. The drain electrode (not shown) of switching element 93 is connected to wiring layer 29 via a plurality of vias 41. A switching element 13 is disposed above switching element 93. The source electrode (not shown) of switching element 93 is connected to the source electrode SE1 of switching element 13 via a plurality of vias 41. The drain electrode of switching element 93 is disposed, for example, on the surface of switching element 93 (the surface opposite wiring layer 29 in the Z direction). The source electrode of switching element 93 is disposed, for example, on the surface of switching element 93 (the surface opposite source electrode SE1 in the Z direction). The drain electrode DE2 of switching element 14 is connected in series with switching element 93.

[0226] A switching element 94 is disposed below wiring layer 25. The drain electrode (not shown) of switching element 94 is connected to wiring layer 25 via a plurality of vias 41. A switching element 14 is disposed below switching element 94. The source electrode (not shown) of switching element 94 is connected to the source electrode SE2 of switching element 14 via a plurality of vias 41. The drain electrode of switching element 94 is disposed, for example, on the surface of switching element 94 (the surface opposite wiring layer 25 in the Z direction). The source electrode of switching element 94 is disposed, for example, on the surface of switching element 94 (the surface opposite source electrode SE2 in the Z direction).

[0227] Figure 24 This is an example of a cross-sectional structure representing semiconductor device 1B, along with... Figure 4 A cross-sectional view of the same line as line II-II.

[0228] like Figure 24 As shown, a gate electrode GE1 is provided on the front side of the switching element 13. A gate electrode GE2 is provided on the front side of the switching element 14.

[0229] A wiring layer 95 is provided below the switching element 93. The switching element 93 is connected to the wiring layer 95 via a through-hole 41. A QN-off drive circuit 91 is provided above the wiring layer 95 and below the switching element 13. The QN-off drive circuit 91 is connected to the wiring layer 95 via a through-hole 41.

[0230] A wiring layer 96 is provided above the switching element 94. The switching element 94 is connected to the wiring layer 96 via a through-hole 41. A QN-off drive circuit 92 is provided below the wiring layer 96 and above the switching element 14. The QN-off drive circuit 92 is connected to the wiring layer 96 via a through-hole 41.

[0231] Figure 25 This is a diagram showing the high-frequency current path of semiconductor device 1B.

[0232] like Figure 25 As shown, the high-frequency current path RT3 of semiconductor device 1B is a wiring layer from wiring layer 26 through via 41 above wiring layer 26, drain electrode DE1, source electrode SE1, via 41 below source electrode SE1, switching element 93, via 41 below switching element 93, via 41 below wiring layer 29, wiring layer 28, via 41 below wiring layer 28, drain electrode DE2, source electrode SE2, via 41 above source electrode SE2, switching element 94, and via 41 above switching element 94, up to wiring layer 25.

[0233] The semiconductor device 1B of this embodiment includes: a switching element 13 having a drain electrode DE1 and a source electrode SE1 disposed on the front side; a switching element 14 having a source electrode SE2 and a drain electrode DE2 disposed on the front side; switching elements 93 and 94; and a substrate 20 having a built-in capacitor 15.

[0234] Switching element 93 is disposed between source electrode SE1 and drain electrode DE2. Switching element 94 is disposed between drain electrode DE1 and source electrode SE2. More specifically, switching element 93 is disposed between wiring layer 29 and switching element 13. Switching element 94 is disposed between wiring layer 25 and switching element 14.

[0235] Because of the above-described structure, in this embodiment, the length of the high-frequency current path RT3 can be set to the same length as the high-frequency current path RT1 shown in the first embodiment. Therefore, the parasitic inductance of the loop formed by capacitor 15 and switching elements 13, 14, 93, and 94 can be reduced. Thus, according to this embodiment, similar to the first embodiment, noise can be reduced and power conversion efficiency can be improved.

[0236] 4. Fourth Implementation Method

[0237] The semiconductor device according to the fourth embodiment will be described. The semiconductor device 1C of the fourth embodiment has the following structure: the switching elements 13, 14, 63, and 64 of the semiconductor device 1A are replaced with normally-on switching elements, and normally-off switching elements and a QN-off drive circuit are added to the semiconductor device 1A. Hereinafter, the differences from the second embodiment will be described.

[0238] 4.1 Circuit Structure of Semiconductor Devices

[0239] use Figure 26 The circuit structure of semiconductor device 1C is described. Figure 26 This is a circuit diagram illustrating an example of the circuit structure of a semiconductor device 1C.

[0240] Semiconductor device 1C includes control terminals T1 and T2, drive circuits 11 and 12, input / output terminals T3 to T5, switching elements 13 and 14, capacitor 15, control terminals T6 and T7, drive circuits 61 and 62, input / output terminals T8 and T9, switching elements 63 and 64, and capacitor 65. Furthermore, semiconductor device 1C includes control terminals T10 and T11, QN-off drive circuits 91 and 92, switching elements 93 and 94, control terminals T12 and T13, QN-off drive circuits 101 and 102, and switching elements 103 and 104.

[0241] Control terminals T1 and T2, input / output terminals T3 to T5, capacitor 15, control terminals T6 and T7, input / output terminals T8 and T9, and capacitor 65 are as shown in the second embodiment. Figure 12 same.

[0242] The drive circuits 11 and 12, switching elements 13 and 14, control terminals T10 and T11, QN-off drive circuits 91 and 92, and switching elements 93 and 94 are the same as those shown in the third embodiment. Figure 21 same.

[0243] The third terminal of switching element 63 is connected to node N9. The third terminal of switching element 64 is connected to node N10. Switching elements 63 and 64 comprise at least one of, for example, an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT, and a JFET. Furthermore, switching elements 63 and 64 are normally-on switching elements.

[0244] Control terminal T12 is the terminal to which the control signal IH4 is input from the outside. The control signal IH4 is a signal used to control the operation of the QN-off drive circuit 101. The control signal IH4 is, for example, a signal at the "H" level or a signal at the "L" level.

[0245] Control terminal T13 is the terminal to which the control signal IL4 is input from the outside. The control signal IL4 is a signal used to control the operation of the QN-off drive circuit 102. The control signal IL4 is, for example, a "H" level signal or a "L" level signal.

[0246] The QN-off drive circuit 101 is a circuit that drives the switching element 103. The QN-off drive circuit 101 is connected to the control terminal T12 and the switching element 103. The QN-off drive circuit 101 turns the switching element 103 on or off based on the control signal IH4.

[0247] The QN-off drive circuit 102 is a circuit that drives the switching element 104. The QN-off drive circuit 102 is connected to the control terminal T13 and the switching element 104. The QN-off drive circuit 102 turns the switching element 104 on or off based on the control signal IL4.

[0248] Drive circuit 61 operates in the same manner as drive circuit 11. Drive circuit 62 operates in the same manner as drive circuit 12. QN-off drive circuit 101 operates in the same manner as QN-off drive circuit 91. QN-off drive circuit 102 operates in the same manner as QN-off drive circuit 92. Therefore, when the power supply is in an unpredictable state, the switching elements on the high side of switching elements 63 and 103, and the switching elements on the low side of switching elements 64 and 104, are both in the off state. On the other hand, when the power supply is in a stable state, the switching elements on the high side of switching elements 63 and 103 and the switching elements on the low side of switching elements 64 and 104 are alternately in the on or off state.

[0249] Control signal IH2 is the same as control signal IH1. Control signal IL2 is the same as control signal IL1. Therefore, drive circuit 61 operates synchronously with drive circuit 11. Drive circuit 62 operates synchronously with drive circuit 12.

[0250] Control signal IH4 is the same as control signal IH3. Control signal IL4 is the same as control signal IL3. Therefore, QN-off drive circuit 101 operates synchronously with QN-off drive circuit 91. QN-off drive circuit 102 operates synchronously with QN-off drive circuit 92.

[0251] Switching element 103 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 103 is connected to QN-off drive circuit 101. The second terminal of switching element 103 is connected to node N9. The third terminal of switching element 103 is connected to node N4. Switching element 104 has a first terminal, a second terminal, and a third terminal. The first terminal of switching element 104 is connected to QN-off drive circuit 102. The second terminal of switching element 104 is connected to node N10. The third terminal of switching element 104 is connected to node N6. Switching elements 103 and 104 include at least one of, for example, an n-channel MOSFET and a p-channel MOSFET. Furthermore, switching elements 103 and 104 are normally off switching elements.

[0252] Alternatively, in the semiconductor device 1C, the drive circuits 61 and 62, and the control terminals T6 and T7 may not be included, and the drive circuits 11 and 12, and the control terminals T1 and T2 may be shared in the same manner as in the second embodiment. Furthermore, in the semiconductor device 1C, the QN-off drive circuits 101 and 102, and the control terminals T12 and T13 may not be included, and the QN-off drive circuits 91 and 92, and the control terminals T10 and T11 may be shared. In this case, the control electrode of the switching element 103 is connected to the QN-off drive circuit 91. The control electrode of the switching element 104 is connected to the QN-off drive circuit 92.

[0253] Below, as an example, we will explain the case where switching elements 13, 14, 63, and 64 are n-channel MOSFETs, and switching elements 93, 94, 103, and 104 are p-channel MOSFETs.

[0254] Figure 27 This is a circuit diagram illustrating an example of the structure of each switching element in a semiconductor device 1C.

[0255] like Figure 27 As shown, switching element 63 is transistor TR3. Switching element 64 is transistor TR4. Transistors TR3 and TR4 are n-channel MOSFETs. Furthermore, transistors TR3 and TR4 are normally-on transistors.

[0256] The source electrode of switching element 63 is connected to node N9. The source electrode of switching element 64 is connected to node N10.

[0257] Switching element 103 is transistor TR7. Switching element 104 is transistor TR8. Transistors TR7 and TR8 are p-channel MOSFETs. Furthermore, transistors TR7 and TR8 are normally off transistors.

[0258] Switching elements 13, 14, 93, and 94 are the same as those shown in the third embodiment. Figure 22 same.

[0259] The gate electrode (control electrode) of switching element 103 is connected to QN-off drive circuit 101. The drain electrode of switching element 103 is connected to node N4. The source electrode of switching element 103 is connected to node N9. The gate electrode (control electrode) of switching element 104 is connected to QN-off drive circuit 102. The drain electrode of switching element 104 is connected to node N6. The source electrode of switching element 104 is connected to node N10.

[0260] The source electrode of switching element 63 and the source electrode of switching element 103 are connected in series. The drain electrode of switching element 103 and the drain electrode of switching element 64 are connected in series. The source electrode of switching element 64 and the source electrode of switching element 104 are connected in series.

[0261] 4.2 Structure of Semiconductor Devices

[0262] The structure of semiconductor device 1C will be described. Semiconductor device 1C has a structure that combines two semiconductor devices 1B. Figure 28 This is an example of a cross-sectional structure of the semiconductor device 1C, shown along the same path as in the first embodiment. Figure 4 A cross-sectional view of the same line as line II.

[0263] like Figure 28 As shown, in semiconductor device 1C, the structure to the left of the X-axis, with line AA as the boundary, has the same structure as semiconductor device 1B, while the structure to the right of the X-axis has the structure resulting from rotating semiconductor device 1B 180 degrees around line AA as the rotation axis. Switching element 103 corresponds to switching element 93. Switching element 104 corresponds to switching element 94.

[0264] A switching element 103 is disposed above wiring layer 29. The drain electrode (not shown) of switching element 103 is connected to wiring layer 29 via a plurality of vias 41. A switching element 63 is disposed above switching element 103. The source electrode (not shown) of switching element 103 is connected to the source electrode SE3 of switching element 63 via a plurality of vias 41. The drain electrode of switching element 103 is disposed, for example, on the surface of switching element 103 (the surface opposite wiring layer 29 in the Z direction). The source electrode of switching element 103 is disposed, for example, on the surface of switching element 103 (the surface opposite the source electrode SE3 of switching element 63 in the Z direction).

[0265] A switching element 104 is disposed below the wiring layer 74. The drain electrode (not shown) of the switching element 104 is connected to the wiring layer 74 via a plurality of vias 41. A switching element 64 is disposed below the switching element 104. The source electrode (not shown) of the switching element 104 is connected to the source electrode SE4 of the switching element 64 via a plurality of vias 41. The drain electrode of the switching element 104 is disposed, for example, on the surface of the switching element 104 (the surface opposite the wiring layer 74 in the Z direction). The source electrode of the switching element 104 is disposed, for example, on the surface of the switching element 104 (the surface opposite the source electrode SE4 of the switching element 64 in the Z direction).

[0266] Figure 29 This is an example of a cross-sectional structure representing a semiconductor device 1C, along with... Figure 4 A cross-sectional view of the same line as line II-II.

[0267] like Figure 29 As shown, in semiconductor device 1C, along with... Figure 4 The cross-sectional structure of the same line as line II-II is defined by line AA, and differs between the structure on the left side of the X-axis and the structure on the right side of the X-axis.

[0268] A gate electrode GE3 is provided on the front side of the switching element 63. A gate electrode GE4 is provided on the front side of the switching element 64.

[0269] Figure 30 This is a diagram showing the high-frequency current path of a semiconductor device IC and the magnetic flux generated by the high-frequency current.

[0270] like Figure 30 As shown, the high-frequency current path of the semiconductor device 1C includes the features shown in the third embodiment. Figure 25 The path (hereinafter, marked as "Third Path RT3").

[0271] Furthermore, the semiconductor device 1C includes a path (hereinafter referred to as "fourth path RT4") from wiring layer 75 through via 41 above wiring layer 75, drain electrode DE3, via 41 below source electrode SE3, switching element 103, via 41 below switching element 103, wiring layer 29, via 41 below wiring layer 29, wiring layer 28, via 41 below wiring layer 28, drain electrode DE4, source electrode SE4, via 41 above source electrode SE4, switching element 104, and via 41 above switching element 104, all the way to wiring layer 74.

[0272] Due to the aforementioned structure, in this embodiment, the high-frequency current paths in the third path RT3 and the fourth path RT4 are shortened, similar to the first embodiment. Therefore, the parasitic inductance of the loop formed by capacitor 15 and switching elements 13, 14, 93, and 94 can be reduced. The parasitic inductance of the loop formed by capacitor 65 and switching elements 63, 64, 103, and 104 can also be reduced. Thus, according to this embodiment, the same effects as the first embodiment are achieved.

[0273] In addition, such as Figure 30 As shown, in this embodiment, the direction of the magnetic flux Φ3 generated by the high-frequency current flowing through the third path RT3 (from the front of the paper towards the depth) is opposite to the direction of the magnetic flux Φ4 generated by the high-frequency current flowing through the fourth path RT4 (from the depth of the paper towards the front). Therefore, the magnetic fluxes generated in the two paths RT3 and RT4 respectively cancel each other out. Thus, noise emitted to the outside due to the generation of magnetic flux can be suppressed. Therefore, according to this embodiment, the same effect as the second embodiment is achieved.

[0274] 5. Variations, etc.

[0275] As described above, the semiconductor device (1) of the embodiment includes: a first switching element (13) having a first electrode (DE1) and a second electrode (SE1) disposed on the front side (S1); a second switching element (14) having a third electrode (SE2) and a fourth electrode (DE2) disposed on the front side (S3); a first capacitor (15) including a first wiring layer (25) connected to the third electrode (SE2), a second wiring layer (26) connected to the first electrode (DE1), and a first bulk dielectric layer (51) disposed between the first wiring layer and the second wiring layer; and a substrate (20) having the first switching element (13) embedded therein. The circuit comprises a first switching element (13), a second switching element (14), and a first capacitor (15); a third wiring layer (22(T5)) connected to the first wiring layer (25) and subjected to a first voltage (VDC-); a fourth wiring layer (21(T4)) connected to the second wiring layer (26) and subjected to a second voltage (VDC+) higher than the first voltage (VDC-); and a fifth wiring layer (23(T3)) connected to the second electrode (SE1) and the fourth electrode (DE2) and subjected to a third voltage (VSW) in a range above the first voltage (VDC-) and below the second voltage (VDC+). The first capacitor (15) is disposed between the first switching element (13) and the second switching element (14). The third electrode (SE2) is disposed opposite to the first electrode (DE1) in the first direction (Z). The fourth electrode (DE2) is disposed opposite to the second electrode (SE1) in the first direction (Z) and is connected in series with the second electrode (SE1).

[0276] Furthermore, the implementation method is not limited to the method described above, and various modifications can be made.

[0277] In this specification, "connection" means electrical connection, which does not exclude the presence of other components between them.

[0278] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

[0279] [Explanation of Labels in the Attached Image]

[0280] 1, 1A, 1B, 1C… Semiconductor devices, 11, 12… Drive circuits, 13, 14… Switching elements, 15… Capacitors, 20… Substrate, 21-30… Wiring layers, 41… Through-holes, 51… Dielectric layers, 61, 62… Drive circuits, 63, 64… Switching elements, 65… Capacitors, 71-76… Wiring layers, 81… Dielectric layers, 91, 92… QN-off drive circuits, 93, 94… Switching elements, 101, 102… QN-off drive circuits, 103, 104… Switching elements, T1, T2, T6, T7, T10, T11, T12, T13… Control terminals, T3, T4, T5, T8, T9… Input / output terminals.

Claims

1. A semiconductor device comprising: The first switching element has a first electrode and a second electrode disposed on its front side; The second switching element has a third electrode and a fourth electrode on its front side; The first capacitor includes a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer disposed between the first wiring layer and the second wiring layer. The substrate has the first switching element, the second switching element, and the first capacitor built into it; The third wiring layer is connected to the first wiring layer and is subjected to a first voltage; The fourth wiring layer, connected to the second wiring layer, is subjected to a second voltage that is higher than the first voltage; as well as The fifth wiring layer, connected to the second electrode and the fourth electrode, is subjected to a third voltage ranging from above the first voltage to below the second voltage. The first capacitor is disposed between the first switching element and the second switching element. The third electrode is configured opposite to the first electrode in the first direction. The fourth electrode is disposed opposite to the second electrode in the first direction and is connected in series with the second electrode.

2. The semiconductor device according to claim 1, wherein, The first electrode and the second electrode are arranged opposite each other in a second direction that intersects the first direction. The third electrode and the fourth electrode are arranged opposite each other in the second direction.

3. The semiconductor device according to claim 1, wherein, The thickness of the first dielectric layer is thinner than the thickness of the first switching element and thinner than the thickness of the second switching element.

4. The semiconductor device according to claim 1, wherein, The first dielectric layer comprises silicon or barium titanate.

5. The semiconductor device according to claim 1, wherein, The area of ​​the front side of the second wiring layer is larger than the area of ​​the front side of the first switching element. The area of ​​the front side of the first wiring layer is larger than the area of ​​the front side of the second switching element.

6. The semiconductor device according to claim 1, wherein, The second wiring layer protrudes along a second direction intersecting the first direction compared to the second switching element. The first wiring layer protrudes along the second direction compared to the first switching element.

7. The semiconductor device according to claim 1, wherein, It also includes a sixth wiring layer that connects to the second wiring layer and the fourth wiring layer. The back side of the first switching element is connected to the sixth wiring layer via at least one first through-hole. The back side of the second switching element is connected to the third wiring layer via at least one second through-hole.

8. The semiconductor device according to claim 1, wherein, It also has: The third switching element has a fifth electrode and a sixth electrode on its front side; The fourth switching element has a seventh electrode and an eighth electrode on its front side; The second capacitor includes a seventh wiring layer connected to the seventh electrode, an eighth wiring layer connected to the fifth electrode, and a second dielectric layer disposed between the seventh wiring layer and the eighth wiring layer; The ninth wiring layer, connected to the seventh wiring layer, is subjected to the first voltage; as well as The tenth wiring layer, connected to the eighth wiring layer, is subjected to the second voltage. The third switching element, the fourth switching element, and the second capacitor are embedded in the substrate. The fifth wiring layer is connected to the sixth electrode and the eighth electrode. The second capacitor is disposed between the third switching element and the fourth switching element. The seventh electrode is disposed opposite to the fifth electrode in the first direction. The eighth electrode is disposed opposite to the sixth electrode in the first direction and is connected in series with the sixth electrode.

9. The semiconductor device according to claim 8, wherein, The fifth electrode and the sixth electrode are arranged opposite each other in a second direction that intersects with the first direction. The seventh electrode and the eighth electrode are arranged opposite each other in the second direction.

10. The semiconductor device according to claim 1, wherein, The area of ​​the front side of the fifth wiring layer is smaller than the area of ​​the front side of the third wiring layer.

11. The semiconductor device according to claim 1, wherein, The first switching element and the second switching element include at least one of an n-channel MOSFET, a p-channel MOSFET, a GaN transistor, a SiC transistor, an IGBT (Insulated Gate Bipolar Transistor), and a JFET (Junction Field Effect Transistor).

12. A semiconductor device comprising: The first switching element has a first electrode and a second electrode disposed on its front side; The second switching element has a third electrode and a fourth electrode on its front side; The substrate has the first switching element and the second switching element built into it; The first wiring layer is connected to the third electrode and is subjected to a first voltage; The second wiring layer is connected to the first electrode and is subjected to a second voltage that is higher than the first voltage. as well as The third wiring layer, connected to the second electrode and the fourth electrode, is subjected to a third voltage ranging from above the first voltage to below the second voltage. The third electrode is configured opposite to the first electrode in a first direction. The fourth electrode is disposed opposite to the second electrode in the first direction and is connected in series with the second electrode.

13. The semiconductor device according to claim 12, wherein, The first electrode and the second electrode are arranged opposite each other in a second direction that intersects the first direction. The third electrode and the fourth electrode are arranged opposite each other in the second direction.

14. The semiconductor device according to claim 12, wherein, It also has: The third switching element has a fifth electrode and a sixth electrode on its front side; The fourth switching element has a seventh electrode and an eighth electrode on its front side; The fourth wiring layer, connected to the seventh electrode, is subjected to the first voltage; as well as The fifth wiring layer, connected to the fifth electrode, is subjected to the second voltage. The third and fourth switching elements are embedded in the substrate. The third wiring layer is connected to the sixth electrode and the eighth electrode. The seventh electrode is disposed opposite to the fifth electrode in the first direction. The eighth electrode is disposed opposite to the sixth electrode in the first direction and is connected in series with the sixth electrode.

15. The semiconductor device according to claim 14, wherein, The fifth electrode and the sixth electrode are arranged opposite each other in a second direction that intersects with the first direction. The seventh electrode and the eighth electrode are arranged opposite each other in the second direction.

16. A semiconductor device comprising: The switching element has a first electrode and a second electrode disposed on its front side; The second switching element has a third electrode and a fourth electrode on its front side; Third switching element; Fourth switching element; A first capacitor, connected to the fourth switching element, includes a first wiring layer connected to the third electrode via the fourth switching element, a second wiring layer connected to the first electrode, and a first dielectric layer disposed between the first wiring layer and the second wiring layer; The substrate has the first switching element, the second switching element, the third switching element, the fourth switching element and the first capacitor built into it; The third wiring layer is connected to the first wiring layer and is subjected to a first voltage; The fourth wiring layer, connected to the second wiring layer, is subjected to a second voltage that is higher than the first voltage; as well as The fifth wiring layer is connected to the third switching element and the fourth electrode, and is connected to the second electrode via the third switching element. A third voltage, ranging from above the first voltage to below the second voltage, is applied to it. The first capacitor is disposed between the first switching element and the second switching element. The third electrode is configured opposite to the first electrode in a first direction. The fourth electrode is disposed opposite to the second electrode in the first direction and is connected in series with the third switching element. The third switching element is disposed between the second electrode and the fourth electrode. The fourth switching element is disposed between the first electrode and the third electrode.

17. The semiconductor device according to claim 16, wherein, The first electrode and the second electrode are arranged opposite each other in a second direction that intersects the first direction. The third electrode and the fourth electrode are arranged opposite each other in the second direction.

18. The semiconductor device according to claim 16, wherein, It also has: The fifth switching element has a fifth electrode and a sixth electrode on its front side; The sixth switching element has a seventh electrode and an eighth electrode on its front side; The seventh switching element; Eighth switching element; The second capacitor, connected to the eighth switching element, includes a sixth wiring layer connected to the seventh electrode via the eighth switching element, a seventh wiring layer connected to the fifth electrode, and a second dielectric layer disposed between the sixth wiring layer and the seventh wiring layer; The eighth wiring layer, connected to the sixth wiring layer, is subjected to the first voltage; as well as The ninth wiring layer, connected to the seventh wiring layer, is subjected to the second voltage. The fifth switching element, the sixth switching element, the seventh switching element, the eighth switching element, and the second capacitor are embedded in the substrate. The fifth wiring layer is connected to the seventh switching element and the seventh electrode, and is also connected to the sixth electrode via the seventh switching element. The second capacitor is disposed between the fifth switching element and the sixth switching element. The seventh electrode is disposed opposite to the fifth electrode in the first direction. The eighth electrode is disposed opposite to the sixth electrode in the first direction and is connected in series with the seventh switching element. The seventh switching element is disposed between the sixth electrode and the eighth electrode; The eighth switching element is disposed between the fifth electrode and the seventh electrode.

19. The semiconductor device according to claim 18, wherein, The fifth electrode and the sixth electrode are arranged opposite each other in a second direction that intersects with the first direction. The seventh electrode and the eighth electrode are arranged opposite each other in the second direction.

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