Power balance optimization method and system for asymmetric cascaded H-bridge inverter

Abstract

The invention discloses a power balance optimization method and system for an asymmetric cascaded H-bridge inverter. The method comprises the following steps: acquiring a target switch state combination of the asymmetric cascaded H-bridge inverter; according to a preset total modulation signal, adopting a preset mixed carrier pulse width modulation strategy to recombine the signals, the signals, the signals, the signals, the signals and the square wave signals with the preset angular frequency in the target switch state combination, and obtaining a driving modulation signal of a switch device in each H-bridge unit in a period; and performing logical operation on the driving modulation signals of the switching devices and the square wave signals of the 1 / 2 output voltage fundamental wave period to obtain final driving signals of the switching devices in the asymmetric cascade H-bridge inverter. The power balancing speed can be improved, and the working safety and reliability of the inverter are effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of PWM modulation technology for asymmetric cascaded H-bridge multilevel inverters, and particularly relates to a power balancing optimization method and system for asymmetric cascaded H-bridge inverters. Background Technology

[0002] The inverter's topology and modulation strategy are key factors determining the output voltage waveform quality and performance. In the field of multilevel inverters, while diode-clamped inverters, flying capacitor inverters, and symmetrically cascaded H-bridge inverters each have their applications, they all have significant limitations. Diode-clamped inverters have complex topologies that are difficult to expand, and they suffer from significant DC bus capacitor voltage imbalance. Flying capacitor inverters require a large number of flying DC capacitors, resulting in voltage imbalance and the need for additional pre-charge circuits, increasing system complexity and cost. Symmetrically cascaded H-bridge inverters require numerous independent power supplies, increasing system size, weight, and cost. Compared to symmetrically cascaded H-bridge inverters, asymmetrically cascaded H-bridge inverters can achieve a higher number of output levels with fewer H-bridge units, improving output voltage waveform quality and reducing cost, thus gaining more attention. However, when using traditional hybrid modulation strategies, asymmetric cascaded H-bridge multilevel inverters suffer from problems such as power backflow, power imbalance, and uneven heating, which seriously affect the stability and reliability of inverter operation. In addition, the existing modulation strategies of asymmetric cascaded H-bridge multilevel inverters are complex and difficult to fully solve these problems. For example, they cannot solve the problems of power backflow and power balancing at the same time. Power balancing takes a long time and the modulation strategy is difficult to implement, which makes it difficult to meet the needs of practical applications. Summary of the Invention

[0003] This invention provides a power equalization optimization method and system for asymmetric cascaded H-bridge inverters, which solves the technical problems of long power equalization time and difficulty in implementing modulation strategies.

[0004] In a first aspect, the present invention provides a power balancing optimization method for an asymmetric cascaded H-bridge inverter, comprising: Obtain the target switching state combination of the asymmetric cascaded H-bridge inverter. The target switching state combination is the switching state combination with non-opposite polarity among the redundant switching state combinations of the asymmetric cascaded H-bridge inverter. The asymmetric cascaded H-bridge inverter contains H-bridge units. Based on the preset total modulation signal, a preset hybrid carrier pulse width modulation strategy is used to modulate the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle. The H-bridge unit includes low-voltage H-bridge units and high-voltage H-bridge units. The driving modulation signals of each switching device are combined with a square wave signal that has half the fundamental period of the output voltage. Logical operations are performed to obtain the final drive signals for the switching devices in the asymmetric cascaded H-bridge inverter.

[0005] Furthermore, the preset total modulation signal is used to apply a preset hybrid carrier pulse width modulation strategy to the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The reassembly yields the drive modulation signals for the switching devices in each H-bridge unit within one cycle, including: Acquire the first carrier signal Second carrier signal Third carrier signal Fourth carrier signal Fifth carrier signal and the sixth carrier signal The first carrier signal and the second carrier signal The frequency is Peak-to-peak value is 2, phase difference is 2 The third carrier signal is an isosceles triangular carrier distributed between 0 and 2. and the fourth carrier signal The frequency is The fifth carrier signal has a peak-to-peak value of 1 and isosceles triangular carriers distributed in opposite directions in the vertical direction between 2 and 4. and the sixth carrier signal The frequency is The peak-to-peak value is 1, and the isosceles triangular carriers are distributed in the same direction in the vertical direction between 4 and 6. According to the preset modulation system Determine the total modulation signal and the total modulation signal The signal is compared with the first carrier signal, the second carrier signal, the third carrier signal, the fourth carrier signal, the fifth carrier signal, and the sixth carrier signal, respectively. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. According to the signal The signal The signal The signal The signal The signal and the square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle.

[0006] Furthermore, the expression for the driving modulation signal is: , In the formula, This is the drive modulation signal for the first switching device in the first low-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the first low-voltage H-bridge unit. for Non-signals, This is the drive modulation signal for the third switching device in the first low-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the first low-voltage H-bridge unit. for Non-signal; , In the formula, This is the drive modulation signal for the first switching device in the second low-voltage H-bridge unit. For signal Non-signals, For signal Non-signals, This is the drive modulation signal for the second switching device in the second low-voltage H-bridge unit. for Non-signals, This is the drive modulation signal for the third switching device in the second low-voltage H-bridge unit. For signal Non-signals, Square wave signal Non-signals, This is the drive modulation signal for the fourth switching device in the second low-voltage H-bridge unit. for Non-signal; , In the formula, This is the drive modulation signal for the first switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the third switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the first high-voltage H-bridge unit. for Non-signal; , In the formula, This is the drive modulation signal for the first switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the third switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the second high-voltage H-bridge unit. for The non-signal.

[0007] Furthermore, the expression for the final driving signal is: , In the formula, This is the final drive signal for the first switching device in the first high-voltage H-bridge unit. This is the final drive signal for the second switching device in the first high-voltage H-bridge unit. This is the final drive signal for the third switching device in the first high-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the first high-voltage H-bridge unit. for Non-signals, for Non-signals, It is a square wave signal with a period of 1 / 2 of the fundamental period of the output voltage. for Non-signal; , In the formula, This is the final drive signal for the first switching device in the second high-voltage H-bridge unit. This is the final drive signal for the second switching device in the second high-voltage H-bridge unit. for Non-signals, This is the final drive signal for the third switching device in the second high-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the second high-voltage H-bridge unit. for Non-signal; , In the formula, This is the final drive signal for the first switching device in the first low-voltage H-bridge unit. This is the final drive signal for the second switching device in the first low-voltage H-bridge unit. for Non-signals, This is the final drive signal for the third switching device in the first low-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the first low-voltage H-bridge unit. This is the final drive signal for the third switching device in the first low-voltage H-bridge unit; , In the formula, This is the final drive signal for the first switching device in the second low-voltage H-bridge unit. This is the final drive signal for the second switching device in the second low-voltage H-bridge unit. This is the final drive signal for the third switching device in the second low-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the second low-voltage H-bridge unit. for Non-signals, for The non-signal.

[0008] Secondly, the present invention provides a power balancing optimization system for an asymmetric cascaded H-bridge inverter, comprising: The acquisition module is configured to acquire a target switching state combination of an asymmetric cascaded H-bridge inverter. The target switching state combination is a non-opposite polarity switching state combination among the redundant switching state combinations of the asymmetric cascaded H-bridge inverter, wherein the asymmetric cascaded H-bridge inverter contains H-bridge units. The reassembly module is configured to, based on a preset total modulation signal, employ a preset hybrid carrier pulse width modulation strategy to modulate the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle. The H-bridge unit includes low-voltage H-bridge units and high-voltage H-bridge units. The optimization module is configured to combine the driving modulation signals of each switching device with a square wave signal of 1 / 2 the fundamental period of the output voltage. Logical operations are performed to obtain the final drive signals for the switching devices in the asymmetric cascaded H-bridge inverter.

[0009] Thirdly, an electronic device is provided, comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the power balancing optimization method for an asymmetric cascaded H-bridge inverter according to any embodiment of the present invention.

[0010] Fourthly, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein when the program instructions are executed by a processor, the processor performs the steps of the power balancing optimization method for an asymmetric cascaded H-bridge inverter according to any embodiment of the present invention.

[0011] The power balancing optimization method and system for asymmetrical cascaded H-bridge inverters disclosed in this application uses 1 / 4 of the fundamental frequency cycle as a reference. It cyclically distributes the drive signals of the switching devices among H-bridge units of the same voltage level so that the output voltage waveform of one H-bridge unit is symmetrical with the output voltage waveform of another H-bridge unit of the same voltage level about 1 / 4 of the fundamental frequency cycle. This balances the power among H-bridge units of the same voltage level within half a fundamental frequency cycle, improves the power balancing speed, and effectively enhances the safety and reliability of the inverter operation. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart of a power balancing optimization method for an asymmetric cascaded H-bridge inverter provided in an embodiment of the present invention; Figure 2 This is a topology diagram of an asymmetric cascaded H-bridge inverter provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a conventional hybrid modulation strategy for an asymmetric cascaded H-bridge inverter according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a hybrid carrier pulse width modulation strategy provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of power equalization under a hybrid carrier pulse width modulation strategy provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of an equalization optimization method under a hybrid carrier pulse width modulation strategy provided in an embodiment of the present invention. Figure 7 The voltage waveforms output by each H-bridge unit under a conventional hybrid modulation strategy provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the voltage waveforms output by each H-bridge unit under a hybrid carrier pulse width modulation strategy, provided in an embodiment of the present invention. Figure 9 This is a waveform diagram of the output power of each H-bridge unit under a conventional hybrid modulation strategy provided in an embodiment of the present invention; Figure 10 The present invention provides an embodiment of the output power waveform diagram of each H-bridge unit under a hybrid carrier pulse width modulation strategy; Figure 11 This is a spectrum diagram of the output voltage provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the output waveforms of each H-bridge unit under a hybrid carrier pulse width modulation strategy after power equalization optimization, provided in an embodiment of the present invention. Figure 13 This is a schematic diagram of the output waveforms of each H-bridge unit under a hybrid carrier pulse width modulation strategy after power equalization optimization, provided in an embodiment of the present invention. Figure 14 A schematic diagram of the waveform and spectrum of the inverter output voltage under a hybrid carrier pulse width modulation strategy after power equalization optimization, provided as an embodiment of the present invention. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] like Figure 1 As shown, the power balancing optimization method for asymmetric cascaded H-bridge inverters specifically includes the following steps: Step S101 obtains the target switching state combination of the asymmetric cascaded H-bridge inverter. The target switching state combination is the switching state combination with non-opposite polarity among the redundant switching state combinations of the asymmetric cascaded H-bridge inverter.

[0016] In this step, the topology of the asymmetric cascaded H-bridge inverter is as follows: Figure 2 As shown, this topology consists of two low-voltage H-bridge units and two high-voltage H-bridge units cascaded together. The low-voltage H-bridge units are... This indicates that its DC source voltage is E. and represent The four switching devices in it, and They are respectively and The driving modulation signal; used by the high-voltage H-bridge unit This indicates that its DC source voltage is 2E. and represent The four switching devices in it, and They are respectively and The driving signal. and These are the output voltages of the first low-voltage H-bridge unit H1 and the second low-voltage H-bridge unit H2, respectively. and The output voltages of L1 and L2 are respectively. This is the output voltage of the inverter, determined by... Figure 2 It can be seen that they satisfy the following: (1) but, (2) Define high-voltage H-bridge unit The switching state function is Its value is: (3) Correspondingly, the high-voltage H-bridge unit outputs three voltage levels: 2E, 0, and -2E.

[0017] Define low-voltage H-bridge unit The switching state function is Its value is: (4) but, (5) Correspondingly, the low-voltage H-bridge unit outputs three voltage levels: E, 0, and -E.

[0018] Combining equations (1), (3), and (5), it can be seen that... It can be represented as: (6) According to the knowledge of permutations and combinations, a four-unit, thirteen-level asymmetrical cascaded H-bridge inverter has a total of A total of 13 output levels were obtained from various switching state combinations: ±6E, ±5E, ±4E, ±3E, ±2E, ±E, and 0. Among these 81 switching state combinations, some have opposite polarities. As shown in equations (3), (5), and (6), opposite polarity switching state combinations mean that the output voltages of the H-bridges in the synthesized inverter have opposite polarities, which can cause power backflow. Therefore, it is necessary to select 31 switching state combinations with non-opposite polarities to ensure that the output voltages of the H-bridges in the synthesized inverter have non-opposite polarities, thereby solving the power backflow problem. Inverter output voltage The relationship between the thirteen combinations of switching states with different levels and polarities is shown in Table 1.

[0019] Table 1. Relationship between inverter output voltage level and switching state combinations with non-opposite polarity. , For example, when the inverter output voltage level is When the switching state is 1, the switching state value output by the first low-voltage H-bridge unit is 0, the switching state value output by the first high-voltage H-bridge unit is 1, and the switching state value output by the second high-voltage H-bridge unit is 1; and the switching state value output by the first low-voltage H-bridge unit is 0, the switching state value output by the second low-voltage H-bridge unit is 1, the switching state value output by the first high-voltage H-bridge unit is 1, and the switching state value output by the second high-voltage H-bridge unit is 1.

[0020] As shown in Table 1 and equations (3) and (5), the polarity of the output voltage of each H-bridge unit remains non-isolated during the positive and negative half-cycles, that is, when the inverter output voltage... When positive, the output voltage of each H-bridge unit is positive or zero; when inverted, its output voltage... When the value is negative, the output voltage of each H-bridge unit is negative or zero, thus effectively avoiding power backflow and ensuring the inverter's excellent output voltage harmonic characteristics.

[0021] Step S102: Based on the preset total modulation signal, a preset hybrid carrier pulse width modulation strategy is used to modulate the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle.

[0022] Figure 3 This is a schematic diagram of the traditional hybrid modulation strategy for an asymmetric cascaded H-bridge inverter. The two high-voltage H-bridge units use stepped wave modulation, while the two low-voltage H-bridge units use carrier amplitude shift modulation.

[0023] Depend on Figure 3 It can be seen that during the positive half-cycle, when the inverter's output is at level E, the output voltage polarity of the low-voltage H-bridge unit L1 is opposite to that of the high-voltage H-bridge unit H1; when the inverter's output is at level 3E, the output voltage polarity of the low-voltage H-bridge unit L1 is opposite to that of the high-voltage H-bridge units H1 and H2. A similar phenomenon exists during the negative half-cycle. This indicates that in these regions, the low-voltage H-bridge unit L1 will absorb power from the high-voltage H-bridge units H1 or H2, i.e., power backflow occurs. This phenomenon causes voltage fluctuations on the DC side of the low-voltage H-bridge unit L1, making the output voltage of the H-bridge unit L1 unstable and distorting the inverter's output voltage waveform.

[0024] Further analysis revealed that the output voltage waveforms of H-bridge units H1 and H2 or L1 and L2 at the same voltage level differed significantly, i.e. , Furthermore, each H-bridge unit is cascaded, meaning the current flowing through each unit is equal. As can be seen from the average output power shown in equation (7), the output power among each H-bridge unit is unbalanced.

[0025] (7) In the formula, The average power output of the H-bridge unit. This represents the instantaneous value of the output voltage of the H-bridge unit. This represents the instantaneous value of the inverter's output current. , This is the fundamental frequency period.

[0026] The fundamental reason for power imbalance lies in the different conduction times of the switching devices in each H-bridge unit. These different conduction times lead to variations in the losses of the switching devices, resulting in different heat generation and temperature rise, which in turn affects the inverter's lifespan and increases additional operation and maintenance costs. Therefore, power backflow and power imbalance are significant factors hindering the widespread application of traditional hybrid modulation strategies.

[0027] To address the limitations of traditional hybrid modulation strategies and minimize carrier requirements to simplify implementation, this invention proposes an improved hybrid carrier pulse width modulation strategy. Its modulation principle is as follows: Figure 4 As shown.

[0028] exist Figure 4 middle, The total modulation signal is obtained by taking the absolute value of a standard sine wave signal. The first carrier signal... and the second carrier signal The frequency is Peak-to-peak value is 2, phase difference is 2 The third carrier signal is an isosceles triangular carrier distributed between 0 and 2. and the fourth carrier signal The frequency is The fifth carrier signal has a peak-to-peak value of 1 and isosceles triangular carriers distributed in opposite directions in the vertical direction between 2 and 4. and the sixth carrier signal The frequency is The peak-to-peak value is 1, and the isosceles triangular carriers are distributed in the same direction in the vertical direction between 4 and 6.

[0029] Assumption For modulation schemes, the total modulation signal is... It can be represented as: (8) Under the hybrid carrier pulse width modulation strategy, the H-bridge switching state function combination corresponding to the rising phase of the inverter output voltage during the first quarter of the positive half-cycle is as follows: This can be described as: [0, 0, 0, 0] → [1, 0, 0, 0] → [1, 1, 0, 0] → [1, 0, 1, 0] → [1, 1, 1, 0] → [0, 1, 1, 1] → [1, 1, 1, 1]. The reverse process corresponds to the level falling phase. The level falling phase in the first 1 / 4 of the negative half-cycle is: [0, 0, 0, 0] → [0, -1, 0, 0] → [-1, -1, 0, 0] → [0, -1, 0, -1] → [-1, -1, 0, -1] → [-1, -1, -1, -1]. The reverse process corresponds to the level rising phase.

[0030] The specific modulation method is as follows: When ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. For example, signals It is by and The signal obtained by the comparator, when Greater than or equal to hour, High level 1; when Less than hour, The level is low (0). Other signals are similar. Based on the stated signal... The signal The signal The signal The signal The signal and the square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle, i.e.: (9) In the formula, This is the drive modulation signal for the first switching device in the first low-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the first low-voltage H-bridge unit. for Non-signals, This is the drive modulation signal for the third switching device in the first low-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the first low-voltage H-bridge unit. for Non-signal; (10) In the formula, This is the drive modulation signal for the first switching device in the second low-voltage H-bridge unit. For signal Non-signals, For signal Non-signals, This is the drive modulation signal for the second switching device in the second low-voltage H-bridge unit. for Non-signals, This is the drive modulation signal for the third switching device in the second low-voltage H-bridge unit. For signal Non-signals, Square wave signal Non-signals, This is the drive modulation signal for the fourth switching device in the second low-voltage H-bridge unit. for Non-signal; (11) In the formula, This is the drive modulation signal for the first switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the third switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the first high-voltage H-bridge unit. for Non-signal; (12) In the formula, This is the drive modulation signal for the first switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the third switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the second high-voltage H-bridge unit. for The non-signal.

[0031] Depend on Figure 4 It can be seen that under the hybrid carrier pulse width modulation strategy, the output voltage polarities of the two high-voltage H-bridge units and the two low-voltage H-bridge units remain non-opposite during the positive and negative half-cycles of the inverter's output voltage, thus overcoming the power backflow phenomenon present in the traditional hybrid modulation strategy.

[0032] The following analysis addresses the power balancing mechanism among units of the same voltage level under a hybrid carrier pulse width modulation strategy.

[0033] For ease of explanation, the voltage waveform obtained by the hybrid carrier pulse width modulation strategy is divided into positive and negative half-cycles. For example... Figure 5 As shown, the output voltages of units H1 and H2 are respectively represented by... Indicated; the output voltages of units L1 and L2 are respectively represented by express.

[0034] The average output power of the cascaded H-bridge unit within a single fundamental cycle of the inverter is expressed by equation (13): , (13) In the formula, This represents the average power output of the high-voltage H-bridge unit. The average power output of the low-voltage H-bridge unit. This represents the instantaneous value of the output voltage during the positive half-cycle of the high-voltage H-bridge unit. This represents the instantaneous value of the output voltage during the positive half-cycle of the low-voltage H-bridge unit. This represents the instantaneous value of the output voltage during the negative half-cycle of the high-voltage H-bridge unit. This is the instantaneous value of the negative half-cycle of the output voltage of the low-voltage H-bridge unit; Because of the level combination method used in the hybrid carrier pulse width modulation strategy, the first half of the output voltage waveform of the H-bridge unit is the same as the second half of the output voltage waveform of another H-bridge unit of the same voltage level, only opposite in polarity. Therefore: (14) In the formula, This represents the average power output during the positive half-cycle of the first high-voltage H unit. This represents the average power output during the negative half-cycle of the first high-voltage H unit. This represents the average power output during the negative half-cycle of the second high-voltage H unit. This represents the average power output during the positive half-cycle of the first high-voltage H unit; (15) In the formula, This represents the average power output during the positive half-cycle of the first low-voltage H unit. This represents the average power output during the negative half-cycle of the first low-voltage H unit. This represents the average power output during the negative half-cycle of the second low-voltage H unit. This represents the average power output during the positive half-cycle of the second low-voltage H unit; Combining equation (14) and equation (15), we get: , Therefore, the hybrid carrier pulse width modulation strategy enables two H-bridge units at the same voltage level to achieve automatic output power balance within one fundamental cycle.

[0035] Step S103: Mix the driving modulation signals of each switching device with a square wave signal of 1 / 2 the fundamental period of the output voltage. Logical operations are performed to obtain the final drive signals for the switching devices in the asymmetric cascaded H-bridge inverter.

[0036] like Figure 6 As shown. Among them, It is a square wave signal with a period of 1 / 2 of the fundamental period of the output voltage. The switching device drive signals of each H-bridge unit obtained from equations (9) to (12) are then compared with... Logical operations are performed to obtain new drive signals for the switching devices, as shown in equations (14) to (17). Essentially, this involves exchanging the drive signals of the switching devices in units H1 and H2, and units L1 and L2, located in intervals 2 (1 / 4 of the fundamental period) and 4 (1 / 4 of the fundamental period). Specifically: (16) In the formula, This is the final drive signal for the first switching device in the first high-voltage H-bridge unit. This is the final drive signal for the second switching device in the first high-voltage H-bridge unit. This is the final drive signal for the third switching device in the first high-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the first high-voltage H-bridge unit. for Non-signals, for Non-signals, It is a square wave signal with a period of 1 / 2 of the fundamental period of the output voltage. for Non-signal; (17) In the formula, This is the final drive signal for the first switching device in the second high-voltage H-bridge unit. This is the final drive signal for the second switching device in the second high-voltage H-bridge unit. for Non-signals, This is the final drive signal for the third switching device in the second high-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the second high-voltage H-bridge unit. for Non-signal; (18) In the formula, This is the final drive signal for the first switching device in the first low-voltage H-bridge unit. This is the final drive signal for the second switching device in the first low-voltage H-bridge unit. for Non-signals, This is the final drive signal for the third switching device in the first low-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the first low-voltage H-bridge unit. This is the final drive signal for the third switching device in the first low-voltage H-bridge unit; (19) In the formula, This is the final drive signal for the first switching device in the second low-voltage H-bridge unit. This is the final drive signal for the second switching device in the second low-voltage H-bridge unit. This is the final drive signal for the third switching device in the second low-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the second low-voltage H-bridge unit. for Non-signals, for The non-signal.

[0037] To verify the accuracy and feasibility of the improved hybrid carrier pulse width modulation strategy and its power equalization optimization method, a simulation model of a thirteen-level asymmetric cascaded H-bridge inverter with a voltage ratio of 2:2:1:1 was built using MATLAB 2018b / Simulink. The simulation parameters are shown in Table 2.

[0038] Table 2 Simulation Parameters , Figure 7 and Figure 8 The modulation schemes of the asymmetric cascaded H-bridge inverters are as follows: When the values ​​are 0.75, 0.85, and 0.95, the output voltages of H-bridge units H1, H2, L1, and L2 before and after optimization using the traditional hybrid modulation strategy and the improved hybrid carrier pulse width modulation strategy are compared. , and the inverter's output voltage The waveform.

[0039] Depend on Figure 7 It can be seen that when the traditional hybrid modulation strategy is adopted, the output voltages of the high-voltage H-bridge units H1 and H2 are... The waveform remains a rectangular wave with positive and negative symmetry, and its width increases with increasing modulation depth. For the low-voltage H-bridge unit L2, even at higher modulation depths... At that time, there was no voltage output. Moreover, regardless of the modulation scheme... With values ​​of 0.75, 0.85, or 0.95, the low-voltage H-bridge unit L1 exhibits an output voltage with opposite polarity, leading to power backflow. Furthermore, the waveform differences in the output voltage between H-bridge units H1 and H2, as well as between L1 and L2, are significant, indicating substantial differences in the conduction duration of the switching devices. This results in unbalanced output power, and the uneven heating of the switching devices due to the varying conduction durations further impacts the inverter's lifespan.

[0040] like Figure 8 As shown in section (a), under the unoptimized hybrid carrier pulse width modulation strategy, the high-voltage H-bridge units H1 and H2 output low-frequency PWM waves. With increasing modulation intensities, the pulse width of the PWM wave in the middle portion gradually increases. H-bridge units H1, H2, L1, and L2 consistently participate in the inverter voltage output, and the low-voltage H-bridge units L1 and L2 do not exhibit opposite polarity output voltages; the output voltage polarity of each H-bridge unit remains non-opposite. Figure 8 As shown in section (b), under the optimized hybrid carrier pulse width modulation strategy, in addition to retaining the characteristics before optimization, the output voltage waveforms of the high-voltage H-bridge units H1 and H2 and the low-voltage H-bridge units L1 and L2 are also symmetrical about 1 / 4 of the fundamental period. The optimized inverter output voltage... The waveform and the inverter output voltage before optimization The waveform remains the same.

[0041] The instantaneous output power of each H-bridge unit H1, H2, L1, and L2 in an asymmetric cascaded H-bridge inverter under traditional hybrid modulation strategy and hybrid carrier pulse width modulation strategy are as follows: Figure 9 and Figure 10 As shown.

[0042] from Figure 9 It can be seen that under the traditional hybrid modulation strategy, the low-voltage H-bridge unit L1 has a modulation index of The instantaneous output power at values ​​of 0.75, 0.85, and 0.95 all have portions below the horizontal axis, meaning the output power is negative, indicating power absorption or power backflow. Furthermore, there are significant differences in output power between high-voltage H-bridge units and between low-voltage H-bridge units, indicating power imbalance. Figure 10 As can be seen at point (a), under the hybrid carrier pulse width modulation strategy, regardless of whether the modulation index is 0.75, 0.85, or 0.95, and regardless of whether it is before or after optimization, the instantaneous output power of all H-bridge units is above the horizontal axis, that is, the output power is positive, meaning there is no power backflow. Furthermore, the average output power between high-voltage H-bridge units and between low-voltage H-bridge units is basically equal, i.e., power balance. From... Figure 10 As can also be seen in section (b), after the optimization method is adopted, regardless of whether the modulation index is 0.75, 0.85, or 0.95, the instantaneous output power waveform of the H-bridge unit at the same voltage level is similar to that of the MHC-PWM modulation strategy. The left and right sides are symmetrical, and the average output power is almost the same within half a fundamental frequency cycle. This shows that the optimized scheme can balance the power between H1 and H2, as well as between L1 and L2, within half a fundamental frequency cycle. Furthermore, in =0.85 and When the modulation index is higher, such as 0.95, the ratio of the average output power of H-bridge units with different voltage levels is approximately the ratio of the DC side voltage, thereby achieving power balance between high and low voltage H-bridge units.

[0043] Since the optimization only changes the output voltage waveform of each H-bridge unit, while the inverter output voltage waveform remains unaffected, the THD is the same before and after optimization. Figure 11 Inverter output voltage The spectrum diagrams are shown, where (a) is the inverter output voltage spectrum under the traditional hybrid modulation strategy and (b) is the inverter output voltage spectrum under the MHC-PWM modulation strategy.

[0044] Depend on Figure 11 It can be seen that regardless of whether the traditional hybrid modulation strategy or the hybrid carrier pulse width modulation strategy is used, the inverter output voltage The fundamental frequency amplitude is positively linearly correlated with the modulation index, while THD is negatively linearly correlated with the modulation index. Inverter output voltage under both strategies... The THDs are very close, but the hybrid carrier pulse width modulation strategy not only solves the power backflow problem compared with the traditional hybrid modulation strategy, but also balances the power between H-bridge units of the same voltage level.

[0045] To further verify the feasibility of the hybrid carrier pulse width modulation strategy and its power equalization optimization method proposed in this invention, an experimental platform for a four-unit 2:2:1:1 type thirteen-level asymmetric cascaded H-bridge inverter was built, and its real-time control was achieved using DSP+FPGA. The experimental parameters are shown in Table 3.

[0046] Table 3 ACHB Platform Parameters

[0047] Figure 12 , Figure 13 The optimized hybrid carrier pulse width modulation strategy is presented separately. The waveforms of output voltage, output current, and output power of the four H-bridge units are shown at modulation depths of 0.95 and 0.75. Comparing the waveforms of H-bridge units of the same voltage level at the same modulation depth, it can be seen that the output voltage waveforms of H1 and H2 are symmetrical about 1 / 4 of the fundamental period, and the output voltage waveforms of L1 and L2 are also symmetrical about 1 / 4 of the fundamental period. When = 0.95, the average output power of the two high-voltage H-bridge units are respectively , The average output power of the two low-voltage H-bridge units are respectively , .when When = 0.75, the average output power of the two high-voltage H-bridge units are respectively , The average output power of the two low-voltage H-bridge units are respectively , It is evident that the optimized hybrid carrier pulse width modulation strategy not only solves the power backflow problem, but also achieves power balance among H-bridge units of the same voltage level within 1 / 2 of the fundamental frequency period. Furthermore, it can balance the power between high- and low-voltage H-bridge units under high modulation schemes.

[0048] Figure 14 For a 13-level asymmetric cascaded H-bridge inverter with modulation The inverter output voltage and its spectrum obtained under the optimized MHC-PWM strategy when the voltage is 0.95 and 0.75. Figure 14 It can be seen that when the modulation index increases from 0.75 to 0.95, the inverter output voltage... The voltage level changes from 11 to 13, and its harmonics are mainly concentrated in... 1 / 2 The results are consistent with the simulation results.

[0049] In summary, the method of this application firstly selects non-opposite polarity switching state combinations from the redundant switching state combinations of the inverter, thereby ensuring that the polarity of each H-bridge output voltage in the synthesized inverter output voltage is non-opposite, thus solving the power backflow problem and ensuring the inverter's excellent output voltage harmonic characteristics. Secondly, through logic operations, the drive signals of the H-bridge unit switching devices are recombined so that the first half-cycle of the output voltage waveform of one H-bridge unit is the same as the second half-cycle of the output voltage waveform of another H-bridge unit of the same voltage level, thereby balancing the power among H-bridge units of the same voltage level within one fundamental cycle. However, the output voltage waveform of the same H-bridge can still have significant differences between the positive and negative half-waves, resulting in different output power and inconsistent switching device losses, which can seriously affect the service life of the inverter. Therefore, a corresponding optimization scheme was proposed. Based on 1 / 4 of the fundamental frequency period, the drive signals of the switching devices are cyclically distributed among H-bridge units of the same voltage level so that the output voltage waveform of one H-bridge unit is symmetrical with the output voltage waveform of another H-bridge unit of the same voltage level about 1 / 4 of the fundamental frequency period. In this way, the power between H-bridge units of the same voltage level is balanced within half of the fundamental frequency period, thereby improving the power balancing speed and effectively improving the safety and reliability of the inverter operation.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power balancing optimization method for an asymmetric cascaded H-bridge inverter, characterized in that, include: Obtain the target switching state combination of the asymmetric cascaded H-bridge inverter. The target switching state combination is the switching state combination with non-opposite polarity among the redundant switching state combinations of the asymmetric cascaded H-bridge inverter. The asymmetric cascaded H-bridge inverter contains H-bridge units. Based on the preset total modulation signal, a preset hybrid carrier pulse width modulation strategy is used to modulate the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle. The H-bridge unit includes low-voltage H-bridge units and high-voltage H-bridge units. The fundamental frequency period; The driving modulation signals of each switching device are combined with a square wave signal that has half the fundamental period of the output voltage. Logical operations are performed to obtain the final drive signals for the switching devices in the asymmetric cascaded H-bridge inverter.

2. The power balancing optimization method for an asymmetric cascaded H-bridge inverter according to claim 1, characterized in that, The asymmetric cascaded H-bridge inverter is an inverter formed by cascading a first low-voltage H-bridge unit, a second low-voltage H-bridge unit, a first high-voltage H-bridge unit, and a second high-voltage H-bridge unit.

3. The power balancing optimization method for an asymmetric cascaded H-bridge inverter according to claim 1, characterized in that, The preset total modulation signal is used to apply a preset hybrid carrier pulse width modulation strategy to the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The reassembly yields the drive modulation signals for the switching devices in each H-bridge unit within one cycle, including: Acquire the first carrier signal Second carrier signal Third carrier signal Fourth carrier signal Fifth carrier signal and the sixth carrier signal The first carrier signal and the second carrier signal The frequency is Peak-to-peak value is 2, phase difference is 2 The third carrier signal is an isosceles triangular carrier distributed between 0 and 2. and the fourth carrier signal The frequency is The fifth carrier signal has a peak-to-peak value of 1 and isosceles triangular carriers distributed in opposite directions in the vertical direction between 2 and 4. and the sixth carrier signal The frequency is The peak-to-peak value is 1, and the isosceles triangular carriers are distributed in the same direction in the vertical direction between 4 and 6. According to the preset modulation system Determine the total modulation signal and the total modulation signal The signal is compared with the first carrier signal, the second carrier signal, the third carrier signal, the fourth carrier signal, the fifth carrier signal, and the sixth carrier signal, respectively. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. when ≥ At that time, signal A high level is 1, and a low level is 0. According to the signal The signal The signal The signal The signal The signal and the square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle.

4. The power balancing optimization method for an asymmetric cascaded H-bridge inverter according to claim 3, characterized in that, in, The expression for the driving modulation signal is: ， In the formula, This is the drive modulation signal for the first switching device in the first low-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the first low-voltage H-bridge unit. for Non-signals, This is the drive modulation signal for the third switching device in the first low-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the first low-voltage H-bridge unit. for Non-signal; ， In the formula, This is the drive modulation signal for the first switching device in the second low-voltage H-bridge unit. For signal Non-signals, For signal Non-signals, This is the drive modulation signal for the second switching device in the second low-voltage H-bridge unit. for Non-signals, This is the drive modulation signal for the third switching device in the second low-voltage H-bridge unit. For signal Non-signals, Square wave signal Non-signals, This is the drive modulation signal for the fourth switching device in the second low-voltage H-bridge unit. for Non-signal; ， In the formula, This is the drive modulation signal for the first switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the third switching device in the first high-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the first high-voltage H-bridge unit. for Non-signal; ， In the formula, This is the drive modulation signal for the first switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the second switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the third switching device in the second high-voltage H-bridge unit. This is the drive modulation signal for the fourth switching device in the second high-voltage H-bridge unit. for The non-signal.

5. The power balancing optimization method for an asymmetric cascaded H-bridge inverter according to claim 4, characterized in that, in, The expression for the final driving signal is: ， In the formula, This is the final drive signal for the first switching device in the first high-voltage H-bridge unit. This is the final drive signal for the second switching device in the first high-voltage H-bridge unit. This is the final drive signal for the third switching device in the first high-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the first high-voltage H-bridge unit. for Non-signals, for Non-signals, It is a square wave signal with a period of 1 / 2 of the fundamental period of the output voltage. for Non-signal; ， In the formula, This is the final drive signal for the first switching device in the second high-voltage H-bridge unit. This is the final drive signal for the second switching device in the second high-voltage H-bridge unit. for Non-signals, This is the final drive signal for the third switching device in the second high-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the second high-voltage H-bridge unit. for Non-signal; ， In the formula, This is the final drive signal for the first switching device in the first low-voltage H-bridge unit. This is the final drive signal for the second switching device in the first low-voltage H-bridge unit. for Non-signals, This is the final drive signal for the third switching device in the first low-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the first low-voltage H-bridge unit. This is the final drive signal for the third switching device in the first low-voltage H-bridge unit; ， In the formula, This is the final drive signal for the first switching device in the second low-voltage H-bridge unit. This is the final drive signal for the second switching device in the second low-voltage H-bridge unit. This is the final drive signal for the third switching device in the second low-voltage H-bridge unit. This is the final drive signal for the fourth switching device in the second low-voltage H-bridge unit. for Non-signals, for The non-signal.

6. A power balancing optimization system for an asymmetric cascaded H-bridge inverter, characterized in that, include: The acquisition module is configured to acquire a target switching state combination of an asymmetric cascaded H-bridge inverter. The target switching state combination is a non-opposite polarity switching state combination among the redundant switching state combinations of the asymmetric cascaded H-bridge inverter, wherein the asymmetric cascaded H-bridge inverter contains H-bridge units. The reassembly module is configured to, based on a preset total modulation signal, employ a preset hybrid carrier pulse width modulation strategy to modulate the signal in the target switching state combination. ,Signal ,Signal ,Signal ,Signal ,Signal and preset angular frequency square wave signal The signals are recombined to obtain the drive modulation signals of the switching devices in each H-bridge unit within one cycle. The H-bridge unit includes low-voltage H-bridge units and high-voltage H-bridge units. The fundamental frequency period; The optimization module is configured to combine the driving modulation signals of each switching device with a square wave signal of 1 / 2 the fundamental period of the output voltage. Logical operations are performed to obtain the final drive signals for the switching devices in the asymmetric cascaded H-bridge inverter.

7. An electronic device, characterized in that, include: At least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1 to 5.

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