Metal-containing hard mask opening method using boron-containing and halogen-containing precursors

Abstract

An example semiconductor processing method may include providing a boron and halogen containing precursor and an oxygen containing precursor to a processing region of a semiconductor process chamber. The substrate may be accommodated in the processing region. The metal-containing hard shielding material layer can be arranged on the substrate. The silicon-containing material layer may be disposed on the metal-containing hard shield material layer. The method may include forming a plasma effluent containing boron and halogen precursors and oxygen-containing precursors. The method may include contacting a substrate with a plasma effluent containing boron and halogen precursors and oxygen-containing precursors. This contact may etch features in the metal-containing hard shield material layer. This contact may form a passivation material layer on sidewalls of features in the metal-containing hard shield material layer.

Description

Technical Field

[0001] This application claims priority under the Patent Act to U.S. Non-Provisional Patent Application No. 18 / 817,646, filed August 28, 2024, entitled "METAL-CONTAINING HARDMASK OPENING METHODS USING BORON-AND-HALOGEN-CONTAINING PRECURSORS", and to U.S. Provisional Patent Application No. 63 / 539,189, filed September 19, 2023, entitled "METAL-CONTAINING HARDMASK OPENING METHODS USING BORON-AND-HALOGEN-CONTAINING PRECURSORS", both of which are incorporated herein by reference in their entirety for all purposes.

[0002] This technology relates to semiconductor manufacturing processes and equipment. More specifically, this technology relates to etching operations involving hard metal mask materials. Background Technology

[0003] Integrated circuits can be fabricated by creating intricately patterned material layers on a substrate surface. Creating patterned material on the substrate requires controlled methods for removing exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have etching processes that etch one material faster than another to facilitate, for example, pattern transfer processes. Such etching processes are called selective for the first material. Due to the diversity of materials, circuits, and processes, selective etching processes for multiple materials have been developed.

[0004] Depending on the materials used in the process, etching processes can be described as wet or dry. Wet HF etching preferentially removes silicon oxide compared to other dielectrics and materials. However, wet processes may struggle to penetrate certain confined trenches and can sometimes deform the remaining material. Dry etching, generated in localized plasma within the substrate processing area, can penetrate more confined trenches and exhibit less deformation of the fine remaining structure. However, localized plasma can damage the substrate by generating arcs during discharge.

[0005] Therefore, there is a need for improved systems and methods for producing high-quality components and structures. This technology can meet these and other needs. Summary of the Invention

[0006] An exemplary semiconductor processing method may include providing a boron- and halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor process chamber. A substrate may be housed in the processing region. A metal-containing hard mask material layer may be disposed on the substrate. A silicon-containing material layer may be disposed on the metal-containing hard mask material layer. The method may include forming a plasma outflow of the boron- and halogen-containing precursor and the oxygen-containing precursor. The method may include contacting the substrate with the plasma outflow of the boron- and halogen-containing precursor and the oxygen-containing precursor. This contact may etch features in the metal-containing hard mask material layer. This contact may form a passivation material layer on the sidewalls of the features in the metal-containing hard mask material layer.

[0007] In some embodiments, the boron- and halogen-containing precursor may be or may include boron trichloride (BCl3). The oxygen-containing precursor may be or may include diatomic oxygen (O2). The metal-containing hard mask material layer may include tungsten. The method may include providing a halogen-containing precursor to a processing region along with the boron- and halogen-containing precursor. The halogen-containing precursor may be or may include diatomic chlorine (Cl2), hydrogen bromide (HBr), or both. The metal-containing hard mask material layer may be characterized by a metal content greater than or about 40 atomic percent. The silicon-containing material layer may be or may include silicon oxide. The passivation material layer may be or may include boron- and oxygen-containing materials. The metal-containing hard mask material layer may be characterized by a critical size less than or about 20 nm. The semiconductor process chamber operating temperature may be greater than or about 20 °C. The boron- and halogen-containing precursor and the oxygen-containing precursor may be silicon-free.

[0008] Some embodiments of this technology may cover semiconductor processing methods. The methods may include: i) providing a boron- and halogen-containing precursor to a processing region of a semiconductor process chamber. A substrate may be housed in the processing region. A metal-containing hard mask material layer may be disposed on the substrate. A silicon-containing material layer may be disposed on the metal-containing hard mask material layer. The methods may include: ii) forming a plasma outflow of the boron- and halogen-containing precursor. The methods may include: iii) contacting the substrate with the boron- and halogen-containing precursor plasma outflow. This contact may etch features in the metal-containing hard mask material layer. The methods may include: iv) providing an oxygen-containing precursor to a processing region of a semiconductor process chamber. The methods may include: v) contacting the substrate with the oxygen-containing precursor. This contact may oxidize a portion of the sidewalls of features in the metal-containing hard mask material layer.

[0009] In some embodiments, the method may include: providing one or more halogen-containing precursors to a processing region of a semiconductor process chamber, accompanied by boron-containing and halogen-containing precursors. The flow rate ratio of the one or more halogen-containing precursors to the boron-containing and halogen-containing precursors may be greater than or about 50:1. Operations i) to v) may be repeated for a second cycle. In the second cycle, operation iii) may be repeated to form a passivation material layer on the sidewalls characterized in the metal hard mask material layer.

[0010] Some embodiments of this technology may cover semiconductor processing methods. The methods may include: providing a boron- and halogen-containing precursor to a processing region of a semiconductor process chamber. A substrate may be housed in the processing region. A metal hard mask material layer may be disposed on the substrate. A patterned layer of silicon material may be disposed on the metal hard mask material layer. The methods may include: forming a plasma outflow of the boron- and halogen-containing precursor. The methods may include: contacting the substrate with the plasma outflow of the boron- and halogen-containing precursor. This contact may etch a first portion of a feature in the metal hard mask material layer. The methods may include: providing an oxygen-containing precursor to a processing region of a semiconductor process chamber. The methods may include: contacting the substrate with the oxygen-containing precursor. This contact may oxidize the sidewalls of a feature in the metal hard mask material layer. The methods may include: providing a boron- and halogen-containing precursor to a processing region of a semiconductor process chamber. The methods may include: forming a plasma outflow of the boron- and halogen-containing precursor. The method may include: contacting a substrate with a plasma effluent containing boron and halogen precursors. This contact may etch a second portion of features in a layer containing a hard metal mask material. This contact may form a passivation material layer on the sidewalls of the features in the layer containing the hard metal mask material.

[0011] In some embodiments, the boron- and halogen-containing precursor may be or may include boron trichloride (BCl3). The method may include: forming a plasma effluent containing an oxygen-containing precursor.

[0012] Such a technique offers numerous advantages over conventional systems and techniques. For example, this process can increase the passivation of the sidewall material containing the metallic hard mask material during the etching operation. Furthermore, this process can prevent pattern stripping or collapse caused by poor sidewall passivation, as is common in conventional techniques. These and other embodiments, along with their numerous advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0013] The nature and advantages of the technology disclosed herein can be further understood by referring to the rest of the specification and the diagrams.

[0014] Figure 1 shows a top plan view of an exemplary processing system according to some embodiments of the present technology.

[0015] Figure 2 shows a schematic cross-sectional view of an exemplary process chamber according to some embodiments of the present technology.

[0016] Figures 3A to 3B show selected operations in etching methods according to some embodiments of the present technology.

[0017] Figures 4A to 4C are cross-sectional views of a substrate material on which operations are being performed according to some embodiments of the present technology.

[0018] Several diagrams are included in this work in an illustrative manner. It should be understood that these diagrams are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, as illustrative diagrams, these diagrams are intended to aid understanding and may not include all appearances or information compared to a realistic representation, and may include redundant or exaggerated material for illustrative purposes.

[0019] In the accompanying drawings, similar parts and / or features may have the same component symbol. Furthermore, parts of the same class may be distinguished by adding a letter after the component symbol (the letter distinguishing similar parts). If only the first component symbol is used in the specification, the description applies to any similar part having the same first component symbol, regardless of what the second symbol is. Detailed Implementation

[0020] As structures evolve, the aspect ratios of features and other structures increase, sometimes dramatically. During semiconductor processing, features can be etched through one or more materials, such as a layer containing a metal hard mask. When forming features, holes can extend through the entire thickness of the metal hard mask layer before contacting the substrate or other underlying material. As the aspect ratios of features and other structures increase, the resulting feature or hole dimensions may become critically reduced. Ideally, these critical dimensions should be uniform throughout the feature or hole.

[0021] Conventional techniques typically use halogen-containing precursors to etch features into a metal-containing hard mask. To form passivation on the sidewalls of the metal-containing hard mask, oxygen-containing precursors can be provided to form both metal and oxygen passivation. However, as the metal content of the hard mask increases, the metal and oxygen passivation may not be strong enough to passivate the sidewalls. Other conventional techniques include silicon-containing and / or oxygen-containing precursors to form silicon and oxygen passivation, but this may result in silicon and oxygen deposition at the etch front, potentially reducing etch selectivity during hard mask opening processes. Other conventional techniques include bromine-containing precursors to form both metal and bromine passivation, but this material may volatilize at elevated temperatures. Therefore, conventional techniques struggle to uniformly etch metal-containing hard masks due to poor passivation performance.

[0022] This technology overcomes these problems by using a combination of precursors (such as boron- and halogen-containing precursors and oxygen-containing precursors) simultaneously or sequentially in the etching process to provide a strong passivation material on the sidewalls of the features to be etched. This technology provides a much stronger boron- and oxygen-containing passivation material than conventional metal- and oxygen-containing materials. This technology also avoids the undesirable deposition problems associated with silicon-containing precursors. Finally, the boron- and oxygen-containing passivation material of this technology is more resilient to elevated temperatures.

[0023] While the remainder of the disclosure will conventionally use the disclosed techniques to identify specific etching processes, it will be readily understood that the systems and methods described are equally applicable to deposition and cleaning processes that may occur within the chambers. Therefore, the techniques should not be considered limited to use with these etching processes or chambers. Furthermore, although exemplary chambers are described to provide a basis for this technique, it should be understood that the technique can actually be applied to any semiconductor processing chamber that allows for the described single-chamber operation. Similarly, although specific etching operations will be described, it should be understood that the processes are equally applicable to other processes in which etching can be performed. Therefore, the examples presented should not be considered as limiting the scope of the techniques described herein.

[0024] Figure 1 shows a top plan view of one embodiment of a processing system 10 with deposition, etching, baking, and / or hardening chambers according to an embodiment. The tooling or processing system 10 depicted in Figure 1 may include a plurality of process chambers 24a to 24d, a transfer chamber 20, a service chamber 26, an integrated metering chamber 28, and a pair of loading gate chambers 16a to 16b. The process chambers may include any number of structures or components, as well as any number of process chambers or combinations of process chambers.

[0025] To transfer substrates between chambers, transfer chamber 20 may include a robotic transfer mechanism 22. Transfer mechanism 22 may have a pair of substrate transfer blades 22a, each attached to a remote end of an extendable arm 22b. Blades 22a can be used to bring individual substrates into and out of process chambers. In operation, one of the substrate transfer blades of transfer mechanism 22 (such as blade 22a) can retrieve a substrate W from one of the loading gate chambers (such as chambers 16a to 16b) and bring the substrate W to a first stage of processing, such as the processing in chambers 24a to 24d described below. Chambers may be included to perform individual or combined operations of the techniques described. For example, while one or more chambers may be configured for deposition or etching operations, one or more other chambers may be configured for pre-processing operations and / or one or more post-processing operations described herein. This technology covers any number of configurations that can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0026] If a chamber is occupied, the robot can wait until processing is complete, then remove the processed substrate from the chamber using a blade 22a, and a second blade can be inserted to insert a new substrate. Once the substrate has been processed, it can be moved to the second stage of processing. For each move, the transfer mechanism 22 typically has one blade carrying the substrate and an empty blade to perform the substrate exchange. The transfer mechanism 22 can wait at each chamber until the exchange can be completed.

[0027] Once processing within the final process chamber is complete, the transfer mechanism 22 can move the substrate W from the final process chamber and transfer it to a cassette within loading gate chambers 16a to 16b. The substrate can be moved from loading gate chambers 16a to 16b into the fab interface 12. The fab interface 12 is typically operable to transfer substrates between pod loaders 14a to 14d in an atmospheric pressure clean environment and loading gate chambers 16a to 16b. A clean environment within the fab interface 12 is typically provided through an air filtration process (e.g., HEPA filtration). The fab interface 12 may also include a substrate orienter / aligner for properly aligning the substrate prior to processing. At least one substrate robot (e.g., robots 18a to 18b) can be positioned within the fab interface 12 to transfer substrates between multiple locations within the fab interface 12 and to other locations communicating with the fab interface 12. Robots 18a to 18b can be configured to travel from one end of the factory interface 12 to the second end along a track system within the factory interface 12.

[0028] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals, which can provide adaptive control over any process performed in the process chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices to measure various film properties, such as thickness, roughness, and composition, and the metrology devices may further have the ability to characterize grating parameters (such as critical dimensions, sidewall angles, and feature heights) automatically under vacuum.

[0029] Each process chamber 24a to 24d can be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of process chambers and combinations of process chambers can be used in the multi-chamber processing system 10. For example, any process chamber can be configured to perform several substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre-cleaning, pretreatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that can be performed in any chamber or any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. Those skilled in the art to which this application pertains will readily understand that any other processes, including any processes described below, can be similarly performed in specific chambers incorporated within the multi-chamber processing system 10.

[0030] Figure 2 shows a schematic cross-sectional view of an exemplary process chamber 100 suitable for patterning a material layer disposed on a substrate 302 within the process chamber 100. The exemplary process chamber 100 is suitable for patterning processes, but it should be understood that this technique can be performed in any number of chambers, and the substrate support according to this technique can be included in an etching chamber, a deposition chamber, a processing chamber, or any other process chamber. The plasma process chamber 100 may include a chamber body 105 defining a chamber volume 101 in which the substrate can be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 coupled to a ground 126. The sidewalls 112 may have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma process chamber 100. The dimensions of the chamber body 105 and related components of the plasma process chamber 100 are not limited and are generally proportionally larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter and 450 mm diameter, such as display or solar cell substrates.

[0031] The chamber body 105 supports the chamber cover assembly 110 to enclose the chamber volume 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate pick-up port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 302 into and out of the plasma process chamber 100. The pick-up port 113 may be coupled to a transfer chamber and / or other chambers of the substrate handling system as described above. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to vent and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0032] Gas control panel 160 can be coupled to chamber body 105 via gas line 167 to supply process gases to chamber volume 101. Gas control panel 160 may include one or more process gas sources 161, 162, 163, 164, and may additionally include inert gases, non-reactive gases, and reactive gases, as may be used for any number of processes. Examples of process gases that may be supplied by gas control panel 160 include, but are not limited to: hydrocarbon gases, including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, and any number of additional materials. In addition, process gases may include nitrogen-containing gases, chlorine-containing gases, fluorine-containing gases, oxygen-containing gases, and hydrogen-containing gases, such as H2, NH3, H2O, H2O2, O2, O3, NF3, HF, F2, CH4, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, BCl3, PF3, PH3, COS, and SO2, as well as any number of additional precursors.

[0033] Valve 166 can control the flow of process gas from sources 161, 162, 163, and 164 from gas control board 160 and can be managed by controller 165. The gas flow supplied from gas control board 160 to chamber body 105 may include a combination of gases from one or more sources. Cover assembly 110 may include nozzle 114. Nozzle 114 may be one or more ports for introducing process gas from sources 161, 162, 164, and 163 of gas control board 160 into chamber volume 101. After the process gas is introduced into plasma process chamber 100, the gas can be aroused to form plasma. Antenna 148, such as one or more induction coils, may be provided adjacent to plasma process chamber 100. Antenna power supply 142 can supply power to antenna 148 via matching circuit 141, inductively coupling energy such as RF energy to the process gas to maintain plasma formed by the process gas within the chamber volume 101 of plasma process chamber 100. Alternatively, or in addition to antenna power supply 142, process electrodes below and / or above substrate 302 can be used to capacitively couple RF power to the process gas to maintain plasma within chamber volume 101. The operation of power supply 142 can be controlled by a controller (such as controller 165), which can also control the operation of other components within plasma process chamber 100.

[0034] A substrate support stage 135 can be disposed within the chamber volume 101 to support the substrate 302 during processing. The substrate support stage 135 may include an electrostatic chuck ("ESC") 122 for holding the substrate 302 during processing. The electrostatic chuck 122 uses electrostatic attraction to hold the substrate 302 to the substrate support stage 135. The ESC 122 may be powered by an RF power supply 125 integrated with matching circuitry 124. The ESC 122 may include electrodes 121 embedded within a dielectric body. The electrodes 121 may be coupled to the RF power supply 125 and can provide a bias voltage that attracts plasma ions formed by process gases in the chamber volume 101 to the ESC 122 and the substrate 302 located on the stage. The RF power supply 125 may be cyclically turned on and off, or pulsed, during processing of the substrate 302. ESC 122 may have an isolator 128, the purpose of which is to reduce the attraction of the sidewalls of ESC 122 to plasma, thereby extending the maintenance life of ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from plasma gases and extend the maintenance interval of the plasma process chamber 100.

[0035] Electrode 121 may be coupled to power supply 150. Power supply 150 may provide a clamping voltage of approximately 500 volts to approximately 15,000 volts to electrode 121. Power supply 150 may also include a system controller for controlling the operation of electrode 121 by directing DC current to clamp and declamp substrate 302. For example, similar to RF power supply 125, power supply 150 may provide a bias voltage that attracts plasma ions formed by process gases in chamber volume 101 to ESC 122 and substrate 302 located on the stage. Power supply 150 may be cycled on and off, or pulsed, during processing of substrate 302. In embodiments, power supply 150 may be provided with RF power, DC current, or voltage, or a combination thereof, applicable to clamping and / or biasing. In additional embodiments, various power supplies may be configured to supply RF power and DC current or voltage for clamping and / or biasing. ESC 122 may include a heater disposed within a pedestal and connected to a power source for heating the substrate, and a cooling base 129 supporting ESC 122 may include conduits for circulating heat transfer fluid to maintain the temperature of ESC 122 and the substrate 302 disposed thereon. ESC 122 may be configured to operate within the temperature range required for the thermal budget of the components manufactured on substrate 302. For example, depending on the process being performed, ESC 122 may be configured to maintain substrate 302 at a temperature of about -150 °C or below about 500 °C or higher.

[0036] A cooling base 129 may be provided to assist in controlling the temperature of the substrate 302. To reduce process drift and time, the temperature of the substrate 302 can be maintained substantially constant by the cooling base 129 throughout the time the substrate 302 is in the cleaning chamber. Although any temperature can be used, in some embodiments, the temperature of the substrate 302 can be maintained at a temperature between about -150 °C and about 500 °C throughout the subsequent cleaning process. A cover ring 130 may be disposed on the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gases to a desired portion of the exposed top surface of the substrate 302 while isolating the top surface of the substrate support pedestal 135 from the plasma environment mask within the plasma process chamber 100. The lifting pin can be selectively translating through the substrate support 135 to lift the substrate 302 above the substrate support 135, so as to facilitate the access of the substrate 302 by a transfer robot or other suitable transfer mechanism as described above.

[0037] The process sequence can be controlled using controller 165, which regulates the airflow from gas control panel 160 into plasma process chamber 100 and other processing parameters. When executed by the CPU, the software routine transforms the CPU into a specific-purpose computer, such as a controller, which controls the plasma process chamber 100 to perform the process according to this disclosure. The software routine can also be stored and / or executed by a second controller, which may be associated with the plasma process chamber 100.

[0038] The chambers discussed above can be used for exemplary methods, including etching methods. See Figures 3A and 3B, which illustrate exemplary operations in methods 300 and 350 according to embodiments of the present technology. Before the first operation of a method, the substrate may be processed in one or more ways before being placed into the processing area of ​​the chamber in which method 300 or method 350 may be performed. For example, a metal-containing hard mask material layer may be formed on the substrate. Alternatively, a silicon-containing material layer (such as silicon oxide) may be formed on the metal-containing hard mask material layer, and one or more patterns may then be formed through the silicon-containing material layer. Some or all of these operations may be performed in the chambers or system tools described above, or some or all of these operations may be performed in different chambers on the same system tool, which may include chambers in which the operations of method 300 and / or method 350 are performed.

[0039] Method 300 and / or method 350 may include several operations, which may or may not be specifically related to some embodiments of the methods according to the present technology. For example, many operations are described to provide a broader scope of structure formation, but these operations are not critical to the technology or may be performed by alternative methods, which will be described further below. Method 300 and / or method 350 may describe the operations schematically shown in Figures 4A to 4C, and the illustrations in Figures 4A to 4C will be described with reference to the operations of methods 300 and 350. It should be understood that Figures 4A to 4C are only partially schematic, and the substrate may contain any number of structural blocks having the configurations illustrated in the figures, as well as alternative structural configurations that may still benefit from the operations of the present technology.

[0040] Methods 300 and / or 350 may or may not involve operations as appropriate to develop a semiconductor structure prior to a specific manufacturing operation. It should be understood that methods 300 and / or 350 can be performed on any number of semiconductor structures, and Figure 4A illustrates an example structure in which contact cleaning or etching processes can be performed. As illustrated in Figure 4A, the processed semiconductor structure 400 may include a substrate 405, which may have a layer 410 containing a metal hard mask material, such as a metal and boron material, a metal and carbon material, or a metal and silicon material. The metal-containing hard mask material layer 410 is characterized by a metal content greater than or about 10 atomic percent, and is further characterized by the following metal contents: greater than or about 15 atomic percent, greater than or about 20 atomic percent, greater than or about 25 atomic percent, greater than or about 30 atomic percent, greater than or about 35 atomic percent, greater than or about 40 atomic percent, greater than or about 45 atomic percent, greater than or about 50 atomic percent, greater than or about 55 atomic percent, greater than or about 60 atomic percent, greater than or about 65 atomic percent, greater than or about 70 atomic percent, greater than or about 75 atomic percent, greater than or about 80 atomic percent or more. In an embodiment, the metal-containing hard mask material layer 410 may be a tungsten-containing hard mask material layer (e.g., tungsten boride, tungsten carbide, tungsten silicide, etc.) covering the substrate 405. However, the hard mask material 410 is not limited to metals and may include any other material, such as, but not limited to: arsenic (As), gold (Au), chromium (Cr), iron (Fe), gallium (Ga), germanium (Ge), hafnium (Hf), molybdenum (Mo), niobium (Nb), antimony (Sb), tin (Sn), tantalum (Ta), vanadium (V), zirconium (Zr), indium (In), or any other material useful for hard mask applications.

[0041] A silicon-containing material layer 415 may cover a metal-containing hard mask material layer 410 and may be patterned to form one or more holes 420 extending through the silicon-containing material layer 415. In embodiments, the silicon-containing material layer 415 may be silicon oxide or any other silicon-containing material. One or more holes 420 may be defined by sidewalls formed by the silicon-containing material layer 415. It should be understood that the structures mentioned are not intended to be limiting and may similarly cover any of a variety of other semiconductor structures. Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, in which there is an oxygen-containing material to be removed relative to one or more other materials. Furthermore, while high aspect ratio structures may benefit from this technique, this technique is equally applicable to lower aspect ratios and any other structures.

[0042] As shown, various materials can be present and exposed to the etchant material. Methods 300 and / or 350 can be performed to etch or remove a portion of the exposed metal-containing hard mask material layer 410 within the hole 420, while minimizing the etching of other materials such as the overlying silicon-containing material layer 415. By utilizing the processing conditions (e.g., temperature) and precursors according to embodiments of the present technology, the etching rate of the metal-containing hard mask material layer 410 relative to the silicon-containing material layer 415 can be increased. Furthermore, compared to conventional techniques, the contour control of features etched into the metal-containing hard mask material layer 410 is more uniform.

[0043] Operations 305 of method 300 and 355 of method 350 may include providing a precursor (such as an etchant precursor) to a processing region. The processing region may house a substrate 405, such as a processed semiconductor structure 400, which may have one or more material layers disposed on the substrate 405, such as a metal-containing hard mask material layer 410 and a silicon-containing material layer 415. The metal-containing hard mask material layer 410 may be exposed within openings or vias 420 in the silicon-containing material layer 415. The precursor may include boron- and halogen-containing precursors, oxygen-containing precursors, and / or halogen-containing precursors. In embodiments, one or more inert gases or carrier gases may also be provided along with the precursor. For example, the precursor may include any number of carrier gases, which may include argon (Ar), helium (He), nitrogen, or other rare, inert, or useful precursors. The carrier gas may be used to dilute the precursor, which may further reduce the etch rate to allow sufficient diffusion through the vias. In operations 310 of method 300 and 360 of method 350, plasma effluent may be formed, for example, within the processing region of a semiconductor process chamber. The plasma effluent may include plasma effluent from any of the precursors discussed above. Operations 305 and 310, as well as operations 355 and 360, may occur in various sequences and, in some embodiments, may be substantially simultaneous. Furthermore, in different embodiments, plasma may be formed from the precursor or from one or more inert gases before the addition of the etchant precursor.

[0044] As illustrated in Figure 4B, in operation 315 of method 300 and operation 365 of method 350, the semiconductor structure 400 and substrate 405 can contact the plasma effluent 425 of the etchant precursor, which can perform etching or removal of the metal hard mask material layer 410 to form feature 430 in the metal hard mask material layer 410. The plasma effluent 425 can contact the semiconductor structure 400 and all exposed surfaces, including the surfaces to be etched (such as the metal hard mask material layer 410) and the surfaces to be retained (such as the silicon material layer 415).

[0045] Furthermore, as shown in Figure 4C, in operation 320 of method 300, a passivation material 435, such as a boron- and oxygen-containing material layer, may be formed on the sidewalls of the metal-containing hard mask material layer 410 defining feature 430. In method 350, since operation 355 may or may not include an oxygen-containing precursor in the provision of the precursor, a separate passivation process can be performed. In an embodiment, method 350 may include: in operation 370, providing an oxygen-containing precursor to a processing region of a semiconductor process chamber. In operation 375, method 350 may include: forming a plasma effluent of the oxygen-containing precursor. In operation 380, method 350 may include: contacting a substrate with the oxygen-containing precursor or the plasma effluent of the oxygen-containing precursor. This contact may oxidize a portion of the sidewalls of feature 430 in the metal-containing hard mask material layer 410. Residual boron material from boron- and halogen-containing precursors can react with the oxidized portions of the sidewalls of feature 430 in the metal-containing hard mask material layer 410 to form passivation material 435. Alternatively, some or all of the operations of method 350 can be repeated for additional cycles, and the boron- and halogen-containing precursors can react with the oxidized portions of the sidewalls of feature 430 in the metal-containing hard mask material layer 410 to form passivation material 435.

[0046] Precursors used in etching processes may include boron- and halogen-containing precursors, oxygen-containing precursors, and / or halogen-containing precursors, along with one or more inert gases or carrier gases. Example boron- and halogen-containing precursors may be or may include boron trichloride (BCl3), which may be provided to the processing area. Other boron and halogen sources may be used in combination with BCl3 or as alternatives to BCl3. For example, boron- and halogen-containing precursors may be or may include boron trifluoride (BF3) or other boron- and halogen-containing materials. In embodiments, the boron- and halogen-containing precursors and oxygen-containing precursors may be silicon-free. Furthermore, during the etching process, the processing area may remain silicon-free and / or silicon-free. Example oxygen-containing precursors may be or may include diatomic oxygen (O2), which may be provided to the processing area. Other oxygen sources may be used in combination with O2 or as alternatives to O2. For example, oxygen-containing precursors may include one or more materials, including ozone (O3), vapor (H2O), hydrogen peroxide (H2O2), or additional oxygen-containing materials. Example halogen-containing precursors may be or may include diatomic chlorine (Cl2), which may be provided to the processing area. Other halogen sources may be used in combination with Cl2 or as a substitute for Cl2. For example, halogen-containing precursors may be or may include titanium tetrachloride (TiCl4), diatomic fluorine (F2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or additional halogen-containing materials. By providing additional halogen-containing precursors, the etching rate can be increased.

[0047] A flow rate ratio of one or more halogen-containing precursors to boron- and halogen-containing precursors can be maintained to balance the amount of etching and passivation. In embodiments, the flow rate ratio of one or more halogen-containing precursors to boron- and halogen-containing precursors can be greater than or about 50:1, and can be greater than or about 55:1, greater than or about 60:1, greater than or about 65:1, greater than or about 70:1, greater than or about 75:1, greater than or about 80:1, greater than or about 85:1, greater than or about 90:1, greater than or about 95:1, greater than or about 100:1, or greater, but the flow rate ratio of one or more halogen-containing precursors to boron- and halogen-containing precursors can also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges. In other embodiments, the flow rate of the boron- and halogen-containing precursors can be greater than that of the one or more halogen-containing precursors. For example, the flow rate ratio of boron-containing and halogen precursors to one or more halogen-containing precursors may be greater than or about 1:1, greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, greater than or about 5:1 or greater.

[0048] The plasma effluent formed from the precursor can be formed locally in the processing area or in a remote plasma system. For example, the plasma effluent can be generated with or without one or more carrier gases (such as Ar, He, diatomic nitrogen (N2), H2, or mixtures thereof) using a remote plasma source (RPS), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP). The plasma effluent can be a low-level plasma to limit the amount of bombardment and resulting sputtering, the possibility of clogging the orifice 420, and / or the bending / bowing of feature 430. In embodiments, the plasma power may be less than or about 5,000 W, and may be less than or about 4,500 W, less than or about 4,000 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,500 W, less than or about 1,500 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, or even less. However, the plasma power may also be included in the range between any two of these stated figures, or in any smaller range covered by any of the stated ranges. By utilizing low-level plasma power, the plasma effluent can be better controlled for delivery through the holes 420 of the silicon-containing material layer 415, while limiting sputtering of the silicon-containing material layer 415 and other exposed surfaces.

[0049] As illustrated in Figure 4C, the resulting feature 430 may extend through the metal-containing hard mask material layer 410. Although the aspect ratio and depth of the etched feature 430 may depend on the thickness of the metal-containing hard mask material layer 410, the feature 430 may be characterized by an aspect ratio greater than or about 2:1, or a height-to-width ratio measured from the upper surface of the substrate 405 to the upper surface of the metal-containing hard mask material layer 410. In embodiments, the feature 430 may be characterized by the following aspect ratios: greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 40:1, greater than or about 50:1, or greater, but the aspect ratio may also be included in the range between any two of these stated figures, or in any smaller range covered by any of the stated ranges. Furthermore, the depth of feature 430 measured from the upper surface of substrate 405 to the upper surface of the metal hard mask material layer 410 may be greater than or about 20 nm, and may be greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, greater than or about 200 nm, greater than or about 300 nm, greater than or about 400 nm, greater than or about 500 nm, greater than or about 750 nm, greater than or about 1,000 nm, greater than or about 2,000 nm, greater than or about 3,000 nm, greater than or about 4,000 nm, greater than or about 5,000 nm or greater, but the depth may also be included in the range between any two of these stated numbers, or in any smaller range covered by any stated range. The critical size or width of feature 430 may be less than or about 150 nm, and may be less than or about 125 nm, less than or about 100 nm, less than or about 75 nm, less than or about 50 nm, less than or about 45 nm, less than or about 40 nm, less than or about 35 nm, less than or about 30 nm, less than or about 28 nm, less than or about 26 nm, less than or about 24 nm, less than or about 22 nm, less than or about 20 nm, less than or about 19 nm, less than or about 18 nm, less than or about 17 nm, less than or about 16 nm, less than or about 15 nm or smaller, but the critical size or width may also be included in the range between any two of these numbers, or in any smaller range covered by any of the stated ranges.

[0050] Increasing the etching rate of the metal-containing hard mask material layer 410 can also lead to an increase in etch selectivity between the metal-containing hard mask material layer 410 and the silicon-containing material layer 415. In embodiments, this contact can selectively etch the metal-containing hard mask material layer 410 relative to the silicon-containing material layer 415 with a selectivity greater than or about 2:1, and the etch selectivity can be greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 6:1, greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1 or greater, but the etch selectivity can also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges.

[0051] Process conditions may also affect the operations performed in method 300. In some embodiments, each operation of method 300 may be performed during a constant temperature period, while in others, the temperature may be adjusted during different operations. For example, the semiconductor process chamber operating temperature (which may include the substrate, stage, or chamber temperature) during method 300 may be maintained at a temperature greater than or about 20 °C, and in some embodiments, the temperature may be maintained at or greater than 50 °C, greater than or about 75 °C, greater than or about 100 °C, greater than or about 150 °C, greater than or about 200 °C, greater than or about 250 °C, greater than or about 300 °C, greater than or about 325 °C, greater than or about 350 °C, greater than or about 375 °C, greater than or about 400 °C, greater than or about 425 °C, greater than or about 450 °C, greater than or about 475 °C, greater than or about 500 °C, greater than or about 525 °C, greater than or about 550 °C, or higher, but the temperature may also be included in a range between any two of these stated numbers, or in any smaller range covered by any of the stated ranges. For example, the operating temperature of a semiconductor process chamber can be between about 300 °C and about 500 °C, or between any other value mentioned above.

[0052] The pressure within the process chamber can be controlled during method 300. For example, during plasma effluent formation and etching operations, the semiconductor process chamber operating pressure can be maintained at less than or about 50 mTorr, and can be maintained at less than or about 45 mTorr, less than or about 40 mTorr, less than or about 35 mTorr, less than or about 30 mTorr, less than or about 25 mTorr, less than or about 20 mTorr, less than or about 15 mTorr, less than or about 10 mTorr, less than or about 5 mTorr or lower, but the pressure can also be included in a range between any two of these stated figures, or in any smaller range covered by any of the stated ranges. The pressure within the process chamber can affect the ability to flow into the via 420. For example, as the pressure increases, the difficulty for the plasma effluent to penetrate the via 420 and reach the etching lead of feature 430 may increase.

[0053] In the foregoing description, numerous details have been set forth for illustrative purposes in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art to which this application pertains that certain embodiments may be practiced without some of these details or with additional details.

[0054] Having disclosed several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the art, several well-known processes and components have not been described. Therefore, the foregoing description should not be construed as limiting the scope of the art. Additionally, methods or processes may be described as performed sequentially or in steps; however, it should be understood that operations may be performed simultaneously or in a different order than those listed.

[0055] Where a range of values ​​is provided, unless otherwise expressly specified herein, it should be understood that each intermediate value between the upper and lower limits of that range is specifically disclosed, with precision to the smallest quantile of the lower limit unit. This includes any narrower range between any stated or unstated intermediate value within the stated range and any other stated or intermediate value within that stated range. The upper and lower limits of such narrower ranges may be independently included in or excluded from the range, and each range in which any of the boundaries, no boundary, or both boundaries are included is also covered by this technique, each range being governed by any specifically excluded boundary in the stated range. Where a stated range includes one or both of these limitations, it also includes ranges excluding one or both of the included limitations.

[0056] As used herein and in the claims of the appended patent application, unless otherwise expressly specified herein, the singular forms “a”, “an”, and “the” include plural references. Thus, for example, reference to “a precursor” includes a plurality of such precursors, and reference to “the layer” includes reference to one or more layers and equivalents known to one of ordinary skill in the art to which this application pertains, and so on.

[0057] Furthermore, when the terms “comprise,” “comprising,” “contain,” “include,” and “including” are used in the specification of this case and in the scope of the patent application below, they are intended to specify the presence of the stated features, integers, components, or operations, but such terms do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, comprising the following steps: A boron- and halogen-containing precursor and an oxygen-containing precursor are provided to a processing area of ​​a semiconductor process chamber, wherein a substrate is housed in the processing area, wherein a metal hard shielding material layer is disposed on the substrate, and wherein a silicon-containing material layer is disposed on the metal hard shielding material layer. The plasma effluents forming the boron- and halogen-containing precursors and the oxygen-containing precursors; and The substrate is brought into contact with the plasma effluents of the boron- and halogen-containing precursors and the oxygen-containing precursors, wherein the contact etches features in the metal-containing hard shielding material layer, and wherein a passivation material layer is formed on the sidewall of the feature in the metal-containing hard shielding material layer.

2. The semiconductor processing method of claim 1, wherein the boron-containing and halogen precursor comprises boron trichloride (BCl3).

3. The semiconductor processing method of claim 1, wherein the oxygen-containing precursor comprises diatomic oxygen (O2).

4. The semiconductor processing method of claim 1, wherein the metal-containing hard shielding material layer comprises tungsten.

5. The semiconductor processing method as described in claim 1, further comprising the following steps: Along with the boron- and halogen-containing precursor, the halogen-containing precursor is provided to the processing area.

6. The semiconductor processing method of claim 1, wherein the halogen-containing precursor comprises: diatomic chlorine (Cl2), hydrogen bromide (HBr), or both.

7. The semiconductor processing method of claim 1, wherein the metal-containing hard shielding material layer is characterized by having a metal content of greater than or about 40 atomic percent.

8. The semiconductor processing method of claim 1, wherein the silicon-containing material layer comprises silicon oxide.

9. The semiconductor processing method of claim 1, wherein the passivation material layer comprises a boron- and oxygen-containing material.

10. The semiconductor processing method of claim 1, wherein the feature in the metal-containing hard shielding material layer is characterized by a critical size of less than or about 20 nm.

11. The semiconductor processing method of claim 1, wherein the semiconductor process chamber operating temperature is greater than or about 20 °C.

12. The semiconductor processing method of claim 1, wherein the boron-containing and halogen-containing precursor and the oxygen-containing precursor are free of silicon.

13. A semiconductor processing method, comprising the following steps: i) Providing boron- and halogen-containing precursors to a processing area of ​​a semiconductor process chamber, wherein a substrate is housed in the processing area, wherein a metal hard shielding material layer is disposed on the substrate, and wherein a silicon-containing material layer is disposed on the metal hard shielding material layer. ii) Formation of the plasma effluent containing the boron and halogen precursor; iii) Contact the substrate with the plasma effluent containing the boron and halogen precursor, wherein the contact etches features in the metal hard shielding material layer. iv) Providing an oxygen-containing precursor to the processing area of ​​the semiconductor process chamber; as well as v) The substrate is brought into contact with the oxygen-containing precursor, wherein the contact oxidizes a portion of the sidewall of the feature in the metal-containing hard shielding material layer.

14. The semiconductor processing method of claim 13, further comprising the following steps: The boron- and halogen-containing precursor is used to provide one or more halogen-containing precursors to the processing area of ​​the semiconductor process chamber.

15. The semiconductor processing method of claim 14, wherein the flow rate ratio of the one or more halogen-containing precursors to the boron-containing and halogen-containing precursors is greater than or about 50:

1.

16. The semiconductor processing method of claim 13, wherein operations i) to v) are repeated in the second cycle.

17. The semiconductor processing method of claim 16, wherein in the second cycle, operation iii) is repeated to form a passivation material layer on the sidewalls of the feature in the metal hard shielding material layer.

18. A semiconductor processing method, comprising the following steps: Boron- and halogen-containing precursors are provided to a processing area of ​​a semiconductor process chamber, wherein a substrate is housed in the processing area, wherein a metal hard shielding material layer is disposed on the substrate, and wherein a patterned silicon-containing material layer is disposed on the metal hard shielding material layer. The plasma effluent containing the boron and halogen precursor is formed; The substrate is brought into contact with the plasma effluent containing boron and halogen precursors, wherein the contact is etched with a first portion of a feature in the metal hard shielding material layer. Oxygen-containing precursors are provided to the processing area of ​​the semiconductor process chamber; The substrate is brought into contact with the oxygen-containing precursor, wherein the contact oxidizes the sidewall of the feature in the metal-containing hard shielding material layer; The boron- and halogen-containing precursor is provided to the processing area of ​​the semiconductor process chamber; The plasma effluent forming the boron- and halogen-containing precursor; and The substrate is brought into contact with the plasma effluent containing boron and halogen precursors, wherein the contact etches a second portion of the feature in the metal hard shielding material layer, and wherein the contact forms a passivation material layer on the sidewall of the feature in the metal hard shielding material layer.

19. The semiconductor processing method of claim 18, wherein the boron-containing and halogen precursor comprises boron trichloride (BCl3).

20. The semiconductor processing method of claim 18, further comprising the following steps: The plasma effluent that forms the oxygen-containing precursor.

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