A single register multiplexing circuit and parameter configuration method for parameter configuration

Abstract

The application discloses a single-register multiplexing circuit and parameter configuration method for parameter configuration, and relates to the technical field of parameter configuration.The circuit comprises a group of configuration registers for storing and providing calibration parameters to an analog IP, wherein the configuration registers are multiplexed in a test mode and a normal working mode; and a multiplexing module coupled to the data input end of the configuration registers, used for selecting one way of data from a plurality of configuration data sources according to a preset priority strategy and writing the data into the configuration registers; wherein the plurality of configuration data sources at least include a default initial value, a nonvolatile memory loaded value and a test interface written value.The application effectively eliminates the problem that parameters cannot be effectively in real time in the traditional double-register architecture due to the separation of test registers and working registers, so that the calibration parameters written through the interface in the test stage can directly act on the analog IP, and it is not necessary to re-verify the power supply after burning the memory, thereby significantly improving the calibration efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of parameter configuration, in particular to a single register multiplexing circuit and a parameter configuration method. BACKGROUND

[0002] Currently, in the existing chip design, the calibration of analog IPs (such as ADC, PLL, LDO, etc.) usually relies on a double register architecture: one set is used for the CP test phase, allowing dynamic writing of calibration parameters through the test interface; the other set is used for normal working mode, whose value is loaded from the non-volatile memory at power-on and is write-protected. The two sets of registers are switched by a multiplexer according to the mode signal to achieve a balance between test flexibility and running stability. However, under this architecture, the parameters written in the test phase only act on the test-specific registers and cannot directly drive the actual working analog IPs, resulting in the need to reprogram the parameters to the memory and re-power on after each calibration adjustment to verify the calibration effect, which seriously restricts the test efficiency. SUMMARY

[0003] Therefore, the present application provides a single register multiplexing circuit and a parameter configuration method for parameter configuration, which can realize instant mapping and verification of calibration parameters. The present application provides the following technical solutions:

[0004] A single register multiplexing circuit for parameter configuration, comprising:

[0005] a set of configuration registers for storing and providing calibration parameters to analog IPs, the configuration registers being multiplexed in test mode and normal working mode;

[0006] a multiplexing module coupled to the data input end of the configuration registers for selecting one way of data from multiple configuration data sources according to a preset priority strategy and writing the data into the configuration registers;

[0007] wherein the multiple configuration data sources at least include default initial values, non-volatile memory loaded values, and test interface written values.

[0008] Optionally, the multiplexing module is configured to select data according to a three-level priority strategy:

[0009] the highest priority is the default initial value, which is forced to be selected when the chip is powered on or reset;

[0010] the second highest priority is the non-volatile memory loaded value, which is selected when the non-volatile memory data is ready and the chip is in normal working mode;

[0011] the lowest priority is the test interface written value, which is selected when the chip is in test mode and has write permission.

[0012] Optionally, the output end of the configuration register is real-time mapped to the control end of the analog IP;

[0013] When detecting abnormal configuration register value, invalid write permission or input source switching abnormality, automatically fallback the value of the configuration register to the default initial value to drive the analog IP into preset safe working state.

[0014] Optionally, the write operation of the configuration register is constrained by permission and abnormality control logic, including:

[0015] When the chip is in test mode and high permission write instruction is received, allowing modification of the configuration register through the test interface;

[0016] When the chip is in safe start stage and the non-volatile memory data is ready, automatically enabling high permission mode and writing the non-volatile memory load value into the configuration register.

[0017] Optionally, the output end of the configuration register is coupled to the control input end of the analog IP, and the output value of the configuration register is updated to the analog IP in the current clock cycle or the next clock cycle after receiving valid write data, without relying on reset signal or power restart operation.

[0018] Optionally, the configuration register is a multi-bit register, each bit of which corresponds to different adjustable parameters in the analog IP, and the value of the configuration register directly controls at least one of the analog characteristics of the analog IP, such as bias current, gain, bandwidth or timing, through bit mapping.

[0019] The application further discloses a parameter configuration method applied to the single register multiplexing circuit, including the following steps:

[0020] The calibration parameters are stored and provided to the analog IP through a group of configuration registers, and the configuration registers are multiplexed in test mode and normal working mode.

[0021] A plurality of configuration data sources are selected according to a preset priority strategy through a plurality of selection modules coupled to the data input end of the configuration register, and one way of data is written into the configuration register;

[0022] The plurality of configuration data sources at least include default initial value, non-volatile memory load value and test interface write value.

[0023] The output value of the configuration register is mapped to the control end of the analog IP to control the analog characteristics thereof.

[0024] Optionally, the step of selecting one of the configuration data sources to write into the configuration register according to the preset priority strategy comprises:

[0025] Forcing to select the default initial value to write into the configuration register when the chip is powered on or reset;

[0026] Selecting the non-volatile memory load value to write into the configuration register when the non-volatile memory data is ready and the chip is in normal working mode;

[0027] Selecting the test interface write value to write into the configuration register when the chip is in test mode and has write permission.

[0028] Optionally, the method further comprises:

[0029] When an abnormal value of the configuration register, invalid write permission or abnormal input source switching is detected, the value of the configuration register is rolled back to the default initial value to drive the analog IP into a preset safe working state.

[0030] Optionally, the write operation of the configuration register is constrained by permission and abnormality control logic, comprising:

[0031] When the chip is in test mode and a high permission write instruction is received, allowing the configuration register to be modified through the test interface;

[0032] When the chip is in a safe start phase and the non-volatile memory data is ready, automatically enabling a high permission mode to write the non-volatile memory load value into the configuration register.

[0033] According to the technical solution of the present application, by only setting a set of configuration registers commonly used in test mode and normal working mode, and dynamically selecting the input source from the default initial value, the non-volatile memory load value and the test interface write value according to the preset priority strategy by the multi-way selection module, the problem that the parameters cannot be effectively verified in real time due to the separation of the test register and the working register in the traditional dual-register architecture is effectively eliminated, so that the calibration parameters written through the interface in the test stage can directly act on the analog IP, without the need to re-power on and verify after burning the memory, which significantly improves the calibration efficiency. At the same time, this scheme eliminates a complete set of redundant registers and their control logic, greatly saving the chip area and reducing the manufacturing cost under the premise of ensuring the functional integrity and system safety. BRIEF DESCRIPTION OF DRAWINGS

[0034] For the purpose of illustration and not limitation, the present application will now be described in conjunction with the embodiments of the present application and the accompanying drawings, in which:

[0035] Figure 1is a structural schematic diagram of a single register multiplexing circuit for parameter configuration in the embodiment of the application;

[0036] Figure 2 is a flow schematic diagram of a parameter configuration method in the embodiment of the application. DETAILED DESCRIPTION

[0037] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0038] It should be noted that the features in the embodiments of the present application and the embodiments can be combined with each other without conflict. The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

[0039] Reference Figure 1 The present embodiment discloses a single register multiplexing circuit for parameter configuration, which comprises a group of configuration registers 100, a multiplexing module 200, a non-volatile memory 300, a test interface 400 and permission and exception control logic 500.

[0040] The configuration register 100 is a multi-bit register, for example, 8 bits, 12 bits or 16 bits, and the specific bit width is determined according to the demand of the controlled analog IP. The output end thereof is directly coupled to the control input end of the analog IP 600. The configuration register 100 is multiplexed in the test mode and the normal working mode of the chip, and is used for receiving debugging parameters in the CP test stage and providing the final calibration value to the analog IP 600 in the normal working mode. The single register multiplexing structure eliminates the redundant second set of registers and the switching MUX in the traditional scheme, and significantly saves the chip area.

[0041] The data input end of the configuration register 100 is connected to the multiplexing module 200. The multiplexing module 200 selects one way from three configuration data sources to write into the configuration register 100 according to a preset priority strategy.

[0042] (1) Default initial value (Default Value), which is usually a safe starting value of the analog IP 600, and is stored in a hardwired logic or a read-only register;

[0043] (2) Memory Load Value, from non-volatile memory 300 (such as eFuse, OTP or Flash), which is the final calibration parameter programmed after test completion;

[0044] (3) Test Interface Write Value, written by external test equipment through test interface 400 (such as I2C, JTAG or dedicated debug bus).

[0045] The multiplexing module 200 adopts a three-level priority arbitration mechanism:

[0046] The highest priority is the default initial value, which is forced to be selected when the chip is powered on or the reset signal (RST) is valid, ensuring that the system can enter a safe working point under any abnormal start state;

[0047] The second highest priority is the non-volatile memory load value, which is selected when the chip completes power-on initialization, the non-volatile memory 300 data ready signal (MEM_RDY) is valid, and the chip is in normal working mode (TEST_MODE=0);

[0048] The lowest priority is the test interface write value, which is selected only when TEST_MODE=1 (test mode) and the permission and abnormal control logic 500 determines to allow writing. The three-level priority can be arbitrated by a lightweight state machine, avoiding the risk of metastable state caused by multiple signal competition and improving system robustness.

[0049] The write operation of the configuration register 100 is strictly constrained by the permission and abnormal control logic 500. The permission and abnormal control logic 500 monitors the chip working mode, memory state and write instruction permission bit in real time. Only when any of the following conditions is met, the write operation on the configuration register 100 is allowed:

[0050] The chip is in test mode (TEST_MODE=1), and the received write instruction contains high permission identification (such as a specific key or privileged address), at which time the write value of the test interface 400 can be accepted;

[0051] The chip is in the safe start phase (i.e. a short window after power-on and before normal working mode is enabled), and the MEM_RDY signal of the non-volatile memory 300 is valid, at which time the high permission mode is automatically enabled, and the memory load value is written to the configuration register 100. This permission mechanism effectively prevents illegal tampering or misoperation from causing the analog IP to lose control.

[0052] The output value of the configuration register 100 is updated to the control terminal of the analog IP 600 in the current clock cycle or the next clock cycle after the valid data is written, without relying on the reset signal or power restart. For example, in a synchronous digital system, the configuration register 100 can be implemented by using an edge-triggered D flip-flop, and the Q output directly drives the digital-to-analog conversion control unit of the analog IP 600. This real-time mapping mechanism allows the tester to immediately observe the performance response (such as output spectrum, setup time, etc.) of the analog IP after writing new parameters through I2C, without repeatedly powering on and off, greatly shortening the calibration period.

[0053] Further, each bit or bit field of the configuration register 100 has a predefined bit mapping relationship with different adjustable parameters in the analog IP 600. For example, the [7:4] bits control the bias current intensity, the [3:2] bits set the gain level, and the [1:0] bits adjust the bandwidth compensation. This structured coding allows a single register to accurately control multiple analog characteristics, avoiding the resource waste of the traditional scheme of configuring a separate register for each parameter.

[0054] In addition, an exception detection and rollback mechanism is integrated into the permission and exception control logic 500. When any of the following exceptions is detected: the value of the configuration register 100 is out of the legal range, the write permission is invalid, a conflict occurs during the input source switching process, or the non-volatile memory 300 fails the verification, the permission and exception control logic 500 will immediately force the multiplexing module 200 to switch to the default initial value and lock the output of the configuration register 100, driving the analog IP 600 to enter a preset safe working state. This mechanism ensures that even in extreme cases such as test misoperation or memory damage, the chip can still maintain basic functions, significantly improving product reliability.

[0055] In summary, the embodiment achieves efficient, safe, and flexible analog IP parameter configuration while saving area through the cooperative design of single-register multiplexing, three-level priority selection, permission control, real-time mapping, and exception rollback, overcoming the fundamental defects of the existing dual-register architecture.

[0056] Reference Figure 2 The present embodiment further discloses a parameter configuration method for an analog IP, which can be performed in the single-register multiplexing circuit as described in the foregoing embodiments, and can also be applied to other chip systems with multiple source input selection and register multiplexing capabilities.

[0057] The method in the present embodiment includes the following steps:

[0058] S100: Store and provide calibration parameters to analog IP through a configuration register, which is multiplexed in test mode and normal working mode. Unlike the traditional double-register scheme, this method only relies on a single register as the only carrier of parameter configuration, thereby avoiding the verification delay problem caused by the separation of test parameters and working parameters.

[0059] S200: Through a multiplexing module coupled to the data input end of the configuration register, select a way of data from multiple configuration data sources according to a preset priority strategy and write the data into the configuration register. The multiple configuration data sources at least include: default initial value, non-volatile memory loaded value and test interface written value. The default initial value is a safe starting reference value of the analog IP, which is usually fixed in the chip design stage; the non-volatile memory loaded value is the final calibration parameter burned after the test is completed; and the test interface written value is issued in real time by the external test equipment through the communication interface such as I2C and JTAG in the debugging stage.

[0060] The specific execution logic of the priority strategy is as follows:

[0061] When the chip is powered on or the reset signal is valid, no matter what mode it is in, the default initial value is forced to be selected to write into the configuration register, so as to ensure that the analog IP can enter a controllable state in any abnormal starting scene;

[0062] When the chip completes power-on initialization, the non-volatile memory data ready signal (MEM_RDY) is valid, and the chip is in normal working mode (TEST_MODE=0), the non-volatile memory loaded value is automatically selected to write into the configuration register, so that the analog IP runs in the optimal calibration state;

[0063] When the chip is in test mode (TEST_MODE=1) and the permission and abnormal control logic determine that the current write instruction has high permission identification (such as a specific address, a key or a privilege bit), the test interface written value is allowed to be selected to write into the configuration register.

[0064] The three-level priority can be uniformly arbitrated by a lightweight state machine, avoiding the logic conflict or metastable state risk caused by multiple condition concurrent judgment, and improving the reliability of the method execution.

[0065] S300: After the write operation is completed, the output value of the configuration register is mapped to the control terminal of the analog IP in the current clock cycle or the next clock cycle. There is no need to wait for reset or re-power. For example, in a synchronous system, the configuration register can be implemented by using an edge-triggered register, and the output thereof directly drives a digital-to-analog conversion or bias control unit inside the analog IP. The real-time mapping mechanism enables the tester to immediately observe the performance response of the analog IP, such as output spectrum, setup time, phase noise, etc., through the ATE device after sending a write command, thereby significantly improving the calibration iteration efficiency.

[0066] Further, to ensure system safety, the method further includes an abnormality detection and rollback mechanism: during parameter writing or source switching, if an abnormality such as the configuration register value exceeding a legal range, invalid write permission, input source switching conflict, or non-volatile memory check failure is detected, the current write operation is immediately aborted, and the value of the configuration register is forcibly rolled back to the default initial value, and the analog IP is driven to enter a preset safe working state. The rollback action is triggered by a hardware abnormality detection module, and the response delay is not more than one clock cycle, thereby ensuring that the analog IP will not be disabled due to illegal parameters.

[0067] In addition, the write operation of the configuration register is strictly constrained by permission and abnormality control logic. Only when any of the following conditions is met, the write operation is allowed to be performed:

[0068] The chip is in a test mode, and the received write instruction contains a high permission identifier, at this time, the configuration register is allowed to be modified through the test interface;

[0069] The chip is in a safe startup phase (i.e., a short window after power-on and before the normal working mode is enabled), and the non-volatile memory data is ready, at this time, the system automatically enables the high permission mode, and writes the memory load value into the configuration register. The permission identifier and the mode signal need to be verified together, and a single signal is invalid, which effectively prevents false triggering or malicious tampering.

[0070] In summary, by means of single-register multiplexing, three-level priority dynamic selection, permission collaborative verification, and abnormality fast rollback, the method realizes efficient, safe, and real-time configuration of the analog IP parameters without relying on additional hardware redundancy, and solves the problem of low test efficiency caused by the fact that parameters cannot take effect immediately in the traditional method.

[0071] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can occur depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A single register multiplexing circuit for parameter configuration, characterized in that, The application comprises the following steps: a set of configuration registers are used to store and provide calibration parameters for analog IPs, and the configuration registers are multiplexed in test mode and normal working mode; a multiplexing module is coupled to the data input end of the configuration registers, and is used to select one way of data from a plurality of configuration data sources according to a preset priority strategy and write the data into the configuration registers, wherein the plurality of configuration data sources at least include default initial values, non-volatile memory loading values and test interface writing values; the multiplexing module is configured to select data according to a three-level priority strategy: the highest priority is the default initial value, which is forced to be selected when the chip is powered on or reset; the second highest priority is the non-volatile memory loading value, which is selected when the non-volatile memory data is ready and the chip is in normal working mode; the lowest priority is the test interface writing value, which is selected when the chip is in test mode and has write permission.

2. The single register multiplexing circuit for parameter configuration of claim 1, wherein, the output end of the configuration register is mapped to the control end of the analog IP in real time; when the configuration register value is abnormal, the write permission is invalid or the input source switching is abnormal, the value of the configuration register is automatically rolled back to the default initial value to drive the analog IP into a preset safe working state.

3. The single register multiplexing circuit for parameter configuration of claim 1, wherein, the write operation of the configuration register is restricted by permission and abnormality control logic, including: when the chip is in test mode and a high permission write instruction is received, the configuration register is allowed to be modified through the test interface; when the chip is in the safe start stage and the non-volatile memory data is ready, the high permission mode is automatically enabled, and the non-volatile memory loading value is written into the configuration register.

4. The single register multiplexing circuit for parameter configuration of claim 3, wherein, the output end of the configuration register is coupled to the control input end of the analog IP, and after receiving valid write data, the output value of the configuration register is updated to the analog IP in the current clock cycle or the next clock cycle, without relying on the reset signal or power restart operation.

5. The single register multiplexing circuit for parameter configuration of claim 1, wherein, the configuration register is a multi-bit register, each bit of which corresponds to a different adjustable parameter in the analog IP, and the value of the configuration register directly controls at least one of the bias current, gain, bandwidth or timing of the analog IP through bit mapping.

6. A parameter configuration method applied to the single register multiplexing circuit according to any one of claims 1-5, characterized in that, The application comprises the following steps: a set of configuration registers are used to store and provide calibration parameters for analog IPs, and the configuration registers are multiplexed in test mode and normal working mode; a multiplexing module is coupled to the data input end of the configuration registers, and is used to select one way of data from a plurality of configuration data sources according to a preset priority strategy and write the data into the configuration registers, wherein the plurality of configuration data sources at least include default initial values, non-volatile memory loading values and test interface writing values; the multiplexing module is configured to select data according to a three-level priority strategy: the highest priority is the default initial value, which is forced to be selected when the chip is powered on or reset; the second highest priority is the non-volatile memory loading value, which is selected when the non-volatile memory data is ready and the chip is in normal working mode; the lowest priority is the test interface writing value, which is selected when the chip is in test mode and has write permission. the output end of the configuration register is mapped to the control end of the analog IP in real time; when the configuration register value is abnormal, the write permission is invalid or the input source switching is abnormal, the value of the configuration register is automatically rolled back to the default initial value to drive the analog IP into a preset safe working state. the write operation of the configuration register is restricted by permission and abnormality control logic, including: when the chip is in test mode and a high permission write instruction is received, the configuration register is allowed to be modified through the test interface; when the chip is in the safe start stage and the non-volatile memory data is ready, the high permission mode is automatically enabled, and the non-volatile memory loading value is written into the configuration register. the output end of the configuration register is coupled to the control input end of the analog IP, and after receiving valid write data, the output value of the configuration register is updated to the analog IP in the current clock cycle or the next clock cycle, without relying on the reset signal or power restart operation. the configuration register is a multi-bit register, each bit of which corresponds to a different adjustable parameter in the analog IP, and the value of the configuration register directly controls at least one of the bias current, gain, bandwidth or timing of the analog IP through bit mapping. When the non-volatile memory data is ready and the chip is in normal working mode, the non-volatile memory loading value is selected to write into the configuration register; when the chip is in test mode and has write permission, the test interface write value is selected to write into the configuration register; and the output value of the configuration register is mapped to the control end of the analog IP to control the analog characteristics thereof.

7. The parameter configuring method according to claim 6, wherein Also included are: When the configuration register value is detected to be abnormal, the write permission is invalid, or the input source switching is abnormal, the value of the configuration register is rolled back to the default initial value to drive the analog IP into a preset safe working state.

8. The parameter configuring method according to claim 6, wherein The write operation of the configuration register is constrained by permission and abnormality control logic, including: When the chip is in test mode and a high-permission write instruction is received, modification of the configuration register through the test interface is allowed; When the chip is in a safe start stage and the non-volatile memory data is ready, a high-permission mode is automatically enabled, and the non-volatile memory loading value is written into the configuration register.

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