Cavity silicon-on-insulator wafer and method of making same

Abstract

The application provides a cavity silicon-on-insulator wafer and a preparation method thereof. The method comprises the following steps: providing a first silicon wafer and a second silicon wafer; forming an insulating layer on a bonding surface of the first silicon wafer; forming a cavity structure at a target position, wherein the target position is located on the second silicon wafer entirely, or partially on the second silicon wafer and extends through the insulating layer, or partially on the second silicon wafer and extends through the insulating layer to the first silicon wafer; and bonding the first silicon wafer and the second silicon wafer through the insulating layer to obtain the cavity silicon-on-insulator wafer, so that the manufacturing process can be simplified.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, specifically to a silicon wafer on a cavity insulator and its fabrication method. Background Technology

[0002] Silicon on insulator (SOI) significantly improves insulation, reduces parasitic capacitance and leakage current by introducing an insulating buried layer between the silicon substrate and the top silicon layer, while also offering advantages such as high speed and low power consumption. In integrated circuits, it can improve radio frequency performance, simplify three-dimensional integration, and withstand high voltage, and is widely used in 5G communications, automotive electronics, and AI chips. In microelectromechanical systems (MEMS), the insulating layer acts as an etch stop layer to facilitate high-precision structural processing, while also enabling complex three-dimensional MEMS structures, improving sensor performance, and reducing process complexity. It is widely used in the manufacturing of sensor chips such as high-temperature pressure sensors, micromechanical gyroscopes, and accelerometers.

[0003] Cavity silicon on insulator (CSOI) is an advanced semiconductor manufacturing technology that improves upon the traditional SOI structure. Its core feature is the embedding of cavities within the SOI structure, which further optimizes the electrical and thermal performance of the device. Compared to traditional SOI, the introduction of cavities effectively reduces parasitic capacitance, thereby improving device speed and energy efficiency; it significantly reduces power consumption by optimizing electrical isolation and thermal conduction; the cavity structure helps reduce electron scattering and interference, improving device stability; and it exhibits greater stability at high temperatures, extending the device's operating temperature range. Furthermore, for MEMS devices, the introduction of patterned cavities simplifies the manufacturing process, eliminating the need for releasing movable structures.

[0004] Currently, the manufacturing process of silicon wafers on cavity insulators mainly includes substrate silicon wafer oxidation and etching, surface treatment, silicon wafer bonding, top silicon thinning and polishing, etc., which is a very complex process. Summary of the Invention

[0005] In view of the above problems, the present invention provides a silicon wafer on a cavity insulator and a method for preparing the same, which solves at least one of the above problems.

[0006] According to a first aspect of the present invention, a method for fabricating a silicon wafer on a cavity insulator is provided, the method comprising:

[0007] Provide a first silicon wafer and a second silicon wafer;

[0008] An insulating layer is formed on the bonding surface of the first silicon wafer;

[0009] A cavity structure is formed at the target location, wherein the target location is entirely located on the second silicon wafer, or partially located on the second silicon wafer and extends through the insulating layer, or partially located on the second silicon wafer and extends through the insulating layer into the first silicon wafer;

[0010] The first silicon wafer and the second silicon wafer are bonded together through the insulating layer to obtain a silicon wafer on a cavity insulator.

[0011] According to an embodiment of the present invention, forming a cavity structure at the target location includes forming the cavity structure at the target location by means of dry etching or wet etching.

[0012] According to an embodiment of the present invention, the method further includes: forming an oxide layer on the alignment surface of the first silicon wafer, the alignment surface being opposite to the bonding surface.

[0013] According to an embodiment of the present invention, the method further includes: etching the oxide layer to form alignment marks.

[0014] According to an embodiment of the present invention, the method further includes etching the alignment surface of the first silicon wafer to form alignment marks.

[0015] According to an embodiment of the present invention, the method further includes: performing a bonding pretreatment on the first silicon wafer and the second silicon wafer.

[0016] According to an embodiment of the present invention, bonding the first silicon wafer and the second silicon wafer through the insulating layer to obtain a silicon wafer on a cavity insulator includes: bonding the first silicon wafer with alignment marks and the second silicon wafer with the cavity structure through the insulating layer under vacuum conditions to obtain a silicon wafer on a cavity insulator.

[0017] According to an embodiment of the present invention, the method further includes annealing the silicon wafer on the cavity insulator.

[0018] According to an embodiment of the present invention, after providing the first silicon wafer and the second silicon wafer, the method further includes: performing standard cleaning on the first silicon wafer and the second silicon wafer.

[0019] A second aspect of the present invention also provides a silicon-on-a-cavity insulator, comprising:

[0020] A first silicon wafer having a bonding surface;

[0021] An insulating layer formed on the bonding surface of the first silicon wafer;

[0022] A second silicon wafer bonded to the first silicon wafer through the insulating layer;

[0023] The second silicon wafer has a cavity structure, and the spatial distribution of the cavity structure is any one of the following:

[0024] All located on the second silicon wafer; or,

[0025] Partially located on the second silicon wafer and extending through the insulating layer; or,

[0026] Part of it is located on the second silicon wafer and extends through the insulating layer into the interior of the first silicon wafer.

[0027] The cavity insulator-on-silicon wafer and its fabrication method provided by the present invention, by designing at least part of the cavity structure in the second silicon wafer, i.e. the top silicon layer, and by controlling the cavity depth, the thickness of the remaining top silicon layer can be precisely controlled, thereby completing the fabrication of the cavity insulator-on-silicon wafer without the need for thinning and polishing after bonding, reducing the complexity of the process. Attached Figure Description

[0028] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0029] Figure 1 A flowchart illustrating a method for fabricating silicon wafers on a cavity insulator is shown schematically.

[0030] Figure 2 The schematic diagram illustrates the bonding edge defects and edge chipping during grinding and polishing in the fabrication method of silicon wafers on cavity insulators.

[0031] Figure 3 A flowchart illustrating a method for fabricating a silicon wafer on a cavity insulator according to an embodiment of the present invention is shown schematically.

[0032] Figures 4A-4C A schematic diagram illustrating the location of the cavity structure according to an embodiment of the present invention is shown.

[0033] Figure 5 A schematic flowchart illustrating the fabrication process of silicon wafer on a cavity insulator according to an embodiment of the present invention is shown. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0036] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0037] Currently, the manufacturing process of silicon wafers on cavity insulators mainly includes substrate silicon wafer oxidation and etching, surface treatment, silicon wafer bonding, and top silicon thinning and polishing, such as... Figure 1 As shown. The complexity of the manufacturing process is one of its main drawbacks, especially in thinning and polishing. Because the thickness of the top silicon layer (also known as the device layer) needs to be precisely controlled at the micrometer level, after silicon wafer bonding, most of the silicon substrate needs to be removed by etching or mechanical grinding, followed by chemical mechanical polishing (CMP) to achieve the required surface roughness. This process requires precise thickness control while avoiding damage to the device layer, placing extremely high precision demands on the etching, grinding, and polishing processes. Furthermore, due to the presence of the silicon wafer chamfer, bonding defects are inevitable at the edges of the bonded silicon wafer, making it highly susceptible to edge chipping of the top silicon layer during thinning and polishing, such as… Figure 2 As shown, this problem needs to be solved through processes such as post-bonding trimming, which further increases the process complexity of silicon wafers on cavity insulators.

[0038] The complexity of the manufacturing process is one of the main drawbacks limiting the development and application of silicon-on-insulator (SOI) technology, especially in thinning and polishing. The thickness of the top silicon layer needs to be precisely controlled at the micrometer level, and the surface roughness generally needs to be controlled at the nanometer level, which places extremely high precision requirements on the etching, grinding, and polishing processes. Furthermore, due to the presence of defects at the edges of the bonded silicon wafers, edge trimming and other methods are required during the thinning and polishing process to avoid edge chipping, further increasing the process complexity of SOI.

[0039] Therefore, this invention provides a method for fabricating a silicon-on-cavity (SOC) insulator, comprising: providing a first silicon wafer 10 and a second silicon wafer 20; forming an insulating layer 30 on the bonding surface of the first silicon wafer 10; forming a cavity structure A at a target location, wherein the target location is entirely located on the second silicon wafer 20, or partially located on the second silicon wafer 20 and extending through the insulating layer 30, or partially located on the second silicon wafer 20 and extending through the insulating layer 30 into the first silicon wafer 10; and bonding the first silicon wafer 10 and the second silicon wafer 20 through the insulating layer 30 to obtain the SOC insulator. By designing the cavity location, the manufacturing process is simplified, and the fabrication of the SOC insulator can be completed without thinning and polishing, greatly reducing the process complexity of the SOC insulator and saving manufacturing costs.

[0040] This invention provides a silicon wafer on a cavity insulator, comprising: a first silicon wafer 10 having a bonding surface; an insulating layer 30 formed on the bonding surface of the first silicon wafer 10; and a second silicon wafer 20 bonded to the first silicon wafer 10 through the insulating layer 30; wherein the second silicon wafer 20 has a cavity structure A, and the spatial distribution of the cavity structure A is any one of the following: entirely located on the second silicon wafer 20; or partially located on the second silicon wafer 20 and extending through the insulating layer 30; or partially located on the second silicon wafer 20 and extending through the insulating layer 30 into the interior of the first silicon wafer 10.

[0041] Figure 3 A flowchart illustrating a method for fabricating a silicon wafer on a cavity insulator according to an embodiment of the present invention is shown.

[0042] like Figure 3 As shown, the method for fabricating the silicon wafer on the cavity insulator includes operations S310-S340.

[0043] In operation S310, a first silicon wafer 10 and a second silicon wafer 20 are provided.

[0044] According to an embodiment of the present invention, the first silicon wafer 10 can be used as the top silicon layer and the second silicon wafer 20 can be used as the bottom silicon layer.

[0045] In operation S320, an insulating layer 30 is formed on the bonding surface of the first silicon wafer 10.

[0046] According to an embodiment of the present invention, the bonding surface refers to the surface of the first silicon wafer 10 that will subsequently be bonded to the second silicon wafer 20. The insulating layer 30 is formed by growing or depositing a material with insulating properties on the bonding surface of the first silicon wafer 10 through a specific process. This insulating layer 30 plays an electrical isolation role in the cavity insulator silicon wafer, preventing direct conduction between the first silicon wafer 10 and the second silicon wafer 20.

[0047] In operation S330, a cavity structure A is formed at the target location.

[0048] According to embodiments of the present invention, participants Figures 4A-4C .like Figure 4A As shown, the target location can be entirely located on the second silicon wafer 20. (As illustrated...) Figure 4B As shown, the target location may be partially located on the second silicon wafer 20 and extend through the insulating layer 30. Figure 4C As shown, the target location may be partially located in the second silicon wafer 20 and extend through the insulating layer 30 into the first silicon wafer 10.

[0049] According to an embodiment of the present invention, the shape of the cavity structure A can be circular, polygonal, annular, irregular, etc.

[0050] According to embodiments of the present invention, the number of cavity structures A can be one or more. Correspondingly, the depths of the multiple cavity structures A can be the same or different.

[0051] Understandably, after the cavity structure A is formed, the second silicon wafer 20 has a preset thickness. This means that the thickness of the remaining second silicon wafer 20, i.e., the top layer silicon, can be precisely controlled by controlling the depth of the cavity structure A. For example, if the cavity depth is precisely controlled at 8 micrometers during fabrication, then the remaining top layer silicon thickness is the initial top layer silicon thickness minus 8 micrometers. If the initial top layer silicon thickness is 10 micrometers, then the remaining top layer silicon thickness is 2 micrometers.

[0052] In operation S340, the first silicon wafer 10 and the second silicon wafer 20 are bonded together through the insulating layer 30 to obtain a silicon wafer on a cavity insulator.

[0053] According to embodiments of the present invention, bonding refers to tightly connecting the first silicon wafer 10 and the second silicon wafer 20 together through an insulating layer 30 between them to form an integral structure. Bonding methods include, but are not limited to, silicon-silicon bonding and eutectic bonding. Through the bonding process, the first silicon wafer 10 and the second silicon wafer 20 can be bonded at the atomic level, ensuring the stability of the cavity structure A and the performance of the device.

[0054] According to an embodiment of the present invention, by designing at least a portion of the cavity structure A in the second silicon wafer 20, i.e. the top layer silicon, the thickness of the remaining top layer silicon can be precisely controlled by controlling the cavity depth. Thus, the silicon wafer on the cavity insulator can be fabricated without the need for thinning and polishing after bonding, reducing the complexity of the process.

[0055] In some embodiments, after providing the first silicon wafer 10 and the second silicon wafer 20, the first silicon wafer 10 and the second silicon wafer 20 may be subjected to standard cleaning. The cleaning objects may be the surfaces of the first silicon wafer 10 and the second silicon wafer 20, including bonding surfaces and other surfaces that may participate in subsequent processes.

[0056] In some embodiments, the cavity structure A can be formed at the target location using dry etching or wet etching. By controlling the cavity depth through precise dry etching or wet etching processes, the thickness of the remaining top silicon layer (micrometer level) can be precisely controlled, eliminating the need for thinning and polishing after bonding and completely avoiding edge chipping issues, thus fundamentally reducing process complexity.

[0057] Dry etching is a process that uses high-energy particle beams such as plasma or ion beams to physically bombard and chemically react with materials, thereby removing the material to form a specific structure. It possesses anisotropic etching characteristics, enabling precise control over the shape and size of the etched material, achieving high aspect ratio etched structures. Forming a cavity structure A at a target location can be achieved through precise mask design and etching process control, etching only in a pre-determined area where the cavity needs to be formed (the target location), removing material from that area to create the desired cavity shape and size.

[0058] Wet etching is a process in which a silicon wafer is immersed in an etching solution, and the material on the surface of the wafer is removed through a chemical reaction to form the desired structure. Forming a cavity structure A at a target location may require first forming an etching mask at the target location using processes such as photolithography to protect areas that do not need etching. Then, the sample is immersed in the etching solution, allowing the material at the target location to react chemically with the etching solution and be removed, thereby forming the cavity.

[0059] In some embodiments, an oxide layer 40 may be formed on the alignment surface of the first silicon wafer 10, with the alignment surface opposite the bonding surface. The oxide layer 40 is then etched to form alignment marks 41 and 42. It is understood that the number of alignment marks may be one or more, and this invention is not limited thereto.

[0060] In some embodiments, alignment marks 41 and 42 can be formed directly on the alignment surface of the first silicon wafer 10. Then, an oxide layer 40 is formed on the alignment surface of the first silicon wafer 10, with the alignment surface facing the bonding surface.

[0061] In some embodiments, the first silicon wafer 10 and the second silicon wafer 20 undergo pre-bonding treatment. For example, cleaning the bonding surfaces, activating the bonding surfaces, etc.

[0062] In some embodiments, a first silicon wafer 10 with alignment marks 41, 42 and a second silicon wafer 20 with a cavity structure A can be bonded under vacuum conditions through an insulating layer 30 to obtain a silicon wafer on a cavity insulator.

[0063] In some embodiments, the silicon wafer on the cavity insulator may be annealed after bonding is completed.

[0064] Figure 5A flowchart illustrating a method for fabricating a silicon wafer on a cavity insulator according to an embodiment of the present invention is shown.

[0065] like Figure 5 As shown, the method for fabricating a silicon wafer on a cavity insulator includes operations S1-S7.

[0066] S1. Prepare the first and second silicon wafers (substrate silicon and top layer silicon) and perform standard cleaning.

[0067] S2. Perform double-sided oxidation on the substrate silicon.

[0068] S3. Dry etching / wet etching is performed on the top silicon layer to obtain the cavity structure.

[0069] S4. Dry etching / wet etching is performed on the silicon substrate to obtain alignment marks.

[0070] S5. Perform surface treatment on the substrate silicon with alignment marks and the top layer silicon with cavity structure;

[0071] S6. Bond the substrate silicon with alignment marks and the top layer silicon with cavity structure under vacuum conditions;

[0072] S7. Anneal the silicon wafer on the bonded cavity insulator.

[0073] In this process, the order of S4 and S2 can be interchanged. Alignment marks can be obtained by etching the substrate silicon first, and then oxidation can be performed.

[0074] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for fabricating a silicon wafer on a cavity insulator, characterized in that, The method includes: Provide a first silicon wafer and a second silicon wafer; An insulating layer is formed on the bonding surface of the first silicon wafer; A cavity structure is formed at the target location, wherein the target location is entirely located on the second silicon wafer, or partially located on the second silicon wafer and extends through the insulating layer, or partially located on the second silicon wafer and extends through the insulating layer into the first silicon wafer; The first silicon wafer and the second silicon wafer are bonded together through the insulating layer to obtain a silicon wafer on a cavity insulator; The depth of the cavity structure is configured such that the thickness of the remaining portion of the second silicon wafer above the cavity structure after bonding is equal to the thickness of the target device layer.

2. The method for preparing a silicon wafer on a cavity insulator according to claim 1, characterized in that, The process of forming a cavity structure at the target location includes: A cavity structure is formed at the target location using dry etching or wet etching.

3. The method for preparing a silicon wafer on a cavity insulator according to claim 1, characterized in that, The method further includes: An oxide layer is formed on the alignment surface of the first silicon wafer, the alignment surface being opposite to the bonding surface.

4. The method for preparing a silicon wafer on a cavity insulator according to claim 3, characterized in that, The method further includes: The oxide layer is etched to form alignment marks.

5. The method for preparing a silicon wafer on a cavity insulator according to claim 1 or 3, characterized in that, The method further includes: Alignment marks are formed by etching the alignment surface of the first silicon wafer.

6. The method for preparing a silicon wafer on a cavity insulator according to claim 1, characterized in that, The method further includes: The first and second silicon wafers undergo pre-bonding treatment.

7. The method for preparing a silicon wafer on a cavity insulator according to claim 1, characterized in that, The step of bonding the first silicon wafer and the second silicon wafer through the insulating layer to obtain a silicon wafer on a cavity insulator includes: A first silicon wafer with alignment marks and a second silicon wafer with the cavity structure are bonded together under vacuum conditions through the insulating layer to obtain a silicon wafer on a cavity insulator.

8. The method for preparing a silicon wafer on a cavity insulator according to claim 1, characterized in that, The method further includes: Annealing is performed on the silicon wafer on the cavity insulator.

9. The method for preparing a silicon wafer on a cavity insulator according to claim 1, characterized in that, After providing the first silicon wafer and the second silicon wafer, the method further includes: The first silicon wafer and the second silicon wafer are subjected to standard cleaning.

10. A silicon wafer on a cavity insulator, characterized in that, include: A first silicon wafer having a bonding surface; An insulating layer formed on the bonding surface of the first silicon wafer; A second silicon wafer bonded to the first silicon wafer through the insulating layer; The second silicon wafer has a cavity structure, and the spatial distribution of the cavity structure is any one of the following: All located on the second silicon wafer; or, Partially located on the second silicon wafer and extending through the insulating layer; or, Part of it is located on the second silicon wafer and extends through the insulating layer into the interior of the first silicon wafer; The depth of the cavity structure is configured such that the thickness of the remaining portion of the second silicon wafer above the cavity structure after bonding is equal to the thickness of the target device layer.

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