Power supply circuit and electronic equipment
By introducing a delay circuit into the power supply circuit, the power-down time is detected and extended, thus solving the problem of power-down timing mismatch in electronic devices, avoiding device damage, and improving the reliability of the power supply circuit.
Patent Information
- Application Number
- CN202511121957.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-12
- Publication Date
- 2025-11-25
AI Technical Summary
If electronic devices fail to meet power-down timing requirements when powered off, it may cause damage to the devices.
A delay circuit is introduced into the power supply circuit. By detecting the interruption of the enable signal of the power control module, the power-down time of some power modules is extended to ensure that multiple power supplies are powered down in a predetermined sequence.
This avoids damage to components caused by simultaneous power outages from multiple power sources, thus improving the reliability of the power supply circuit.
Smart Images
Figure CN121012136A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of electronic devices, and particularly relates to a power supply circuit and an electronic device. BACKGROUND
[0002] In the related art, multiple power supplies exist in the circuit of an electronic device, and the multiple power supplies supply power to different loads of the electronic device. When the multiple power supplies are powered on, the power-on timing requirements of the electronic device need to be met. The reason is that the initialization action needs to be performed when the electronic device is powered on, and the initialization action needs to rely on a certain power-on sequence to ensure that no abnormal leakage occurs. Correspondingly, the electronic device also needs to follow the corresponding power-off timing requirements when it is powered off, otherwise problems such as device damage and chip state lockout may occur.
[0003] However, abnormal situations may occur when the electronic device is in use, such as software crash, system freezing, and application program dead loop. When such problems occur, the electronic device cannot be normally operated and used, and generally needs to be forcibly powered off and restarted through a specific key. Since the operation of forcibly powering off and restarting is controlled by hardware, the system software cannot participate in the power-off timing control, which will cause the enable signal output end of the controller to be reset and powered off, which will also cause the multiple power supplies to be powered off at the same time, and the power-off timing requirements cannot be met. This may cause damage to the devices of the electronic device. SUMMARY
[0004] The application aims to provide a power supply circuit and an electronic device, which can solve the problem that the electronic device cannot meet the power-off timing requirements when it is powered off in the related art, which may cause damage to the devices.
[0005] In a first aspect, an embodiment of the application provides a power supply circuit, comprising:
[0006] a power supply control module, the power supply control module comprising a plurality of signal output ends, the signal output ends being configured to output an enable signal;
[0007] a plurality of power supply modules, the plurality of power supply modules being electrically connected with the plurality of signal output ends; in a case where the power supply modules receive the enable signal, the power supply modules are powered on and output a power supply signal, the power supply signal being configured to supply power to a load;
[0008] at least one delay circuit, the delay circuit being electrically connected with at least two signal output ends and an output end of a power supply module;
[0009] In a case where the delay circuit detects that the output end of the power supply module outputs the power supply signal and the at least two signal output ends have no enable signal, the delay circuit outputs the power supply signal through the output end of the power supply module within a delay time length.
[0010] In a second aspect, an electronic device is provided, comprising:
[0011] The power supply circuit as claimed in the first aspect.
[0012] The embodiments of the present application add a delay circuit in the power supply circuit, and detect whether the enable signal of the power supply control module is interrupted by the detection circuit in the delay circuit. In the case that the power supply module is still in the power supply state of outputting the power supply signal, but the enable signal is interrupted, the delay circuit outputs the power supply signal to the output end of at least one of the plurality of power supply modules within the delay time, thereby delaying the power-off time of the power supply module, making the power-off times of the plurality of power supply modules different, avoiding simultaneous power-off and causing device damage, and improving the reliability of the power supply circuit.
[0013] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS
[0014] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:
[0015] Figure 1 A circuit diagram of a power supply circuit of some embodiments of the present application is shown;
[0016] Figure 2 A waveform diagram of an enable signal of some embodiments of the present application is shown;
[0017] Figure 3 A waveform diagram of a power supply signal of some embodiments of the present application is shown;
[0018] Figure 4 A circuit diagram of a power supply circuit of some embodiments of the present application is shown;
[0019] Figure 5 A waveform diagram of an enable signal of some embodiments of the present application is shown;
[0020] Figure 6 A waveform diagram of a power supply signal of some embodiments of the present application is shown.
[0021] REFERENCE NUMERALS:
[0022] 10 power supply circuit, 100 power supply control module, 102 power supply module, 1022 first power supply module, 1024 second power supply module, 104 delay circuit, 1043 first delay circuit, 1044 first detection circuit, 1046 first energy storage circuit, 106 load;
[0023] The gpio signal output end, the gpio1 first signal output end, the gpio2 second signal output end, the D1 exclusive or gate module, the D2 and gate module, the S1 switch device, the com static contact, the ch1 first movable contact, the ch2 second movable contact, the ctral control end, the C1 first capacitor, the C2 second capacitor, the R1 first resistor. DETAILED DESCRIPTION
[0024] The embodiments of the present application will be described in detail below with reference to the drawings, in which the same or similar components have the same reference numerals throughout the several views. The embodiments described below are examples for explaining the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.
[0025] The terms "first", "second" in the description and claims of the present application can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally means that the front and rear associated objects are in an "or" relationship.
[0026] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.
[0027] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0028] The following will be described in detail Figures 1 to 6 The power supply circuit and electronic equipment according to the embodiments of the present application are described.
[0029] In some embodiments of the present application, a power supply circuit is provided, Figure 1 and Figure 4 The circuit diagram of the power supply circuit of some embodiments of the present application is shown as Figure 1 and Figure 4 The power supply circuit 10 includes a power supply control module 100, a plurality of power supply modules 102 and at least one delay circuit 104, as shown.
[0030] The power supply control module 100 includes a plurality of signal output terminals gpio, which are used to output an enable signal.
[0031] The plurality of power supply modules 102 are respectively electrically connected with the plurality of signal output terminals gpio; in the case that the power supply module 102 receives the enable signal, the power supply module 102 is powered on and outputs a power supply signal, which is used to supply power to the load 106.
[0032] The delay circuit 104 is electrically connected with at least two signal output terminals gpio and an output terminal of a power supply module.
[0033] In the case that the delay circuit 104 detects that the output terminal of a power supply module 102 outputs a power supply signal, and at least two signal output terminals gpio have no enable signal, the delay circuit 104 outputs the power supply signal through the output terminal of the power supply module 102 within a delay time.
[0034] In the embodiments of the present application, the power supply circuit 10 is applied to an electronic device. The power supply circuit 10 includes a plurality of power supply modules 102, each of which corresponds to a power supply and is responsible for supplying power to one load 106 in the electronic device.
[0035] The power supply control module 100 includes a plurality of signal output terminals gpio, which are respectively electrically connected with the plurality of power supply modules 102, and the plurality of signal output terminals gpio correspond one-to-one with the plurality of power supply modules 102. After the power supply circuit 10 is powered on, the power supply control module 100 controls the plurality of signal output terminals gpio to output the enable signal in turn according to the set power-on sequence. When any power supply module receives the enable signal, this power supply module starts to output the power supply signal to the load 106.
[0036] Since different loads 106 in the electronic device play different roles, the electronic device has a responsive requirement for the upper limit sequence of the power supply circuit 10. Generally speaking, the earlier the power-on of the power-consuming device, the more important it is. Or, the power-on process of the power-consuming device that powers on late needs the support of the power-consuming device that powers on early.
[0037] Correspondingly, when the electronic device is turned off, the process of the power supply circuit 10 controlling the power-down of multiple power modules 102 also needs to follow the corresponding power-down sequence to ensure that each load 106 can be shut down normally and to prevent problems such as device damage.
[0038] In actual operation of electronic devices, some special scenarios exist. These include software crashes, system freezes, and applications getting stuck in infinite loops. When these scenarios occur, users will be unable to operate the electronic device normally or use its shutdown or restart functions. In such cases, users typically need to perform a "forced shutdown" or "warm restart." Forced shutdowns or "warm restarts" are generally implemented through hardware on the electronic device's main control board. For example, when a user presses and holds the power button, or simultaneously presses the power button and volume control button, the main control board will immediately perform a forced shutdown and restart. At this time, the outputs of multiple GPIO terminals of the power control module 100 will simultaneously change from 1 to low level, and all power supply modules will simultaneously lose their enable signals.
[0039] Taking the power supply circuit 10, which includes two power supplies, or two power modules 102, as an example. Figure 2 The following are waveform diagrams of the enable signals of some embodiments of this application, such as... Figure 2 As shown, the two signal output ports GPIO follow the power-on sequence T1 when powered on. However, when performing a "forced shutdown" or "warm start", the enable signals of the two signal output ports GPIO simultaneously return to 0. At this time, the two power modules 102 will stop outputting power supply signals simultaneously, which cannot meet the power-off sequence and may cause device damage.
[0040] In response to the above problems, such as Figure 1 As shown, this application includes a delay circuit 104. When it is detected that the power supply module is outputting a power supply signal, but the enable signal suddenly returns to 0, the delay circuit 104 will replace the power supply module 102 to output a power supply signal to the load 106 during the delay period.
[0041] By reasonably setting the delay duration of different delay circuits 104, the power-off time of the loads 106 connected to different power modules 102 can be different, thereby realizing the control of multiple power supplies to power off separately according to a certain power-off sequence.
[0042] For example, Figure 3 The following are waveform diagrams of the power supply signals of some embodiments of this application, such as... Figure 2 and Figure 3As shown, the two power supply signals V1 and V2 follow the power-on sequence T1 at power-on, and when performing “forced shutdown” or “hot start”, even if the enable signals of the two signal output terminals gpio are both 0 at the same time, the power supply signals V1 and V2 output by the two power supplies can be powered off in sequence according to the power-off sequence t1 under the action of the energy storage circuit, thereby avoiding device damage caused by simultaneous power-off.
[0043] In the embodiments of the present application, the delay circuit 104 is added in the power supply circuit 10, and the detection circuit in the delay circuit 104 detects whether the enable signal of the power supply control module 100 is interrupted. In the case where it is detected that the power supply module 102 is still in the power supply state of outputting the power supply signal, but the enable signal is interrupted, the delay circuit 104 outputs the power supply signal to the output terminal of at least one of the plurality of power supply modules 102 within the delay time, thereby delaying the power-off time of this power supply module 102, making the power-off times of the plurality of power supply modules 102 different, so as to meet the requirement of the power-off sequence when forced power-off restarts, avoid device damage, and improve the reliability of the power supply circuit 10.
[0044] In some embodiments of the present application, Figure 4 The circuit diagram of the power supply circuit 10 of some embodiments of the present application is shown in Figure 4 As shown, the number of signal output terminals gpio and power supply modules 102 is n+1, the number of delay circuits 104 is n, and n is a positive integer greater than 1; wherein the delay time corresponding to the energy storage circuit of the n-1th delay circuit 104 is t n-1 , the delay time corresponding to the energy storage circuit of the nth delay circuit 104 is t n , and t n >t n-1 .
[0045] In the embodiments of the present application, the power supply circuit 10 includes n+1 power supplies. Correspondingly, the power supply control module 100 includes n+1 signal output terminals gpio, and the n+1 signal output terminals gpio are connected to the n+1 power supply modules 102 in one-to-one correspondence.
[0046] Exemplarily, Figure 5 The waveform diagram of the enable signal of some embodiments of the present application is shown in Figure 6 The waveform diagram of the power supply signal of some embodiments of the present application is shown in Figure 5 and Figure 6 As shown, the number of delay circuits 104 is n, and the delay times of the n delay circuits 104 are different. The delay time of the nth delay circuit 104 is t n , and the delay time of the n-1th delay circuit 104 is t n-1For example, assuming that in n+1 power supply, the first power supply is powered first, and the n+1 power supply is powered last. When the "forced shutdown" or "hot start" occurs, the power module 102 of the n+1 power supply is directly powered off because it is not electrically connected to the delay circuit 104. The power module 102 of the n power supply is electrically connected to the first delay circuit 104, and is powered off after a delay of t1. The power module 102 of the n-1 power supply is electrically connected to the second delay circuit 104, and is powered off after a delay of t2.
[0047] By analogy, the power module 102 of the first power supply is electrically connected to the n delay circuit 104, and is powered off after a delay of t n .
[0048] Exemplarily, t n may be expressed by the following formula (1):
[0049] t n = t1+t2+…+t (n-1) ; (1)
[0050] Thus, the n+1 power supply is powered off according to the set power-off sequence, ensuring the power-off sequence during "forced shutdown" or "hot start", and improving the reliability of the power supply circuit 10, wherein tn represents the delay time of the n delay circuit.
[0051] In some embodiments of the present application, the power module 102 includes a first power module 1022 and a second power module 1024.
[0052] The signal output end gpio includes a first signal output end gpio1 and a second signal output end gpio2, the first signal output end gpio1 is electrically connected to the first power module 1022, and the second signal output end gpio2 is electrically connected to the second power module 1024; the delay circuit 104 includes a first delay circuit 1043, and the first delay circuit 1043 includes a first detection circuit 1044 and a first energy storage circuit 1046.
[0053] The first detection circuit 1044 is electrically connected to the first signal output end gpio1, the second signal output end gpio2 and the output end of the second power module 1024, and the first detection circuit 1044 is used to output the first power supply signal at the output end of the second power module 1024, and control the first energy storage circuit 1046 to output the first power supply signal in the case that the first signal output end gpio1 and the second signal output end gpio2 have no enable signal.
[0054] In the embodiment of the present application, the first detection circuit 1044 detects the enable signals of the first signal output end gpio1 and the second signal output end gpio2 respectively, and detects the first power supply signal output by the second power supply module 1024. When the first power supply signal output by the second power supply module 1024 is detected, it indicates that the second power supply module 1024 has completed power-on. If the enable signals of the first signal output end gpio1 and the second signal output end gpio2 are not detected at this time, it indicates that the situation of "forced shutdown" or "hot start" occurs after the power-on of the power supply circuit 10. At this time, the first energy storage circuit 1046 outputs the first power supply signal, which prolongs the power-down time of the power supply path where the second power supply module 1024 is located, so that the power-down time of the power supply path where the second power supply module 1024 is located is later than that of the power supply path where the first power supply module 1022 is located, thereby realizing the power-down of the multiple power supplies in sequence according to the power-down time sequence, avoiding the situation that the device is damaged due to the simultaneous power-down of the multiple power supplies, and being beneficial to improving the reliability of the power supply circuit.
[0055] In some embodiments of the present application, the power-on time sequence of the first power supply module 1022 and the second power supply module 1024 is adjacent, and the power-on time sequence of the second power supply module 1024 is earlier than that of the first power supply module 1022.
[0056] In the embodiment of the present application, as shown in Figure 4 , the power-on time sequence of the first power supply module 1022 and the second power supply module 1024 is adjacent, and the second power supply module 1024 is powered on earlier than the first power supply module 1022. That is, after the second power supply module 1024 is powered on, the first power supply module 1022 is powered on immediately. The first delay circuit 1043 is used for delay power-down processing of the second power supply module 1024, so that the power-down time of the second power supply module 1024 is later than that of the first power supply module 1022. That is, under the action of the first delay circuit 1043, after the first power supply module 1022 is powered down, the second power supply module 1024 starts to be powered down.
[0057] The present application can ensure that each power supply module corresponding to the load can normally complete the power-down operation by setting the power-down sequence of the power supply module powered on first and powered down later, thereby avoiding the situation that the device is damaged due to the simultaneous power-down of the multiple power supplies.
[0058] In some embodiments of the present application, as shown in Figure 1 , the first detection circuit 1044 includes an exclusive-NOR gate module D1 and an AND gate module D2. The first input end of the exclusive-NOR gate module D1 is electrically connected with the first signal output end gpio1, and the second input end of the exclusive-NOR gate module D1 is electrically connected with the second signal output end gpio2.
[0059] The first input end of the AND gate module D2 is electrically connected with the output end of the XNOR gate module D1, the second input end of the AND gate module D2 is electrically connected with the output end of the second power supply module 1024, and the output end of the AND gate module D2 is electrically connected with the first energy storage circuit; wherein, in the case that the output of the AND gate module D2 is a high level, the electrical path between the first energy storage circuit and the output end of the second power supply module 1024 is conducted; in the case that the output of the AND gate module D2 is a low level, the electrical path between the first energy storage circuit and the output end of the second power supply module 1024 is cut off.
[0060] In the embodiments of the present application, each detection circuit, including the first detection circuit 1044, comprises an XNOR gate module D1 and an AND gate module D2. As shown in Figure 1 , the two input ends of the XNOR gate module D1 are connected with the first signal output end gpio1 and the second signal output end gpio2 respectively. The two input ends of the AND gate module D2 are connected with the output end of the XNOR gate module D1 and the output end of the second power supply module 1024 respectively.
[0061] Then according to the circuit logic shown in Figure 1 , the truth table can be obtained as shown in Table 1:
[0062] Table 1
[0063]
[0064] , the two items of gpio1 and gpio2 are the states of the first signal output end gpio1 and the second signal output end gpio2 respectively, the value of high level represents the output of the enable signal, and the value of low level represents the absence of the enable signal. The V2 power-on state item is the state of the second power supply module 1024, the value of high level represents the output of the first power supply signal, and the value of low level represents the absence of the second power supply signal. In the energy storage circuit working state item, N represents that the energy storage circuit does not work, and Y represents that the energy storage circuit works.
[0065] , the second power supply signal output by the second power supply module 1024 is used to charge the energy storage circuit. In the forced restart power-off state of the power supply circuit, the second power supply signal is output through the energy storage circuit.
[0066] The present application realizes the detection circuit through the XNOR gate module D1 and the AND gate module D2, can control the working state of the energy storage circuit according to the real-time state of the power supply circuit 10, realizes the charging of the energy storage circuit when the power supply circuit 10 works normally, and prolongs the power supply time of one power supply through the energy storage circuit when the power supply circuit 10 is forced to restart and power off, so as to realize the power-off of multiple power supplies according to the power-off sequence respectively.
[0067] In some embodiments of the present application, the first energy storage circuit 1046 includes a switching device S1, a first capacitor C1 and a first resistor R1. The switching device S1 includes a control terminal ctral, a static contact com, a first moving contact ch1 and a second moving contact ch2, the second moving contact ch2 being an unconnected contact; the control terminal ctral is electrically connected with the output terminal of the AND gate module D2, and the static contact com is electrically connected with the output terminal of the second power supply module 1024.
[0068] The first end of the first capacitor C1 is electrically connected with the first moving contact ch1, and the second end of the first capacitor C1 is grounded; the first end of the first resistor R1 is electrically connected with the first moving contact ch1, and the second end of the first resistor R1 is electrically connected with the first end of the first capacitor C1; wherein, in the case that the output of the AND gate module D2 is high, the static contact com is electrically connected with the first moving contact ch1; in the case that the output of the AND gate module D2 is low, the static contact com is electrically connected with the second moving contact ch2.
[0069] In the embodiments of the present application, the energy storage circuit is a resistor-capacitor circuit (RC circuit). The energy storage circuit includes a switching device S1, a resistor and a capacitor. Taking the first energy storage circuit 1046 as an example, the first energy storage circuit 1046 includes a switching device S1, a first capacitor C1 and a first resistor R1. Among them, the switching device S1 is a single-pole double-throw switch.
[0070] The control terminal ctral of the switching device S1 is electrically connected with the output terminal of the AND gate module D2, when the AND gate module D2 outputs 1, the switching device S1 controls the static contact com to be electrically connected with the first moving contact ch1. At this time, the RC circuit is connected, if the power supply circuit 10 works normally, the first power supply signal output by the second power supply module charges the first capacitor C1. If the power supply circuit 10 is forced to restart power-off, the first capacitor C1 and the first resistor R1 are discharged to delay the power-off time of the power supply loop where the second power supply module is located.
[0071] When the AND gate module D2 outputs 1, the switching device S1 controls the static contact com to be electrically connected with the second moving contact ch2. Since the second moving contact ch2 is an unconnected (NC) contact, at this time the first energy storage circuit 1046 is equivalent to a bypass.
[0072] Exemplarily, as shown in Table 1, when the circuit is not powered on, gpio1=0, gpio2=0, V2=0, D2=0, the static contact com is connected with the second moving contact ch2 (hanging), at this time the first energy storage circuit 1046 is equivalent to a bypass. At this time, the power-on and power-off of the load 106 have no effect.
[0073] In the process of V1 being powered off and V2 being powered on, gpio1 = 0, gpio2 = 1, V2 = 0, D2 = 0, the static contact com is electrically connected with the second moving contact, and the first energy storage circuit 1046 is bypassed.
[0074] In the process of V1 being powered off and V2 being powered on, gpio1 = 0, gpio2 = 1, V2 = 0, D2 = 0, the static contact com is electrically connected with the second moving contact, and the first energy storage circuit 1046 is bypassed.
[0075] In the process of V1 being powered off and V2 being powered on, gpio1 = 0, gpio2 = 1, V2 = 0, D2 = 0, the static contact com is electrically connected with the second moving contact, and the first energy storage circuit 1046 is bypassed.
[0076] In the process of V1 being powered off and V2 being powered on, gpio1 = 0, gpio2 = 1, V2 = 0, D2 = 0, the static contact com is electrically connected with the second moving contact, and the first energy storage circuit 1046 is bypassed.
[0077] In some embodiments of the present application, the switch device S1 is further configured to control the static contact com to be disconnected from the first moving contact ch1 when the voltage value of the first power supply signal is less than the voltage threshold.
[0078] In the present embodiment, when the power supply circuit 10 is working normally, the second power supply module 1024 outputs a stable first power supply signal, and at this time, the voltage of the first power supply signal is maintained unchanged under the control of the second power supply module 1024, and the switch device S1 always controls the static contact com to be connected with the first moving contact ch1.
[0079] When the power supply circuit 10 is powered off abnormally, the second power supply module 1024 stops outputting the first power supply signal. At this time, the first energy storage circuit 1046 discharges through the first capacitor C1 and the first resistor R1, thereby outputting the first power supply signal to the output end of the second power supply module. Since the first capacitor C1 can store limited electrical energy, as the first capacitor C1 discharges, the first power supply signal output by the first energy storage circuit 1046 continuously decreases. When the voltage value of the first power supply signal decreases to less than the voltage threshold, the switch device S1 controls the static contact com to be disconnected from the first moving contact ch1, so that the first energy storage circuit 1046 is bypassed. At this time, the power supply circuit in which the second power supply module 1024 is located is powered off.
[0080] The present application can realize the regulation of the delay time of the delay circuit 104 without relying on software based on the discharge voltage of the capacitor.
[0081] In some embodiments of the present application, the first delay circuit 1043 corresponds to a first delay time, and the first delay time is associated with a capacitance value of the first capacitor C1 and a resistance value of the first resistor R1.
[0082] In the embodiments of the present application, the first delay circuit 1043 provides a delay power-off function for the power supply loop where the second power supply module 1024 is located. The first capacitor C1 and the first resistor R1 form an RC circuit. By adjusting the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1, the duration of the output power supply signal of the first delay circuit 1043, i.e., the first delay time, can be accurately adjusted.
[0083] The capacitance value of the first capacitor C1 and the resistance value of the first resistor R1 satisfy the following relationship:
[0084]
[0085] The voltage threshold is VL, the full voltage value of the first capacitor is V, the first delay time is t, the resistance value of the first resistor is R, the capacitance value of the first capacitor is C, and e is the natural base.
[0086] Suppose the minimum voltage value of the first power supply signal required by the power supply loop where the second power supply module 1024 is located is also the voltage threshold VL. Let the capacitance value of the first capacitor C1 be C, let the capacitor voltage of the first capacitor C1 when fully charged be V, let the resistance value of the first resistor R1 be R, and let the first delay time be t. The relationship between the first delay time and the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1 can be expressed by the above formula (2).
[0087] In some embodiments of the present application, the power supply circuit 10 further comprises a second capacitor C2, the first end of the second capacitor C2 is electrically connected to the output end of the power supply module 102, and the second end of the second capacitor C2 is grounded.
[0088] In the embodiments of the present application, the second capacitor C2 is a power supply capacitor and a filter capacitor for a power supply loop. By setting the second capacitor C2, the voltage stability of the power supply signal can be improved, the signal fluctuation in the power supply signal can be reduced, and the power supply quality can be improved.
[0089] In some embodiments of the present application, among the plurality of power supply modules 102, the longer the delay time corresponding to the delay circuit electrically connected to the power supply module with the earlier power-up sequence.
[0090] In the embodiments of the present application, among the plurality of power supply modules of the power supply circuit, the power supply module that is powered on first is powered off last.
[0091] For example, suppose there are n+1 power modules 102, which are powered on in reverse order of their numbers. That is, the (n+1)th power module 102 is powered on first, followed by the nth power module 102, then the (n-1)th power module 102, and so on, until the first power module 102 is powered on last. Generally speaking, the earlier the electrical equipment is powered on, the more important it is. Alternatively, the power-on process of electrical equipment powered on at night requires the support of electrical equipment powered on in the morning.
[0092] Therefore, when powering down, the (n+1)th power module 102, which was powered on earliest, needs to be powered down latest, thus the delay durations of the n delay circuits 104 decrease sequentially. For example, the first power module 102 powers down first, then the second power module 102, then the third power module 102, and so on, until the (n+1)th power module 102 powers down last.
[0093] For example, the delay duration t corresponding to the nth delay circuit 104 electrically connected to the output terminal of the (n+1)th power module 102 is... n The longest. The delay duration t corresponding to the nth delay circuit 104 electrically connected to the output terminal of the nth power module 102. n-1 Less than t n Similarly, the delay duration t1 corresponding to the first delay circuit 104 electrically connected to the output terminal of the first power module 102 is the shortest.
[0094] By setting the power-off sequence so that the load 106 that is powered on first is powered off last, it can be ensured that each load 106 can be powered off normally, thus improving the power supply reliability of the power supply circuit.
[0095] This application also proposes an electronic device, which includes the power supply circuit as described in any of the above embodiments, and thus can achieve all the same technical effects. To avoid repetition, it will not be described again here.
[0096] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0097] While the embodiments of the application have been shown and described, it is to be understood that the embodiments can be varied, modified, substituted and changed by those skilled in the art without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
Claims
1. A power supply circuit, characterized in that, include: A power control module, the power control module including multiple signal output terminals, the signal output terminals being used to output enable signals; Multiple power modules are provided, each of which is electrically connected to a plurality of signal output terminals; when a power module receives the enable signal, the power module powers on and outputs a power supply signal, which is used to supply power to the load. At least one delay circuit, the delay circuit being electrically connected to at least two of the signal output terminals and the output terminal of the power module; Wherein, when the delay circuit detects that the output terminal of one power module outputs the power supply signal, and at least two of the signal output terminals do not have the enable signal, the delay circuit outputs the power supply signal through the output terminal of the power module within the delay period.
2. The power supply circuit according to claim 1, characterized in that, The power module includes a first power module and a second power module; The signal output terminal includes a first signal output terminal and a second signal output terminal. The first signal output terminal is electrically connected to the first power module, and the second signal output terminal is electrically connected to the second power module. The delay circuit includes a first delay circuit, which includes a first detection circuit and a first energy storage circuit. The first detection circuit is electrically connected to the first signal output terminal, the second signal output terminal, and the output terminal of the second power module. The first detection circuit is used to control the first energy storage circuit to output the first power supply signal when the output terminal of the second power module outputs the first power supply signal and when there is no enable signal at the first signal output terminal and the second signal output terminal.
3. The power supply circuit according to claim 2, characterized in that, The power-on timings of the first power module and the second power module are adjacent, and the power-on timing of the second power module is earlier than that of the first power module.
4. The power supply circuit according to claim 2, characterized in that, The first detection circuit includes: The XNOR gate module has its first input terminal electrically connected to the first signal output terminal, and its second input terminal electrically connected to the second signal output terminal. An AND gate module is provided, wherein the first input terminal of the AND gate module is electrically connected to the output terminal of the XOR gate module, the second input terminal of the AND gate module is electrically connected to the output terminal of the second power supply module, and the output terminal of the AND gate module is electrically connected to the first energy storage circuit; wherein, when the output of the AND gate module is high, the electrical path between the output terminals of the first energy storage circuit and the second power supply module is open; when the output of the AND gate module is low, the electrical path between the output terminals of the first energy storage circuit and the second power supply module is closed.
5. The power supply circuit according to claim 4, characterized in that, The first energy storage circuit includes: A switching device, comprising a control terminal, a stationary contact, a first moving contact, and a second moving contact, wherein the second moving contact is an unconnected contact; the control terminal is electrically connected to the output terminal of the AND gate module, and the stationary contact is electrically connected to the output terminal of the second power supply module; A first capacitor, wherein a first terminal of the first capacitor is electrically connected to the first moving contact, and a second terminal of the first capacitor is grounded; A first resistor, the first end of which is electrically connected to the first moving contact, and the second end of which is electrically connected to the first end of the first capacitor; Specifically, when the output of the AND gate module is high, the stationary contact is electrically connected to the first moving contact; when the output of the AND gate module is low, the stationary contact is electrically connected to the second moving contact.
6. The power supply circuit according to claim 5, characterized in that, The switching device is further configured to control the stationary contact to disconnect from the first moving contact when the voltage value of the first power supply signal is less than a voltage threshold.
7. The power supply circuit according to claim 5, characterized in that, The delay duration corresponding to the first delay circuit is the first delay duration, which is related to the capacitance value of the first capacitor and the resistance value of the first resistor.
8. The power supply circuit according to any one of claims 1 to 7, characterized in that, Also includes: The second capacitor has its first terminal electrically connected to the output terminal of the power module, and its second terminal grounded.
9. The power supply circuit according to any one of claims 1 to 7, characterized in that, Among the multiple power modules, the delay circuit connected to the power module with the earlier power-on sequence has a longer delay duration.
10. An electronic device, characterized in that, include: The power supply circuit as described in any one of claims 1 to 9.