Semiconductor devices with trench gates and methods for forming them

Abstract

This invention provides a semiconductor device with a trench gate and a method for forming the same. First, a first exposure process and a first etching process are performed to form the bottom gate oxide of the trench. Next, a single-crystal silicon layer is formed. Then, a second exposure process and a second etching process are performed to form the trench, exposing the top surface of the bottom gate oxide. Finally, the trench gate is formed, located within the trench and on the bottom gate oxide. The first and second exposure processes use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. An unexpected benefit of this invention is that it allows for easier control of the bottom gate oxide thickness of the trench. Furthermore, forming the bottom gate oxide before the single-crystal silicon layer and the trench avoids the problem of premature sealing of the bottom gate oxide caused by high-density plasma processing after trench formation. This simplifies the process and provides the possibility of a thicker bottom gate oxide for small-critical-size MOS devices, contributing to increased device density.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device with a trench gate and a method for forming the same. Background Technology

[0002] In the Thick Bottom Oxide (TBO) process of metal-oxide-semiconductor field-effect transistors (MOSFETs), the thickness of the bottom gate oxide is typically increased to reduce Miller capacitance, improve switching speed, and optimize electric field distribution. Traditional TBO processes suffer from the following problems: the oxide layer formed by high-density plasma (HDP) deposition tends to accumulate heavily at the top of the trench, leading to sealing and insufficient gate oxide thickness at the bottom of the trench, thus hindering subsequent processes. Furthermore, the sidewall HDP process and pad oxide removal process often damage the bottom gate oxide, resulting in process failure. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device with a trench gate and a method for forming the same, in order to solve the problem that the bottom gate oxide is often damaged in the thick bottom gate oxide process, leading to process failure.

[0004] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor device with a trench gate, comprising:

[0005] A substrate is provided on which a first oxide layer is formed;

[0006] A first photoresist layer is formed on the first oxide layer, and a first exposure process and a first development process are performed to obtain a patterned first photoresist layer.

[0007] The first etching process is performed, using the patterned first photoresist layer as a mask to etch a portion of the first oxide layer, and the remaining first oxide layer serves as the bottom gate oxide of the trench;

[0008] A monocrystalline silicon layer is formed, the monocrystalline silicon layer covering the substrate and the bottom gate oxide;

[0009] A second photoresist layer is formed on the single-crystal silicon layer, and a second exposure process and a second development process are performed to obtain a patterned second photoresist layer.

[0010] A second etching process is performed to etch the single-crystal silicon layer using a patterned second photoresist layer as a mask to form trenches that expose the top surface of the bottom gate oxide.

[0011] A trench gate is formed, wherein the trench gate is located within the trench and covers the bottom gate oxide;

[0012] The first exposure process and the second exposure process use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer.

[0013] Optionally, the thickness of the first oxide layer is greater than the target thickness of the bottom gate oxide of the trench.

[0014] Optionally, a second oxide layer is formed before performing the second etching process step. The second oxide layer covers the monocrystalline silicon layer to protect the top surface of the monocrystalline silicon layer during the second etching process.

[0015] Optionally, the second etching process is an anisotropic dry etching process.

[0016] Optionally, the thickness of the monocrystalline silicon layer is greater than the sum of the target thickness of the bottom gate oxide of the trench and the target depth of the trench.

[0017] Optionally, the first photoresist layer is a negative photoresist, and the second photoresist layer is a positive photoresist.

[0018] Optionally, prior to the step of forming the trench gate, the method further includes:

[0019] A sacrificial layer is formed, which covers the sidewalls of the trench;

[0020] Remove the sacrificial layer and simultaneously remove the second oxide layer on the single-crystal silicon layer;

[0021] A gate oxide layer is formed, which covers the sidewalls of the trench.

[0022] Optionally, the gate oxide layer can be formed using a thermal oxidation process to repair overlay misalignment in the second exposure process.

[0023] Optionally, a thermal oxidation process is used to form the sacrificial layer to repair the damage to the sidewalls of the trench during the second etching process.

[0024] Based on the same inventive concept, the present invention also provides a semiconductor device with a trench gate, which is prepared by the method for forming a semiconductor device with a trench gate as described in any one of the above-mentioned methods.

[0025] In the method for forming a semiconductor device with a trench gate provided by the present invention, a first oxide layer is first formed on a substrate, a first photoresist layer is formed on the first oxide layer, and a first exposure process and a first development process are performed to obtain a patterned first photoresist layer; a first etching process is performed, using the patterned first photoresist layer as a mask to etch a portion of the first oxide layer, with the remaining first oxide layer serving as the bottom gate oxide of the trench; then a single-crystal silicon layer is formed, and a second photoresist layer is formed on the single-crystal silicon layer, and a second exposure process and a second development process are performed to obtain a patterned second photoresist layer; a second etching process is performed, using the patterned second photoresist layer as a mask to etch the single-crystal silicon layer to form a trench, the trench exposing the top surface of the bottom gate oxide, and then a trench gate is formed, the trench gate being located within the trench and on the bottom gate oxide, wherein the first exposure process and the second exposure process use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. An unexpected benefit of this invention is that by changing the thickness of the first oxide layer, the thickness of the bottom gate oxide of the trench can be more easily controlled. Furthermore, by forming the bottom gate oxide of the trench first and then forming the single-crystal silicon layer and the trench, the problem of premature sealing caused by high-density plasma forming the bottom gate oxide after trench formation is avoided. This simplifies the process, improves product reliability, and provides the possibility of a thick bottom gate oxide for small critical size MOS devices, which helps to increase device density. Attached Figure Description

[0026] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0027] Figure 1 This is a flowchart of a method for forming a semiconductor device with a trench gate according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the first oxide layer according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of the structure of a semiconductor device with a trench gate after forming a patterned first photoresist layer according to an embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the bottom gate oxide layer of the trench is formed, according to an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of the structure of a semiconductor device with a trench gate after forming a single-crystal silicon layer according to an embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the second oxide layer according to an embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of the structure of a semiconductor device with a trench gate after forming a patterned second photoresist layer according to an embodiment of the present invention.

[0034] Figure 8 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the trench is formed, according to an embodiment of the present invention.

[0035] Figure 9 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of a sacrificial layer, according to an embodiment of the present invention.

[0036] Figure 10 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the sacrificial layer has been removed, according to an embodiment of the present invention.

[0037] Figure 11 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the gate oxide layer according to an embodiment of the present invention.

[0038] Figure 12 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the trench gate according to an embodiment of the present invention.

[0039] In the attached figures: 10-substrate; 11-first oxide layer; 11a-bottom gate oxide of the trench; 12-patterned first photoresist layer; 13-single crystal silicon layer; 14-second oxide layer; 15-patterned second photoresist layer; 16-trench; 17-sacrificial layer; 18-gate oxide layer; 19-trench gate; 20-interlayer dielectric layer. Detailed Implementation

[0040] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0041] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0042] Figure 1 This is a flowchart illustrating a method for forming a semiconductor device with a trench gate according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a semiconductor device with a trench gate, including:

[0043] Step S10: Provide a substrate on which a first oxide layer is formed;

[0044] Step S20: A first photoresist layer is formed on the first oxide layer, and a first exposure process and a first development process are performed to obtain a patterned first photoresist layer.

[0045] Step S30: Perform the first etching process, using the patterned first photoresist layer as a mask to etch a portion of the first oxide layer, and the remaining first oxide layer as the bottom gate oxide of the trench;

[0046] Step S40: Form a single-crystal silicon layer, the single-crystal silicon layer covering the substrate and the bottom gate oxide;

[0047] Step S50: A second photoresist layer is formed on the single crystal silicon layer, and a second exposure process and a second development process are performed to obtain a patterned second photoresist layer.

[0048] Step S60: Perform a second etching process to etch the single-crystal silicon layer using a patterned second photoresist layer as a mask to form a trench, the trench exposing the top surface of the bottom gate oxide;

[0049] Step S70: Forming a trench gate, the trench gate being located within the trench and covering the bottom gate oxide; wherein the first exposure process and the second exposure process use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer.

[0050] Figure 2 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the first oxide layer according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a semiconductor device with a trench gate after forming a patterned first photoresist layer according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the bottom gate oxide layer of the trench is formed, according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of a semiconductor device with a trench gate after forming a single-crystal silicon layer according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the second oxide layer according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure of a semiconductor device with a trench gate after forming a patterned second photoresist layer according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the trench is formed, according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of a sacrificial layer, according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the sacrificial layer has been removed, according to an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of a semiconductor device with a trench gate after the formation of the gate oxide layer according to an embodiment of the present invention. Figure 12 This is a schematic diagram of the structure of a semiconductor device with a trench gate after trench gate formation according to an embodiment of the present invention. To make the above-mentioned objects, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 12 Specific embodiments of the present invention will be described in detail below.

[0051] like Figure 2 As shown, a substrate 10 is provided, which serves as an operating platform for subsequent processes. The substrate 10 can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, the substrate can be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 includes, for example, a silicon substrate and an epitaxial layer (EPI) on the silicon substrate.

[0052] Please continue to refer to this. Figure 2 A first oxide layer 11 is formed on the substrate 10 using thermal oxidation or chemical vapor deposition. The thickness of the first oxide layer 11 is, for example, 2000 to 2500 angstroms. The first oxide layer 11 serves as the thick bottom oxide (TBO) for subsequent trenches. Since subsequent etching processes will deplete a certain amount of the first oxide layer 11, the thickness of the first oxide layer 11 is greater than the target thickness of the bottom gate oxide of the trench. In this embodiment, the bottom gate oxide of the trench is formed using thermal oxidation or chemical vapor deposition. By changing the thickness of the first oxide layer 11, the thickness of the bottom gate oxide of the trench can be more easily controlled.

[0053] like Figure 3 As shown, a first photoresist layer is formed on the first oxide layer 11, and a first exposure process and a first development process are performed to obtain a patterned first photoresist layer 12.

[0054] like Figure 4 As shown, a first etching process is performed, in which a portion of the first oxide layer 11 is etched using a patterned first photoresist layer 12 as a mask, and the remaining first oxide layer 11 serves as the bottom gate oxide 11a of the trench. The first etching process is, for example, a dry etching process.

[0055] like Figure 5 As shown, a single-crystal silicon layer 13 is formed, which covers the substrate 10 and the bottom gate oxide 11a of the trench. The single-crystal silicon layer 13 can be formed using an epitaxial growth process. Considering the losses to the single-crystal silicon layer caused by subsequent etching and thermal oxidation processes, the thickness of the single-crystal silicon layer 13 is greater than the sum of the target thickness of the bottom gate oxide 11a of the trench and the target depth of the subsequently formed trench.

[0056] like Figure 6 As shown, before performing the second etching process, a second oxide layer 14 is formed. The second oxide layer 14 covers the monocrystalline silicon layer 13 to protect the top surface of the monocrystalline silicon layer from etching during the second etching process. The second oxide layer 14 is also called a pad oxide layer and is formed using a thermal oxidation process or a chemical vapor deposition process.

[0057] like Figure 7 As shown, a second photoresist layer is formed on the single-crystal silicon layer 13, covering the second oxide layer 14. A second exposure process and a second development process are then performed to obtain a patterned second photoresist layer 15. The first exposure process and the second exposure process use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. In this embodiment, the first photoresist layer is, for example, a negative photoresist, and the second photoresist layer is a positive photoresist.

[0058] like Figure 8 As shown, a second etching process is performed, using a patterned second photoresist layer 15 as a mask to etch the second oxide layer 14 and the single-crystal silicon layer 13 to form a trench 16, which exposes the top surface of the bottom gate oxide 11a. During etching of the single-crystal silicon layer 13, end-point detection (EPD) can be used to identify the underlying bottom gate oxide 11a. Upon identification of the underlying bottom gate oxide 11a, a small amount of over-etch (OE) is added, and the second etching process is stopped. The second etching process is, for example, an anisotropic dry etching process.

[0059] like Figure 9 As shown, a sacrificial layer 17 is formed, which covers the sidewalls of the trench 16. The material of the sacrificial layer 17 is, for example, silicon oxide. Preferably, the sacrificial layer 17 is formed by a thermal oxidation process, in which oxygen reacts with the trench sidewalls damaged in the second etching process to generate silicon oxide, thereby repairing the damage to the sidewalls of the trench 16 in the second etching process.

[0060] like Figure 10 As shown, the sacrificial layer 17 is removed, along with the second oxide layer 14 on the single-crystal silicon layer 13, and the polymer generated during the second etching process. A wet etching process can be used to remove the sacrificial layer 17, the second oxide layer 14, and the polymer. The solution used in the wet etching process is, for example, hydrofluoric acid. During the removal of the sacrificial layer 17, the second oxide layer 14, and the polymer, a small amount of the bottom gate oxide 11a of the trench is also etched; that is, when the first oxide layer is formed, the thickness of the first oxide layer is greater than the target thickness of the bottom gate oxide 11a of the trench.

[0061] like Figure 11 As shown, a gate oxide layer 18 is formed, which covers the sidewalls of the trench 16. Preferably, the gate oxide layer 18 is formed using a thermal oxidation process to correct overlay deviations in the second exposure process. In the thermal oxidation process, silicon on the sidewalls of the trench is consumed to form silicon oxide, with a conversion rate of approximately 0.6 Si to 1.0 SiO2. If there are fluctuations in the overlay (OVL) during the photolithography process in the second exposure process, the thermal oxidation process can cover the offset of the aforementioned overlay deviation. When the gate oxide layer 18 is formed using the thermal oxidation process, an oxide layer is also formed on the top surface of the single-crystal silicon layer, meaning the top surface of the single-crystal silicon layer is consumed. Therefore, when forming the single-crystal silicon layer 13, the thickness of the single-crystal silicon layer 13 is greater than the sum of the target thickness of the bottom gate oxide 11a of the trench and the target depth of the trench.

[0062] like Figure 12As shown, a trench gate 19 is formed, located within the trench 16 and on the bottom gate oxide 11a. The trench gate 19 is made of polycrystalline silicon and can be formed using a chemical vapor deposition process. After forming the trench gate 19, an interlayer dielectric (ILD) layer 20 is formed. The ILD layer is used to isolate the top layer metal and the bottom layer device, i.e., to isolate the trench gate 19 and the top layer metal. In this embodiment, a thick bottom oxide (TBO) is formed first, followed by the formation of the monocrystalline silicon layer 13 and the trench 16 within the monocrystalline silicon layer 13. This avoids the premature sealing caused by high-density plasma formation of the bottom gate oxide after trench formation and the bottom oxide damage caused by pad oxide removal. This effectively simplifies the process, improves product reliability, and provides the possibility of a thick bottom oxide (TBO) for small critical dimension (CD) MOS devices, effectively increasing device density.

[0063] Please continue to refer to this. Figure 12 This embodiment also provides a semiconductor device with a trench gate, fabricated using the method for forming a semiconductor device with a trench gate as described in any one of the above embodiments. The device includes a substrate 10 and a single-crystal silicon layer 13 located on the substrate 10. A bottom gate oxide 11a and a trench gate 19 are formed within the single-crystal silicon layer 13. A gate oxide layer 18 is formed between the trench gate 19 and the single-crystal silicon layer 13. An interlayer dielectric layer 20 is formed on the trench gate 19, which is used to isolate the top layer metal and the bottom layer device, i.e., to isolate the trench gate 19 and the top layer metal. This embodiment employs a thick bottom oxide (TBO) layer first, followed by the formation of a single-crystal silicon layer 13 and the trench 16 within it. This avoids the premature sealing caused by high-density plasma forming of the bottom gate oxide after trench formation and the bottom oxide damage caused during pad oxide removal. This effectively simplifies the process, improves product reliability, and provides the possibility of a thick bottom oxide (TBO) layer for small critical dimension (CD) MOS devices, thereby effectively increasing device density.

[0064] In summary, in the method for forming a semiconductor device with a trench gate provided in this embodiment of the invention, a first oxide layer is first formed on a substrate, a first photoresist layer is formed on the first oxide layer, and a first exposure process and a first development process are performed to obtain a patterned first photoresist layer; a first etching process is performed, using the patterned first photoresist layer as a mask to etch a portion of the first oxide layer, with the remaining first oxide layer serving as the bottom gate oxide of the trench; then a single-crystal silicon layer is formed, and a second photoresist layer is formed on the single-crystal silicon layer, and a second exposure process and a second development process are performed to obtain a patterned second photoresist layer; a second etching process is performed, using the patterned second photoresist layer as a mask to etch the single-crystal silicon layer to form a trench, the trench exposing the top surface of the bottom gate oxide, and then a trench gate is formed, the trench gate being located within the trench and on the bottom gate oxide, wherein the first exposure process and the second exposure process use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. An unexpected benefit of this invention is that by changing the thickness of the first oxide layer, the thickness of the bottom gate oxide of the trench can be more easily controlled. Furthermore, by forming the bottom gate oxide of the trench first and then forming the single-crystal silicon layer and the trench, the problem of premature sealing caused by high-density plasma forming the bottom gate oxide after trench formation is avoided. This simplifies the process, improves product reliability, and provides the possibility of a thick bottom gate oxide for small critical size MOS devices, which helps to increase device density.

[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0066] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A method of forming a semiconductor device having a trench gate, characterized by, The method comprises the following steps: providing a substrate, wherein a first oxide layer is formed on the substrate; forming a first photoresist layer on the first oxide layer, and performing a first exposure process and a first development process to obtain a patterned first photoresist layer; performing a first etching process to etch part of the first oxide layer as a mask of the patterned first photoresist layer, and the remaining first oxide layer as a bottom gate oxide of a trench; forming a single crystal silicon layer, wherein the single crystal silicon layer covers the substrate and the bottom gate oxide; forming a second photoresist layer on the single crystal silicon layer, and performing a second exposure process and a second development process to obtain a patterned second photoresist layer; performing a second etching process to etch the single crystal silicon layer as a mask of the patterned second photoresist layer, so as to form a trench, wherein the trench exposes a top surface of the bottom gate oxide; forming a trench gate, wherein the trench gate is located in the trench and covers the bottom gate oxide; wherein the first exposure process and the second exposure process use the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer.

2. The method for forming a semiconductor device having a trench gate according to claim 1, wherein The thickness of the first oxide layer is greater than the target thickness of the bottom gate oxide of the trench.

3. The method for forming a semiconductor device having a trench gate according to claim 1, wherein Before performing the second etching process, a second oxide layer is formed, wherein the second oxide layer covers the single crystal silicon layer, so as to protect the top surface of the single crystal silicon layer in the second etching process.

4. The method for forming a semiconductor device having a trench gate according to claim 1, wherein The second etching process is an anisotropic dry etching process.

5. The method for forming a semiconductor device having a trench gate according to claim 1, wherein The thickness of the single crystal silicon layer is greater than the sum of the target thickness of the bottom gate oxide of the trench and the target depth of the trench.

6. The method for forming a semiconductor device having a trench gate according to claim 1, wherein The first photoresist layer is a negative photoresist, and the second photoresist layer is a positive photoresist.

7. The method for forming a semiconductor device having a trench gate according to claim 3, wherein Before the step of forming the trench gate, the method further comprises the following steps: forming a sacrificial layer, wherein the sacrificial layer covers the sidewall of the trench; removing the sacrificial layer, and simultaneously removing the second oxide layer on the single crystal silicon layer; forming a gate oxide layer, wherein the gate oxide layer covers the sidewall of the trench.

8. The method for forming a semiconductor device having a trench gate according to claim 7, wherein The gate oxide layer is formed by a thermal oxidation process, so as to repair the overlaying deviation in the second exposure process.

9. The method for forming a semiconductor device having a trench gate according to claim 7, wherein The sacrificial layer is formed by a thermal oxidation process, so as to repair the damage to the sidewall of the trench in the second etching process.

10. A semiconductor device having a trench gate, characterized by, The semiconductor device with a trench gate is prepared by using the method according to any one of claims 1-9.

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