Radio frequency switch circuit and forming method
By adding a shallow trench isolation structure and an air gap to the RF switching circuit, the parasitic capacitance problem between the source and drain terminals and the underlying silicon was solved, achieving uniform voltage distribution and improved power handling capability.
Patent Information
- Application Number
- CN202511158252.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-18
- Publication Date
- 2025-11-25
AI Technical Summary
In existing RF switching circuits, the parasitic capacitance between the source and drain terminals of the MOSFET and the underlying silicon is relatively large, resulting in uneven voltage distribution and affecting power handling capability.
Increasing the thickness of the shallow trench isolation structure in the RF switching circuit and forming an air gap therein reduces the parasitic capacitance between the source and drain terminals and the underlying silicon, thereby increasing the equivalent lateral off-state capacitance.
By reducing parasitic capacitance, a uniform distribution of voltage differences at each stage of the RF switching circuit is achieved, thereby improving power handling capability.
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Figure CN121013401A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a radio frequency switch circuit and its fabrication method. Background Technology
[0002] In radio frequency (RF) front-end circuitry, RF switching circuits are essential components. RF switching circuits are used to electrically connect antennas to the transmit or receive paths of an RF system, allowing multiple components to be connected to the antenna. Typically, RF switching circuits are configured using a stack of multiple MOSFETs.
[0003] Please refer to Figure 1 The existing RF switch circuit includes an SOI (Single-Instrument Unit), which comprises an adjacent first region A and a second region B. Both the first region A and the second region B's SOI include a stacked bottom silicon 110, a buried oxide layer 120, and a top silicon 130. A spaced gate 140 is formed on the surface of the top silicon 130, a gate oxide layer 150 is formed below the gate 140, and sidewalls 160 are formed on both sides of the gate 140. A source terminal 170 and a drain terminal 180 are also present within the top silicon 130 on both sides of the gate 140.
[0004] Then, the parasitic capacitance between the bottom of the source terminal 170 and the drain terminal 180 of the first two stages of the stack and the bottom silicon 110 is relatively large. The large parasitic capacitance has a significant impact on the voltage distribution of the RF switching circuit. Furthermore, the larger the parasitic capacitance, the greater the voltage difference in the RF switching circuit, the worse the distribution uniformity, and the degraded power handling capability of the RF switching circuit. Summary of the Invention
[0005] The purpose of this invention is to provide a radio frequency (RF) switch circuit and its fabrication method, which can reduce the parasitic capacitance between the source terminal and the underlying silicon layer, as well as the parasitic capacitance between the drain terminal and the underlying silicon layer. This results in smaller voltage differences between each stage of the RF switch circuit, more uniform voltage distribution, and thus improved power handling capability of the RF switch circuit.
[0006] To achieve the above objectives, the present invention provides a method for forming a radio frequency switch circuit, comprising:
[0007] SOIs are provided, each of which includes a stacked bottom silicon layer, a buried oxide layer, and a top silicon layer.
[0008] A plurality of spaced-apart first shallow trench isolation structures and a plurality of spaced-apart active regions are formed within the top silicon layer, wherein the first shallow trench isolation structures and the active regions are adjacent to each other.
[0009] The first two levels of the active region are designated as the first region, and the rest are designated as the second region. The first shallow trench isolation structure, buried oxide layer and a partial thickness of the underlying silicon in the first region are etched to form a second shallow trench spaced apart. The width of the second shallow trench in the underlying silicon is greater than the width in the buried oxide layer.
[0010] The first two levels of the active region are designated as the first region, and the rest are designated as the second region. Starting from the surface of the first shallow trench isolation structure in the first region, the first shallow trench isolation structure, the buried oxide layer, and a portion of the underlying silicon are etched downwards in sequence. A portion of the underlying silicon is also etched laterally to form a second shallow trench with intervals. The width of the second shallow trench in the underlying silicon is greater than the width in the buried oxide layer.
[0011] A gate structure of a MOS transistor is formed on the surface of the top silicon in both the first and second regions. The source and drain terminals of the MOS transistor are formed in the top silicon on both sides of each gate structure, wherein the second shallow trench isolation structure is located below the source and drain terminals in the first region.
[0012] Optionally, in the method for forming the radio frequency switch circuit, the method of forming a plurality of spaced-apart first shallow trench isolation structures and a plurality of spaced-apart active regions within the top silicon layer includes:
[0013] The top silicon layer is etched to expose the surface of the buried oxide layer, thereby forming a first shallow trench within the top silicon layer;
[0014] The first shallow trench is filled with oxide to form a first shallow trench isolation structure.
[0015] Optionally, in the method for forming the radio frequency switch circuit, the etching precision of the top silicon layer to form the first shallow trench is 0.1 μm to 0.2 μm.
[0016] Optionally, in the method for forming the radio frequency switch circuit, after providing the SOI, the method further includes:
[0017] A pad oxide layer and a nitride layer are sequentially formed on the surface of the top silicon in both the first and second regions.
[0018] Optionally, in the method for forming the radio frequency switch circuit, the nitride layer, the pad oxide layer, and the top silicon layer are etched sequentially to form a first shallow trench isolation structure.
[0019] Optionally, in the method for forming the radio frequency switch circuit, after filling the second shallow trench with oxide to form the second shallow trench isolation structure, the method further includes:
[0020] Remove the nitride layer and the second nitride layer to expose the surface of the top silicon layer.
[0021] Optionally, in the method for forming the radio frequency switch circuit, the gate structure includes a gate oxide layer and a gate located on the surface of the active region, and sidewalls located on both sides of the gate oxide layer and the gate.
[0022] Optionally, in the method for forming the radio frequency switch circuit, the resistance of the underlying silicon is greater than 1000 ohm·cm.
[0023] Optionally, in the method for forming the radio frequency switch circuit, a first shallow trench isolation structure, a buried oxide layer, and a partially thick layer of underlying silicon in the first region are dry-etched to form a second shallow trench spaced apart. A portion of the underlying silicon is wet-etched starting from the portion of the second shallow trench located within the underlying silicon, such that the width of the second shallow trench located in the underlying silicon is greater than the width located in the buried oxide layer.
[0024] Accordingly, the present invention provides a radio frequency switching circuit, comprising:
[0025] SOI, wherein each SOI comprises a stacked bottom silicon, a buried oxide layer and a top silicon;
[0026] The first region comprises several spaced-apart second shallow trench isolation structures and several spaced-apart active regions within the top silicon, buried oxide layer and part of the thickness of the bottom silicon. The second shallow trench isolation structures and the active regions are adjacent to each other, and an air gap is formed within the second shallow trench isolation structures. The first region consists of the first two active regions, and the second region consists of the remaining active regions.
[0027] The first shallow trench isolation structure and the active region are all located in the top silicon, buried oxide layer and part of the thickness of the bottom silicon in the second region. The first shallow trench isolation structure and the active region are adjacent to each other. The width of the second shallow trench isolation structure located in the bottom silicon is greater than the width of the second shallow trench isolation structure located in the buried oxide layer.
[0028] The gate structure of the MOS transistor is located on the surface of the top silicon in the first and second regions, and the source and drain terminals are located in the top silicon on both sides of the gate structure, wherein the second shallow trench isolation structure is located below the source and drain terminals in the first region.
[0029] In the RF switch circuit and its formation method provided by this invention, the embodiments of this invention increase the thickness of the shallow trench isolation structure in the first two stages of the RF circuit and form an air gap therein. This reduces the parasitic capacitance between the source and drain terminals of the first two stages of the RF switch circuit and the underlying silicon, and increases the equivalent lateral off-state capacitance. This results in a smaller voltage difference between each stage of the RF switch circuit, a more uniform voltage distribution, and improved power handling capability of the RF switch circuit. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the structure of a prior art radio frequency switch circuit;
[0031] Figure 2 This is a flowchart of a method for forming a radio frequency switch circuit according to an embodiment of the present invention;
[0032] Figures 3 to 8 This is a schematic diagram of the structure of the radio frequency switch circuit according to an embodiment of the present invention;
[0033] In the diagram: 110-bottom silicon, 120-buried oxide layer, 130-top silicon layer, 140-gate, 150-gate oxide layer, 160-sidewall, 170-source, 180-drain, 201-bottom silicon, 202-buried oxide layer, 203-active region, 204-pad oxide layer, 205-nitride layer, 206-first shallow trench, 207-first shallow trench isolation structure, 208-second shallow trench, 209-second shallow trench isolation structure, 210-air gap, 211-gate, 212-gate oxide layer, 213-sidewall, 214-source, 215-drain. Detailed Implementation
[0034] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0035] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0036] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0037] Please refer to Figure 2 The present invention provides a method for forming a radio frequency switch circuit, comprising:
[0038] S11: Provides SOI, each SOI consisting of a stacked bottom silicon, buried oxide layer and top silicon;
[0039] S12: Several first shallow trench isolation structures and several active regions are formed at intervals in the top silicon layer, with the first shallow trench isolation structures and active regions being adjacent to each other.
[0040] S13: The first two levels of the active region are designated as the first region, and the rest are designated as the second region. The first shallow trench isolation structure, buried oxide layer and part of the thickness of the bottom silicon in the first region are etched to form the second shallow trenches that are spaced apart. The width of the second shallow trenches in the bottom silicon is greater than the width in the buried oxide layer.
[0041] S14: The first two levels of the active region are designated as the first region, and the rest are designated as the second region. Starting from the surface of the first shallow trench isolation structure in the first region, the first shallow trench isolation structure, the buried oxide layer, and a portion of the underlying silicon are etched downwards in sequence, and a portion of the underlying silicon is etched laterally to form a second shallow trench with intervals. The width of the second shallow trench in the underlying silicon is greater than the width in the buried oxide layer.
[0042] S15: A gate structure of a MOS transistor is formed on the surface of the top silicon of both the first and second regions. The source and drain terminals of the MOS transistor are formed in the top silicon on both sides of each gate structure, wherein the second shallow trench isolation structure is located below the source and drain terminals of the first region.
[0043] Please refer to Figure 3 The system provides an SOI, which includes a bottom silicon layer 201 and a buried oxide layer 202 and a top silicon layer sequentially located on the surface of the bottom silicon layer 201. The bottom silicon layer 201 is a high-resistivity substrate with a resistance greater than 1000 ohm·cm. Ions are implanted into the top silicon layer to form an ion implantation region.
[0044] Next, please refer to Figure 4 The nitride layer 205, the pad oxide layer 204, and the ion implantation region are etched to form multiple first shallow trenches 206 in the ion implantation region. The surface of the buried oxide layer 202 is exposed in the first shallow trenches 206. The etching precision of the first shallow trenches 206 is 0.1μm to 0.2μm, specifically 0.15μm. Therefore, the first shallow trenches 206 are 0.15μm.
[0045] Next, please refer to Figure 5 An oxide layer is filled into the first shallow trench 206 and the surface of the oxide layer is ground to form multiple first shallow trench isolation structures 207. The multiple first shallow trench isolation structures 207 divide the ion implantation area into multiple active regions 203. Each active region 203 is used to form a MOS transistor, so multiple stacked MOS transistors can be formed. The first two active regions are selected as the first region A, and the rest are selected as the second region B.
[0046] Next, please refer to Figure 6 The first shallow trench isolation structure 207, buried oxide layer 202, and a partial thickness of bottom silicon 201 are etched downward from the surface of the first shallow trench isolation structure 207 in the first region A. The thickness of the bottom silicon 201 is greater than 0.5 μm, and a portion of the bottom silicon 201 is etched laterally to widen the bottom of the second shallow trench 208. The width of one side of the laterally etched bottom silicon 201 is greater than 0.5 μm, thereby widening the width of the second shallow trench 208 within the bottom silicon 201.
[0047] Next, please refer to Figure 7 An oxide layer is filled into the second shallow trench 208 and the surface of the oxide layer is ground to form a second shallow trench isolation structure 209. Therefore, the width of the second shallow trench isolation structure 209 at the bottom silicon 201 is greater than the width at the buried oxide layer 202. Due to the large depth-to-width ratio of the second shallow trench, an air gap 210 is formed at the bottom of the second shallow trench isolation structure 209. The size of the air gap 210 may be an equilateral triangle.
[0048] Next, please refer to Figure 8 The nitride layer 205 and the pad oxide layer 204 of the first region A and the second region B, as well as a portion of the thickness of the first shallow trench isolation structure 207 and the second shallow trench isolation structure 209, are removed to expose the surface of the active region 203, making the first shallow trench isolation structure 207 and the second shallow trench isolation structure 209 flush with the surface of the active region 203. The thickness of the second shallow trench isolation structure 209 is greater than that of the first shallow trench isolation structure 207. Next, a gate 211 is formed on the surface of the active region 203, and a gate oxide layer 212 is pre-formed below the gate 211. Then, sidewalls 213 are formed on both sides of the gate 211 and the gate oxide layer 212. A source terminal 214 and a drain terminal 215 are formed in the active regions 203 on both sides of the gate 211, respectively. The above gate structure and the source terminal 214 and drain terminal 215 are conventional technologies and will not be described in detail here. In this embodiment of the invention, the distance from the source and drain terminals of the MOSFET to the surface of the underlying silicon 201 is increased in the first region. This increases the thickness of the oxide layer between the source and drain terminals of the MOSFET in the first region and the underlying silicon 201, thus reducing the parasitic capacitance between the source and drain terminals of the MOSFET in the first region and the underlying silicon 201. Furthermore, this embodiment of the invention does not change the parasitic capacitance between the source and drain terminals of the MOSFET in the second region and the underlying silicon 201, and therefore does not affect the function of the second region.
[0049] Please continue to refer to Figure 8The present invention also provides a radio frequency switch circuit formed by a method for forming a radio frequency switch circuit, comprising: SOI, each SOI including a stacked bottom silicon 201, a buried oxide layer 202 and a top silicon; a plurality of spaced second shallow trench isolation structures 209 and a plurality of spaced active regions 203, each located within the top silicon, buried oxide layer 202 and a portion of the thickness of the bottom silicon 201 in a first region, the second shallow trench isolation structures 209 and the active regions 203 being adjacent; and a plurality of spaced first shallow trench isolation structures 207 and a plurality of spaced active regions 207, each located within the top silicon, buried oxide layer 202 and a portion of the thickness of the bottom silicon 201 in a second region. 3. A first shallow trench isolation structure 207 and an active region 203 are adjacent, wherein the first region is the first two active regions, and the second region is the remaining active regions. An air gap 210 is formed within the second shallow trench isolation structure 209. The width of the second shallow trench isolation structure 209 located within the bottom silicon layer 201 is greater than the width of the second shallow trench isolation structure 209 located within the buried oxide layer 202. A gate structure of a MOS transistor is located on the surface of the top silicon layer in both the first and second regions, and a source terminal 214 and a drain terminal 215 are located in the top silicon layer on both sides of the gate structure, respectively. The second shallow trench isolation structure 209 is partially located below the source terminal 214 and drain terminal 215 in the first region. The gate structure includes a gate oxide layer 212, a gate 211, and a sidewall 213.
[0050] In summary, in the RF switch circuit and its formation method provided in this embodiment of the invention, the thickness of the shallow trench isolation structure is increased in the first two stages of the RF circuit, and an air gap is formed therein. This reduces the parasitic capacitance between the source and drain terminals of the first two stages of the RF switch circuit and the underlying silicon, and increases the equivalent lateral off-state capacitance. This results in a smaller voltage difference between each stage of the RF switch circuit, a more uniform voltage distribution, and improved power handling capability of the RF switch circuit.
[0051] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for forming a radio frequency switch circuit, characterized in that, include: SOIs are provided, each of which includes a stacked bottom silicon layer, a buried oxide layer, and a top silicon layer. A plurality of spaced-apart first shallow trench isolation structures and a plurality of spaced-apart active regions are formed within the top silicon layer, wherein the first shallow trench isolation structures and the active regions are adjacent to each other. The first two levels of the active region are designated as the first region, and the rest are designated as the second region. Starting from the surface of the first shallow trench isolation structure in the first region, the first shallow trench isolation structure, the buried oxide layer, and a portion of the underlying silicon are etched downwards in sequence. A portion of the underlying silicon is also etched laterally to form a second shallow trench with intervals. The width of the second shallow trench in the underlying silicon is greater than the width in the buried oxide layer. The second shallow trench is filled with oxide to form a second shallow trench isolation structure. An air gap is formed in the second shallow trench isolation structure. The thickness of the second shallow trench isolation structure is greater than the thickness of the first shallow trench isolation structure. The width of the second shallow trench isolation structure located in the bottom silicon is greater than the width of the second shallow trench isolation structure located in the top silicon. A gate structure of a MOS transistor is formed on the surface of the top silicon in both the first and second regions. The source and drain terminals of the MOS transistor are formed in the top silicon on both sides of each gate structure, wherein the second shallow trench isolation structure is located below the source and drain terminals in the first region.
2. The method for forming a radio frequency switch circuit as described in claim 1, characterized in that, The method for forming a plurality of spaced-apart first shallow trench isolation structures and a plurality of spaced-apart active regions within the top silicon layer includes: The top silicon layer is etched to expose the surface of the buried oxide layer, thereby forming a first shallow trench within the top silicon layer; The first shallow trench is filled with oxide to form a first shallow trench isolation structure.
3. The method for forming a radio frequency switch circuit as described in claim 2, characterized in that, The etching precision for forming the first shallow trench on the top silicon layer is 0.1 μm to 0.2 μm.
4. The method for forming a radio frequency switch circuit as described in claim 1, characterized in that, Starting from the surface of the first shallow trench isolation structure in the first region, the first shallow trench isolation structure, the buried oxide layer, and a portion of the underlying silicon are etched downwards in sequence. In the lateral etching of the underlying silicon, the thickness of the etched underlying silicon is greater than 0.5 μm, and the single-sided width of the lateral etching of the underlying silicon is greater than 0.5 μm.
5. The method for forming a radio frequency switch circuit as described in claim 1, characterized in that, After providing SOI, it also includes: A pad oxide layer and a nitride layer are sequentially formed on the surface of the top silicon in both the first and second regions.
6. The method for forming a radio frequency switch circuit as described in claim 5, characterized in that, The nitride layer, the pad oxide layer, and the top silicon layer are etched sequentially to form the first shallow trench isolation structure.
7. The method for forming a radio frequency switch circuit as described in claim 6, characterized in that, After filling the second shallow trench with oxide to form the second shallow trench isolation structure, the process further includes: Remove the nitride layer and the second nitride layer to expose the surface of the top silicon layer.
8. The method for forming a radio frequency switch circuit as described in claim 1, characterized in that, The gate structure includes a gate oxide layer and a gate located on the surface of the active region, and sidewalls located on both sides of the gate oxide layer and the gate.
9. The method for forming a radio frequency switch circuit as described in claim 1, characterized in that, Dry etching is used to etch the first shallow trench isolation structure, buried oxide layer, and a portion of the underlying silicon in the first region to form a second shallow trench spaced apart. Wet etching is then performed on a portion of the underlying silicon starting from the portion of the second shallow trench located within the underlying silicon, such that the width of the second shallow trench on the underlying silicon is greater than the width on the buried oxide layer.
10. A radio frequency switch circuit formed by the radio frequency switch circuit forming method according to any one of claims 1 to 9, characterized in that, include: SOI, wherein each SOI comprises a stacked bottom silicon, a buried oxide layer and a top silicon; The first region comprises several spaced-apart second shallow trench isolation structures and several spaced-apart active regions within the top silicon, buried oxide layer and part of the thickness of the bottom silicon. The second shallow trench isolation structures and the active regions are adjacent to each other, and an air gap is formed within the second shallow trench isolation structures. The first region consists of the first two active regions, and the second region consists of the remaining active regions. The first shallow trench isolation structure and the active region are all located in the top silicon, buried oxide layer and part of the thickness of the bottom silicon in the second region. The first shallow trench isolation structure and the active region are adjacent to each other. The width of the second shallow trench isolation structure located in the bottom silicon is greater than the width of the second shallow trench isolation structure located in the buried oxide layer. The gate structure of the MOS transistor is located on the surface of the top silicon in the first and second regions, and the source and drain terminals are located in the top silicon on both sides of the gate structure, wherein the second shallow trench isolation structure is located below the source and drain terminals in the first region.