Imaging device

Abstract

The first structure (171) has a photoelectric conversion unit (110), one of a pair of first wiring layers (151b, 152a), and a first substrate (141). The second structure (172) has the other of the pair of first wiring layers (151b, 152a) and a second substrate (142). A first via hole (161) penetrates through the first substrate (141) and directly connects the first wiring layer pair (151b, 152a). The charge storage region (35) is provided on one of a plurality of substrates including the first substrate (141) and the second substrate (142). The charge storage region (35) is electrically connected to the first via hole (161) and stores charge. One of the pair of first wiring layers (151b, 152a), the first substrate (141), the other of the pair of first wiring layers (151b, 152a), and the second substrate (142) are arranged in this order.

Description

Technical Field

[0001] This disclosure relates to camera devices. Background Technology

[0002] Camera devices are used in digital cameras, digital video cameras, and the like. Known types include enlarged camera devices represented by MOS-type image sensors such as CMOS (Complementary Metal Oxide Semiconductor) and charge-transfer camera devices represented by CCD (Charge Coupled Device) image sensors. In recent years, camera devices, especially those mounted on mobile devices such as smartphones and mobile phones with integrated cameras, have been constrained by space limitations, and miniaturization of camera devices is being explored.

[0003] As a means of miniaturization, integration is considered not only in the planar direction of the camera device but also in the height direction.

[0004] Patent Document 1 discloses a structure in which the transistors constituting the pixel are disposed on multiple wafers as a discrete unit pixel of an image sensor having a three-dimensional structure.

[0005] Prior art literature

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2008-536330 Summary of the Invention

[0008] There is a need for technology suitable for providing small and low-noise camera devices.

[0009] The camera device disclosed herein has at least one pixel.

[0010] Each pixel in the at least one pixel has:

[0011] The first structure includes a photoelectric conversion unit that converts light into charge, one side of a first wiring layer pair, and a first substrate;

[0012] The second structure has the other side of the first wiring layer pair and a second substrate;

[0013] A first via penetrates the first substrate, directly connecting the first wiring layer pairs; and

[0014] A charge storage region is disposed on one of a plurality of substrates including the first substrate and the second substrate, stores the charge, and is electrically connected to the first via.

[0015] The first wiring layer pair, the first substrate, the other side of the first wiring layer pair, and the second substrate are arranged in this order.

[0016] The technology disclosed herein is suitable for providing a small and low-noise imaging device. Attached Figure Description

[0017] Figure 1A This is a circuit diagram of the camera device according to the first embodiment.

[0018] Figure 1B This is a cross-sectional view of the camera device according to the first embodiment.

[0019] Figure 1C This is a cross-sectional view showing the structure of the periphery of the first substrate.

[0020] Figure 2 This is a cross-sectional view of the camera device involved in the first reference method.

[0021] Figure 3 This is a cross-sectional view of the camera device involved in the second reference method.

[0022] Figure 4A This is the circuit diagram of the camera device with transistor configuration (6) in Table 1.

[0023] Figure 4B This is a cross-sectional view of the camera device with transistor configuration (6) in Table 1.

[0024] Figure 5 This is the circuit diagram of the camera device with transistor configuration (4) in Table 1.

[0025] Figure 6A This is an explanatory diagram of the manufacturing method of the camera device according to the first embodiment.

[0026] Figure 6B This is an explanatory diagram of the manufacturing method of the camera device according to the first embodiment.

[0027] Figure 6C This is an explanatory diagram of the manufacturing method of the camera device according to the first embodiment.

[0028] Figure 6D This is an explanatory diagram of the manufacturing method of the camera device according to the first embodiment.

[0029] Figure 6E This is an explanatory diagram of the manufacturing method of the camera device according to the first embodiment.

[0030] Figure 7 This is a flowchart of the manufacturing method of the camera device according to the first embodiment.

[0031] Figure 8A This is a circuit diagram of the camera device according to the second embodiment.

[0032] Figure 8B This is a cross-sectional view of the camera device according to the second embodiment.

[0033] Figure 9A This is a circuit diagram of the camera device according to the third embodiment.

[0034] Figure 9B This is a cross-sectional view of the camera device according to the third embodiment.

[0035] Figure 10A This is a circuit diagram of the camera device according to the fourth embodiment.

[0036] Figure 10B This is a cross-sectional view of the camera device according to the fourth embodiment.

[0037] Figure 10C This is a cross-sectional view showing the structure of the periphery of the second substrate.

[0038] Figure 11 This is a circuit diagram of the camera device with transistor configuration (11) in Table 3B.

[0039] Figure 12 This is the circuit diagram of the camera device with transistor configuration (12) in Table 3B.

[0040] Figure 13 This is a circuit diagram of the camera device with transistor configuration (19) in Table 3D.

[0041] Figure 14 This is a circuit diagram of the camera device with transistor configuration (23) in Table 3D.

[0042] Figure 15 This is a circuit diagram of the camera device with transistor configuration (24) in Table 3D.

[0043] Figure 16 This is a circuit diagram of the camera device with transistor configuration (35) in Table 3F.

[0044] Figure 17 This is a circuit diagram of the camera device with transistor configuration (36) in Table 3F.

[0045] Figure 18A This is a circuit diagram of the camera device according to the fifth embodiment.

[0046] Figure 18B This is a cross-sectional view of the camera device according to the fifth embodiment.

[0047] Figure 18CThis is a cross-sectional view showing the structure of the periphery of the third substrate.

[0048] Figure 19 This is the circuit diagram of the camera device with transistor configuration (7) in Table 4B.

[0049] Figure 20A This is a circuit diagram of the camera device according to the sixth embodiment.

[0050] Figure 20B This is a cross-sectional view of the camera device according to the sixth embodiment.

[0051] Figure 21 A diagram schematically illustrating an example configuration of a camera system according to an embodiment. Detailed Implementation

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The numerical values, shapes, materials, constituent elements, positions and connection methods of constituent elements, steps, and order of steps shown in the embodiments are merely examples and are not intended to limit the present disclosure.

[0053] In the implementation, terms such as "upper" and "lower" are merely used to specify the mutual configuration between components, and are not intended to limit the posture of the camera device during use or the posture of the camera device components and manufacturing equipment during the manufacturing process.

[0054] In this implementation, a "via" refers to wiring that connects different wiring layers. A via includes a conductor disposed within it. A "trench" refers to a groove. A "substrate" can also be referred to as a "wafer".

[0055] In implementation, "connection" and "electrical connection" can be substituted for each other as long as there is no particular contradiction.

[0056] (First Embodiment)

[0057] Figure 1A and Figure 1B These are circuit diagrams and cross-sectional views of the imaging device 101 according to the first embodiment. The imaging device 101 is a front-side illumination (FSI) type. The imaging device 101 includes a photoelectric conversion unit 110, a protective film 119, a color filter 120, a microlens 130, a reset transistor 13, an amplifying transistor 11, a selection transistor 12, a first substrate 141, a second substrate 142, a first plurality of wiring layers 151, a second plurality of wiring layers 152, a first via 161, and a via 166. These elements are included in the pixels 190 of the imaging device 101. In a typical example, these elements are included in each pixel 190 of the plurality of pixels 190 of the imaging device 101. Figure 1B In the diagram, the first plurality of routing layers 151 and the second plurality of routing layers 152 are depicted in a simplified manner.

[0058] like Figure 1A As shown, the camera device 101 includes a charge accumulation node 30. The charge accumulation node 30 accumulates charge. The charge accumulation node 30 includes... Figure 1B The charge accumulation region 35 is shown.

[0059] The photoelectric conversion unit 110 includes a photoelectric conversion film 111, a pixel electrode 112, and a counter electrode 113. The photoelectric conversion film 111 is disposed between the pixel electrode 112 and the counter electrode 113. The photoelectric conversion film 111 is located outside the first substrate 141. In this embodiment, the photoelectric conversion film 111 contains an organic material. However, the photoelectric conversion film 111 may also contain an inorganic material.

[0060] The microlens 130 has a light-focusing function, concentrating light onto the photoelectric conversion unit 110. The color filter 120 performs color separation. The protective film 119 protects the photoelectric conversion unit 110.

[0061] like Figure 1A As shown, the photoelectric conversion unit 110 is electrically connected to one of the source and drain of the reset transistor 13 and the gate 11g of the amplification transistor 11. Specifically, the pixel electrode 112 is electrically connected to them. One of the source and drain of the reset transistor 13 constitutes a charge accumulation region 35. That is, the charge accumulation region 35 is included in the reset transistor 13. The charge accumulation region 35 is a diffusion region disposed on the substrate. One of the source and drain of the amplification transistor 11 is electrically connected to one of the source and drain of the selection transistor 12.

[0062] Specifically, the photoelectric conversion unit 110 converts light into electrical charge via the photoelectric conversion film 111. This charge can be stored in the charge storage node 30. A power supply voltage is supplied to the other of the source and drain of the amplifying transistor 11 via voltage line 21. The amplifying transistor 11 outputs a signal corresponding to the potential of the charge storage node 30 to the signal line 22 via the selection transistor 12. The selection transistor 12 determines the timing of the signal output from the amplifying transistor 11. Specifically, a voltage is supplied to the gate 12g of the selection transistor 12 in the pixel 190 selected by a control circuit (not shown). This turns the selection transistor 12 on, outputting a signal from the other of its source and drain.

[0063] A reset voltage is supplied to the other of the source and drain of the reset transistor 13 via voltage line 23. The reset transistor 13 resets the charge stored in the charge storage node 30. Specifically, a voltage is supplied to the gate 13g of the reset transistor 13, thereby turning the reset transistor 13 on, and the reset voltage is supplied to the charge storage node 30, thus resetting the charge in the charge storage node 30.

[0064] A reset transistor 13 is disposed on the first substrate 141. An amplifying transistor 11 and a selecting transistor 12 are disposed on the second substrate 142. A microlens 130, a color filter 120, a protective film 119, a photoelectric conversion unit 110, a first plurality of wiring layers 151, the first substrate 141, a second plurality of wiring layers 152, and the second substrate 142 are arranged in this order. The first plurality of wiring layers 151 is disposed on the light-incident side closer to the first substrate 141 than the first substrate 141. The second plurality of wiring layers 152 is disposed on the light-incident side closer to the second substrate 142 than the second substrate 142.

[0065] Figure 1C This is a cross-sectional view showing the structure of the periphery of the first substrate 141. The first plurality of wiring layers 151 includes wiring layer 151a and wiring layer 151b. The photoelectric conversion unit 110, wiring layer 151a, wiring layer 151b, and the first substrate 141 are arranged in this order. The second plurality of wiring layers 152 includes wiring layer 152a and wiring layer 152b. The first substrate 141, wiring layer 152a, wiring layer 152b, and the second substrate 142 are arranged in this order.

[0066] The first plurality of wiring layers 151 are electrically connected to each other. The first plurality of wiring layers 151 are conductors, for example, containing metal. In the illustrated example, wiring layers 151a and 151b are electrically connected through via 151x. The second plurality of wiring layers 152 are electrically connected to each other. The second plurality of wiring layers 152 are conductors, for example, containing metal. In the illustrated example, wiring layers 152a and 152b are electrically connected through via 152x. A first via 161 penetrates the first substrate 141, electrically connecting wiring layers 151b and 152a. The first via 161 is a conductor, for example, containing metal. The first plurality of wiring layers 151, the second plurality of wiring layers 152, and the first via 161 are electrically connected to the charge accumulation region 35.

[0067] Via 166 electrically connects wiring layer 151b and charge storage area 35.

[0068] The imaging device 101 includes a first structure 171 and a second structure 172. The first structure 171 includes a microlens 130, a color filter 120, a protective film 119, a photoelectric conversion unit 110, a first plurality of wiring layers 151, and a first substrate 141. The second structure 172 includes a second plurality of wiring layers 152 and a second substrate 142. The first structure 171 and the second structure 172 are bonded to each other at a first bonding interface 181.

[0069] As described below, during the manufacture of the imaging device 101, a structure 170 including a first substrate 141 is formed and bonded to a second structure 172. The first bonding interface 181 is specifically the bonding interface associated with this bonding. After bonding, a first through-hole 161 is formed.

[0070] Wiring layers 151b and 152a constitute a first wiring layer pair 151b and 152a. A first via 161 directly connects the first wiring layer pair 151b and 152a. This configuration is suitable for providing a fine and low-noise imaging device 101. Hereinafter, the reasons for this will be compared with the first reference embodiment and explained in detail.

[0071] Figure 2 This is a cross-sectional view of the imaging device 801 according to the first reference method. The imaging device 801 includes a photoelectric conversion unit 810, a microlens 130, a color filter 120, a protective film 119, a transfer transistor 15, a reset transistor 13, an amplifying transistor 11, a selection transistor 12, a first substrate 841, a second substrate 842, multiple wiring layers 852, and a Cu-Cu bonding pad 861. The Cu-Cu bonding pad 861 includes a first Cu pad 861a and a second Cu pad 861b.

[0072] The photoelectric conversion unit 810 is a photodiode disposed on the first substrate 841. The transfer transistor 15 is disposed on the first substrate 841. The reset transistor 13, the amplification transistor 11, and the selection transistor 12 are disposed on the second substrate 842. The microlens 130, the color filter 120, the protective film 119, the first substrate 841, the multiple wiring layers 852, and the second substrate 842 are arranged in this order.

[0073] One of the source and drain of the transfer transistor 15 is connected to the photoelectric conversion unit 810. The other of the source and drain of the transfer transistor 15 forms a charge storage region 35. The charge storage region 35 is electrically connected to one of the source and drain of the reset transistor 13 and the gate 11g of the amplification transistor 11 via a Cu-Cu junction 861 and a plurality of wiring layers 852.

[0074] The imaging device 801 includes a structure 870 and a structure 872. Structure 870 includes a first Cu pad 861a and a first substrate 841. Structure 872 includes a second Cu pad 861b, multiple wiring layers 852, and a second substrate 842. Structures 870 and 872 are bonded to each other via a Cu-Cu bond 861 at a bonding interface 881. Using a Cu-Cu bond 861 is disadvantageous from the viewpoint of providing a miniaturized and low-noise imaging device 801. This is because the Cu-Cu bond 861 tends to increase the size of the imaging device 801 and also tends to increase the parasitic capacitance of the charge accumulation node 30.

[0075] In contrast, as described above, in this embodiment, the first wiring layer pairs 151b and 152a are directly connected via the first via 161. Furthermore, the first wiring layer pairs 151b and 152a are connected using the first via 161 without using Cu-Cu bonding. More generally, the first wiring layer pairs 151b and 152a are connected using the first via 161 without using conductor pad pairs. The first via 161 does not easily increase the size of the imaging device 101, nor does it easily increase the parasitic capacitance of the charge accumulation node 30. Therefore, this configuration is suitable for providing a compact and low-noise imaging device 101.

[0076] The camera device 101 includes one or more pixels 190. Each pixel 190 includes a first structure 171, a second structure 172, a first via 161, and a charge accumulation region 35.

[0077] In the plan view, at a position that overlaps with at least one of the microlens 130 and the color filter 120, a first structure 171, a second structure 172, a first via 161, and a charge accumulation region 35 may be configured.

[0078] In this embodiment, wiring layer 151b is the wiring layer closest to the first substrate 141 among the first plurality of wiring layers 151 in the first structure 171. Wiring layer 151b may also be the only wiring layer in the first structure 171. Either of these methods is advantageous from the viewpoint of shortening the first via 161. This is advantageous from the viewpoint of suppressing the parasitic capacitance of the charge accumulation node 30.

[0079] In this embodiment, wiring layer 152a is the wiring layer closest to the first substrate 141 among the second plurality of wiring layers 152 in the second structure 172. Wiring layer 152a may also be the only wiring layer in the second structure 172. Either of these methods is advantageous from the viewpoint of shortening the first via 161. This is advantageous from the viewpoint of suppressing the parasitic capacitance of the charge accumulation node 30.

[0080] The first substrate 141 includes a first semiconductor layer 141x and a first oxide film 141y. A first via 161 penetrates the first oxide film 141y. The first oxide film 141y prevents the first via 161 from being connected to the first semiconductor layer 141x. Specifically, the first oxide film 141y is an embedded oxide film. The first oxide film 141y, when embedded in the first substrate 141, separates the semiconductor elements in the first substrate 141. The embedded oxide film reduces the parasitic capacitance of the charge accumulation node 30 caused by the first semiconductor layer 141x. In the illustrated example, the first oxide film 141y penetrates the first substrate 141. This configuration is advantageous from the viewpoint of preventing the first via 161 from being connected to the first semiconductor layer 141x. However, the first oxide film 141y may not penetrate the first substrate 141.

[0081] In this embodiment, the first semiconductor layer 141x comprises silicon. The first oxide film 141y is an insulating film. The first oxide film 141y comprises silicon oxide.

[0082] As can be understood from the above description, a first transistor is disposed on the first substrate 141. A second transistor is disposed on the second substrate 142. A third transistor is disposed on the second substrate 142. Specifically, the first transistor, the second transistor, and the third transistor are disposed in one pixel 190 or in each of a plurality of pixels 190. This configuration of separately disposing of multiple transistors on individual substrates is advantageous from the viewpoint of ensuring the size of each transistor. This helps to achieve low-noise transistors. Specifically, ensuring that the gate length L and gate width W of the transistors can help to achieve low-noise transistors. Alternatively, the configuration of separately disposing of multiple transistors on individual substrates is advantageous from the viewpoint of miniaturizing the imaging device 101.

[0083] One of the first transistor and the second transistor can be an amplifying transistor 11. Ensuring the size of the amplifying transistor 11 to achieve a low-noise amplifying transistor 11 is particularly advantageous from the viewpoint of achieving a high-performance imaging device 101.

[0084] The other of the first and second transistors can be a reset transistor 13. The third transistor can be a select transistor 12.

[0085] In the illustrated example, the first transistor is the reset transistor 13. The second transistor is the amplification transistor 11. The third transistor is the selection transistor 12.

[0086] In this embodiment, the gate of the second transistor (amplifying transistor 11 in the illustrated example) is disposed between the photoelectric conversion section 110 and the second substrate 142 in the thickness direction of the second substrate 142. This configuration is advantageous from the viewpoint of realizing a low-noise second transistor. Hereinafter, the reasons for this will be explained in detail by comparing it with the second reference embodiment.

[0087] Figure 3 This is a cross-sectional view of the imaging device 901 according to the second reference method. The imaging device 901 includes a photoelectric conversion unit 910, a microlens 130, a color filter 120, a protective film 119, a transfer transistor 15, a reset transistor 13, an amplification transistor 11, a selection transistor 12, a first substrate 941, a second substrate 942, a wiring layer 952, and vias 961 and 962.

[0088] The photoelectric conversion unit 910 is a photodiode disposed on the first substrate 941. The transfer transistor 15 is disposed on the first substrate 941. The reset transistor 13, the amplification transistor 11, and the selection transistor 12 are disposed on the second substrate 942. The microlens 130, the color filter 120, the protective film 119, the first substrate 941, the second substrate 942, and the wiring layer 952 are arranged in this order.

[0089] One of the source and drain of the transfer transistor 15 is connected to the photoelectric conversion unit 910. The other of the source and drain of the transfer transistor 15 forms a charge storage region 35. The charge storage region 35 is electrically connected to the gate 11g of the amplification transistor 11 via via 961, wiring layer 952 and via 962 in sequence.

[0090] The camera device 901 includes a structure 970 and a structure 972. The structure 970 includes a first substrate 941. The structure 972 includes a wiring layer 952 and a second substrate 942. The structures 970 and 972 are bonded to each other at a bonding interface 981.

[0091] In the second reference configuration, via 961 extends from the first substrate 941 side through the wiring layer 952 side of the second substrate 942 and is connected to the wiring layer 952. The gate 11g of the amplifying transistor 11 is located on the side closer to the wiring layer 952 than the second substrate 942 and is connected to the wiring layer 952 through via 962. In this way, via 961, wiring layer 952, and via 962 form an electrical path 965 connecting the charge storage region 35 and the gate 11g.

[0092] exist Figure 3In this configuration, the gate 11g is located lower than the second substrate 942. A via 961 of the electrical path 965 extends downward through the second substrate 942 from the charge accumulation region 35 side. The electrical path 965 then has a return portion 966 that returns upward to the gate 11g. In this configuration, where the gate 11g is located lower than the second substrate 942 and the via 961 extends downward through the second substrate 942, it is difficult to position the gate 11g on the second substrate 942 at the peripheral portion 967 of the via 961.

[0093] In contrast, as described above, in this embodiment, the gate of the second transistor (amplifying transistor 11 in the illustrated example) is disposed between the photoelectric conversion section 110 and the second substrate 142 in the thickness direction of the second substrate 142. In this configuration, a via penetrating the second substrate 142 can be omitted, and the charge storage region 35 can be electrically connected to the gate of the second transistor via the first via 161. Therefore, the gate configuration is not constrained by vias penetrating the second substrate 142. This is advantageous from the viewpoint of avoiding excessive miniaturization of the second transistor and achieving a low-noise second transistor.

[0094] In this embodiment, in the thickness direction of the first substrate 141, the gate of the first transistor (reset transistor 13 in the illustrated example) is disposed between the photoelectric conversion section 110 and the first substrate 141. In the thickness direction of the second substrate 142, the gate of the third transistor (selection transistor 12 in the illustrated example) is disposed between the photoelectric conversion section 110 and the second substrate 142.

[0095] In this embodiment, a reset transistor 13 is disposed on a first substrate 141. An amplification transistor 11 is disposed on a second substrate 142. A selection transistor 12 is disposed on the second substrate 142. This configuration is advantageous from the viewpoint of reducing the number of vias penetrating the substrate in the imaging device 101. By reducing the number of vias penetrating the substrate, the area required to configure the vias can be reduced. This is advantageous from the viewpoint of ensuring the size of the transistors. In addition, by reducing the number of vias penetrating the substrate, the imaging device 101 is easier to manufacture. This can help improve the reliability of the imaging device 101.

[0096] Specifically, in this embodiment, each of one or more pixels 190 is provided with a reset transistor 13, an amplification transistor 11, and a selection transistor 12. This is for... Figures 4A to 5 The same applies to other examples.

[0097] According to the inventors' research, by improving the transistor configuration, the number of vias penetrating the substrate for connecting transistors can be reduced. Table 1 shows the results of this research. Table 1 shows the relationship between the above-mentioned number of vias and substrates with various transistor configurations. Specifically, in Table 1,

[0098] • "RX" is the reset transistor 13.

[0099] • “SF” stands for amplifier transistor 11.

[0100] • “SEL” is the selection transistor 12.

[0101] • “Layer 1” refers to the transistors disposed on the first substrate 141.

[0102] • The “second layer” refers to the transistors disposed on the second substrate 142.

[0103] • The “Via count” between “Layer 1” and “Layer 2” refers to the number of vias that penetrate the first substrate 141.

[0104] Furthermore, "RX" is not intended to limit the interpretation of the behavior of reset transistor 13. The same applies to "SF", "SEL" and "OF" (described later).

[0105] [Table 1]

[0106]

[0107] according to Figure 1B It is understood that the first embodiment corresponds to the transistor configuration (1) in Table 1.

[0108] Figure 4A and Figure 4B These are the circuit diagram and cross-sectional view of the camera device with transistor configuration (6) in Table 1. Figure 5 This is the circuit diagram of the camera device with transistor configuration (4) in Table 1. Figure 1A , Figure 4A and Figure 5 The circuits are electrically equivalent.

[0109] In the transistor configuration in Table 1 (6), i.e. Figure 4A and Figure 4B In this example, amplifying transistor 11 is disposed on the first substrate 141. Selecting transistor 12 is disposed on the first substrate 141. Resetting transistor 13 is disposed on the second substrate 142.

[0110] In the transistor configuration (4) in Table 1, i.e. Figure 5 In this example, reset transistor 13 is disposed on the first substrate 141. Amplification transistor 11 is disposed on the first substrate 141. Selection transistor 12 is disposed on the second substrate 142.

[0111] Various modifications can be made to the imaging device 101. The number of wiring layers included in the first plurality of wiring layers 151 is not particularly limited; it can be 2, 3, or more than 4, as shown in the figure. The number of wiring layers included in the second plurality of wiring layers 152 is not particularly limited; it can be 2, 3, or more than 4, as shown in the figure. Some elements in the imaging device 101 can be omitted. For example, the protective film 119, the color filter 120, and the microlens 130 can be omitted. The number of pixels 190 in the imaging device 101 can be one or more. The first oxide film 141y can also be omitted.

[0112] Figures 6A to 6E This is an explanatory diagram of the manufacturing method of the camera device 101 according to the first embodiment. Figure 7 This is a flowchart of the manufacturing method of the camera device 101 according to the first embodiment. Hereinafter, refer to... Figures 6A to 6E and Figure 7 The manufacturing method of the camera device 101 is explained.

[0113] exist Figure 6A Parts (1) to parts (3) and Figure 7 In steps S101 to S103, the second structure 172 is formed. Figure 6B Parts (4) to parts (7) and Figure 7 In steps S104 to S107, structure 170 is formed. Figure 6C Parts (8) to parts (10) and Figure 7 In steps S108 to S110, a joint is formed between the second structure 172 and the structure 170. Figure 6D Parts (11) to parts (13) and Figure 7 In steps S111 to S113, a structure is formed up to the wiring layer 151b. Figure 6E Part (14) and part (15) and Figure 7 In steps S114 and S115, a structure is formed that is higher than the wiring layer 151b. The manufacturing method of the camera device 101 will be described in detail below.

[0114] In step S101, as Figure 6A As shown in part (1), a second substrate 142 is prepared.

[0115] Next, in step S102, as Figure 6AAs shown in part (2), an amplifying transistor 11 and a selecting transistor 12 are formed on the second substrate 142. An insulating film 186a is formed above the second substrate 142, covering the amplifying transistor 11 and the selecting transistor 12. Then, the upper surface 186as of the insulating film 186a is planarized. In this example, the insulating film 186a is a silicon oxide film.

[0116] Next, in step S103, as Figure 6A As shown in part (3), a second plurality of wiring layers 152 are formed. Specifically, the formation of wiring layers and the formation of insulating portions are performed alternately and repeatedly. As a result, a configuration in which the second plurality of wiring layers 152 are formed above the second substrate 142 and covered by an insulating film 186 is formed. The upper surface 186s of the insulating film 186 is planarized. The insulating film 186 includes an insulating film 186a. In this example, the insulating film 186 is a silicon oxide film. Thus, a second structure 172 is obtained.

[0117] In step S104, as Figure 6B As shown in section (4), a first substrate 141 is prepared. In this example, an SOI (Silicon on Insulator) substrate is prepared as the first substrate 141. Specifically, the first substrate 141 is a laminated substrate formed by stacking a silicon film 141a, an insulating film 141b, and a silicon film 141c in this order. In this example, the insulating film 141b is a silicon oxide film.

[0118] Next, in step S105, as Figure 6B As shown in part (5), a reset transistor 13 is formed on the first substrate 141. An insulating film 185a is formed above the first substrate 141 in such a way that it covers the reset transistor 13. Then, the upper surface 185as of the insulating film 185a is planarized.

[0119] Next, in step S106, as Figure 6B As shown in part (6), the support substrate 187 is attached to the upper surface 185as of the insulating film 185a.

[0120] Next, in step S107, as Figure 6B As shown in part (7), the first substrate 141 is thinned from the opposite side of the support substrate 187. For example, this thinning is achieved by grinding. In the illustrated example, by thinning, the silicon film 141a is selectively removed, exposing the lower surface 141bs of the insulating film 141b. Thus, a structure 170 is obtained, comprising the first substrate 141 after the silicon film 141a has been removed and supported by the support substrate 187.

[0121] Next, in step S108, as follows Figure 6CAs shown in part (8), the lower surface 141bs of the insulating film 141b and the upper surface 186s of the insulating film 186 are made to overlap. In this way, the second structure 172 and the structure 170 are made to overlap.

[0122] Next, in step S109, as Figure 6C As shown in part (9), the lower surface 141bs and the upper surface 186s are joined. For example, the joining is performed by plasma activation, applying pressure, etc. Thus, the second structure 172 and the structure 170 are joined. Figure 6C In part (9), the first joint interface 181 is indicated as the joint interface between the second structure 172 and the structure 170.

[0123] Next, in step S110, as Figure 6C As shown in part (10), the support substrate 187 is peeled off from the structure 170.

[0124] Next, in step S111, as follows Figure 6D As shown in part (11), grooves 188a and 188b are formed on the upper surface 185as of the insulating film 185a.

[0125] Next, in step S112, as Figure 6D As shown in part (12), a first via 189a and a via 189b are formed. The first via 189a communicates with the trench 188a and extends in this order within the insulating film 185a, the silicon film 141c, the insulating film 141b, and the insulating film 186, exposing the wiring layer 152a. The via 189b communicates with the trench 188b, extends within the insulating film 185a, and exposes the gate 13g of the reset transistor 13.

[0126] Next, in step S113, as Figure 6D As shown in part (13), the first via 189a, trench 188a, via 189b, and trench 188b are filled with a conductor. The conductor is, for example, metal. The conductor in the first via 189a constitutes the first via 161. The conductor in the via 189b constitutes the via 167. The conductors in the trenches 188a and 188b constitute the wiring layer 151b. In this embodiment, the first via 161, via 167, and wiring layer 151b are formed by a single operation of filling with a conductor.

[0127] Next, in step S114, as Figure 6E As shown in part (14), a conductive structure 176 is formed above the wiring layer 151b. The conductive structure 176 includes the portion of the first plurality of wiring layers 151 other than the wiring layer 151b, and the pixel electrode 112. The details of step S114 are described below.

[0128] First, in step S114, portions of the first plurality of wiring layers 151 other than wiring layer 151b are formed. Specifically, the formation of each wiring layer and the subsequent formation of the insulating portion are performed once, or the formation of wiring layers and the formation of the insulating portion are performed alternately and repeatedly. As a result, a configuration in which the first plurality of wiring layers 151 are covered by an insulating film 185 is formed at a position above the second substrate 142. The upper surface 185s of the insulating film 185 is planarized. The insulating film 185 includes an insulating film 185a. In this example, the insulating film 185 is a silicon oxide film.

[0129] Second, in step S114, a pixel electrode 112 is formed on the upper surface 185s of the insulating film 185.

[0130] Next, in step S115, as Figure 6E As shown in part (15), a photoelectric conversion film 111, a counter electrode 113, a protective film 119, a color filter 120, and a microlens 130 are formed above the conductive structure 176. The photoelectric conversion film 111 is formed, for example, by vacuum evaporation or spin coating. As described above, in this embodiment, the photoelectric conversion film 111 contains an organic material.

[0131] As can be understood from the above description, the manufacturing method involved in this embodiment sequentially includes a first bonding step, a first perforation step, a first via formation step, and a first film formation step. In the first bonding step, a structure 170 including a first substrate 141 is bonded to a second structure 172. In the first perforation step, a first through-hole 189a is formed on the first substrate 141. In the first via formation step, the first through-hole 189a is filled with a first conductor, thereby forming a first via 161. In the first film formation step, a photoelectric conversion film 111 is formed.

[0132] In the manufacturing method described above, immediately after step S105, the wiring layers belonging to the first plurality of wiring layers 151 are not formed. This shortens the first via 189a and the first via 161. Therefore, it is easier to manufacture the camera device 101. This helps improve the reliability of the camera device 101. However, it is also possible to form part or all of the first plurality of wiring layers 151 immediately after step S105.

[0133] As can be understood from the above description, a single routing layer can be used instead of the first plurality of routing layers 151. In this case, no routing layer is formed in step S114. Alternatively, a single routing layer can be used instead of the second plurality of routing layers 152. In this case, the number of routing layers formed in step S103 is one.

[0134] The first substrate 141 prepared in step S104 may not be an SOI substrate. For example, a silicon substrate may be prepared as the first substrate 141 in step S104. In one example of this case, an insulating film is formed on the first substrate 141. Then, in step S109, the formed insulating film is bonded to an insulating film 186. The insulating film formed on the first substrate 141 is, for example, a silicon oxide film.

[0135] In step S109, the second structure 172 and structure 170 may also be joined using adhesives, bumps, conductor pad pairs, etc. In this case, a joining preparation corresponding to this joining method can be performed. Joining via conductor pad pairs is, for example, a Cu-Cu joint.

[0136] Thinning in step S107 can shorten the first via 189a and the first via 161. However, this thinning is not necessary. In addition, in step S113, it is not necessary to form the first via 161, via 167 and wiring layer 151b by a single operation of burying the conductor.

[0137] In the above description, the formation of the first oxide film 141y is omitted. The first oxide film 141y can be formed by a suitable method.

[0138] Other embodiments are described below. Hereinafter, the same reference numerals are used for elements common to the embodiments already described and those described subsequently, and their descriptions are sometimes omitted. Descriptions related to each embodiment are applicable to each other as long as they do not contradict each other technically. Embodiments can also be combined with each other as long as they do not contradict each other technically.

[0139] (Second Implementation)

[0140] Figure 8A and Figure 8B These are circuit diagrams and cross-sectional views of the imaging device 201 according to the second embodiment. The imaging device 201 includes an overflow transistor 14. The overflow transistor 14 is included in the pixels 190 of the imaging device 201. In a typical example, the overflow transistor 14 is included in each of the plurality of pixels 190 of the imaging device 201.

[0141] The photoelectric conversion unit 110 is electrically connected to one of the source and drain of the reset transistor 13, one of the source and drain of the overflow transistor 14, the gate 14g of the overflow transistor 14, and the gate 11g of the amplification transistor 11. Specifically, the pixel electrode 112 is electrically connected to them. One of the source and drain of the reset transistor 13 constitutes a charge storage region 35. Additionally, one of the source and drain of the overflow transistor 14 constitutes a charge storage region 35. That is, the charge storage region 35 is shared by the reset transistor 13 and the overflow transistor 14. The first via 161 is electrically connected to the charge storage region 35.

[0142] A voltage is applied to the other of the source and drain of the overflow transistor 14 via voltage line 24. As described above, the gate 14g of the overflow transistor 14 is electrically connected to the charge storage region 35. If strong light is incident on the photoelectric conversion unit 110, the charge in the charge storage region 35 increases, and the overflow transistor 14 becomes conductive. Thus, excess charge accumulated in the charge storage region 35 is discharged through the overflow transistor 14. This protects various transistors and ensures the safety of the imaging device 201.

[0143] The imaging device 201 includes four transistors: a reset transistor 13, an overflow transistor 14, an amplification transistor 11, and a selection transistor 12. Two of the four transistors are disposed on a first substrate 141, and the remaining two are disposed on a second substrate 142. This configuration, which separates the transistors into pairs and disposes them on separate substrates, is advantageous from the viewpoint of ensuring the size of each transistor. Alternatively, this configuration is advantageous from the viewpoint of miniaturizing the imaging device 201.

[0144] In the thickness direction of the first substrate 141, the gate 14g of the overflow transistor 14 is disposed between the photoelectric conversion unit 110 and the first substrate 141.

[0145] A reset transistor 13 and an overflow transistor 14 are disposed on the first substrate 141. An amplification transistor 11 and a selection transistor 12 are disposed on the second substrate 142. This configuration is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device 201.

[0146] Specifically, each of one or more pixels 190 is equipped with a reset transistor 13, an overflow transistor 14, an amplification transistor 11, and a selection transistor 12. This is for... Figures 9A to 19 The same applies to other examples.

[0147] According to the inventors' research, in the second embodiment, similar to the first embodiment, by improving the transistor arrangement, the number of vias penetrating the substrate for connecting the transistors can be suppressed. Table 2 shows the results of this research. Table 2 shows the relationship between the substrates with various transistors and the aforementioned number of vias. Specifically, in Table 2,

[0148] • "OF" stands for overflow transistor 14.

[0149] [Table 2]

[0150]

[0151] according to Figure 8B It is understood that the second embodiment corresponds to the transistor configuration (1) in Table 2.

[0152] The manufacturing method of the imaging device 201 according to the second embodiment, compared with the manufacturing method of the imaging device 101 according to the first embodiment, adds the formation of an overflow transistor 14. Specifically, in step S105, the overflow transistor 14 is formed together with the reset transistor 13 on the first substrate 141. An insulating film 185a is formed at a position above the first substrate 141 such that it covers the reset transistor 13 and the overflow transistor 14.

[0153] (Third Implementation)

[0154] Figure 9A and Figure 9B These are the circuit diagram and cross-sectional view of the camera device 301 according to the third embodiment.

[0155] A reset transistor 13 and an overflow transistor 14 are disposed on the second substrate 142. An amplification transistor 11 and a selection transistor 12 are disposed on the first substrate 141.

[0156] Via 166 electrically connects wiring layer 151b and gate 11g of amplifier transistor 11.

[0157] In this embodiment, in the thickness direction of the first substrate 141, the gate 11g of the amplifying transistor 11 and the gate 12g of the selecting transistor 12 are disposed between the photoelectric conversion section 110 and the first substrate 141. In the thickness direction of the second substrate 142, the gate 13g of the reset transistor 13 and the gate 14g of the overflow transistor 14 are disposed between the photoelectric conversion section 110 and the second substrate 142.

[0158] A reset transistor 13 and an overflow transistor 14 are disposed on the second substrate 142. An amplification transistor 11 and a selection transistor 12 are disposed on the first substrate 141. This configuration is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device 301.

[0159] according to Figure 9B It is understood that the third embodiment corresponds to the transistor configuration (6) in Table 2.

[0160] The manufacturing method of the imaging device 301 according to the third embodiment differs from the manufacturing method of the imaging device 201 according to the second embodiment in that the steps related to transistors are modified. Specifically, in step S102, a reset transistor 13 and an overflow transistor 14 are formed on the second substrate 142. An insulating film 186a is formed above the second substrate 142 to cover the reset transistor 13 and the overflow transistor 14. In step S105, an amplification transistor 11 and a selection transistor 12 are formed. An insulating film 185a is formed above the first substrate 141 to cover the amplification transistor 11 and the selection transistor 12. In step S112, a through-hole 189b communicates with a trench 188b, extends within the insulating film 185a, and exposes the gate 12g of the selection transistor 12.

[0161] The third embodiment involves Figure 9A and the second embodiment involved Figure 8A The circuits are electrically equivalent. Here, we compare the third embodiment with the second embodiment. In the third embodiment, the first via 161 passes through the first substrate 141, which is the substrate on which the amplifying transistor 11 is disposed. In contrast, in the second embodiment, the first via 161 does not pass through the second substrate 142, which is the substrate on which the amplifying transistor 11 is disposed. In the second embodiment, the area in the second substrate 142 on which the amplifying transistor 11 can be mounted is less likely to be limited by the first via 161. This is advantageous from the viewpoint of ensuring the size of the amplifying transistor 11.

[0162] (Fourth implementation)

[0163] Figure 10A and Figure 10B These are circuit diagrams and cross-sectional views of the imaging device 401 according to the fourth embodiment. The imaging device 401 includes a third substrate 143, a third plurality of wiring layers 153, and a second via 162. These elements are included in the pixels 190 of the imaging device 401. In a typical example, these elements are included in each of the plurality of pixels 190 of the imaging device 401.

[0164] A reset transistor 13 and an overflow transistor 14 are disposed on the first substrate 141. An amplifying transistor 11 is disposed on the second substrate 142. A selection transistor 12 is disposed on the third substrate 143. The microlens 130, color filter 120, protective film 119, photoelectric conversion unit 110, first plurality of wiring layers 151, first substrate 141, second plurality of wiring layers 152, second substrate 142, third plurality of wiring layers 153, and third substrate 143 are arranged in this order. The third plurality of wiring layers 153 is disposed on the light incident side closer to the third substrate 143 than the third substrate 143.

[0165] Figure 10C This is a cross-sectional view showing the structure of the periphery of the second substrate 142. The third plurality of wiring layers 153 includes wiring layer 153a and wiring layer 153b. The second substrate 142, wiring layer 153a, wiring layer 153b and the third substrate 143 are arranged in this order.

[0166] The third plurality of wiring layers 153 are electrically connected to each other. The third plurality of wiring layers 153 are conductors, for example, containing metal. In the illustrated example, wiring layers 153a and 153b are electrically connected through via 153x. A second via 162 penetrates the second substrate 142, electrically connecting wiring layers 152b and 153a. The second via 162 is a conductor, for example, containing metal. The second plurality of wiring layers 152, the third plurality of wiring layers 153, and the second via 162 are electrically connected to the charge storage region 35.

[0167] The camera device 401 includes a third structure 173. The third structure 173 includes a third plurality of wiring layers 153 and a third substrate 143. The second structure 172 and the third structure 173 are bonded to each other at a second bonding interface 182.

[0168] As described below, during the manufacture of the imaging device 401, a structure including a second substrate 142 is formed and bonded to a third structure 173. The second bonding interface 182 is specifically the bonding interface associated with this bonding. After bonding, a second via 162 is formed.

[0169] Routing layers 152b and 153a constitute a second routing layer pair 152b and 153a. A second via 162 directly connects the second routing layer pair 152b and 153a. Alternatively, the second routing layer pair 152b and 153a are connected using the second via 162 without using Cu-Cu bonding. This configuration is suitable for providing a fine and low-noise imaging device 401. More generally, the second routing layer pair 152b and 153a are connected using the second via 162 without using conductor pad pairs.

[0170] The camera device 401 includes one or more pixels 190. Each pixel 190 includes a first structure 171, a second structure 172, a third structure 173, a first via 161, a second via 162, and a charge accumulation region 35.

[0171] In the plan view, at a position that overlaps with at least one of the microlens 130 and the color filter 120, a first structure 171, a second structure 172, a third structure 173, a first via 161, a second via 162, and a charge accumulation region 35 may be configured.

[0172] In this embodiment, wiring layer 152b is the wiring layer closest to the second substrate 142 among the second plurality of wiring layers 152 in the second structure 172. Wiring layer 152b may also be the only wiring layer in the second structure 172.

[0173] In this embodiment, wiring layer 153a is the wiring layer closest to the second substrate 142 among the third plurality of wiring layers 153 in the third structure 173. Wiring layer 153a may also be the only wiring layer in the third structure 173.

[0174] The first substrate 141 may include a first semiconductor layer 141x and a first oxide film 141y. A first via 161 may penetrate the first oxide film 141y. Specifically, the first oxide film 141y may be an embedded oxide film. The first oxide film 141y can be embedded in the first substrate 141 to separate semiconductor devices within the first substrate 141. In one example, the first oxide film 141y penetrates the first substrate 141. However, the first oxide film 141y may not penetrate the first substrate 141.

[0175] The second substrate 142 may include a second semiconductor layer 142x and a second oxide film 142y. The second via 162 may include the second oxide film 142y. Specifically, the second oxide film 142y may be an embedded oxide film. The second oxide film 142y can be embedded in the second substrate 142 to element semiconductor devices in the second substrate 142. In one example, the second oxide film 142y penetrates the second substrate 142. However, the second oxide film 142y may not penetrate the second substrate 142.

[0176] The first semiconductor layer 141x and the second semiconductor layer 142x may contain silicon. The first oxide film 141y and the second oxide film 142y may be insulating films. The first oxide film 141y and the second oxide film 142y may contain silicon oxide.

[0177] As can be understood from the above description, a first transistor is disposed on the first substrate 141. A second transistor is disposed on the second substrate 142. A third transistor is disposed on the third substrate 143. Specifically, the first transistor, the second transistor, and the third transistor are disposed in one pixel 190 or in each of a plurality of pixels 190. Distributing the multiple transistors separately on the three substrates is advantageous from the viewpoint of ensuring the size of each transistor. In this embodiment, a fourth transistor is disposed on the first substrate 141.

[0178] In the illustrated example, the first transistor is the reset transistor 13. The second transistor is the amplification transistor 11. The third transistor is the selection transistor 12. The fourth transistor is the overflow transistor 14.

[0179] As described above, ensuring the size of the amplifying transistor 11 to achieve a low-noise amplifying transistor 11 is particularly advantageous from the viewpoint of realizing a high-performance imaging device 401. From this viewpoint, it is effective to place the amplifying transistor 11 on a substrate with a relatively small number of transistors. In this embodiment, in one pixel 190, the number of transistors in the first substrate 141 is two, and the number of transistors in the second substrate 142 is one. The amplifying transistor 11 is disposed on the second substrate 142. Therefore, this embodiment conforms to the above-described viewpoint.

[0180] In this embodiment, in the thickness direction of the first substrate 141, the gates of the first transistor and the fourth transistor are disposed between the photoelectric conversion section 110 and the first substrate 141. In the thickness direction of the second substrate 142, the gate of the second transistor is disposed between the photoelectric conversion section 110 and the second substrate 142. In the thickness direction of the third substrate 143, the gate of the third transistor is disposed between the photoelectric conversion section 110 and the third substrate 143.

[0181] In this embodiment, a reset transistor 13 is disposed on a first substrate 141. An overflow transistor 14 is disposed on a first substrate 141. An amplification transistor 11 is disposed on a second substrate 142. A selection transistor 12 is disposed on a third substrate 143. This configuration is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device 401.

[0182] According to the inventors' research, in the fourth embodiment, similar to the first to third embodiments, by improving the arrangement of the transistors, the number of vias penetrating the substrate for connecting the transistors can be suppressed. Tables 3A to 3F show the results of this research. Tables 3A to 3F show the relationship between the substrates with various transistors and the aforementioned number of vias. Specifically, in Tables 3A to 3F,

[0183] • The “third layer” refers to the transistors disposed on the third substrate 143.

[0184] • The “Via count” between “2nd layer” and “3rd layer” refers to the number of vias that penetrate the 2nd substrate 142.

[0185] [Table 3A]

[0186]

[0187] [Table 3B]

[0188]

[0189] [Table 3C]

[0190]

[0191] [Table 3D]

[0192]

[0193] [Table 3E]

[0194]

[0195] [Table 3F]

[0196]

[0197] according to Figure 10B It is understood that the fourth embodiment corresponds to the transistor configuration (1) in Table 3A.

[0198] Figure 11 This is the circuit diagram of the camera device with transistor configuration (11) in Table 3B. Figure 11 In this example, amplifying transistor 11 is disposed on the first substrate 141. Selecting transistor 12 is disposed on the first substrate 141. Overflow transistor 14 is disposed on the second substrate 142. Reset transistor 13 is disposed on the third substrate 143.

[0199] Figure 12 This is the circuit diagram of the camera device with transistor configuration (12) in Table 3B. Figure 12 In this example, amplifying transistor 11 is disposed on the first substrate 141. Selecting transistor 12 is disposed on the first substrate 141. Resetting transistor 13 is disposed on the second substrate 142. Overflow transistor 14 is disposed on the third substrate 143.

[0200] Figure 13 This is a circuit diagram of the camera device with transistor configuration (19) in Table 3D. Figure 13In this example, reset transistor 13 is disposed on the first substrate 141. Overflow transistor 14 is disposed on the second substrate 142. Amplification transistor 11 is disposed on the second substrate 142. Select transistor 12 is disposed on the third substrate 143.

[0201] Figure 14 This is a circuit diagram of the camera device with transistor configuration (23) in Table 3D. Figure 14 In this example, overflow transistor 14 is disposed on the first substrate 141. Amplifying transistor 11 is disposed on the second substrate 142. Selecting transistor 12 is disposed on the second substrate 142. Reset transistor 13 is disposed on the third substrate 143.

[0202] Figure 15 This is a circuit diagram of the camera device with transistor configuration (24) in Table 3D. Figure 15 In this example, reset transistor 13 is disposed on the first substrate 141. Amplification transistor 11 is disposed on the second substrate 142. Selection transistor 12 is disposed on the second substrate 142. Overflow transistor 14 is disposed on the third substrate 143.

[0203] Figure 16 This is the circuit diagram of the camera device with the transistor configuration (35) in Table 3F. Figure 16 In this example, overflow transistor 14 is disposed on the first substrate 141. Reset transistor 13 is disposed on the second substrate 142. Amplification transistor 11 is disposed on the third substrate 143. Selection transistor 12 is disposed on the third substrate 143.

[0204] Figure 17 This is the circuit diagram of the camera device with the transistor configuration (36) in Table 3F. Figure 17 In this example, reset transistor 13 is disposed on the first substrate 141. Overflow transistor 14 is disposed on the second substrate 142. Amplification transistor 11 is disposed on the third substrate 143. Select transistor 12 is disposed on the third substrate 143.

[0205] Figure 10A and Figures 11 to 17 The circuits are electrically equivalent.

[0206] Various modifications can be made to the imaging device 401. For example, the overflow transistor 14 can be omitted. The number of wiring layers included in the third plurality of wiring layers 153 is not particularly limited; it can be 2, 3, or more than 4, as shown in the figure. The second oxide film 142y can also be omitted.

[0207] In the first embodiment, the method for manufacturing the second structure 172 was described in steps S101 to S103. This description can be applied to the method for manufacturing the third structure 173 in the fourth embodiment, with suitable substitutions. Suitable substitutions include the following:

[0208] • Replace “second substrate 142” with “third substrate 143”.

[0209] • Replace “amplifier transistor 11 and selector transistor 12” with “selector transistor 12”.

[0210] Replace “2nd Multiple Routing Layer 152” with “3rd Multiple Routing Layer 153”.

[0211] In the first embodiment, steps S104 to S114 describe the method for manufacturing portions of the structure 170 and conductive structure 176 in the first structure 171. This description can be applied to the method for manufacturing the second structure 172 of the fourth embodiment (except for the pixel electrode 112) with suitable substitutions. Suitable substitutions include the following:

[0212] • Replace “first substrate 141” with “second substrate 142”.

[0213] Replace "Reset Transistor 13" with "Amplifier Transistor 11".

[0214] • Replace “Construct 170” with “Construct”

[0215] • Replace “Construct 2 172” with “Construct 3 173”.

[0216] Replace "Through Hole 189a" with "Through Hole 2".

[0217] Replace "1st via 161" with "2nd via 162".

[0218] Replace “First Multiple Routing Layer 151” with “Second Multiple Routing Layer 152”.

[0219] In the fourth embodiment, the first structure 171 can be formed in accordance with the second embodiment.

[0220] The manufacturing method of the camera device 401 in the fourth embodiment can be modified in the same way as in the first to third embodiments.

[0221] As can be understood from the above description, the manufacturing method involved in this embodiment sequentially includes a second bonding step, a second through-hole step, and a second via-hole formation step. In the second bonding step, a structure including a second substrate 142 is bonded to the third structure 173. In the second through-hole step, a second through-hole is formed on the second substrate 142. In the second via-hole formation step, the second through-hole is filled with a second conductor, thereby forming a second via 162.

[0222] (Fifth Embodiment)

[0223] Figure 18A and Figure 18B These are circuit diagrams and cross-sectional views of the imaging device 501 according to the fifth embodiment. The imaging device 501 includes a fourth substrate 144, a fourth plurality of wiring layers 154, and a third via 163. These elements are included in the pixels 190 of the imaging device 501. In a typical example, these elements are included in each of the plurality of pixels 190 of the imaging device 501.

[0224] An overflow transistor 14 is disposed on the first substrate 141. A reset transistor 13 is disposed on the second substrate 142. An amplifying transistor 11 is disposed on the third substrate 143. A selection transistor 12 is disposed on the fourth substrate 144. The microlens 130, color filter 120, protective film 119, photoelectric conversion unit 110, first plurality of wiring layers 151, first substrate 141, second plurality of wiring layers 152, second substrate 142, third plurality of wiring layers 153, third substrate 143, fourth plurality of wiring layers 154, and fourth substrate 144 are arranged in this order. The fourth plurality of wiring layers 154 is positioned closer to the light incident side than the fourth substrate 144.

[0225] Figure 18C This is a cross-sectional view showing the structure of the periphery of the third substrate 143. The fourth plurality of wiring layers 154 includes wiring layer 154a and wiring layer 154b. The third substrate 143, wiring layer 154a, wiring layer 154b and the fourth substrate 144 are arranged in this order.

[0226] The fourth plurality of wiring layers 154 are electrically connected to each other. The fourth plurality of wiring layers 154 are conductive, for example, containing metal. In the illustrated example, wiring layers 154a and 154b are electrically connected through via 154x. A third via 163 penetrates the third substrate 143, electrically connecting wiring layers 153b and 154a. The third via 163 is conductive, for example, containing metal. The third plurality of wiring layers 153, the fourth plurality of wiring layers 154, and the third via 163 are electrically connected to the charge accumulation region 35.

[0227] The camera device 501 includes a fourth structure 174. The fourth structure 174 includes a fourth plurality of wiring layers 154 and a fourth substrate 144. The third structure 173 and the fourth structure 174 are bonded to each other at a third bonding interface 183.

[0228] As described below, during the manufacture of the imaging device 501, a structure including a third substrate 143 is formed and bonded to a fourth structure 174. The third bonding interface 183 is specifically the bonding interface associated with this bonding. After bonding, a third via 163 is formed.

[0229] Routing layers 153b and 154a constitute a third routing layer pair 153b and 154a. A third via 163 directly connects the third routing layer pair 153b and 154a. Alternatively, the third routing layer pair 153b and 154a are connected using the third via 163 without using Cu-Cu bonding. This configuration is suitable for providing a fine and low-noise imaging device 501. More generally, the third routing layer pair 153b and 154a are connected using the third via 163 without using conductor pad pairs.

[0230] The camera device 501 includes one or more pixels 190. Each pixel 190 includes a first structure 171, a second structure 172, a third structure 173, a fourth structure 174, a first via 161, a second via 162, a third via 163, and a charge accumulation area 35.

[0231] In the plan view, at a position that overlaps with at least one of the microlens 130 and the color filter 120, a first structure 171, a second structure 172, a third structure 173, a fourth structure 174, a first via 161, a second via 162, a third via 163, and a charge accumulation region 35 may be configured.

[0232] In this embodiment, wiring layer 153b is the wiring layer closest to the third substrate 143 among the third plurality of wiring layers 153 in the third structure 173. Wiring layer 153b may also be the only wiring layer in the third structure 173.

[0233] In this embodiment, wiring layer 154a is the wiring layer closest to the third substrate 143 among the fourth plurality of wiring layers 154 in the fourth structure 174. Wiring layer 154a may also be the only wiring layer in the fourth structure 174.

[0234] The first substrate 141 may include a first semiconductor layer 141x and a first oxide film 141y. A first via 161 may penetrate the first oxide film 141y. Specifically, the first oxide film 141y may be an embedded oxide film. The first oxide film 141y can be embedded in the first substrate 141 to separate semiconductor devices within the first substrate 141. In one example, the first oxide film 141y penetrates the first substrate 141. However, the first oxide film 141y may not penetrate the first substrate 141.

[0235] The second substrate 142 may include a second semiconductor layer 142x and a second oxide film 142y. The second via 162 may include the second oxide film 142y. Specifically, the second oxide film 142y may be an embedded oxide film. The second oxide film 142y can be embedded in the second substrate 142 to element semiconductor devices in the second substrate 142. In one example, the second oxide film 142y penetrates the second substrate 142. However, the second oxide film 142y may not penetrate the second substrate 142.

[0236] The third substrate 143 may include a third semiconductor layer 143x and a third oxide film 143y. A third via 163 may penetrate the third oxide film 143y. Specifically, the third oxide film 143y may be an embedded oxide film. The third oxide film 143y can be embedded in the third substrate 143 to separate semiconductor devices within the third substrate 143. In one example, the third oxide film 143y penetrates the third substrate 143. However, the third oxide film 143y may not penetrate the third substrate 143.

[0237] The first semiconductor layer 141x, the second semiconductor layer 142x, and the third semiconductor layer 143x may contain silicon. The first oxide film 141y, the second oxide film 142y, and the third oxide film 143y may be insulating films. The first oxide film 141y, the second oxide film 142y, and the third oxide film 143y may contain silicon oxide.

[0238] As can be understood from the above description, a first transistor is disposed on the first substrate 141. A second transistor is disposed on the second substrate 142. A third transistor is disposed on the third substrate 143. A fourth transistor is disposed on the fourth substrate 144. Specifically, each of one or more pixels 190 has a first transistor, a second transistor, a third transistor, and a fourth transistor disposed thereon. Distributing the multiple transistors separately on the four substrates is advantageous from the viewpoint of ensuring the size of each transistor.

[0239] In the illustrated example, the first transistor is the overflow transistor 14. The second transistor is the reset transistor 13. The third transistor is the amplification transistor 11. The fourth transistor is the selection transistor 12.

[0240] In this embodiment, in the thickness direction of the first substrate 141, the gate of the first transistor is disposed between the photoelectric conversion section 110 and the first substrate 141. In the thickness direction of the second substrate 142, the gate of the second transistor is disposed between the photoelectric conversion section 110 and the second substrate 142. In the thickness direction of the third substrate 143, the gate of the third transistor is disposed between the photoelectric conversion section 110 and the third substrate 143. In the thickness direction of the fourth substrate 144, the gate of the fourth transistor is disposed between the photoelectric conversion section 110 and the fourth substrate 144.

[0241] In this embodiment, overflow transistor 14 is disposed on the first substrate 141. Reset transistor 13 is disposed on the second substrate 142. Amplification transistor 11 is disposed on the third substrate 143. Selection transistor 12 is disposed on the fourth substrate 144. This configuration is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device 501.

[0242] According to the inventors' research, in the fifth embodiment, similar to the first to fourth embodiments, by improving the arrangement of the transistors, the number of vias penetrating the substrate for connecting the transistors can be suppressed. Tables 4A to 4D show the results of this research. Tables 4A to 4D show the relationship between the substrates in which various transistors are arranged and the aforementioned number of vias. Specifically, in Tables 4A to 4D, "4th layer" refers to the transistors disposed on the 4th substrate 144.

[0243] • The “Via count” between “3rd layer” and “4th layer” refers to the number of vias that penetrate the 3rd substrate 143.

[0244] [Table 4A]

[0245] transistor configuration ① ② ③ ④ ⑤ ⑥ Level 1 OF OF OF OF OF OF Via roots 1 1 1 1 1 1 2nd floor RX RX SF SF SEL SEL Via roots 1 1 2 2 2 2 3rd floor SF SEL RX SEL SF RX Via roots 1 2 2 1 1 2 4th floor SEL SF SEL RX RX SF

[0246] [Table 4B]

[0247]

[0248] [Table 4C]

[0249]

[0250] [Table 4D]

[0251]

[0252] according to Figure 18BIt is understood that the fifth embodiment corresponds to the transistor configuration (1) in Table 4A.

[0253] Figure 19 This is the circuit diagram of the camera device with transistor configuration (7) in Table 4B. Figure 19 In this example, reset transistor 13 is disposed on the first substrate 141. Overflow transistor 14 is disposed on the second substrate 142. Amplification transistor 11 is disposed on the third substrate 143. Select transistor 12 is disposed on the fourth substrate 144.

[0254] Figure 18A and Figure 19 The circuits are electrically equivalent.

[0255] Various modifications can be made to the camera device 501. The number of wiring layers included in the fourth plurality of wiring layers 154 is not particularly limited; it can be 2, 3, or more than 4, as shown in the figure. The third oxide film 143y may also be omitted.

[0256] In the first embodiment, the method for manufacturing the second structure 172 was described in steps S101 to S103. This description can be applied to the method for manufacturing the fourth structure 174 in the fifth embodiment, with suitable substitutions. Suitable substitutions include the following:

[0257] • Replace “Second substrate 142” with “Fourth substrate 144”.

[0258] • Replace “amplifier transistor 11 and selector transistor 12” with “selector transistor 12”.

[0259] Replace “2nd Multiple Routing Layer 152” with “4th Multiple Routing Layer 154”.

[0260] In the first embodiment, steps S104 to S114 describe the method for manufacturing portions of the structure 170 and conductive structure 176 in the first structure 171. This description can be applied to the method for manufacturing the third structure 173 of the fifth embodiment (except for the pixel electrode 112) with suitable substitutions. Suitable substitutions include the following:

[0261] • Replace “first substrate 141” with “third substrate 143”.

[0262] Replace "Reset Transistor 13" with "Amplifier Transistor 11".

[0263] • Replace “Construct 170” with “Construct”

[0264] • Replace “Construct 2 172” with “Construct 4 174”.

[0265] Replace "Through Hole 189a" with "Through Hole 3".

[0266] Replace "1st via 161" with "3rd via 163".

[0267] Replace “1st Multiple Routing Layer 151” with “3rd Multiple Routing Layer 153”.

[0268] In the first embodiment, steps S104 to S114 describe the method for manufacturing portions of the structure 170 and conductive structure 176 in the first structure 171. This description can be applied to the method for manufacturing the second structure 172 of the fifth embodiment (except for the pixel electrode 112) with suitable substitutions. Suitable substitutions include the following:

[0269] • Replace “first substrate 141” with “second substrate 142”.

[0270] • Replace “Construct 170” with “Construct”

[0271] • Replace “Construct 2 172” with “Construct 3 173”.

[0272] Replace "Through Hole 189a" with "Through Hole 2".

[0273] Replace "1st via 161" with "2nd via 162".

[0274] Replace “First Multiple Routing Layer 151” with “Second Multiple Routing Layer 152”.

[0275] Regarding the manufacture of the first structure 171, the description of step S105 of the first embodiment can be referenced in the description of the fifth embodiment with suitable substitutions. Suitable substitutions include the following:

[0276] Replace “Reset transistor 13” with “Overflow transistor 14”.

[0277] The manufacturing method of the camera device 501 in the fifth embodiment can also be modified in the same way as in the first to fourth embodiments.

[0278] As can be understood from the above description, the manufacturing method involved in this embodiment sequentially includes a third bonding step, a third through-hole step, and a third via-hole formation step. In the third bonding step, a structure including a third substrate 143 is bonded to the fourth structure 174. In the third through-hole step, a third through-hole is formed on the third substrate 143. In the third via-hole formation step, the third through-hole is filled with a third conductor, thereby forming a third via 163.

[0279] The following technology is derived from the fourth and fifth embodiments. Specifically, the method for manufacturing an imaging device includes a repetitive step and a film-forming step. In the repetitive step, a unit step comprising a heightening step, a perforation step, and a via-forming step is performed repeatedly. In the heightening step, a substrate is stacked above the formed structure, thereby increasing the height of the structure. In the perforation step, a through-hole is formed in the substrate. In the via-forming step, a via is formed in the through-hole. In the film-forming step, a photoelectric conversion film is formed above the structure. The number of repetitions of the unit step in the repetitive step can be 2, 3, 4, or more than 5 times. Typically, the film-forming step is performed after the repetitive step.

[0280] (Sixth Embodiment)

[0281] Figure 20A and Figure 20B These are circuit diagrams and cross-sectional views of the imaging device 601 according to the sixth embodiment. In the imaging device 601, the photoelectric conversion unit 110 is a photodiode. The photoelectric conversion unit 110 is disposed within the first substrate 141. Additionally, the imaging device 601 includes a transfer transistor 15. The transfer transistor 15 is disposed on the first substrate 141. The photoelectric conversion unit 110 and the transfer transistor 15 are included in the pixels 190 of the imaging device 601. In a typical example, the photoelectric conversion unit 110 and the transfer transistor 15 are included in each of the plurality of pixels 190 of the imaging device 601.

[0282] The photoelectric conversion unit 110 is electrically connected to one of the source and drain of the transfer transistor 15. The other of the source and drain of the transfer transistor 15, one of the source and drain of the reset transistor 13, and the gate 11g of the amplification transistor 11 are electrically connected. One of the source and drain of the reset transistor 13 constitutes a charge storage region 35. The other of the source and drain of the transfer transistor 15 also constitutes a charge storage region 35. In other words, the charge storage region 35 is shared by the reset transistor 13 and the transfer transistor 15. The first via 161 is electrically connected to the charge storage region 35.

[0283] In this embodiment, in the thickness direction of the first substrate 141, the gate 13g of the reset transistor 13 and the gate 15g of the transfer transistor 15 are disposed between the microlens 130 and the first substrate 141. In the thickness direction of the second substrate 142, the gate 11g of the amplification transistor 11 and the gate 12g of the selection transistor 12 are disposed between the microlens 130 and the second substrate 142.

[0284] The photoelectric conversion unit 110 converts light into electric charge. The transfer transistor 15 transfers the charge from the photoelectric conversion unit 110 to the charge storage region 35.

[0285] (Comparison of the manufacturing methods of embodiments 1 to 5 with the manufacturing method of embodiment 6)

[0286] As described above, in the sixth embodiment, the photoelectric conversion unit 110 is a photodiode. In the sixth embodiment, step S105 is changed to: forming the transfer transistor 15 and the photodiode together with the reset transistor 13 on the first substrate 141. Therefore, after forming the photodiode, the bonding is performed in step S109, and then the formation of the first via 161, the first plurality of wiring layers 151, etc., in steps S111 to S114 is performed.

[0287] In contrast, in embodiments 1 to 5, the photoelectric conversion unit 110 includes a photoelectric conversion film 111. In the method for manufacturing an imaging device where the photoelectric conversion unit 110 includes the photoelectric conversion film 111, a transistor can be formed on the first substrate 141 in step S105, followed by bonding in step S109, then the formation of the first via 161, the first plurality of wiring layers 151, etc., in steps S111 to S114, followed by the formation of the photoelectric conversion unit 110. Since the timing of the formation of the photoelectric conversion unit 110 can be delayed, according to embodiments 1 to 5, the degradation of the photoelectric conversion unit 110 during the manufacturing of the imaging device can be suppressed compared to embodiment 6. This is advantageous from the viewpoint of realizing an imaging device with reliability. When the photoelectric conversion film 111 contains an organic material, the photoelectric conversion film 111 is prone to damage during manufacturing. Therefore, the aforementioned degradation suppression effect is particularly useful when the photoelectric conversion film 111 contains an organic material.

[0288] (Camera System)

[0289] Reference Figure 21 This embodiment describes the camera system 705.

[0290] Figure 21 The diagram illustrates an example configuration of the camera system 705 according to this embodiment. The camera system 705 includes a lens optical system 701, an imaging device 702, a system controller 703, and a camera signal processing circuit 704. The camera system 705 can be, for example, a smartphone, a digital camera, a video camera, or a vehicle-mounted camera.

[0291] The lens optical system 701 may include, for example, a lens group comprising an autofocus lens, a zoom lens, and an aperture stop. The lens optical system 701 focuses light onto the imaging surface of the imaging device 702. As the imaging device 702, the imaging devices described in the first to sixth embodiments described above can be widely used. Furthermore, as the imaging device 702, the imaging devices additionally described in the first to sixth embodiments can be widely used.

[0292] The system controller 703 controls the camera system 705 as a whole. The system controller 703 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0293] The signal processing circuit 704 has the function of processing the output signal from the camera device 702. The signal processing circuit 704 receives output data from the camera device 702 and performs processes such as gamma correction, color interpolation, spatial interpolation, and automatic white balance. The camera device 702 and the signal processing circuit 704 can also be implemented as a single semiconductor device. The semiconductor device can be, for example, a so-called SoC (System on a Chip). With this configuration, the electronic device, including the camera device 702 as a part, can be further miniaturized. The signal processing circuit 704 is, for example, a DSP (Digital Signal Processor).

[0294] Based on the above description, it can be understood that a camera system may include a lens optical system, an imaging device, and a signal processing circuit. The imaging device receives light that has passed through the lens optical system and outputs a signal. The signal processing circuit processes the signal.

[0295] (Postscript)

[0296] The following technology is disclosed through this disclosure.

[0297] (Technology 1)

[0298] A camera device having at least one pixel,

[0299] Each pixel in the at least one pixel has:

[0300] The first structure includes a photoelectric conversion unit that converts light into charge, one side of a first wiring layer pair, and a first substrate;

[0301] The second structure has the other side of the first wiring layer pair and a second substrate;

[0302] A first via penetrates the first substrate, directly connecting the first wiring layer pairs; and

[0303] A charge storage region is disposed on one of a plurality of substrates including the first substrate and the second substrate, stores the charge, and is electrically connected to the first via.

[0304] The first wiring layer pair, the first substrate, the other side of the first wiring layer pair, and the second substrate are arranged in this order.

[0305] Technology 1 is suitable for providing a fine and low-noise imaging device. Furthermore, the expression "at least one pixel" means each pixel among multiple pixels when the number of pixels is multiple. When the number of pixels is one, it means that one pixel.

[0306] (Technology 2)

[0307] The camera device as described in Technique 1,

[0308] One of the first wiring layer pairs is included in the wiring layer closest to the first substrate in the first structure.

[0309] The other party of the first wiring layer pair is included in the wiring layer closest to the first substrate in the second structure.

[0310] Technique 2 is advantageous from the viewpoint of suppressing parasitic capacitance at charge accumulation nodes, including charge accumulation regions.

[0311] (Technology 3)

[0312] The camera device as described in technique 1 or 2

[0313] The first substrate has a first embedded oxide film.

[0314] The first via penetrates the first embedded oxide film.

[0315] Technique 3 is advantageous from the viewpoint of suppressing parasitic capacitance at charge accumulation nodes, including charge accumulation regions.

[0316] (Technology 4)

[0317] The camera device as described in any one of techniques 1 to 3,

[0318] Each pixel in the at least one pixel has:

[0319] A first transistor is disposed on the first substrate; and

[0320] The second transistor is disposed on the second substrate.

[0321] Technology 4 is advantageous in terms of ensuring at least one of the transistor size and reducing the size of the camera device.

[0322] (Technology 5)

[0323] The camera device as described in Technique 4

[0324] One of the first transistor and the second transistor is an amplifying transistor that outputs a signal corresponding to the potential of the charge accumulation region.

[0325] Technology 5 is advantageous from the perspective of achieving high-performance camera devices.

[0326] (Technology 6)

[0327] The camera device as described in Technique 5

[0328] The other of the first transistor and the second transistor is a reset transistor that resets the charge accumulated in the charge accumulation region.

[0329] Technology 6 is advantageous from the perspective of achieving high-performance camera devices.

[0330] (Technology 7)

[0331] The camera device as described in any one of techniques 1 to 6,

[0332] Each pixel in the at least one pixel has:

[0333] The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation region.

[0334] A reset transistor resets the charge accumulated in the charge storage region; and a selection transistor determines the timing of the signal output from the amplifying transistor.

[0335] (a1) The reset transistor is disposed on the first substrate, the amplification transistor is disposed on the second substrate, and the selection transistor is disposed on the second substrate; or,

[0336] (a2) The amplifying transistor is disposed on the first substrate, the selecting transistor is disposed on the first substrate, and the reset transistor is disposed on the second substrate.

[0337] Technique 7 is advantageous from the viewpoint of reducing the number of through-board vias in an imaging device.

[0338] (Technology 8)

[0339] The camera device as described in any one of techniques 1 to 7,

[0340] Each pixel in the at least one pixel has:

[0341] The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation region.

[0342] A reset transistor resets the charge accumulated in the charge accumulation region; and

[0343] An overflow transistor includes a gate electrically connected to the charge storage region, which is turned on in accordance with the potential of the charge storage region to discharge the charge from the charge storage region.

[0344] (A1) The overflow transistor is disposed on the first substrate, the reset transistor is disposed on the first substrate, and the amplification transistor is disposed on the second substrate; or,

[0345] (A2) The amplifying transistor is disposed on the first substrate, the overflow transistor is disposed on the second substrate, and the reset transistor is disposed on the second substrate.

[0346] Technology 8 is advantageous from the viewpoint of suppressing the number of vias in a camera device that penetrate the substrate.

[0347] (Technology 9)

[0348] The camera device as described in any one of techniques 1 to 8,

[0349] Each pixel in the at least one pixel has:

[0350] The third construct; and

[0351] Second through hole,

[0352] The second structure has one of the second wiring layer pairs.

[0353] The third structure includes the other side of the second wiring layer pair and a third substrate among the plurality of substrates.

[0354] The second via penetrates the second substrate, directly connecting the second wiring layer pairs.

[0355] The first party of the second wiring layer pair, the second substrate, the other party of the second wiring layer pair, and the third substrate are arranged in this order.

[0356] Technology 9 is suitable for providing a fine and low-noise imaging device. Furthermore, regarding technologies 1 and 9, one side of the first wiring layer pair may be the same as or different from one side of the second wiring layer pair.

[0357] (Technology 10)

[0358] The camera device as described in Technique 9

[0359] Each pixel in the at least one pixel has:

[0360] A first transistor is disposed on the first substrate;

[0361] A second transistor is disposed on the second substrate; and

[0362] The third transistor is disposed on the third substrate.

[0363] Technology 10 is advantageous in achieving at least one of ensuring the size of the transistor and reducing the size of the camera device.

[0364] (Technology 11)

[0365] The camera device as described in technology 9 or 10

[0366] Each pixel in the at least one pixel has:

[0367] The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation region.

[0368] A reset transistor resets the charge accumulated in the charge accumulation region; and

[0369] The selection of the transistor determines the timing of the signal output from the amplifying transistor.

[0370] (d1) The reset transistor is disposed on the first substrate, the amplification transistor is disposed on the second substrate, and the selection transistor is disposed on the third substrate; or

[0371] (d2) The amplifying transistor is disposed on the first substrate, the selecting transistor is disposed on the first substrate, and the reset transistor is disposed on the third substrate; or

[0372] (d3) The amplifying transistor is disposed on the first substrate, the selecting transistor is disposed on the first substrate, and the reset transistor is disposed on the second substrate; or

[0373] (d4) The amplifying transistor is disposed on the second substrate, the selecting transistor is disposed on the second substrate, and the reset transistor is disposed on the third substrate; or

[0374] (d5) The reset transistor is disposed on the first substrate, the amplification transistor is disposed on the second substrate, and the selection transistor is disposed on the second substrate; or

[0375] (d6) The reset transistor is disposed on the second substrate, the amplification transistor is disposed on the third substrate, and the selection transistor is disposed on the third substrate; or

[0376] (d7) The reset transistor is disposed on the first substrate, the amplification transistor is disposed on the third substrate, and the selection transistor is disposed on the third substrate.

[0377] Technology 11 is advantageous from the viewpoint of suppressing the number of vias in a camera device that penetrate the substrate.

[0378] (Technology 12)

[0379] The camera device as described in any one of techniques 9 to 11,

[0380] Each pixel in the at least one pixel has:

[0381] The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation region.

[0382] A reset transistor resets the charge accumulated in the charge accumulation region; and

[0383] An overflow transistor includes a gate electrically connected to the charge storage region, which is turned on in accordance with the potential of the charge storage region to discharge the charge from the charge storage region.

[0384] (D1) The reset transistor is disposed on the first substrate, the overflow transistor is disposed on the first substrate, and the amplification transistor is disposed on the second substrate; or

[0385] (D2) The amplifying transistor is disposed on the first substrate, the overflow transistor is disposed on the second substrate, and the reset transistor is disposed on the third substrate; or

[0386] (D3) The amplifying transistor is disposed on the first substrate, the reset transistor is disposed on the second substrate, and the overflow transistor is disposed on the third substrate; or

[0387] (D4) The reset transistor is disposed on the first substrate, the overflow transistor is disposed on the second substrate, and the amplification transistor is disposed on the second substrate; or

[0388] (D5) The overflow transistor is disposed on the first substrate, the amplification transistor is disposed on the second substrate, and the reset transistor is disposed on the third substrate; or

[0389] (D6) The reset transistor is disposed on the first substrate, the amplification transistor is disposed on the second substrate, and the overflow transistor is disposed on the third substrate; or

[0390] (D7) The overflow transistor is disposed on the first substrate, the reset transistor is disposed on the second substrate, and the amplification transistor is disposed on the third substrate; or

[0391] (D8) The reset transistor is disposed on the first substrate, the overflow transistor is disposed on the second substrate, and the amplification transistor is disposed on the third substrate.

[0392] Technique 12 is advantageous from the viewpoint of suppressing the number of vias in a camera device that penetrate the substrate.

[0393] (Technology 13)

[0394] The camera device as described in any one of techniques 9 to 12,

[0395] Each pixel in the at least one pixel has:

[0396] The fourth construct; and

[0397] Third through hole,

[0398] The third structure has one of the third wiring layer pairs.

[0399] The fourth structure includes the other side of the third wiring layer pair and a fourth substrate among the plurality of substrates.

[0400] The third via penetrates the third substrate, directly connecting the third wiring layer pairs.

[0401] The third wiring layer pair, the third substrate, the other side of the third wiring layer pair, and the fourth substrate are arranged in this order.

[0402] Technique 13 is suitable for providing a fine and low-noise imaging device. Furthermore, regarding techniques 9 and 13, one side of the second wiring layer pair may be the same as or different from one side of the third wiring layer pair.

[0403] (Technology 14)

[0404] The camera device as described in Technique 13

[0405] Each pixel in the at least one pixel has:

[0406] A first transistor is disposed on the first substrate;

[0407] The second transistor is disposed on the second substrate;

[0408] A third transistor is disposed on the third substrate; and

[0409] The fourth transistor is disposed on the fourth substrate.

[0410] Technology 14 is advantageous in achieving at least one of ensuring the size of the transistor and reducing the size of the camera device.

[0411] (Technology 15)

[0412] The camera device as described in technology 13 or 14

[0413] Each pixel in the at least one pixel has:

[0414] The amplifying transistor outputs a signal corresponding to the potential of the charge accumulation region.

[0415] A reset transistor resets the charge accumulated in the charge storage region;

[0416] The selection of the transistor determines the timing of the signal output from the amplifying transistor; and

[0417] An overflow transistor includes a gate electrically connected to the charge storage region, which is turned on in accordance with the potential of the charge storage region to discharge the charge from the charge storage region.

[0418] (f1) The overflow transistor is disposed on the first substrate, the reset transistor is disposed on the second substrate, the amplification transistor is disposed on the third substrate, and the selection transistor is disposed on the fourth substrate; or

[0419] (f2) The reset transistor is disposed on the first substrate, the overflow transistor is disposed on the second substrate, the amplification transistor is disposed on the third substrate, and the selection transistor is disposed on the fourth substrate.

[0420] Technology 15 is advantageous from the viewpoint of suppressing the number of through-board vias in an imaging device.

[0421] (Technology 16)

[0422] The camera device as described in any one of techniques 1 to 15,

[0423] Each pixel in the at least one pixel has a transistor disposed on the second substrate.

[0424] The transistor includes a gate.

[0425] In the thickness direction of the second substrate, the gate is disposed between the photoelectric conversion section and the second substrate.

[0426] Technology 16 is advantageous from the perspective of achieving a low-noise first transistor.

[0427] (Technology 17)

[0428] The camera device as described in any one of techniques 1 to 16,

[0429] The photoelectric conversion unit includes a photoelectric conversion film.

[0430] The structure of Technique 17 is an example of its construction.

[0431] (Technology 18)

[0432] The camera device as described in Technique 17

[0433] The photoelectric conversion film comprises organic materials.

[0434] The composition of Technique 18 is an example of its composition.

[0435] (Technology 19)

[0436] A camera device, comprising:

[0437] The first structure includes a photoelectric conversion unit that converts light into charge, one side of a first wiring layer pair, and a first substrate;

[0438] The second structure has the other side of the first wiring layer pair and a second substrate;

[0439] The first via penetrates the first substrate; and

[0440] A charge storage region is disposed on one of a plurality of substrates including the first substrate and the second substrate, stores the charge, and is electrically connected to the first via.

[0441] The first wiring layer pair, the first substrate, the other side of the first wiring layer pair, and the second substrate are arranged in this order.

[0442] The first wiring layer is connected using the first via without using Cu-Cu bonding.

[0443] Technology 19 is suitable for providing a small and low-noise camera device.

[0444] (Technology 20)

[0445] A camera system having:

[0446] Lens optical system;

[0447] The imaging device as described in any one of techniques 1 to 19 receives light passing through the lens optical system and outputs a signal; and

[0448] The signal processing circuit processes the signal.

[0449] Technology 20 is suitable for providing a small and low-noise camera device.

[0450] (Technology 21)

[0451] A method for manufacturing a camera device, the camera device comprising:

[0452] The first structure includes a photoelectric conversion film for converting light into charge, one of the first wiring layer pairs, and a first substrate;

[0453] The second structure has the other side of the first wiring layer pair and a second substrate;

[0454] A first via penetrates the first substrate, directly connecting the first wiring layer pairs; and

[0455] A charge storage region is disposed on one of a plurality of substrates including the first substrate and the second substrate, stores the charge, and is electrically connected to the first via.

[0456] The manufacturing method includes, in sequence:

[0457] A structure including the first substrate is joined to the second structure;

[0458] A first through-hole is formed in the first substrate;

[0459] The first through hole is formed by filling it with the first conductor; and the photoelectric conversion film is formed.

[0460] Technology 21 is suitable for providing a small and low-noise camera device.

[0461] (Technology 22)

[0462] The manufacturing method as described in Technique 21

[0463] The camera device includes:

[0464] The third construct; and

[0465] Second through hole,

[0466] The second structure has one of the second wiring layer pairs.

[0467] The third structure includes the other side of the second wiring layer pair and a third substrate among the plurality of substrates.

[0468] The second via penetrates the second substrate, directly connecting the second wiring layer pairs.

[0469] The manufacturing method includes, in sequence:

[0470] A structure including the second substrate is joined to the third structure;

[0471] A second through-hole is formed in the second substrate;

[0472] The second via is formed by filling the second through hole with the second conductor.

[0473] Technology 22 is suitable for providing a small and low-noise camera device.

[0474] (Technology 23)

[0475] The manufacturing method as described in Technique 22

[0476] The camera device includes:

[0477] The fourth construct; and

[0478] Third through hole,

[0479] The third structure has one of the third wiring layer pairs.

[0480] The fourth structure includes the other side of the third wiring layer pair and a fourth substrate among the plurality of substrates.

[0481] The third via penetrates the third substrate, directly connecting the third wiring layer pairs.

[0482] The manufacturing method includes, in sequence:

[0483] A structure including the third substrate is joined to the fourth structure;

[0484] A third through-hole is formed on the third substrate; and

[0485] The third via is formed by filling the third through hole with the third conductor.

[0486] Technology 23 is suitable for providing a small and low-noise camera device.

[0487] (Technology 24)

[0488] A method for manufacturing a camera device includes:

[0489] The process is repeated, sequentially including stacking a substrate above the completed structure to increase the height of the structure, forming through holes in the substrate, and forming vias in the through holes; and

[0490] A photoelectric conversion film is formed at a position higher than the aforementioned structure.

[0491] Technology 24 is suitable for providing a small and low-noise camera device.

[0492] (other)

[0493] One side of the first routing layer pair represents the first routing. The other side of the first routing layer pair represents the second routing. One side of the second routing layer pair represents the third routing. The other side of the second routing layer pair represents the fourth routing. One side of the third routing layer pair represents the fifth routing. The other side of the third routing layer pair represents the sixth routing.

[0494] Industrial applicability

[0495] The camera device disclosed herein is useful for digital cameras and the like. The camera device disclosed herein can also be used, for example, in mobile terminals and the like.

[0496] Explanation of reference numerals in the attached figures:

[0497] Transistors 11, 12, 13, 14, 15

[0498] 11g, 12g, 13g, 14g, 15g gate

[0499] Voltage lines 21, 23, and 24

[0500] 22 signal lines

[0501] 30 Charge accumulation nodes

[0502] 35 Charge accumulation region

[0503] Camera devices 101, 201, 301, 401, 501, 601, 801, and 901

[0504] 110, 810, 910 Photoelectric Conversion Unit

[0505] 111 Photoelectric conversion film

[0506] 112 pixel electrode

[0507] 113 Opposite electrode

[0508] 965 Electrical Path

[0509] Vias 151x, 152x, 153x, 161, 162, 163, 166, 167, 961, 962

[0510] 119 Protective Film

[0511] 120 color filter

[0512] 130 microlenses

[0513] 141, 142, 143, 144, 841, 842, 941, 942 base plate

[0514] 141a and 141c silicon films

[0515] 141b, 185, 186 insulating films

[0516] 141bs lower surface

[0517] 141x, 142x, 143x semiconductor layers

[0518] 141y, 142y, 143y oxide films

[0519] Wiring layers 151, 152, 153, 154, 852, 952

[0520] Constructs 170, 171, 172, 173, 174, 870, 872, 970, 972

[0521] 176 Conductive Structure

[0522] 181, 182, 183, 881, 981 Joint Interface

[0523] 185s and 186s upper surfaces

[0524] 187 Support base plate

[0525] 188a, 188b trenches

[0526] 189a, 189b Through holes

[0527] 190 pixels

[0528] 200 camera system

[0529] 701 Lens Optical System

[0530] 702 Camera Device

[0531] 703 System Controller

[0532] 704 Signal Processing Circuit

[0533] 704 Camera Signal Processing Unit

[0534] 705 Camera System

[0535] 861 Cu-Cu bonding

[0536] 861a, 861b Cu pads

[0537] 966 Return Department

[0538] 967 Peripheral Department

Claims

1. An imaging device comprising at least one pixel, each of the at least one pixel comprises: a first structure having a photoelectric conversion section that converts light into electric charges, a first wiring, and a first substrate; a second structure having a second wiring and a second substrate; a first via that penetrates the first substrate and directly connects the first wiring and the second wiring; and an electric charge accumulation region provided in one of a plurality of substrates including the first substrate and the second substrate, accumulates the electric charges, and is electrically connected to the first via, the photoelectric conversion section, the first wiring, the first substrate, the second wiring, and the second substrate are arranged in this order.

2. The imaging device according to claim 1, the first wiring is included in a wiring layer closest to the first substrate in the first structure, the second wiring is included in a wiring layer closest to the first substrate in the second structure.

3. The imaging device according to claim 1, the first substrate has a first embedded oxide film, the first via penetrates the first embedded oxide film.

4. The imaging device according to claim 1, each of the at least one pixel comprises: a first transistor provided in the first substrate; and a second transistor provided in the second substrate.

5. The imaging device according to claim 4, one of the first transistor and the second transistor is an amplification transistor that outputs a signal corresponding to a potential of the electric charge accumulation region.

6. The imaging device according to claim 5, the other of the first transistor and the second transistor is a reset transistor that resets the electric charges accumulated in the electric charge accumulation region.

7. The imaging device according to claim 1, each of the at least one pixel comprises: an amplification transistor that outputs a signal corresponding to a potential of the electric charge accumulation region; a reset transistor that resets the electric charges accumulated in the electric charge accumulation region; and a selection transistor that determines a timing at which the signal is output from the amplification transistor, (a1) the reset transistor is provided in the first substrate, the amplification transistor is provided in the second substrate, and the selection transistor is provided in the second substrate; or (a2) the amplification transistor is provided in the first substrate, the selection transistor is provided in the first substrate, and the reset transistor is provided in the second substrate.

8. The imaging device according to claim 1, each of the at least one pixel comprises: an amplification transistor that outputs a signal corresponding to a potential of the electric charge accumulation region; a reset transistor that resets the electric charges accumulated in the electric charge accumulation region; and an overflow transistor that includes a gate electrode electrically connected to the electric charge accumulation region, is turned on in accordance with the potential of the electric charge accumulation region, and causes the electric charges to be discharged from the electric charge accumulation region, (A1) the overflow transistor is provided in the first substrate, the reset transistor is provided in the first substrate, and the amplification transistor is provided in the second substrate; or ​ (A2) the amplification transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the reset transistor is provided on the second substrate.

9. The imaging device according to claim 1, each of the at least one pixel includes: a third structure; and a second via hole, the second structure has a third wiring, the third structure has a fourth wiring and a third substrate among the plurality of substrates, the second via hole penetrates the second substrate and directly connects the third wiring and the fourth wiring, the third wiring, the second substrate, the fourth wiring, and the third substrate are arranged in this order.

10. The imaging device according to claim 9, each of the at least one pixel includes: a first transistor provided on the first substrate; a second transistor provided on the second substrate; and a third transistor provided on the third substrate.

11. The imaging device according to claim 9, each of the at least one pixel includes: a reset transistor provided on the first substrate, which resets the electric charge accumulated in the electric charge accumulation region; an amplification transistor provided on the second substrate, which outputs a signal corresponding to the potential of the electric charge accumulation region; and a selection transistor provided on the third substrate, which determines the timing of outputting the signal from the amplification transistor.

12. The imaging device according to claim 9, each of the at least one pixel includes: an amplification transistor, which outputs a signal corresponding to the potential of the electric charge accumulation region; a reset transistor, which resets the electric charge accumulated in the electric charge accumulation region; and a selection transistor, which determines the timing of outputting the signal from the amplification transistor, (d1) the reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the third substrate; or (d2) the amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the third substrate; or (d3) the amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the second substrate; or (d4) the amplification transistor is provided on the second substrate, the selection transistor is provided on the second substrate, and the reset transistor is provided on the third substrate; or (d5) the reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the second substrate; or (d6) the reset transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the third substrate; or (d7) the reset transistor is provided on the first substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the third substrate.

13. The imaging device according to claim 9, Each of the at least 1 pixels includes: an amplification transistor that outputs a signal corresponding to a potential of the charge accumulation region; A reset transistor resets the charge accumulated in the charge storage region; and an overflow transistor that includes a gate electrode electrically connected to the charge accumulation region, and is turned on in correspondence with the potential of the charge accumulation region to cause the charge to be discharged from the charge accumulation region, (D1) the reset transistor is provided on the first substrate, the overflow transistor is provided on the first substrate, and the amplification transistor is provided on the second substrate; or (D2) the amplification transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the reset transistor is provided on the third substrate; or (D3) the amplification transistor is provided on the first substrate, the reset transistor is provided on the second substrate, and the overflow transistor is provided on the third substrate; or (D4) the reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the amplification transistor is provided on the second substrate; or (D5) the overflow transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the reset transistor is provided on the third substrate; or (D6) the reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the overflow transistor is provided on the third substrate; or (D7) the overflow transistor is provided on the first substrate, the reset transistor is provided on the second substrate, and the amplification transistor is provided on the third substrate; or (D8) the reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the amplification transistor is provided on the third substrate.

14. The imaging device according to claim 9, Each of the at least 1 pixels includes: a fourth structure; and a third via, the third structure has a fifth wiring, the fourth structure has a sixth wiring and a fourth substrate among the plurality of substrates, the third via penetrates the third substrate to directly connect the fifth wiring and the sixth wiring, the fifth wiring, the third substrate, the sixth wiring, and the fourth substrate are arranged in this order.

15. The imaging device according to claim 14, Each of the at least 1 pixels includes: a first transistor provided on the first substrate; a second transistor provided on the second substrate; a third transistor provided on the third substrate; and a fourth transistor provided on the fourth substrate.

16. The imaging device according to claim 14, Each of the at least 1 pixels includes: an amplification transistor that outputs a signal corresponding to a potential of the charge accumulation region; a reset transistor that resets the charge accumulated in the charge accumulation region; a selection transistor that determines a timing at which the signal is output from the amplification transistor; and an overflow transistor that includes a gate electrode electrically connected to the charge accumulation region, and is turned on in correspondence with the potential of the charge accumulation region to cause the charge to be discharged from the charge accumulation region, ​ an overflow transistor including a gate electrode electrically connected to the charge accumulation region, which is turned on in correspondence with a potential of the charge accumulation region to cause the charge to be discharged from the charge accumulation region, (f1) the overflow transistor is provided on the first substrate, the reset transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the fourth substrate; or (f2) the reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the fourth substrate.

17. The imaging device according to claim 1, each of the at least one pixel includes a transistor provided on the second substrate, the transistor includes a gate electrode, in a thickness direction of the second substrate, the gate electrode is disposed between the photoelectric conversion portion and the second substrate.

18. The imaging device according to any one of claims 1 to 17, the photoelectric conversion portion includes a photoelectric conversion film.

19. The imaging device according to claim 18, the photoelectric conversion film includes an organic material.

20. A method for manufacturing an imaging device, comprising: joining a first structure including an insulating layer and a first substrate to a second structure including a second wiring and a second substrate in such a manner that the insulating layer, the first substrate, the second wiring, and the second substrate are arranged in this order, to form a joined body; forming a trench on a surface of the joined body on the insulating layer side; forming a via hole that penetrates through the trench to the second wiring; filling the trench and the via hole with an electrically conductive body to form a first wiring and a first via hole; and forming a photoelectric conversion portion.

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