Multi-channel data acquisition method and device and DDIC test equipment

Abstract

The invention is suitable for the technical field of semiconductor testing, and provides a multi-channel data acquisition method and device and DDIC testing equipment, and the multi-channel data acquisition method comprises the steps: controlling a DDIC chip to be tested to output a corresponding gray-scale voltage signal according to a received test pattern; outputting the gray-scale voltage signals to a plurality of target signal acquisition channels; adjusting the temperature values of the plurality of target signal acquisition channels through a temperature sensor deployed on a target signal acquisition board card; and when the temperature values of the plurality of target signal acquisition channels are within a preset temperature range, acquiring target sampling data output by the plurality of target signal acquisition channels. According to the scheme, the temperature regulation control is performed on each signal acquisition channel, and the data acquisition operation is performed after the temperature is stable, so that the thermal stability of each channel in a multi-channel environment is ensured to be consistent with the measurement condition, and the data acquisition consistency of the DDIC chip is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor testing, and particularly relates to a multi-channel data acquisition method and device and a DDIC testing device. BACKGROUND

[0002] A display driver IC (DDIC) is widely used in various displays, and its function is to convert the received image data into a driving voltage and output corresponding gray scale signals to a display panel through multiple source pins. In order to ensure the image display quality, the gray scale output of the DDIC needs to be collected with high precision in the DDIC mass production test, so as to evaluate the consistency and precision performance of its response.

[0003] In a common test system, multiple functional modules such as a communication board, a high-speed digital board, a power supply board and an analog acquisition board are usually included, and multiple signal forms and different power level circuit units are involved in the system. In the continuous operation of the device, the states of the modules may change due to different operating conditions and thermal management characteristics, and the test environment may also change over time and have some effects.

[0004] In a specific test task, the resource allocation mode of each DGT channel is usually non-fixed configuration, that is, each channel may undertake different acquisition tasks in different projects. Therefore, in order to ensure the accuracy of the gray scale data acquisition, the sampling consistency between the channels is of great significance. SUMMARY

[0005] Therefore, the embodiments of the present application provide a multi-channel data acquisition method, device and DDIC testing device, which performs temperature regulation control on each signal acquisition channel, and then performs data acquisition operation after the temperature is stable, so as to ensure the thermal stability and measurement conditions of each channel in the multi-channel environment, thereby improving the data acquisition consistency of the DDIC chip.

[0006] A first aspect of the embodiments of the present application provides a multi-channel data acquisition method applied to a DDIC testing device, wherein the DDIC testing device includes multiple signal acquisition board cards, each of the signal acquisition board cards includes multiple signal acquisition channels, and each of the signal acquisition channels at least includes an impedance conversion unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit and an analog-to-digital conversion unit in sequence.

[0007] The multi-channel data acquisition method includes:

[0008] controlling a to-be-tested DDIC chip to output corresponding gray scale voltage signals according to a received test pattern;

[0009] output the gray scale voltage signal to a plurality of target signal acquisition channels, the target signal acquisition channels being signal acquisition channels called when performing a test task of the to-be-tested DDIC chip;

[0010] adjust a temperature value of the plurality of target signal acquisition channels through a temperature sensor disposed on a target signal acquisition board card, the target signal acquisition board card being a signal acquisition board card on which the target signal acquisition channels are located;

[0011] acquire target sampling data output by the plurality of target signal acquisition channels when the temperature value of the plurality of target signal acquisition channels is within a preset temperature range.

[0012] Embodiments of the present application achieve comprehensive testing of the response capability of a chip in a full gray scale range by receiving a test pattern and controlling a DDIC chip to output a corresponding gray scale voltage signal. Further, a multi-channel synchronous sampling is achieved through a parallel target signal acquisition channel access mechanism. Finally, the temperature of a board card on which the target signal acquisition channels are located is monitored and adjusted, so that the target signal acquisition channels operate under a unified temperature condition and target sampling data is collected under the premise of stable temperature, which significantly improves the data consistency of a DDIC chip in a multi-channel parallel collection process, thereby meeting the actual needs of high-precision gray scale sampling testing.

[0013] In a possible implementation, the multi-channel data collection method further includes:

[0014] in response to a start instruction of the test task of the to-be-tested DDIC chip, sequentially transmitting the same gray scale test voltage signal to each target signal acquisition channel and performing link collection to acquire an initial sampling value of each target signal acquisition channel;

[0015] generating a corresponding channel calibration coefficient according to the initial sampling value and a standard sampling value of each target signal acquisition channel;

[0016] storing the corresponding channel calibration coefficient, and calling the corresponding channel calibration coefficient to calibrate the target sampling data when performing the test task of the to-be-tested DDIC chip.

[0017] In a possible implementation, the generating a corresponding channel calibration coefficient according to the initial sampling value and a standard sampling value of each target signal acquisition channel includes:

[0018] constructing a linear fitting model based on the initial sampling value and the corresponding standard sampling value of each target signal acquisition channel, calculating a proportional factor and an offset of the each target signal acquisition channel, and taking the proportional factor and the offset as the channel calibration coefficient.

[0019] In a possible implementation, the signal acquisition channel further comprises an FPGA unit, and the signal acquisition board card is provided with a heat dissipation structure; the temperature value of the plurality of target signal acquisition channels is adjusted by deploying a temperature sensor on the target signal acquisition board card, comprising:

[0020] obtaining a first temperature value detected by the temperature sensor;

[0021] generating a heat dissipation coefficient of the heat dissipation structure according to the first temperature value by the FPGA unit arranged on the signal acquisition board card;

[0022] According to the heat dissipation coefficient, the temperature value of the plurality of target signal acquisition channels is adjusted to keep within a preset temperature range.

[0023] In a possible implementation, the multi-channel data acquisition method further comprises:

[0024] The target sampling data is collected and analyzed, and a corresponding target gray scale image is generated;

[0025] According to the target gray scale image, a test result of the to-be-tested DDIC chip is generated.

[0026] The second aspect of the embodiment of the application provides a multi-channel data acquisition device configured in a DDIC test equipment, the DDIC test equipment comprising a plurality of signal acquisition board cards, each of the signal acquisition board cards comprising a plurality of signal acquisition channels, each of the signal acquisition channels comprising at least an impedance conversion unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit and an analog-to-digital conversion unit in sequence;

[0027] The multi-channel data acquisition device comprises:

[0028] The signal output module is configured to control the to-be-tested DDIC chip to output a corresponding gray scale voltage signal according to the received test pattern;

[0029] The signal transmission module is configured to output the gray scale voltage signal to a plurality of target signal acquisition channels, the target signal acquisition channels being signal acquisition channels called when performing a test task of the to-be-tested DDIC chip;

[0030] The temperature adjustment module is configured to adjust the temperature value of the plurality of target signal acquisition channels by deploying a temperature sensor on a target signal acquisition board card, the target signal acquisition board card being a signal acquisition board card on which the target signal acquisition channels are located;

[0031] The data acquisition module is configured to obtain target sampling data output by the plurality of target signal acquisition channels when the temperature value of the plurality of target signal acquisition channels is within a preset temperature range.

[0032] In a possible implementation, the multi-channel data acquisition device further comprises:

[0033] an image generation module configured to collect and analyze the target sampling data and generate a corresponding target grayscale image;

[0034] an image analysis module configured to generate a test result of the DDIC chip to be tested according to the target grayscale image.

[0035] In a possible implementation, the analog-to-digital conversion unit corresponding to each signal acquisition channel is configured with a same reference voltage source, and the reference voltage source is output to the reference input end of each analog-to-digital conversion unit through a buffer circuit.

[0036] In a possible implementation, the programmable gain amplification unit in the signal acquisition channel is an operational amplifier, and the precision of the operational amplifier is higher than a preset precision threshold.

[0037] The filtering unit in the signal acquisition channel is composed of a resistor and a capacitor, the resistor is a thin-film resistor, and the capacitor is an NPO type capacitor with a temperature drift coefficient lower than a preset temperature drift threshold.

[0038] A third aspect of the embodiment of the present application provides a DDIC test device, which comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the multi-channel data acquisition method according to the first aspect when executing the computer program.

[0039] A fourth aspect of the embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executable on a processor to implement the multi-channel data acquisition method according to the first aspect.

[0040] A fifth aspect of the embodiment of the present application provides a computer program product, which, when executed on a DDIC test device, enables the DDIC test device to execute the multi-channel data acquisition method according to the first aspect.

[0041] The beneficial effects of the second aspect to the fifth aspect can refer to the beneficial effects of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0043] Figure 1 is a structural schematic diagram of a DDIC test device provided by an embodiment of the present application;

[0044] Figure 2 is a structural schematic diagram of a signal acquisition channel provided by an embodiment of the present application;

[0045] Figure 3 is a flow schematic diagram of a multi-channel data acquisition method provided by an embodiment of the present application;

[0046] Figure 4 is a fan control block diagram provided by an embodiment of the present application;

[0047] Figure 5 is a structural schematic diagram of a multi-channel data acquisition device provided by an embodiment of the present application;

[0048] Figure 6 is a structural schematic diagram of another DDIC test device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, specific details such as specific system structures, techniques, etc. are presented in order to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted in order not to obscure the description of the present application with unnecessary details.

[0050] It should be understood that when used in the specification and the appended claims of the present application, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] It should also be understood that the term "and / or" used in the specification and the appended claims of the present application means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0052] As used in the specification and the appended claims herein, the term "if' can be interpreted as meaning "when" or "upon" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [the described condition or event] is detected" can be interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [the described condition or event]" or "in response to detecting [the described condition or event]" depending on the context.

[0053] In addition, in the description of the present application and the appended claims, the terms "first", "second", "third" and the like are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0054] It should be understood that the size of the serial number of each step in the embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0055] Display Driver IC (DDIC) is widely used in various types of displays. Its function is to convert the received image data into driving voltage and output the corresponding gray scale signal to the display panel through multiple source pins. In order to ensure the image display quality, high-precision collection of gray scale output of DDIC is usually required in DDIC production test to evaluate its response consistency and precision performance.

[0056] In a common test system, multiple functional modules such as communication board, high-speed digital board, power board and analog collection board are usually included, and multiple signal forms and different power level circuit units are involved in the system. During continuous operation of the equipment, the states of each module may change due to different operating conditions and thermal management characteristics, and the test environment may also change over time and have some impact.

[0057] In a specific test task, the resource allocation mode of each DGT channel is usually non-fixed configuration, that is, each channel may undertake different collection tasks in different projects. Therefore, in order to ensure the accuracy of gray scale data collection, the sampling consistency between channels is of great significance.

[0058] In order to improve the sampling consistency between channels, the application provides a multi-channel data acquisition method, device and DDIC test equipment, wherein the response capability of the chip in the full gray scale range is comprehensively tested by receiving a test pattern and controlling the DDIC chip to output a corresponding gray voltage signal; further, the multi-channel synchronous sampling is realized through the parallel target signal acquisition channel access mechanism; finally, the temperature of the board card where the target signal acquisition channel is located is monitored and adjusted, so that each target signal acquisition channel operates under the condition of uniform temperature, and the target sampling data is collected under the premise of stable temperature, which significantly improves the data consistency of the DDIC chip in the multi-channel parallel acquisition process, thereby meeting the actual needs of high-precision gray scale sampling test.

[0059] The multi-channel data acquisition method, device, DDIC test equipment, storage medium and computer program provided by the embodiments of the application are described in detail below with reference to the accompanying drawings.

[0060] Figure 1 The structure schematic diagram of the DDIC test equipment provided by the embodiments of the application is shown. The DDIC test equipment includes a plurality of signal acquisition board cards, and each signal acquisition board card includes a plurality of signal acquisition channels to realize data acquisition of the to-be-tested DDIC chip. The signal acquisition channel at least includes an impedance conversion unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit and an analog-to-digital conversion unit in sequence, which can be specifically referred to as Figure 2 .

[0061] In a possible implementation, the signal acquisition channel in the DDIC test equipment further includes an FPGA unit for real-time processing of the digital signal output by the analog-to-digital conversion unit, such as data buffering, average filtering, etc., and packaging the processed data and transmitting it to the upper host board or image analysis module through a high-speed communication interface (such as a differential pair signal link) for subsequent reconstruction and analysis of the gray scale image in the to-be-tested DDIC chip test.

[0062] In a possible implementation, the analog-to-digital conversion unit corresponding to each signal acquisition channel is configured with the same reference voltage source, which is output to the reference input end of each analog-to-digital conversion unit through a buffer circuit, to ensure the consistency of the reference voltage between the plurality of signal acquisition channels and avoid the difference between the sampling results between the channels caused by reference drift.

[0063] In a possible implementation, to further improve the consistency of channels and signal fidelity in the process of collecting gray scale signals of the DDIC chip, the programmable gain amplification unit in the signal collection channel is an operational amplifier, and the precision of the operational amplifier is higher than a preset precision threshold; the filtering unit in the signal collection channel is composed of a resistor and a capacitor, the resistor is a thin film resistor, and the capacitor is an NPO type capacitor with a temperature drift coefficient lower than a preset temperature drift threshold.

[0064] Specifically, the programmable gain amplification unit in the signal collection channel is selected from a high-precision operational amplifier, specifically an industrial or instrument grade operational amplifier with low input bias current, small input offset voltage and high common-mode rejection ratio, and the overall precision parameter of the operational amplifier is better than the preset precision threshold, for example, the input offset voltage is less than 1 mV, and the gain error is less than 0.05%. Such an operational amplifier can provide stable and consistent gain characteristics between different channels, reducing the channel offset problem caused by amplification error.

[0065] Meanwhile, the filtering unit in the signal collection channel adopts a passive RC low-pass filter composed of a high-precision resistor and a low-temperature drift capacitor. The resistor element is selected from a thin film resistor with low temperature coefficient and small resistance error, for example, the error range is within ±0.1%, and the temperature coefficient is less than 50 ppm / °C; the capacitor element is selected from an NPO type multilayer ceramic capacitor with excellent temperature stability, and the capacitance value changes little with temperature fluctuation, and the performance is stable. Through the above filtering structure, the small tolerance of the cutoff frequency of the filter in each channel based on the theoretical value can be effectively controlled, and the tolerance is usually controlled within ±1%, thereby ensuring that the suppression performance of each channel to the high-frequency noise of the input signal is basically consistent.

[0066] The optimized combination of the programmable gain amplification unit and the filtering unit can cooperatively suppress the signal processing difference between channels caused by factors such as device tolerance and temperature drift, and improve the consistency of the gray scale signal amplitude in the multi-channel sampling process and the measurement accuracy of the whole system.

[0067] In a possible implementation, a plurality of temperature sensors are arranged on each signal collection board card to monitor the temperature state of key devices or regions on the board card in real time. The temperature information is collected by the FPGA unit on the board card and reported to the central control module, and the central control module controls the working state of the heat dissipation structure (such as a fan, a heat conduction plate, etc.) according to the temperature difference of each collection board card, adjusts the heat dissipation rate of each board card, and keeps the working temperature of all collection channels within a preset consistency range, such as 30±5°C.

[0068] In the embodiment of the present application, when actually performing the sampling operation, the DDIC test device first issues a preset test pattern to the to-be-tested DDIC chip, so as to prompt the DDIC chip to output a corresponding gray-scale voltage signal. The gray-scale voltage signal enters the plurality of target signal acquisition channels in sequence through the pin card and the interface board, and forms digital data after impedance conversion, single-ended to differential conversion, amplification adjustment, filtering and analog-to-digital conversion processing. Only when it is confirmed that the temperature state of all target acquisition channels is stable and meets the set requirements, the system starts the sampling action, so as to ensure that the obtained data has good inter-channel consistency and measurement stability.

[0069] The embodiment provides a DDIC test device with reasonable structure, high adjustment precision and good channel consistency, and effectively improves the reliability and test precision of high-resolution gray-scale data acquisition.

[0070] Referring to Figure 3 , a flowchart of a multi-channel data acquisition method provided by an embodiment of the present application is shown. The multi-channel data acquisition method is applied to Figure 1 a DDIC test device shown. The DDIC test device includes a plurality of signal acquisition board cards, each of the signal acquisition board cards includes a plurality of signal acquisition channels, and each of the signal acquisition channels at least includes an impedance conversion unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit and an analog-to-digital conversion unit in sequence.

[0071] Among them, the multi-channel data acquisition method applied to the DDIC test device means that the data acquisition is performed by using a hardware system including a plurality of independent signal acquisition board cards. The device can perform a signal acquisition task for a plurality of output channels of a display driving chip in synchronization, and the test efficiency can be improved by parallel processing capability between the board cards by using a multi-board distributed architecture.

[0072] Among them, the signal acquisition board card includes a plurality of signal acquisition channels means that each physical board card integrates a plurality of independent acquisition links, and the plurality of independent acquisition links can be realized by using a multiplexing circuit design. The signal acquisition demand in different test scenes can be met by configuring independent channels.

[0073] Among them, the signal acquisition channel includes the impedance conversion unit, the single-ended to differential conversion unit, the programmable gain amplification unit, the filtering unit and the analog-to-digital conversion unit in sequence means that a complete signal processing link is constructed. The impedance conversion unit is implemented by using a high-input-impedance operational amplifier to realize signal impedance matching. The single-ended to differential conversion unit is implemented by using a differential amplifier to suppress common-mode interference. The programmable gain amplification unit is implemented by using a digital potentiometer to adjust the gain parameter. The filtering unit is implemented by using an RC network to filter high-frequency noise. The analog-to-digital conversion unit is implemented by using a high-precision ADC chip to realize signal digitization.

[0074] As Figure 3 shown, the method can include the following steps:

[0075] Step 301, controlling the to-be-tested DDIC chip to output corresponding gray scale voltage signals according to the received test pattern.

[0076] The test pattern can refer to a standard gray scale pattern used to test the output performance of the DDIC chip, which is generated by a test system (such as a master control board or host computer of a DDIC test device) and contains multiple pixel gray scales, and is used to simulate the voltage output behavior in the actual image display process. The test pattern is usually sent to the DDIC chip through a high-speed digital signal interface (such as LVDS).

[0077] The gray scale voltage signal refers to a group of analog voltage signals output by the to-be-tested DDIC chip according to the test pattern, which are output through multiple Source Pins and are used to represent different gray scale levels, such as linear voltages between 0V (black) and full scale (white).

[0078] In the embodiments of the present application, the master control board or host computer of the DDIC test device generates a specific gray scale test pattern according to the preset test standard, and sends the pattern data to the control logic of the DDIC chip through the digital interface. The image data analysis unit inside the DDIC chip receives the test pattern and maps each gray scale level in the pattern to a corresponding voltage value, and converts the digital pattern to an analog voltage through the internal digital-to-analog conversion module (DAC). The converted gray scale voltage signal is output to multiple source pins (Source Pins) in sequence. These signals are transmitted to multiple signal acquisition channels through a needle card and an interface board, which are used for subsequent voltage acquisition, analysis and comparison.

[0079] Step 302, outputting the gray scale voltage signal to multiple target signal acquisition channels.

[0080] The target signal acquisition channel is a signal acquisition channel called when performing a test task of the to-be-tested DDIC chip.

[0081] In the embodiments of the present application, the gray scale voltage signal output by the to-be-tested DDIC chip is distributed to the specified acquisition channel, for example, for a to-be-tested DDIC chip with 123 source outputs, 128 signal acquisition channels on 8 signal acquisition board cards may be called for signal acquisition.

[0082] Step 303, adjusting the temperature value of the multiple target signal acquisition channels through the temperature sensor deployed on the target signal acquisition board card.

[0083] In the embodiment of the present application, a temperature sensor is arranged on each signal acquisition board. When a test task of a to-be-tested DDIC chip is performed, the temperature sensor arranged on the target signal acquisition board is called to adjust the temperature value of the target signal acquisition channel.

[0084] In a possible implementation, the signal acquisition channel further comprises an FPGA unit, and the signal acquisition board is provided with a heat dissipation structure; and the temperature value of the plurality of target signal acquisition channels is adjusted by the temperature sensor arranged on the target signal acquisition board, comprising:

[0085] obtaining a first temperature value detected by the temperature sensor;

[0086] generating, by the FPGA unit arranged on the signal acquisition board, a heat dissipation coefficient of the heat dissipation structure according to the first temperature value;

[0087] adjusting the temperature value of the plurality of target signal acquisition channels to be within a preset temperature range according to the heat dissipation coefficient.

[0088] In the embodiment of the present application, the temperature fluctuation of the signal acquisition board caused by the difference in thermal management characteristics of different modules in the test equipment may affect the reference voltage stability of the analog-to-digital conversion unit, and thus the collection accuracy of the gray scale voltage signal is reduced.

[0089] In the embodiment of the present application, before each test task is performed, the temperature sensor can be called to collect a first temperature value of the signal acquisition board, and the data is transmitted to the FPGA unit in real time. After the FPGA unit receives the first temperature value, the target rotating speed or the refrigeration power of the heat dissipation structure is calculated by the lookup table method or the proportional-integral-derivative algorithm, and a corresponding pulse width modulation signal is generated. The signal is sent to the driving circuit of the heat dissipation structure to adjust the rotating speed of the fan or the working current of the semiconductor refrigeration sheet, so as to change the heat dissipation efficiency. When the temperature of the signal acquisition board exceeds the upper limit of the preset temperature range, the FPGA unit increases the heat dissipation coefficient to increase the operating power of the heat dissipation structure; when the temperature is lower than the lower limit of the preset temperature range, the FPGA unit reduces the heat dissipation coefficient to reduce the operating power of the heat dissipation structure. Through the closed-loop control mechanism, the temperature of the signal acquisition board is stably maintained within the preset temperature range, so as to ensure that the reference voltage source of the analog-to-digital conversion unit is not affected by the temperature drift.

[0090] Specifically, the fan can be used as the heat dissipation structure, referring to Figure 4 A fan control block diagram is provided, which comprises a temperature sensor on a signal acquisition board, a signal acquisition board FPGA, a main control board CPU and a main control board FPGA, a fan control board and a fan. The modules interact and control information through I2C, PCIE, PWM and other interfaces.

[0091] The temperature sensor on the signal acquisition board card is used for detecting the temperature of the board card in real time, and the detected temperature value is sent to the FPGA of the board card via an I2C bus; the FPGA of the signal acquisition board card further uploads the temperature value to the CPU of the host board via a PCIE bus, the CPU of the host board collects and analyzes the current temperature data of multiple board cards, judges whether heat dissipation adjustment is needed, and generates a corresponding fan speed control instruction according to the judgment result; the fan speed control instruction is issued to the FPGA of the host board via the PCIE bus, the FPGA of the host board sends the instruction to the fan control board via the I2C bus, and the fan control board outputs a PWM control signal according to the instruction to drive the fan to work, so as to adjust the heat dissipation efficiency of each signal acquisition board card. Through the closed-loop control mechanism, each signal acquisition board card can be kept in a relatively consistent temperature range when collecting the gray scale voltage signals output by the DDIC chip, effectively suppressing channel drift and sampling errors caused by temperature differences, and further improving the consistency of multi-channel data acquisition.

[0092] In step 304, when the temperature values of the plurality of target signal acquisition channels are within the preset temperature range, target sampling data output by the plurality of target signal acquisition channels is acquired.

[0093] In the embodiment of the present application, when the temperature of all target signal acquisition channels stabilizes in the preset range, data collection is started. The analog-to-digital conversion unit of each channel converts the received analog gray scale voltage signal into target sampling data and outputs it to the host unit of the DDIC test equipment through a data interface for analysis.

[0094] In the above embodiment, by receiving a test pattern and controlling the DDIC chip to output corresponding gray scale voltage signals, the response capability of the chip in the full gray scale range is comprehensively tested; further, through the parallel target signal acquisition channel access mechanism, multi-channel synchronous sampling is realized; finally, the temperature of the board card on which the target signal acquisition channel is located is monitored and adjusted, so that each target signal acquisition channel operates under uniform temperature conditions and collects target sampling data under the premise of stable temperature, which significantly improves the data consistency of the DDIC chip in the multi-channel parallel acquisition process, thereby meeting the actual needs of high-precision gray scale sampling test.

[0095] In a possible implementation, the multi-channel data acquisition method further includes:

[0096] The target sampling data is collected and analyzed, and a corresponding target gray scale image is generated;

[0097] According to the target gray scale image, a test result of the to-be-tested DDIC chip is generated.

[0098] Specifically, after obtaining the target sampling data output by the plurality of target signal acquisition channels, the sampling data can be collected and analyzed by an image generation module. For example, the sampling data of different channels can be arranged and combined in a predetermined order to form a complete data matrix. Then, a corresponding target gray scale image is generated based on the data matrix.

[0099] Further, the target gray scale image can be analyzed using an image processing algorithm. For example, the brightness distribution, color uniformity, edge sharpness, and other characteristics in the image can be detected. In this way, the quality and consistency of the gray scale voltage signal output by the DDIC chip under test can be evaluated.

[0100] Finally, based on the analysis results of the target gray scale image, a test result report of the DDIC chip under test is generated. The report can include chip performance indicators, whether the preset standard is met, and other information, which is used to determine whether the chip is qualified.

[0101] Through the above technical solutions, the present application realizes comprehensive evaluation of the output signal of the DDIC chip under test. By converting the sampling data into an intuitive gray scale image, the output characteristics of the chip can be observed and analyzed more intuitively.

[0102] In one possible implementation, in order to ensure the consistency of the data collected by the signal acquisition channel, the sampling data collected by the signal acquisition channel can be calibrated before the test task starts. Specifically, the multi-channel data acquisition method further comprises:

[0103] In response to a start instruction of the test task of the DDIC chip under test, a same gray scale test voltage signal is transmitted to each target signal acquisition channel in turn, and link acquisition is performed to obtain an initial sampling value of each target signal acquisition channel;

[0104] According to the initial sampling value and a standard sampling value of each target signal acquisition channel, a corresponding channel calibration coefficient is generated;

[0105] The corresponding channel calibration coefficient is stored, and the target sampling data is calibrated by calling the corresponding channel calibration coefficient when the test task of the DDIC chip under test is performed.

[0106] The gray scale test voltage signal is a fixed known value, which is input to all target signal acquisition channels by the same signal source. The link acquisition process covers the complete path of impedance transformation, single-ended to differential conversion, programmable gain amplification, filtering, and analog-to-digital conversion. The standard sampling value is a preset theoretical sampling value or a reference value verified by a calibration device. The channel calibration coefficient is calculated by a linear fitting model and includes a proportional factor and an offset. The calibration coefficient is stored in a non-volatile memory to ensure that it can be directly read when the test task is called.

[0107] Specifically, when the test task is started, trigger each channel to complete link acquisition and record initial sampling values by inputting the same gray scale test voltage signal to all target channels. The difference between the initial sampling values and the standard sampling values reflects the gain error and zero drift between channels. Based on a linear fitting model, the initial sampling values and the standard sampling values are least square fitted to calculate the scaling factor and the offset of each channel, and generate the calibration coefficient. After the calibration coefficient is stored, in the formal test process, the target sampling data is corrected in real time by calling the corresponding coefficient to eliminate the inherent deviation between channels. For example, if the initial sampling value of a certain channel is 5% higher than the standard value, the scaling factor in the calibration coefficient is set to 0.95, and the offset is set to the corresponding compensation value, so that the formal test data is consistent with the theoretical value after calibration. Thus, on the basis of temperature regulation, the channel difference is further eliminated, and the accuracy and consistency of multi-channel data acquisition are improved.

[0108] In one possible implementation, according to the initial sampling value and the standard sampling value of each target signal acquisition channel, a corresponding channel calibration coefficient is generated, including:

[0109] Based on the initial sampling value and the corresponding standard sampling value of each target signal acquisition channel, a linear fitting model is constructed, and the scaling factor and the offset of each target signal acquisition channel are calculated and used as the channel calibration coefficient.

[0110] Through the above technical solution, the calibration coefficient of each target signal acquisition channel can be accurately calculated, and the difference between channels can be effectively compensated. Thus, the consistency and accuracy of multi-channel data acquisition are improved, and the reliability of the test result of the DDIC chip is ensured.

[0111] Referring to Figure 5 , a structure schematic diagram of a multi-channel data acquisition device provided by an embodiment of the present application is shown, and only parts related to the embodiment of the present application are shown for ease of description.

[0112] The multi-channel data acquisition device 500 includes:

[0113] The signal output module 501 is configured to control the to-be-tested DDIC chip to output a corresponding gray scale voltage signal according to the received test pattern;

[0114] The signal transmission module 502 is configured to output the gray scale voltage signal to a plurality of target signal acquisition channels. The target signal acquisition channels are signal acquisition channels called when the test task of the to-be-tested DDIC chip is performed.

[0115] The temperature adjusting module 503 is configured to adjust temperature values of the plurality of target signal acquisition channels by a temperature sensor deployed on a target signal acquisition board card, where the target signal acquisition board card refers to a signal acquisition board card on which the target signal acquisition channels are located.

[0116] The data acquisition module 504 is configured to acquire target sampling data output by the plurality of target signal acquisition channels when the temperature values of the plurality of target signal acquisition channels are within a preset temperature range.

[0117] In the embodiments of the present application, the multi-channel data acquisition device further comprises:

[0118] The starting module is configured to, in response to a starting instruction of the to-be-tested DDIC chip test task, sequentially transmit the same gray-scale test voltage signal to each target signal acquisition channel and perform link acquisition to acquire an initial sampling value of each target signal acquisition channel.

[0119] The calibration coefficient generation module is configured to generate a corresponding channel calibration coefficient according to the initial sampling value and a standard sampling value of each target signal acquisition channel.

[0120] The calibration module is configured to store the corresponding channel calibration coefficient and call the corresponding channel calibration coefficient to calibrate the target sampling data when performing the test task of the to-be-tested DDIC chip.

[0121] In the embodiments of the present application, the calibration coefficient generation module can specifically comprise:

[0122] The fitting unit is configured to construct a linear fitting model based on the initial sampling value and the corresponding standard sampling value of each target signal acquisition channel, calculate a scale factor and an offset of the each target signal acquisition channel, and take the scale factor and the offset as the channel calibration coefficient.

[0123] In the embodiments of the present application, the signal acquisition board card is provided with a heat dissipation structure; and the temperature adjusting module can specifically comprise:

[0124] The temperature value acquisition unit is configured to acquire a first temperature value detected by the temperature sensor.

[0125] The heat dissipation coefficient generation unit is configured to generate a heat dissipation coefficient of the heat dissipation structure according to the first temperature value by an FPGA unit configured on the signal acquisition board card.

[0126] The preset temperature adjusting unit is configured to adjust the temperature values of the plurality of target signal acquisition channels to be kept within a preset temperature range according to the heat dissipation coefficient.

[0127] In the embodiments of the present application, the multi-channel data acquisition device further comprises:

[0128] an image generation module configured to aggregate and analyze the target sampling data and generate a corresponding target grayscale image;

[0129] an image analysis module configured to generate a test result of the DDIC chip to be tested according to the target grayscale image.

[0130] In the embodiments of the present application, the analog-to-digital conversion units corresponding to each of the signal acquisition channels are configured with the same reference voltage source, and the reference voltage source is output to the reference input end of each of the analog-to-digital conversion units through a buffer circuit.

[0131] In the embodiments of the present application, the programmable gain amplification unit in the signal acquisition channel is an operational amplifier, and the accuracy of the operational amplifier is higher than a preset accuracy threshold.

[0132] The filtering unit in the signal acquisition channel is composed of a resistor and a capacitor, the resistor is a thin-film resistor, and the capacitor is an NPO type capacitor with a temperature drift coefficient lower than a preset temperature drift threshold.

[0133] The multi-channel data acquisition device 500 provided by the embodiments of the present application can be applied in the multi-channel data acquisition method provided by the foregoing embodiments, and details are described in the description of the multi-channel data acquisition method provided by the foregoing embodiments, which will not be repeated here.

[0134] Figure 6 is another structural schematic diagram of a DDIC test equipment provided by the embodiments of the present application. As shown in the figure, Figure 6 the DDIC test equipment 600 of the embodiment includes at least one processor 610 (only one processor is shown in the figure), a memory 620, and a computer program 621 stored in the memory 620 and executable on the at least one processor 610, and the processor 610 implements the steps in the foregoing multi-channel data acquisition method when executing the computer program 621. Figure 6

[0135] The DDIC test equipment 600 can be a server, a physical server, a computing device, a semiconductor test equipment, etc. The DDIC test equipment can include, but is not limited to, the processor 610 and the memory 620. Those skilled in the art can understand that, Figure 6 ​The DDIC test device 600 is only an example and does not limit the DDIC test device 600, which can include more or fewer components than shown, or combine some components, or include different components, such as a plurality of signal acquisition board cards, each including a plurality of signal acquisition channels, each including, in sequence, an impedance conversion unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit, and an analog-to-digital conversion unit, and each further including an FPGA unit.

[0136] The processor 610 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0137] The memory 620 can be an internal storage unit of the DDIC test device 600, such as a hard disk or a memory of the DDIC test device 600 in some embodiments. The memory 620 can also be an external storage device of the DDIC test device 600, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. provided on the DDIC test device 600 in other embodiments. Further, the memory 620 can include both the internal storage unit and the external storage device of the DDIC test device 600. The memory 620 is used to store an operating system, an application program, a boot loader, data, and other programs, such as program codes of the computer program, etc. The memory 620 can also be used to temporarily store data that has been output or will be output.

[0138] In specific implementations, the processor 610 and the memory 620 described in the embodiments of the present application can execute the embodiments of the semiconductor test data transmission method, which will not be described here.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be realized in the form of hardware or software function unit. In addition, the specific name of each functional unit and module is only for the convenience of mutual distinction, and does not limit the protection scope of the present application. The specific working process of the unit and module in the above system can refer to the corresponding process in the foregoing method embodiment, which will not be described here.

[0140] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0141] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0142] In the embodiments provided in the present application, it should be understood that the disclosed device / DDIC testing equipment and method can be implemented in other ways. For example, the above-described device / DDIC testing equipment embodiments are only schematic, for example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0143] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0144] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0145] The integrated module / unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. The computer program can implement the steps of each method embodiment when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the computer readable medium can include appropriate contents according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0146] The above-mentioned embodiment methods can also be completed by a computer program product, which, when running on the DDIC test equipment, enables the DDIC test equipment to execute the steps in each method embodiment.

[0147] The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, rather than limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A multi-channel data acquisition method, characterized in that, This is applied to DDIC testing equipment, which includes multiple signal acquisition boards. Each signal acquisition board includes multiple signal acquisition channels, and each signal acquisition channel includes at least, in sequence, an impedance transformation unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit, and an analog-to-digital conversion unit. The multi-channel data acquisition method includes: The DDIC chip under test is controlled to output the corresponding grayscale voltage signal according to the received test pattern; The grayscale voltage signal is output to multiple target signal acquisition channels, which are the signal acquisition channels called when performing the test task of the DDIC chip under test; The temperature values ​​of the multiple target signal acquisition channels are adjusted by a temperature sensor deployed on the target signal acquisition board, where the target signal acquisition board refers to the signal acquisition board where the target signal acquisition channel is located. When the temperature values ​​of the multiple target signal acquisition channels are within a preset temperature range, the target sampling data output by the multiple target signal acquisition channels is acquired.

2. The multi-channel data acquisition method as described in claim 1, characterized in that, The multi-channel data acquisition method also includes: In response to the start command of the test task of the DDIC chip under test, the same grayscale test voltage signal is transmitted sequentially to each of the target signal acquisition channels, and link acquisition is performed to obtain the initial sampling value of each of the target signal acquisition channels; Based on the initial sampling value and standard sampling value of each target signal acquisition channel, generate the corresponding channel calibration coefficient; The corresponding channel calibration coefficients are stored, and when the test task of the DDIC chip under test is executed, the corresponding channel calibration coefficients are called to calibrate the target sampling data.

3. The multi-channel data acquisition method as described in claim 2, characterized in that, The step of generating corresponding channel calibration coefficients based on the initial sampled value and standard sampled value of each target signal acquisition channel includes: Based on the initial sampled value and the corresponding standard sampled value of each target signal acquisition channel, a linear fitting model is constructed to calculate the scaling factor and offset of each target signal acquisition channel, which are then used as the channel calibration coefficient.

4. The multi-channel data acquisition method as described in claim 1, characterized in that, The signal acquisition channel further includes an FPGA unit, and the signal acquisition board is equipped with a heat dissipation structure; adjusting the temperature values ​​of the multiple target signal acquisition channels by means of a temperature sensor deployed on the target signal acquisition board includes: Obtain the first temperature value detected by the temperature sensor; The FPGA unit configured on the signal acquisition board generates the heat dissipation coefficient of the heat dissipation structure based on the first temperature value; Based on the heat dissipation coefficient, the temperature values ​​of the multiple target signal acquisition channels are adjusted to maintain them within a preset temperature range.

5. The multi-channel data acquisition method as described in claim 1, characterized in that, The multi-channel data acquisition method also includes: The target sampling data is collected and analyzed, and a corresponding target grayscale image is generated; Based on the target grayscale image, the test results of the DDIC chip under test are generated.

6. A multi-channel data acquisition device, characterized in that, Configured in a DDIC test equipment, the DDIC test equipment includes multiple signal acquisition boards, each of the signal acquisition boards includes multiple signal acquisition channels, and each of the signal acquisition channels includes at least, in sequence, an impedance transformation unit, a single-ended to differential conversion unit, a programmable gain amplification unit, a filtering unit, and an analog-to-digital conversion unit; The multi-channel data acquisition device includes: The signal output module is used to control the DDIC chip under test to output the corresponding grayscale voltage signal according to the received test pattern; The signal transmission module is used to output the grayscale voltage signal to multiple target signal acquisition channels, wherein the target signal acquisition channels are the signal acquisition channels called when performing the test task of the DDIC chip under test; A temperature control module is used to adjust the temperature values ​​of the multiple target signal acquisition channels by means of a temperature sensor deployed on a target signal acquisition board, wherein the target signal acquisition board refers to the signal acquisition board where the target signal acquisition channel is located; The data acquisition module is used to acquire target sampling data output by the multiple target signal acquisition channels when the temperature values ​​of the multiple target signal acquisition channels are within a preset temperature range.

7. The multi-channel data acquisition device as described in claim 6, characterized in that, The multi-channel data acquisition device also includes: The image generation module is used to collect and analyze the target sampling data and generate the corresponding target grayscale image; The image analysis module is used to generate test results for the DDIC chip under test based on the target grayscale image.

8. The multi-channel data acquisition device as described in claim 6, characterized in that, Each of the signal acquisition channels is equipped with the same reference voltage source, which is output to the reference input terminal of each of the analog-to-digital converters through a buffer circuit.

9. The multi-channel data acquisition device as described in claim 6, characterized in that, The programmable gain amplification unit in the signal acquisition channel is an operational amplifier, and the accuracy of the operational amplifier is higher than a preset accuracy threshold. The filtering unit in the signal acquisition channel is composed of resistors and capacitors. The resistors are thin-film resistors, and the capacitors are NPO type capacitors with a temperature drift coefficient lower than a preset temperature drift threshold.

10. A DDIC testing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

Images