Test system of light alarm computer input interface circuit board

Abstract

The invention discloses a test system for a light alarm computer input interface circuit board, which belongs to the technical field of airborne circuit board testing and comprises a switching test device, an upper computer test unit and a programmable instrument. The switching test device comprises an MCU main control module, a test group channel selection module, a relay switching module and a square wave signal conversion circuit. The upper computer test unit comprises an instrument parameter setting module, a test group selection module and a test result judgment module; according to the invention, component-level fault detection is realized, the troubleshooting efficiency is improved, and the time cost is saved; the method is simple and easy to operate and high in practicability, and testers can quickly complete detection of the input interface circuit board after simple training.

Description

Technical Field

[0001] This invention relates to the field of airborne circuit board testing technology, and more specifically to a testing system for a light alarm computer input interface circuit board. Background Technology

[0002] Currently, a certain type of lighting alarm computer input interface circuit board serves as the core interface unit of the alarm system, undertaking key functions such as polarity protection, overvoltage protection, interference filtering, level conversion, waveform shaping, and periodic bit detection signal input. Its performance directly affects the accurate transmission of alarm signals and system reliability. Existing testing methods can only locate board-level faults, resulting in low troubleshooting efficiency.

[0003] Therefore, how to provide a test system for a light alarm computer input interface circuit board with higher troubleshooting efficiency is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a testing system for a computer input interface circuit board with light alarm.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A test system for a light alarm computer input interface circuit board includes a transfer test device, a host computer test unit, and a programmable instrument;

[0007] The switching test device includes an MCU main control module, a test group channel selection module, a relay switching module, and a square wave signal conversion circuit;

[0008] The host computer testing unit includes an instrument parameter setting module, a test group selection module, and a test result judgment module;

[0009] The test group selection module sends the test word to the MCU main control module via serial communication, and the MCU main control module determines the test group of the input interface circuit board based on the test word.

[0010] The MCU main control module is electrically connected to the test group of the input interface circuit board through the test group channel selection module and the relay switching module in sequence, and is used to test the test group of the input interface circuit board.

[0011] The instrument parameter setting module is electrically connected to the programmable instrument and is used to control the programmable instrument to output a square wave signal.

[0012] The programmable instrument is electrically connected to some of the relays in the relay switching module through the square wave signal conversion circuit, wherein the square wave signal conversion circuit is used to change the amplitude of the square wave signal output by the programmable instrument.

[0013] The programmable instrument is electrically connected to the clock pin of the CPLD chip on the input interface circuit board, and is used to trigger the CPLD chip to output test-related signals;

[0014] The CPLD chip is electrically connected to the MCU main control module, and the CPLD chip is used to send the test-related signals to the MCU main control module;

[0015] The MCU main control module uses serial communication to convert the format of the test-related signals and send them to the test result judgment module; wherein, the test result judgment module is used to judge and display whether the test group is abnormal; if the format-converted test-related signals are the same as the test words, the test group is normal, otherwise the test group is abnormal.

[0016] Preferably, the test group channel selection module includes eight 8-to-1 analog switches;

[0017] The three selection input pins of one of the eight 8-to-1 analog switches are respectively connected to the three I / O ports of the MCU main control module, and the common pin is connected to 5V DC power.

[0018] The seven channel pins of one of the eight 8-to-1 analog switches are respectively connected to the common pins of the remaining seven 8-to-1 analog switches.

[0019] The other three I / O ports of the MCU main control module are respectively connected to the three selection input pins of the remaining seven 8-to-1 analog switches.

[0020] Preferably, the relay switching module includes 55 relays;

[0021] The normally closed terminal of the m-th relay is open; where m = 1, 2, ..., 55;

[0022] The normally open terminal of the m-th relay is connected to the m-th test group;

[0023] The positive terminal of the control coil of the m-th relay is connected to the m-th channel pin; wherein, the remaining seven 8-to-1 analog switches have a total of 56 channel pins; the m-th channel pin is the m-th of the 56 channel pins;

[0024] The negative terminal of the control coil of the m-th relay is grounded;

[0025] When m is an integer from 1 to 55 excluding 30 and 32: the common terminal of the m-th relay is connected to 27V DC power;

[0026] When m is 30 or 32: the common terminal of the m-th relay is connected to the programmable instrument through the square wave signal conversion circuit.

[0027] Preferably, the negative terminal of the control coil of the m-th relay is connected to the anode of the diode Dm, and the cathode of the diode Dm is connected to the positive terminal of the control coil of the m-th relay, where m = 1, 2, ..., 55.

[0028] Preferably, when m takes the integer from 1 to 55, excluding 30 and 32;

[0029] The m-th test group consists of a level conversion circuit and the IOm-1 pin of the CPLD connected in sequence from input to output;

[0030] When m is 30;

[0031] The 30th test group consists of a level shifting circuit, an oscillator integrated circuit, and the IO29 pin of a CPLD connected in sequence from input to output; the 30th test group shares a level shifting circuit with the 29th test group.

[0032] When m is 32;

[0033] The 32nd test group consists of a level shifting circuit, an oscillator integrated circuit, and the IO31 pin of a CPLD connected in sequence from input to output; the 32nd test group shares a level shifting circuit with the 31st test group; and the 30th and 32nd test groups share an oscillator integrated circuit.

[0034] Preferably, the square wave signal conversion circuit includes resistor R3, resistor R4, and a transistor;

[0035] One end of the resistor R3 is connected to the programmable instrument, and the other end is connected to the base of the transistor.

[0036] The collector of the transistor is connected to the 27V DC power supply through the resistor R4;

[0037] The emitter of the transistor is grounded.

[0038] Preferably, the adapter test device further includes a voltage conversion module, which is used to convert the 27V DC power to the 5V DC power.

[0039] Preferably, the host computer test unit further includes a power-on control module, which is connected to the voltage conversion module and is used to provide the 27V DC power to the voltage conversion module.

[0040] Preferably, pins IO55 to IO62 of the CPLD chip are connected to the other eight I / O ports of the MCU main control module. The CPLD chip is used to send 8-bit binary parallel data output from pins IO55 to IO62 to the MCU main control module. The MCU main control module is used to convert the 8-bit binary parallel data into hexadecimal data and send it to the test result judgment module. The 8-bit binary parallel data is the test-related signal.

[0041] Preferably, the OUT1 pin of the programmable instrument is connected to the clock pin IN4 of the CPLD chip to provide a first square wave signal to the clock pin IN4; wherein the first square wave signal has a frequency of 1kHz, an amplitude of 5V, and a duty cycle of 50%.

[0042] The OUT2 pin of the programmable instrument is connected to one end of the resistor R3 to provide a second square wave signal to the square wave signal conversion circuit; wherein the frequency of the second square wave signal is 1kHz, the amplitude is 5V, and the duty cycle is 50%; wherein the collector of the transistor outputs a third square wave signal, the frequency of the third square wave signal is 1kHz, the amplitude is 27V, and the duty cycle is 50%.

[0043] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a testing system for a light alarm computer input interface circuit board, which has the following beneficial technical effects:

[0044] (1) The present invention realizes component-level fault detection, which improves troubleshooting efficiency and saves time costs compared with board-level fault location in the prior art;

[0045] (2) This invention is simple and easy to operate, and has strong practicality. After simple training, testers can quickly complete the testing of the input interface circuit board. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1A schematic diagram of a test system for a light alarm computer input interface circuit board provided in a certain embodiment of the present invention;

[0048] Figure 2 The circuit schematic diagram of the MCU main control module provided in a certain embodiment of the present invention;

[0049] Figure 3 A circuit diagram of eight 8-to-1 analog switches provided in a certain embodiment of the present invention;

[0050] Figure 4 A circuit diagram of a relay and level conversion circuit provided in a certain embodiment of the present invention;

[0051] Figure 5 The circuit diagram of a relay, level conversion circuit, and programmable instrument provided in a certain embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] like Figure 1 As shown, this embodiment of the invention discloses a test system for a computer input interface circuit board for light alarms, including a conversion test device, a host computer test unit, and a programmable instrument;

[0054] The switching test device includes an MCU main control module, a test group channel selection module, a relay switching module, and a square wave signal conversion circuit;

[0055] The host computer testing unit includes an instrument parameter setting module, a test group selection module, and a test result judgment module;

[0056] The test group selection module sends the test word to the MCU main control module via serial communication, and the MCU main control module determines the test group of the input interface circuit board based on the test word.

[0057] The MCU main control module is electrically connected to the test group of the input interface circuit board through the test group channel selection module and the relay switching module in sequence, and is used to test the test group of the input interface circuit board.

[0058] The instrument parameter setting module is electrically connected to the programmable instrument and is used to control the programmable instrument to output a square wave signal.

[0059] The programmable instrument is electrically connected to some of the relays in the relay switching module through the square wave signal conversion circuit, wherein the square wave signal conversion circuit is used to change the amplitude of the square wave signal output by the programmable instrument.

[0060] The programmable instrument is electrically connected to the clock pin of the CPLD chip on the input interface circuit board, and is used to trigger the CPLD chip to output test-related signals;

[0061] In one embodiment, such as Figure 5 As shown, the OUT1 pin of the programmable instrument is connected to the clock pin IN4 of the CPLD chip, and is used to provide a first square wave signal to the clock pin IN4; wherein, the frequency of the first square wave signal is 1kHz, the amplitude is 5V, and the duty cycle is 50%.

[0062] The CPLD chip is electrically connected to the MCU main control module, and the CPLD chip is used to send the test-related signals to the MCU main control module;

[0063] The MCU main control module uses serial communication to convert the format of the test-related signals and send them to the test result judgment module; wherein, the test result judgment module is used to judge and display whether the test group is abnormal; if the format-converted test-related signals are the same as the test words, the test group is normal, otherwise the test group is abnormal.

[0064] In one embodiment, the test group channel selection module includes eight 8-to-1 analog switches;

[0065] The three selection input pins of one of the eight 8-to-1 analog switches are respectively connected to the three I / O ports of the MCU main control module, and the common pin is connected to 5V DC power.

[0066] The seven channel pins of one of the eight 8-to-1 analog switches are respectively connected to the common pins of the remaining seven 8-to-1 analog switches.

[0067] The other three I / O ports of the MCU main control module are respectively connected to the three selection input pins of the remaining seven 8-to-1 analog switches.

[0068] In one embodiment, such as Figure 2 and Figure 3 As shown, the MCU main control module uses a single-chip microcomputer P80C51; the eight 8-to-1 analog switches all use CD4051, and are denoted as U1-U8 respectively;

[0069] The P1.0 pin of the P80C51 microcontroller is connected to the C pin of U1;

[0070] The P1.1 pin of the P80C51 microcontroller is connected to the B pin of U1;

[0071] The P1.2 pin of the P80C51 microcontroller is connected to the A pin of U1;

[0072] The P1.3 pin of the P80C51 microcontroller is connected to the C pins of U2-U8 respectively;

[0073] The P1.4 pin of the P80C51 microcontroller is connected to the B pin of U2-U8 respectively;

[0074] The P1.5 pin of the P80C51 microcontroller is connected to the A pin of U2-U8 respectively;

[0075] The X pin of U1 is connected to a 5V DC power supply.

[0076] The X0-X6 pins of U1 are connected to the X pins of U2-U8 respectively;

[0077] U1-U8 _ E __ N _ The pins VEE, GND, and VCC are all grounded, and the VCC pin is connected to 5V DC.

[0078] It is understood that the P1.0, P1.1, and P1.2 pins of the P80C51 microcontroller are used to select which chip from U2 to U8 to use. After determining which chip from U2 to U8 to use, the P1.3, P1.4, and P1.5 pins of the P80C51 microcontroller are then used to determine which channel pin from X0 to X7 to output a high level.

[0079] For example: When pins P1.0, P1.1, and P1.2 output a low level, pin X0 of U1 outputs a high level to pin X of U2, and U2 is selected. If pins P1.3, P1.4, and P1.5 output a low level, pin X0 of U2 outputs a high level to the positive terminal of the control coil of the first relay. When the positive terminal of the control coil of the first relay is high, the first relay is energized (i.e., the common terminal of the first relay is connected to the normally open terminal), and the normally open terminal of the first relay outputs a high level. The high level output by the normally open terminal of the first relay is converted to a low level by the level conversion circuit connected to pin IO0 and then input to pin IO0 of the CPLD chip.

[0080] In one embodiment, the relay switching module includes 55 relays;

[0081] The normally closed terminal of the m-th relay is open; where m = 1, 2, ..., 55;

[0082] The normally open terminal of the m-th relay is connected to the m-th test group;

[0083] The positive terminal of the control coil of the m-th relay is connected to the m-th channel pin; wherein, the remaining seven 8-to-1 analog switches have a total of 56 channel pins; the m-th channel pin is the m-th of the 56 channel pins;

[0084] In one embodiment, such as Figure 3 , Figure 4 and Figure 5 As shown;

[0085] The positive terminals of the control coils of the 1st to 8th relays are connected to pins X0-X7 of U2, respectively.

[0086] The positive terminals of the control coils of the 9th to 16th relays are connected to pins X0-X7 of U3, respectively.

[0087] The positive terminals of the control coils of the 17th to 24th relays are connected to pins X0-X7 of U4, respectively.

[0088] The positive terminals of the control coils of the 25th to 32nd relays are connected to pins X0-X7 of U5, respectively.

[0089] The positive terminals of the control coils of the 33rd to 40th relays are connected to pins X0-X7 of U6, respectively.

[0090] The positive terminals of the control coils of the 41st to 48th relays are connected to the X0-X7 pins of U7, respectively.

[0091] The positive terminals of the control coils of the 49th to 55th relays are connected to the X0-X6 pins of U8, respectively.

[0092] The negative terminal of the control coil of the m-th relay is grounded;

[0093] That is, the negative terminals of the control coils of relays 1 through 55 are all grounded.

[0094] When m is an integer from 1 to 55 excluding 30 and 32: the common terminal of the m-th relay is connected to 27V DC power;

[0095] When m is 30 or 32: the common terminal of the m-th relay is connected to the programmable instrument through the square wave signal conversion circuit.

[0096] In one embodiment, the common terminal of the 30th relay is connected to the OUT2 pin of the programmable instrument through the square wave signal conversion circuit; the common terminal of the 32nd relay is connected to the OUT2 pin of the programmable instrument through the square wave signal conversion circuit.

[0097] The OUT2 pin of the programmable instrument is used to output a second square wave signal; wherein the frequency of the second square wave signal is 1kHz, the amplitude is 5V, and the duty cycle is 50%.

[0098] In one embodiment, the negative terminal of the control coil of the m-th relay is connected to the anode of the diode Dm, and the cathode of the diode Dm is connected to the positive terminal of the control coil of the m-th relay, where m = 1, 2, ..., 55.

[0099] It is understandable that:

[0100] When m = 1, Dm = D1;

[0101] When m = 2, Dm = D2; ...

[0103] When m = 29, Dm = D29;

[0104] When m = 30, Dm = D30;

[0105] When m = 31, Dm = D31;

[0106] When m = 32, Dm = D32; ...

[0108] When m = 54, Dm = D54;

[0109] When m = 55, Dm = D55;

[0110] The diode Dm is a freewheeling diode used to protect the m-th relay from damage.

[0111] In one embodiment, when m takes the integer from 1 to 55 other than 30 and 32;

[0112] The m-th test group consists of a level conversion circuit and the IOm-1 pin of the CPLD connected in sequence from input to output;

[0113] When m is 30;

[0114] The 30th test group consists of a level shifting circuit, an oscillator integrated circuit, and the IO29 pin of a CPLD connected in sequence from input to output; the 30th test group shares a level shifting circuit with the 29th test group.

[0115] When m is 32;

[0116] The 32nd test group consists of a level shifting circuit, an oscillator integrated circuit, and the IO31 pin of a CPLD connected in sequence from input to output; the 32nd test group shares a level shifting circuit with the 31st test group; and the 30th and 32nd test groups share an oscillator integrated circuit.

[0117] It is understandable that the 55 test groups comprise 53 level conversion circuits, all of which have the same structure. Taking the level conversion circuit of the first test group as an example: the level conversion circuit, from input to output, includes diode N1A, Zener diode VR1, resistor R1, resistor R46, capacitor C13, Zener diode VR46, and inverter. The anode of diode N1A is connected to the normally open terminal of the first relay, and the output of the inverter is connected to the IO0 pin of the CPLD chip.

[0118] The oscillator integrated circuit uses CD54HCT123. Pin 1 of CD54HCT123DE is connected to pin IO28 of the CPLD chip; pin 4 is connected to pin IO29 of the CPLD chip; pin 9 is connected to pin IO30 of the CPLD chip; and pin 12 is connected to pin IO31 of the CPLD chip.

[0119] It is understandable that when m is 30, the activated level conversion circuit is used to convert the third-party square wave signal output by the square wave signal conversion circuit with a frequency of 1kHz, an amplitude of 27V, and a duty cycle of 50% into a square wave signal with a frequency of 1kHz, an amplitude of 5V, and a duty cycle of 50%, which is input to pin 1 of CD54HCT123. Pin 4 of CD54HCT123 outputs a square wave signal with a frequency of 1kHz, an amplitude of 5V, and a duty cycle of 50% to pin IO29 of the CPLD chip. Pin IO29 of the CPLD chip is triggered, and the CPLD chip outputs the test-related signal of the 30th test group.

[0120] When m is 32, the activated level conversion circuit converts the 1kHz, 27V, 50% duty cycle square wave signal output by the square wave signal conversion circuit into a 1kHz, 5V, 50% duty cycle square wave signal, which is input to pin 9 of CD54HCT123. Pin 12 of CD54HCT123 outputs a 1kHz, 5V, 50% duty cycle square wave signal to pin IO31 of the CPLD chip. Pin IO29 of the CPLD chip is triggered, and the CPLD chip outputs the test-related signal for the 32nd test group.

[0121] When m is an integer from 1 to 55 excluding 30 and 32, the enabled level conversion circuit is used to convert 27V DC to 0V DC and input it to the IOm-1 pin of the CPLD chip. When the clock pin IN4 of the CPLD chip is rising, the IOm-1 pin of the CPLD chip is triggered, and the CPLD chip outputs the test-related signal of the m-th test group.

[0122] It is understandable that:

[0123] When m = 1, IOm-1 = IO0;

[0124] When m = 2, IOm-1 = IO1; ...

[0126] When m = 29, IOm-1 = IO28;

[0127] When m = 31, IOm-1 = IO30; ...

[0129] When m = 54, IOm-1 = IO53;

[0130] When m = 55, IOm-1 = IO54;

[0131] In one embodiment, the square wave signal conversion circuit includes resistor R3, resistor R4, and a transistor;

[0132] One end of the resistor R3 is connected to the programmable instrument, and the other end is connected to the base of the transistor.

[0133] The collector of the transistor is connected to the 27V DC power supply through the resistor R4;

[0134] The emitter of the transistor is grounded.

[0135] In one embodiment, the OUT2 pin of the programmable instrument is connected to one end of the resistor R3 to provide a second square wave signal to the square wave signal conversion circuit; wherein the second square wave signal has a frequency of 1kHz, an amplitude of 5V, and a duty cycle of 50%; wherein the collector of the transistor outputs a third square wave signal, the third square wave signal having a frequency of 1kHz, an amplitude of 27V, and a duty cycle of 50%.

[0136] It is understood that the square wave signal conversion circuit is used to convert a second square wave signal with a frequency of 1kHz, an amplitude of 5V, and a duty cycle of 50% into a third square wave signal with a frequency of 1kHz, an amplitude of 27V, and a duty cycle of 50%.

[0137] It is understandable that resistors R3 and R4 serve as current limiters, and the transistor acts as a switch.

[0138] In one embodiment, the adapter test device further includes a voltage conversion module for converting the 27V DC power to the 5V DC power.

[0139] In one embodiment, the host computer test unit further includes a power-on control module, which is connected to the voltage conversion module and is used to provide the 27V DC power to the voltage conversion module.

[0140] In one embodiment, pins IO55 to IO62 of the CPLD chip are respectively connected to eight other I / O ports of the MCU main control module; wherein, the CPLD chip is used to send 8-bit binary parallel data output from pins IO55 to IO62 to the MCU main control module, and the MCU main control module is used to convert the 8-bit binary parallel data into hexadecimal data and send it to the test result judgment module; the 8-bit binary parallel data is the test-related signal.

[0141] In one embodiment, the MCU main control module adopts a single-chip microcomputer P80C51;

[0142] The IO55 to IO62 pins of the CPLD chip are respectively connected to the P0.0 to P0.7 pins of the P80C51 microcontroller (e.g., ...). Figure 2 (As shown).

[0143] In one embodiment, when the MCU main control module communicates with the test group selection module (or test result judgment module) via serial port, it uses the following method: Figure 2 The serial communication module shown includes a MAX232 and a nine-pin serial port socket; the microcontroller P80C51 is connected to the test group selection module (or test result judgment module) in sequence through the MAX232, the nine-pin serial port socket, and the serial communication module of the host computer test unit.

[0144] In one embodiment, such as Figure 2 As shown, the MCU main control module also includes a reset circuit and a crystal oscillator circuit. The reset circuit and crystal oscillator circuit can be found in the datasheet of the P80C51 microcontroller.

[0145] Finally, it should be noted that this invention assigns a test word to each of the 55 test groups:

[0146] The working principle of this invention will be explained below using the fourth test group (i.e., the test group containing the IO3 pin of the CPLD chip) as an example:

[0147] Assuming the fourth test group is selected for testing, its test word is 0X04. The tester selects the fourth test group (which includes the CPLD chip's IO3 pin and the level conversion circuit enabled by the IO3 pin) through the test group selection module. The test group selection module sends the test word 0X04 to the P80C51 microcontroller via serial communication. After receiving 0X04, the P80C51 microcontroller controls its P1.0-P1.5 pins to output 000011. After the P80C51 microcontroller's P1.0-P1.5 pins output 000011, the X3 pin of U2 outputs a high level, the fourth relay is energized, and the normally open terminal of the fourth relay outputs a 27V high level to the level conversion circuit connected to the IO3 pin. The level conversion circuit connected to the IO3 pin converts the 27V high level to a 0V low level and inputs it to the CPLD chip's IO3 pin. When the CPLD chip's clock pin IN4 is rising and the IO3 pin... When the pin is low, the IO3 pin is triggered. The CPLD chip controls its I055-IO62 pins to output 8-bit binary parallel data 00000100 and send it to the P80C51 microcontroller. The P80C51 microcontroller converts 00000100 into hexadecimal data 0X04 and sends it to the test result judgment module. The test result judgment module compares the sent test word with the received hexadecimal data. If they match, the fourth test group is considered normal; if they do not match, the fourth test group is considered abnormal. This is because if the fourth test group is abnormal, the level of the IO3 pin may not be normal, and the output of the CPLD chip's I055-IO62 pins will not be 00000100. In that case, the hexadecimal data received by the test result judgment module will be different from the sent test word. By judging whether the sent test word and the received hexadecimal data are the same, the test result judgment module can determine whether there is an abnormality in the test group.

[0148] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0149] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A testing system for a computer input interface circuit board with light alarm function, characterized in that, The application relates to a relay switching test device, which comprises a relay switching test device, a host computer test unit and a programmable instrument. The relay switching test device comprises an MCU master module, a test group channel selection module, a relay switching module and a square wave signal conversion circuit. The host computer test unit comprises an instrument parameter setting module, a test group selection module and a test result judgment module. The test group selection module sends a test word to the MCU master module in a serial communication mode, and the MCU master module determines a test group of an input interface circuit board based on the test word. The MCU master module is electrically connected to the test group of the input interface circuit board through the test group channel selection module and the relay switching module in sequence, and is used for testing the test group of the input interface circuit board. The instrument parameter setting module is electrically connected to the programmable instrument, and is used for controlling the programmable instrument to output a square wave signal. The programmable instrument is electrically connected to part of relays in the relay switching module through the square wave signal conversion circuit, and the square wave signal conversion circuit is used for changing the amplitude of the square wave signal output by the programmable instrument. The programmable instrument is electrically connected to the clock pin of a CPLD chip of the input interface circuit board, and is used for triggering the CPLD chip to output a test related signal. The CPLD chip is electrically connected to the MCU master module, and is used for sending the test related signal to the MCU master module. The MCU master module sends the test related signal to the test result judgment module after format conversion in a serial communication mode, and the test result judgment module is used for judging and displaying whether a test group is abnormal; if the test related signal after format conversion is the same as the test word, the test group is normal, otherwise, the test group is abnormal.

2. The test system of a light warning computer input interface circuit board according to claim 1, characterized in that, The test group channel selection module comprises eight 8-to-1 analog switches. Three selection input pins of one of the eight 8-to-1 analog switches are connected to three IO ports of the MCU master module, and a common pin is connected to 5V direct current. Seven channel pins of one of the eight 8-to-1 analog switches are connected to common pins of the remaining seven 8-to-1 analog switches. The other three IO ports of the MCU master module are connected to three selection input pins of the remaining seven 8-to-1 analog switches.

3. The test system of claim 2, wherein, The relay switching module comprises 55 relays. The normally closed end of the mth relay is disconnected, and m=1, 2,..., 55. The normally open end of the mth relay is connected to the mth test group. The positive end of the control coil of the mth relay is connected to the mth channel pin, and the remaining seven 8-to-1 analog switches have 56 channel pins; the mth channel pin is the mth channel pin in the 56 channel pins. The negative end of the control coil of the mth relay is grounded. When m is an integer from 1 to 55 except 30 and 32, the common end of the mth relay is connected to 27V direct current. When m takes 30 and 32: the common end of the mth relay is connected with the programmable instrument through the square wave signal conversion circuit.

4. The test system of claim 3, wherein, The negative end of the control coil of the mth relay is connected with the anode of diode Dm, and the cathode of the diode Dm is connected with the positive end of the control coil of the mth relay, wherein m = 1, 2, …, 55.

5. The test system of claim 3, wherein: When m takes an integer from 1 to 55 except 30 and 32; The mth test group comprises an input-to-output level conversion circuit and IOm-1 pin of the CPLD connected in sequence; When m takes 30: The 30th test group comprises an input-to-output level conversion circuit, oscillator integrated circuit and IO29 pin of the CPLD connected in sequence; wherein the 30th test group shares a level conversion circuit with the 29th test group; When m takes 32: The 32nd test group comprises an input-to-output level conversion circuit, oscillator integrated circuit and IO31 pin of the CPLD connected in sequence; wherein the 32nd test group shares a level conversion circuit with the 31st test group; the 30th test group and the 32nd test group share an oscillator integrated circuit.

6. The test system of claim 3, wherein, The square wave signal conversion circuit comprises a resistor R3, a resistor R4 and a triode; One end of the resistor R3 is connected with the programmable instrument, and the other end is connected with the base of the triode; The collector of the triode is connected with the 27V DC through the resistor R4; The emitter of the triode is grounded.

7. A test system for a light warning computer input interface circuit board as defined in claim 6, wherein, The adapter test device further comprises a voltage conversion module for converting the 27V DC into 5V DC.

8. The test system of claim 7, wherein, The host computer test unit further comprises a power-on control module connected with the voltage conversion module for providing the voltage conversion module with the 27V DC.

9. The test system of claim 6, wherein, The IO55 pin to IO62 pin of the CPLD chip are connected with the other 8 IO ports of the MCU master module; wherein the CPLD chip is used to send 8-bit binary parallel data output by the IO55 pin-IO62 pin to the MCU master module, and the MCU master module is used to convert the 8-bit binary parallel data into hexadecimal data and send it to the test result judgment module; the 8-bit binary parallel data is the test related signal.

10. The test system of claim 6, wherein: The OUT1 pin of the programmable instrument is connected with the clock pin IN4 of the CPLD chip for providing the clock pin IN4 with a first square wave signal; wherein the frequency of the first square wave signal is 1 kHz, the amplitude is 5V, and the duty cycle is 50%; The OUT2 pin of the programmable instrument is connected with one end of the resistor R3, for providing a second square wave signal for the square wave signal conversion circuit; wherein the frequency of the second square wave signal is 1 kHz, the amplitude is 5 V, and the duty cycle is 50%; wherein the collector of the triode outputs a third square wave signal, the frequency of the third square wave signal is 1 kHz, the amplitude is 27 V, and the duty cycle is 50%.

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