Heterogeneous integration method and structure of thin film lithium niobate and light-transmitting substrate waveguide system

Abstract

The invention relates to the technical field of photon calculation, in particular to a heterogeneous integration method and structure of a thin film lithium niobate and light-transmitting substrate waveguide system.The heterogeneous integration method comprises the steps that S101, a shielding layer is deposited on the first surface of a light-transmitting substrate, the shielding layer is used for protecting the light-transmitting substrate in the subsequent etching process, and the shielding layer is used for protecting the light-transmitting substrate in the subsequent etching process; meanwhile, the optical coupling effect between the light-transmitting substrate and light is improved; s102, depositing a first waveguide layer on the second surface of the shield layer; s103, depositing a covering layer around the first waveguide layer, wherein the covering layer is flush with the upper surface of the first waveguide layer; s104, depositing a second waveguide layer on the first waveguide layer and the covering layer; wherein the second waveguide layer is a thin-film lithium niobate layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photonic computing, in particular to a hetero-integration method and structure of a thin film lithium niobate and a light-transmitting substrate waveguide system. BACKGROUND

[0002] With the increasing demand for AI chip computing power, the demand for high-density computing, machine learning, parallel computing and HPC applications in the field of AI and other fields has put higher requirements on chips. For example, the new generation of EPYC processors of AMD supports up to 384 threads, with a maximum of 192 cores, of which 16 "Zen 5" CCDs (core complex chips) are configured. The CCD chip manufacturing process is advanced, using TSMC's 3-nanometer process, while the central I / O chip (IOD) uses a 4-nanometer process, showing the demand for higher processes for chips in the AI era. With the gradual increase of AI computing power, the hardware circuit is highly complex, and the traditional PCB organic substrate and TSV technology will likely become a short board in the production of AI chips and other high-performance computing chips in the future.

[0003] Glass substrates have high surface flatness and low roughness, which is beneficial to high-density RDL wiring. They have excellent chemical stability and can effectively resist environmental erosion such as moisture, acid and alkali. Glass substrates can effectively resist warping problems during packaging. At the same time, they have superior electrical properties, high resistivity and low dielectric constant, which can reduce transmission loss and ensure interconnection density and signal integrity. In addition, the package size variation of glass substrate packaging brings significant cost benefits. The mismatch between rectangular chips and circular silicon interlayers will cause waste at the edge of the wafer and further deteriorate the use efficiency when the chip size becomes larger. Using large-scale rectangular glass as a carrier or finally as an interlayer can accommodate more chips in one carrier or interlayer, which can significantly improve the efficiency of advanced packaging. Therefore, GCP (glass circuit board) as a new substrate material for the iteration and upgrading of organic substrates, with its low CTE value, low dielectric loss, high Young's modulus, high surface flatness, and large size (510mm*515mm) preparation capability, is more conducive to realizing large size, low power AI computing chips and many other advantages, and is valued worldwide. Based on this, the existing technology proposes to use glass substrates as carriers to prepare various optical devices, such as optical waveguides.

[0004] In addition, lithium niobate is a multifunctional material with electro-optic effect, nonlinear optics, piezoelectricity, ferroelectricity, etc., and has been widely used in optical communication, integrated optoelectronic devices and other fields. Compared with bulk lithium niobate, thin film lithium niobate has excellent electro-optic properties and on-chip integration characteristics, and has gradually become a potential solution for the next generation of photonic integrated devices. The development of modulators, optical microcavities, mode converters and other devices based on thin film lithium niobate platform provides a possibility for solving the current demand for optical communication and signal processing. In order to realize the optoelectronic devices based on thin film lithium niobate, various integrated optical waveguide structures need to be designed. It is of great significance to realize high processing precision and low loss optical waveguide structure through process preparation for the processing of large-scale thin film lithium niobate optoelectronic devices and effectively improving the performance of the devices.

[0005] However, it is still an international problem to process low-loss thin film lithium niobate waveguide. Using photolithography and etching process to process waveguide on thin film lithium niobate wafer is a research hotspot in recent years. The traditional preparation method of thin film lithium niobate waveguide is to etch thin film lithium niobate using metal or silicon dioxide as hard mask, such as patent numbers CN114755761A and CN110764185A. The two patent methods etch thin film lithium niobate using metal hard mask. Since this method uses fluorine-based gas, lithium fluoride and other by-products will inevitably be attached to the surface of the waveguide during the etching process, thereby increasing the sidewall roughness of the waveguide and increasing the transmission loss of the waveguide. On the other hand, the hard mask will reduce the size accuracy of the waveguide preparation, which is not conducive to fine processing.

[0006] Nanoimprint Lithography (NIL) is a method that directly uses mechanical contact and extrusion to make the material being imprinted re-distribute between the template and the substrate. It has the advantages of simple process, low cost, high yield, and large-scale production, and has become the most promising patterning technology. Its precision is not limited by the physical limit of optical diffraction, and it also saves the cost of optical lithography mask and the use of optical imaging equipment, and has wide application in display, semiconductor and other fields.

[0007] For example, the patent application CN119535884A discloses a nanoimprint master and an optical waveguide and a manufacturing method thereof, which can solve the defects of edge failure and uneven residual glue in the grating structure area in the nanoimprint process. The steps for preparing the optical waveguide include: first preparing a master plate, then using the master plate to press the substrate of the sub-plate to form a nanoimprint sub-plate after curing; and using the nanoimprint sub-plate to press the waveguide substrate to form an optical waveguide after curing.

[0008] For example, the patent application with the publication number CN118363259A discloses a nanoimprint template preparation method and an optical waveguide preparation method. The nanoimprint template preparation method includes the following steps: providing a substrate with a silicon oxide layer on the surface; performing a patterning process on the silicon oxide layer to form a pattern structure on the silicon oxide layer, the pattern structure having a micro-nano size; and performing a heat treatment on the substrate with the pattern structure to prepare a nanoimprint template. Meanwhile, an optical waveguide preparation method is also provided, which specifically includes the following steps: using the nanoimprint template to perform nanoimprinting and etching, and transferring the pattern structure with the micro-nano size to a composite waveguide substrate composed of silicon and silicon oxide, so as to obtain an optical waveguide with the pattern structure with the micro-nano size.

[0009] However, the above-mentioned scheme is to deposit a waveguide on a traditional SOI substrate, which is not suitable for preparing an optical waveguide with a large-area pattern structure on a large-area light-transmitting substrate, such as a glass substrate, especially for preparing a thin-film lithium niobate optical waveguide with a large-area pattern structure. SUMMARY

[0010] The present application aims to provide a method and structure for hetero-integration of a thin-film lithium niobate and a light-transmitting substrate waveguide system, which partially solves or alleviates the above-mentioned deficiencies in the prior art, can improve the uniformity of the etched waveguide (i.e., improve the device performance) to a certain extent when preparing an optical waveguide and / or a thin-film lithium niobate waveguide on a large-area light-transmitting substrate, and can protect the structure below the light-transmitting substrate and / or the thin-film lithium niobate layer, thereby preventing damage to the light-transmitting substrate during the etching process and improving the yield of the optical waveguide.

[0011] To solve the above-mentioned technical problems, the present application specifically adopts the following technical solutions: The first aspect of the present application provides a method for hetero-integration of a thin-film lithium niobate and a light-transmitting substrate waveguide system, which includes the following steps: S101, depositing a first shield layer on a first surface of a light-transmitting substrate, the first shield layer being used to protect the light-transmitting substrate during subsequent etching; S102, depositing a first waveguide layer on a second surface of the first shield layer; S103, depositing a first cover layer around the first waveguide layer, the upper surface of the first cover layer being flush with the upper surface of the first waveguide layer; S104, depositing a second shield layer on the upper surface of the first waveguide layer and the upper surface of the first cover layer; S105, depositing a second waveguide layer on the second shield layer; wherein the second waveguide layer is a thin-film lithium niobate layer.

[0012] In some embodiments, the light-transmitting substrate is a glass substrate.

[0013] In some embodiments, the first waveguide layer is patterned on the first mask layer by using nano-imprint lithography in step S102. In some embodiments, the second waveguide layer is patterned on the first cover layer and the first waveguide layer by using nano-imprint lithography in step S105.

[0014] In some embodiments, step S101 specifically comprises: S1011, depositing a first protective layer of silicon dioxide with a first topography and a thickness of H1 on the first surface by using a first deposition process; the first deposition process comprises HDP-CVD, or SACVD, or FCVD; S1012, depositing a second protective layer of silicon dioxide with a second topography and a thickness of H2 on the upper surface of the first protective layer by using a second deposition process; the second deposition process comprises PECVD; wherein the sum of the thickness H2 of the second protective layer and the thickness H1 of the first protective layer is greater than or equal to 1 um; and the first topography of the first protective layer and the second topography of the second protective layer complementarily form the first mask layer with a flat surface.

[0015] In some embodiments, step S104 specifically comprises the steps of: S1041, depositing a third protective layer with a first topography on the upper surface of the first waveguide layer and the upper surface of the first cover layer by using a first deposition process; S1042, depositing a fourth protective layer with a second topography on the third protective layer by using a second deposition process; wherein the sum of the thickness H3 of the fourth protective layer and the thickness H4 of the third protective layer is greater than or equal to 5 um; and the first topography of the third protective layer and the second topography of the fourth protective layer complementarily form the second mask layer with a flat surface.

[0016] In some embodiments, before the patterned first waveguide layer and / or the patterned second waveguide layer are prepared by using nanoimprint lithography technology, the method further comprises the steps of: S401, obtaining the width of the pattern structure corresponding to the waveguide structure in the first waveguide layer and / or the width of the pattern structure corresponding to the waveguide structure in the second waveguide layer on a soft imprint template in advance; S402, for the first waveguide layer, dividing the first waveguide layer into a plurality of regions with a first preset side length R1 centered on a specified pattern structure, and calculating the pattern duty cycle of each region, and performing step S403; and / or, for the second waveguide layer, dividing the second waveguide layer into a plurality of regions with a second preset side length R2 centered on a specified pattern structure, and calculating the image duty cycle of each region, and performing step S403; S403, for the first waveguide layer, determining whether the pattern duty cycle of each region is greater than or equal to a first preset duty cycle threshold, if the pattern duty cycle is greater than or equal to the first preset duty cycle threshold, marking the corresponding region as a dense region; if the pattern duty cycle is less than the first preset duty cycle threshold, marking the corresponding region as a sparse region; and / or, for the second waveguide layer, determining whether the pattern duty cycle of each region is greater than or equal to a second preset duty cycle threshold, if the pattern duty cycle is greater than or equal to the second preset duty cycle threshold, marking the corresponding region as a dense region; if the pattern duty cycle is less than the second preset duty cycle threshold, marking the corresponding region as a sparse region; accordingly, when etching in step S102, for the sparse region, over-etching is performed based on a first preset etching parameter; and for the dense region, over-etching is performed based on a second preset etching parameter; wherein the first preset etching parameter includes a first ICP power, the second preset etching parameter includes a second ICP power, and the second ICP power is greater than the first ICP power; and / or, when etching in step S105, for the sparse region, over-etching is performed based on a seventh preset etching parameter; and for the dense region, over-etching is performed based on an eighth preset etching parameter; wherein the seventh preset etching parameter includes a seventh ICP power, the eighth preset etching parameter includes an eighth ICP power, and the eighth ICP power is greater than the seventh ICP power.

[0017] In some embodiments, before the patterning of the second waveguide layer is prepared by using the nanoimprint lithography technology, the method further comprises the steps of: S601, obtaining the width and height of each pattern structure corresponding to the waveguide structure in the second waveguide layer on the imprinting soft template; S602, dividing the second waveguide layer into multiple regions with a second preset side length R2 as the center of any designated pattern structure, and calculating the average height and average width of the pattern structure in each region; S603, determining whether the average height of each region is greater than or equal to a tenth preset height threshold, and whether the average width is greater than or equal to a first preset width threshold; if the average height is less than or equal to the tenth preset height threshold, and the average width is less than the first preset width threshold, the region is marked as a first-level shallow etching region; if the average height is less than or equal to the tenth preset height threshold, and the average width is greater than or equal to the first preset width threshold, the region is marked as a second-level shallow etching region; if the average height is greater than the tenth preset height threshold, and the average width is less than the first preset width threshold, the region is marked as a first-level deep etching region; if the average height is greater than the tenth preset height threshold, and the average width is greater than or equal to the first preset threshold, the region is marked as a second-level deep etching region; accordingly, the step S105 specifically comprises: for the first-level shallow etching region, performing over-etching based on a ninth preset etching parameter; for the second-level shallow etching region, performing over-etching based on a tenth preset etching parameter; for the first-level deep etching region, performing over-etching based on an eleventh preset etching parameter; for the second-level deep etching region, performing over-etching based on a twelfth preset etching parameter; wherein the ninth preset etching parameter comprises a ninth ICP power, the tenth preset etching parameter comprises a tenth ICP power, the eleventh preset etching parameter comprises an eleventh ICP power, and the twelfth preset etching parameter comprises a twelfth ICP power.

[0018] In a second aspect, the application provides a hetero-integrated structure of a thin film lithium niobate and a light-transmitting substrate waveguide system, which is prepared by using any of the above-mentioned thin film lithium niobate and light-transmitting substrate waveguide system hetero-integration methods. The structure comprises a light-transmitting substrate, a first cover layer on the light-transmitting substrate, and a first waveguide layer on the first cover layer and being patterned; a first cover layer around the first waveguide layer, a second cover layer on the upper surface of the first cover layer and the upper surface of the first waveguide layer, and a second waveguide layer on the second cover layer; the upper surface of the first cover layer is flush with the upper surface of the first waveguide layer; wherein the first cover layer and the second cover layer are both deposited by using pure silicon dioxide material, and the thickness of the first cover layer and the second cover layer is greater than or equal to 1 um.

[0019] In some embodiments, the first cover layer comprises: a first protective layer with a thickness of H1 on the first surface of the light-transmitting substrate; and a second protective layer with a thickness of H2 on the upper surface of the first protective layer; H1+H2≥1um; and / or, the second cover layer comprises: a third protective layer with a thickness of H3 on the first cover layer and the first waveguide layer, and a fourth protective layer with a thickness of H4 on the upper surface of the third protective layer, H3+H4≥5um.

[0020] In some embodiments, the first protective layer or the third protective layer is a silicon dioxide layer with a first topography deposited by a first deposition process; the first deposition process comprises HDP-CVD, or SACVD, or FCVD; the second protective layer or the fourth protective layer is a silicon dioxide layer with a second topography deposited by a second deposition process; the second deposition process comprises PECVD; wherein the first protective layer with the first topography and the second protective layer with the second topography complementarily form a flat first cover layer, or the third protective layer with the first topography and the fourth protective layer with the second topography complementarily form a flat second cover layer.

[0021] Beneficial effects: traditional photolithography technology cannot be used to prepare large-scale waveguide structures on a large-area substrate, while nanoimprint technology enables large-scale implementation of patterned replication, and the pre-patterned graph can guide the etching process, thus greatly reducing the problem of high failure rate caused by "blind etching" in traditional photolithography technology. However, when preparing large-area patterned optical waveguide structures on a light-transmitting substrate, especially using a micron-level or even meter-level light-transmitting substrate as a substrate to integrate a large number of patterned optical waveguides to realize a large-scale optical computer matrix, on the one hand, the large-area pattern structure on the nanoimprint template may not be uniform, and the density of the pattern structure is different, on the other hand, due to the large area, it is not possible to ensure the same etching ratio on the entire light-transmitting substrate during the etching process, therefore, in order to ensure that the waveguide structures (or pattern structures) are completely isolated and the light field does not leak to the adjacent waveguide structures, the waveguide layer is etched in the present application; at the same time, a shielding layer is arranged between the light-transmitting substrate and the waveguide layer, which greatly relaxes the requirement for the etching process: it is no longer necessary to accurately calculate the "just etched" time due to the fear of over-etching, as long as the waveguide layer is etched through, the process window is very wide, and the over-etching process is avoided. The etching product produced by etching to the light-transmitting substrate (the light-transmitting substrate contains a large number of additive elements such as Na, B, Ga, Mg and other metal substances during preparation) affects the performance of the silicon optical waveguide, for example, greatly increases the scattering loss of light propagation in the waveguide, thereby reducing the optical coupling between light and the light-transmitting substrate to reduce the yield of the optical waveguide. Since the shielding layer is deposited from pure silicon dioxide (for example, the purity is 99.9999%), it not only protects the light-transmitting substrate, but also improves the optical coupling between the light-transmitting substrate and the optical waveguide (for example, together with the cover layer to wrap the waveguide layer), thereby improving the yield of the optical waveguide. In addition, the shielding layer with a double-layer structure is deposited by using two different deposition processes, which not only protects the light-transmitting substrate, but also ensures the flatness of the deposited waveguide plane due to the complementarity of the physical topography between the two different processes. The protective layer is prepared, without the need for additional flat layers or other special treatments, which not only reduces the process complexity but also improves the performance of the device to some extent. In addition, due to the large difference between the light-transmitting substrate and the waveguide system, the shielding layer also serves as an "adhesive" to increase the "adhesion" between the light-transmitting substrate and the waveguide layer, and to some extent, prevent the light-transmitting substrate and the waveguide layer from easily falling off.

[0022] Further, the application sets a buffer layer between the cover layer and the waveguide layer, so that even if the waveguide layer in some areas is not etched through because of poor process parameter control, such as 10 nm, the next etching step will almost instantly remove the remaining part because of the extremely fast etching rate of the buffer layer, and quickly expose the underlying pure silicon dioxide cover layer. This greatly reduces the uniformity requirement of the "etching through the waveguide layer" step, making the process easier to control and the yield higher. Moreover, the buffer layer can be directly used as the lower cladding layer together with the pure silicon dioxide cover layer to "in-situ package" the waveguide layer, and the minimum thickness (e.g. 1 um) requirement of the silicon dioxide cover layer as the final protective layer is sufficient, without the need to reserve additional thickness for over-etching.

[0023] In summary, the application maximizes the process window and precision by precisely controlling the etching selectivity ratio between different layers, thereby reducing the difficulty of etching depth control, and further ensuring the uniformity and consistency between the waveguides etched on a large-area light-transmitting substrate.

[0024] Further, since the etching rates of different areas in the pattern are different, for example, the etching rate of the dense area is slower, and the etching rate of the sparse area is faster, therefore, at the same etching time, the waveguide in the sparse area may have been completely etched through or even over-etched, while the waveguide in the dense area has not been etched through. This directly leads to inconsistent performance of different functional areas of the chip. Therefore, in order to avoid this problem, the application increases the ion concentration of etching for the dense area, thereby accelerating the etching rate of the dense area and avoiding setting too long over-etching time.

[0025] Compared with other waveguide layers, the thin film lithium niobate waveguide layer is more fragile, therefore, a very dense waveguide structure is usually not set on the thin film lithium niobate waveguide layer, in addition, since the thin film lithium niobate waveguide layer is directly set on the first waveguide layer, therefore, when patterning the thin film lithium niobate waveguide layer by using nano-imprint lithography technology, not only the fragility of the thin film lithium niobate waveguide layer itself needs to be considered, but also the impact on the underlying waveguide layer needs to be considered, therefore, the application sets a second cover layer on the first waveguide layer, and then sets a second waveguide layer, thereby using the second cover layer to protect the first waveguide layer during over-etching of the second waveguide layer. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. In all the drawings, similar elements or parts are generally identified by similar reference signs. In the drawings, the elements or parts are not necessarily drawn according to the actual proportions. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without paying creative labor.

[0027] Figure 1A Flow chart of the heterogeneous integration method of the thin film lithium niobate and the transparent substrate waveguide system in the embodiment one of the present application; Figure 1B Flow chart of the preparation of the double-layer structure mask layer in the heterogeneous integration method of the thin film lithium niobate and the transparent substrate waveguide system in the embodiment two of the present application; Figure 2 Flow chart of the preparation of the imprinting soft template in the present application; Figure 3 Schematic diagram reflecting the different density of the waveguide structure on the first waveguide layer; Figure 4 Schematic diagram reflecting the corresponding Figure 3 Schematic diagram of the pattern structure of the waveguide structure; Figure 5A Flow chart of the heterogeneous integration method of the thin film lithium niobate and the transparent substrate waveguide system in the embodiment one of the present application; Figure 5B Flow chart of the heterogeneous integration method of the thin film lithium niobate and the transparent substrate waveguide system in the embodiment two of the present application; Figure 6 Flow chart of the patterning of the first waveguide layer by using the nano-imprint lithography technology in the embodiment one or two of the present application; Figure 7 Flow chart of the heterogeneous integration method of the thin film lithium niobate and the transparent substrate waveguide system in the embodiment three of the present application; Figure 8 Flow chart of the partition of the deep etching area and the shallow etching area based on the pattern structure in the heterogeneous integration method of the thin film lithium niobate and the transparent substrate waveguide system in the embodiment four of the present application.

[0028] Reference signs: transparent substrate 100, first mask layer 200-1, second mask layer 200-2, second surface 201, first protective layer 202, second protective layer 203, third protective layer 204, fourth protective layer 205, first waveguide layer 300, imprinting glue layer (i.e. mask layer) 400, imprinting soft template 500, first glue layer 5001, soft film layer 5002, substrate layer 600, electron beam glue layer 700, first cover layer 800-1, second waveguide layer 300B, second cover layer 800-2; pattern structure 120, waveguide structure 110. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0030] Herein, the suffix such as "module", "part" or "unit" used for representing an element is only for facilitating the description of the present application, and has no specific meaning by itself. Therefore, "module", "part" or "unit" can be mixedly used. Herein, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance. Herein, unless otherwise explicitly specified and limited, the terms "mount", "provided with", "connected" and the like should be understood in a broad sense, for example, "connected" can be fixed connection, can be detachable connection, or integral connection; can be mechanical connection, can be direct connection, or indirect connection through an intermediate medium, can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. Herein, "and / or" includes any and all combinations of one or more listed related items. Herein, "multiple" means two or more, that is, it includes two, three, four, five and the like. In the present specification, some embodiments can be disclosed in a format of a certain range. It should be understood that such "in a certain range" description is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent digital values within the range. For example, the description of the range 1-6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, and independent digital values within the range, such as 1, 2, 3, 4, 5 and 6. The above rule applies regardless of the breadth of the range.

[0031] Optical AI chip: A photonic computing chip, also known as a photonic chip or optical computing chip, is a chip specifically designed for processing optical data and performing artificial intelligence (AI) inference. Based on optical principles, it takes optical signals as input and performs computational operations through a series of optical elements and devices. These optical elements can be components such as lasers, optical fibers, and optical modulators, used to process and transmit optical signals. For example, a photonic computing chip converts the optical signal into a weak photocurrent signal using a light-emitting diode (LED). This photocurrent signal is then converted into a voltage signal U by a transimpedance amplifier (TIA), and finally converted into a digital signal by an analog-to-digital converter (ADC). The digital signal is then output to an FPGA for processing. Simultaneously, the FPGA outputs the processed digital signal to a digital-to-analog converter (DAC) to convert the FPGA's digital signal back into an analog signal and input it back to the photonic computing chip.

[0032] Computational unit: A single computational unit used to perform a calculation. For example, using Mach... A single computational unit for photonic computing can be implemented using a Zeidel interferometer (MZI) or a microring structure (MMR). Other examples include photonic computing units utilizing carrier light absorption effects and photonic computing units based on the absorption effects of phase change materials. Specifically, computational units can be categorized into photonic computing units and hybrid computing units.

[0033] Computational Array: An N*N computational array is constructed based on the above computational units. Each intersection of the input row waveguide and the output column waveguide in this array contains a computational unit. If the computational units are photonic computational units, the computational array can also be called a photonic computational array; if the computational units are optoelectronic hybrid computational units, the computational array can also be called an optoelectronic hybrid computational array.

[0034] Transparent substrate: In this document, a transparent substrate refers to a base substrate with a flat, smooth surface and specific geometric dimensions (such as a disc, square, or panel), and exhibits extremely high transmittance, for example, >99.999%, within the target wavelength range (such as the visible light region 380nm-2µm). It is commonly used as a "foundation" or "canvas" for various functional devices (such as circuits, sensors, and waveguides), providing a support platform for subsequent micro / nano fabrication and functional layer deposition. Examples include interposers or redistribution substrates for system-in-package (SIIP), and the fabrication of electrical interconnect vias and optical waveguide structures (such as gratings) within glass. Preferably, the transparent substrate can be a glass substrate, etc.

[0035] Mask layer: the mask layer herein refers to a layer capable of protecting the next material layer of the etching material layer in the etching process, preventing the next material layer from being etched in the etching process, and not needing to be removed in the subsequent process. The refractive index of the mask layer is similar to that of the light-transmitting substrate, so the coupling effect between light and the light-transmitting substrate can be ensured. At the same time, the mask layer can also be wrapped together with the cover layer on the waveguide layer. Preferably, the mask layer can be deposited by using materials such as pure silicon dioxide. For example, the first mask layer 200-1 and the second mask layer 200-2 in the subsequent embodiments.

[0036] Over-etching: over-etching herein refers to continuing to etch for an additional period of time after the end of the preset "just etching to the target depth" time. For example, ideally, a certain depth of waveguide layer needs to be etched just through, and the etching time required is T1 (such as 10 s). However, in actual engineering applications, it is still necessary to continue etching for T2 (20 s), so as to ensure that the corresponding regions on the large-area waveguide layer are all completely etched through the waveguide layer.

[0037] In the preparation of a large number of optical waveguides on a large-area light-transmitting substrate to prepare a large-scale computing matrix, due to the influence of the etching process, it is impossible to ensure that all etching ratios are the same, and after nanoimprinting, it is impossible to ensure the uniformity of all structures, so that the etching depth / etching time is difficult to control, and thus the uniformity and consistency of the optical waveguide structure after etching cannot be guaranteed. In view of this, in the present application, nanoimprint lithography technology, over-etching, and a multi-layer structure are used, and the etching selection ratio between different layers is controlled to maximize the process window and precision, thereby reducing the difficulty of etching depth / etching time control, and thus the uniformity between the waveguides etched on the large-area light-transmitting substrate is guaranteed as much as possible. For example, a mask layer is arranged between the light-transmitting substrate and the waveguide layer, for example, a mask layer composed of a double-layer protective layer. The etching ratio between the upper and lower two layers of structure is controlled to maximize the process window, so that the etching time of the optical waveguide can be as long as possible without damaging the light-transmitting substrate. In addition, the mask layer arranged can be directly encapsulated with the cover layer deposited subsequently as a whole to encapsulate the waveguide structure in situ after etching. In addition, the number of layers of the structure will affect the miniaturization and integration of the device, and therefore, in order to avoid excessive introduction of multi-layer materials, the etching process parameters are adjusted based on the dense and sparse regions of the pattern waveguide structure in the imprinting process, so as to reduce the difference in etching time or etching depth caused by non-uniformity to a certain extent, and thus the uniformity of the waveguide structure is guaranteed in cooperation with the multi-layer structure.

[0038] Embodiment one: see Figure 1A and Figure 5A is a flowchart of an embodiment of a thin-film lithium niobate and light-transmitting substrate waveguide system hetero-integration method of the present application. Specifically, the method comprises the following steps: S101, depositing a first mask layer 200-1 on the first surface 101 of the light-transmitting substrate 100. In the present embodiment, the first mask layer 200-1 is used to protect the light-transmitting substrate 100 in the subsequent etching process, so as to prevent the light-transmitting substrate 100 from being etched in the etching process, while ensuring that the optical coupling between the light and the light-transmitting substrate 100 is not greatly reduced. In some embodiments, the first mask layer 200-1 can be deposited by using a material that is transparent and has no absorption to light, and the etching selectivity ratio between the material and the waveguide layer material is preferably as high as possible (i.e., the etching rate of the waveguide layer is much greater than the etching rate of the protective layer). Preferably, the first mask layer 200-1 is made of pure SiO2. More preferably, the refractive index n1 of the first mask layer 200-1 satisfies the relationship between the refractive index n2 of the light-transmitting substrate 100: n2-△n0≤n1≤n2=△n0. Preferably,△n0=±0.01. Further, the thickness of the first mask layer 200-1 is greater than or equal to 1 um. Specifically, the first mask layer 200-1 can be deposited on the light-transmitting substrate 100 by using a method such as PECVD or HDP CVD.

[0039] S102, depositing a first waveguide layer 300 on the second surface 201 of the first mask layer 200-1. In some embodiments, the first waveguide layer 300 is deposited by using a waveguide material commonly used in the art, such as SiN material or the like.

[0040] S103, depositing a first cover layer 800-1 around the first waveguide layer 300, and the upper surface of the first cover layer 800-1 is flush with the upper surface of the first waveguide layer 300. In some embodiments, the first cover layer 800-1 is deposited on the first waveguide layer 300, so that the first cover layer 800-1 and the first mask layer 200-1 wrap the first waveguide layer 300. In the present embodiment, the first cover layer 800-1 and the first mask layer 200-1 together form an almost symmetrical "sandwich" structure, which wraps the first waveguide layer 300 with high refractive index in the middle. Since the first waveguide layer 300 is directly deposited on the first mask layer 200-1, it is not necessary to separately wrap the waveguide layer by using a separate process, thereby realizing "in-situ packaging" and reducing the risk of contamination or exposure of the waveguide. In the present embodiment, the first cover layer 800-1 and the first mask layer 200-1 are made of the same material. For example, both are made of pure SiO2. Preferably, the first cover layer 800-1 is prepared by using the same deposition process as the first mask layer 200-1.

[0041] S104, depositing a second mask layer 200-2 on the upper surface of the first waveguide layer 300 and the upper surface of the first cover layer 800-1.

[0042] S105, depositing a second waveguide layer 300B on the second cover layer 200-2. In this embodiment, the second waveguide layer 300B is deposited by thin film lithium niobate, and the thickness of the second cover layer 200-2 is greater than or equal to 5um. That is, compared with the first cover layer 200-1 between the first waveguide layer 300 and the light-transmitting substrate 100 made of other materials, the thickness of the second cover layer 200-2 is 5 times or more than that of the first cover layer 200-1.

[0043] Of course, a second cover layer 800-2 can be further deposited on the second waveguide layer 300B.

[0044] The etching process for the waveguide layer made of thin film lithium niobate material (which is a prior art and will not be described here) is different from the etching process for the waveguide layer made of other materials. Because the solid waste of the etching product cannot or is difficult to be cleaned immediately during the etching process, the risk of etching to the light-transmitting substrate is greater during over-etching. Therefore, in order to ensure the uniformity of the waveguide structure and reduce the risk of etching to the underlying structure such as the first waveguide layer 300, a second cover layer 200-2 with a specific thickness is provided to provide sufficient space for over-etching, while not greatly reducing the longitudinal transmission of light.

[0045] Preferably, the width of the second waveguide layer 300B is greater than the width of the first waveguide layer 300, thereby forming a T-shaped heterogeneous waveguide structure to prepare an active modulator. Correspondingly, when preparing the active modulator, the external electrode is also connected through the shallow etching area, so that the electrode is introduced on the basis of controlling the size of the light spot to the greatest extent.

[0046] Preferably, in other embodiments, the first waveguide layer 300 in step S102 and the second waveguide layer 300B in step S105 are both waveguide layers patterned by nanoimprint lithography technology. Specifically, referring to Figure 6 , a layer of imprint glue 400 is first deposited on the first waveguide layer 300 / second waveguide layer 300B, and then the imprint glue layer 400 is imprinted by using a pre-prepared imprint soft mold 500 to form an imprint pattern on the imprint glue layer 400; then the residual layer in the imprint groove after imprinting is etched based on the imprint pattern, and after removing the residual layer, the first waveguide layer 300 / second waveguide layer 300B is etched based on the imprint pattern, thereby obtaining a patterned first waveguide layer 300 / second waveguide layer 300B; finally, the imprint glue layer 400 is removed.

[0047] Specifically, after the pattern transfer is completed, all the remaining imprint glue is removed using wet method (such as solvent, acid) or dry method (such as O2 plasma ashing), leaving a clean and patterned waveguide structure.

[0048] In some embodiments, the etching process must have a high selectivity, i.e. only etching the stamping glue quickly, and hardly etching the first waveguide layer 300 / second waveguide layer 300B below, for example, reactive ion etching (RIE) is used to etch the stamping glue layer. Of course, other processes can also be used to remove the residual layer. In practice, based on the stamping pattern, and using the preset etching selectivity (for example, an empirical value) of the etching gas (such as CF4, CHF3for SiN) to etch the first waveguide layer 300, a patterned first waveguide layer 300 is obtained.

[0049] In this embodiment, over-etching refers to etching the waveguide layer (such as the first waveguide layer 300, or the second waveguide layer 300B) according to the preset etching time (such as 20s), and after the waveguide layer (such as the first waveguide layer 300 at 15s) is etched through, it will slightly etch the mask layer (such as the first mask layer 200-1 located below the first waveguide layer 300, or the second mask layer 200-2 located below the second waveguide layer 300B) below. Of course, since the waveguide layer is over-etched, the final mask layer (such as the first mask layer 200-1, or the second mask layer 200-2) also has a corresponding pattern, and since the preset etching selectivity is large, the process will not etch the mask layer completely, that is, it will not etch the light-transmitting substrate 100 below the first waveguide layer 300, or the first waveguide layer 300 and the first cover layer 800-1 below the second waveguide layer 300B.

[0050] Preferably, over-etching the first waveguide layer 300 with an etching gas with a preset etching selectivity means that the etching rate of the etching gas on the first waveguide layer 300 is much greater than the etching rate of the etching gas on the first mask layer 200-1, so when the first waveguide layer 300 is etched through, it will continue to slightly etch the first mask layer 200-1, but since the etching rate of the first mask layer 200-1 is low and has a certain thickness (such as greater than or equal to 1um), when the preset etching time (such as 20s) is reached, the etching will stop at the first mask layer 200-1, thereby protecting the light-transmitting substrate 100 from being damaged.

[0051] As mentioned above, since the second waveguide layer 300B is to be patterned, if the second waveguide layer 300B formed by the thin film lithium niobate is directly in contact with the first waveguide layer 300, the first waveguide layer 300 can be damaged in the patterning process. Therefore, when the second waveguide layer 300B needs to be patterned by over-etching to prepare different functional devices, a second mask layer 200-2 needs to be provided on the first waveguide layer 300 and the first cover layer 800-1, so as to prevent the first waveguide layer 300 and the first cover layer 800-1 from being damaged in the over-etching process of the second waveguide layer 300B. Specifically, the same principle as described above is adopted, and the second mask layer 200-2 deposited on the first waveguide layer 300 and the first cover layer 800-1 is also pure SiO2. Based on the imprint pattern, and using an etching gas (such as CF4, CHF3for SiN) with a preset etching selectivity ratio (for example, an empirical value of 1:5) to over-etch the second waveguide layer 300B, a patterned second waveguide layer 300B is obtained.

[0052] In this embodiment, over-etching the second waveguide layer 300B by using an etching gas with a preset etching selectivity ratio means that the etching rate of the etching gas on the second waveguide layer 300B is much greater than the etching rate of the etching gas on the second mask layer 200-2 below the second waveguide layer 300B. Therefore, when the second waveguide layer 300B is etched through, the second mask layer 200-2 will continue to be slightly etched, but since the etching rate of the second mask layer 200-2 is low and the second mask layer 200-2 has a certain thickness (for example, greater than or equal to 5 um), when the preset etching time (such as 25s) is reached, the etching will stop at the second mask layer 200-2, thereby protecting the first waveguide layer 300 and the first cover layer 800-1 from being damaged. Similarly, when the second waveguide layer 300B is etched according to the preset etching time (such as 25s), since the second waveguide layer 300B (such as at 20s) is etched through, the second mask layer 200-2 will be slightly etched. Therefore, the final second mask layer 200-2 also has a corresponding pattern, and since the etching selectivity ratio is greater than the fourth preset threshold, the process will not etch the second mask layer 200-2 completely, that is, will not etch the first waveguide layer 300 and the first cover layer 800-1. Moreover, since the second mask layer 200-2 is made of pure silicon dioxide material, it will not greatly affect the optical coupling effect between the second waveguide layer and the first waveguide layer.

[0053] In some embodiments, the step of preparing the soft stamp in the above steps specifically comprises: S301, depositing an e-beam resist layer 700 on the substrate layer 600, and exposing a designated area of the e-beam resist layer 700. S302, developing the exposed e-beam resist layer 700 to obtain a patterned e-beam resist layer 700. In some embodiments, the e-beam resist layer 700 is a positive resist layer, or a negative resist layer; accordingly, if it is a positive resist layer, the e-beam resist layer in the exposed area is removed when the e-beam resist layer is developed in step S302, see Figure 2 ; if it is a negative resist layer, the e-beam resist layer outside the exposed area is removed when the e-beam resist layer is developed in step S302, which is not shown in the figure. S303, etching the substrate layer 600 based on the patterned e-beam resist layer 700 to obtain a patterned substrate layer 600. S304, sequentially depositing the first resist layer 5001 and the soft film layer 5002 on the patterned substrate layer 600. S305, removing the substrate layer 600 to obtain a patterned soft stamp 500.

[0054] In the nanoimprinting process, there may be a height difference in the pattern on the template itself, or a residual layer thickness difference in each groove of the imprinted resist after imprinting, thereby increasing the difficulty of controlling the etching depth / etching time of the subsequent optical waveguide. Although a high-performance soft film can be designed in advance by a high-precision algorithm to ensure the uniformity of the imprint thickness. However, for an existing soft film, redesigning and manufacturing a new template with high performance will greatly increase the cost, and the waiting process for the new template may cause losses due to production stoppage. On the other hand, even if the template has high uniformity, different areas of the soft film will be worn to different degrees after long-term use, resulting in different imprint thicknesses and different residual layer thicknesses in the grooves. Therefore, in order to reduce the risk of non-uniformity of the pattern or the residual layer thickness difference leading to non-uniformity of the optical waveguide obtained by etching, the over-etching combined with the mask layer is used in the embodiment to ensure the uniformity of the optical waveguide, and to protect the light-transmitting substrate 100 and / or the first waveguide layer 300, thereby improving the yield of the waveguide device.

[0055] Embodiment two: the application also provides another method for hetero-integration of a thin film lithium niobate and a light-transmitting substrate waveguide system, which comprises the steps of the above embodiment one, except that, referring to Figure 1B and Figure 5BIn the preparation method of the embodiment, the first shield layer 200-1 between the light-transmitting substrate 100 and the first waveguide layer 300, and / or the second shield layer 200-2 between the first waveguide layer 300 and the second waveguide layer 300B formed by the thin film lithium niobate is not a single-layer shield layer, but a double-layer shield layer, such as a pure silicon dioxide double-layer structure with different properties (including etching rate and etching resistance, morphology) deposited by two different deposition processes. For example, the lower layer structure of the first shield layer 200-1 between the light-transmitting substrate 100 and the first waveguide layer 300 is dense near the light-transmitting substrate 100, and the upper layer structure is relatively sparse near the first waveguide layer 300 (i.e., the lower layer is more etching-resistant than the upper layer), so that the two layers have different morphologies to complementarily form a flat first shield layer, thereby ensuring the uniformity of the waveguide and the stability of the connection between the multi-layer structure. Specifically, step S101 includes: S1011, using a first deposition process, such as HDP-CVD technology, to deposit silicon dioxide with a thickness of H1 and a first morphology on the first surface 101 of the light-transmitting substrate 100 as the first protective layer 202. S1012, using a second deposition process, such as PECVD technology, to deposit silicon dioxide with a thickness of H2 and a second morphology on the upper surface of the first protective layer 202 as the second protective layer 203.

[0056] In the embodiment, the first morphology refers to that the first protective layer 202 includes a smooth and flat lower surface in contact with the light-transmitting substrate 100, and an upper surface opposite to the lower surface and used for depositing the second protective layer 203. The second morphology refers to that the second protective layer 203 includes a third surface in contact with the upper surface of the first protective layer 202, and a fourth surface opposite to the third surface and used for depositing the first waveguide layer 300. Since the first protective layer 202 is directly deposited on the light-transmitting substrate 100, the upper surface thereof is almost flat, and the lower surface thereof has a concave-convex morphology due to the limitation of the deposition process. Correspondingly, since the second protective layer 203 is directly deposited on the upper surface of the first protective layer 202, the morphology of the third surface is complementary to that of the upper surface, and the fourth surface is almost flat due to the maturity of the deposition process, so that the double-layer first shield layer 200-1 has flat upper and lower surfaces (i.e., the fourth surface and the lower surface of the first protective layer 202), and the stress comprehensive action of the double-layer structure can reduce the risk of warping.

[0057] In the embodiment, the HDP-VCD is used to prepare a silicon dioxide layer with a dense structure, hardness and high image stability, and the etching rate thereof is slower than that of the silicon dioxide layer prepared by PECVD which has a relatively sparse structure. Therefore, even if the second protective layer 203 with a smaller thickness is etched through in the over-etching process, the etching process will eventually stop on the first protective layer 202 which is very etching-resistant.

[0058] Generally, in order to ensure sufficient safety, a layer of silicon dioxide with a sufficient thickness can be set as the first protective layer 200-1 to protect the first waveguide layer 300. However, a thicker thickness will affect the subsequent longitudinal stacking, thus affecting the volume of the device. Therefore, in order to ensure that the first waveguide layer 300 can be etched through during the over-etching process, and at the same time, the first protective layer 202 will not be etched through to damage the light-transmitting substrate 100, the second protective layer 203 close to the first waveguide layer 300 is set to be thinner, and can only be etched to the first protective layer 202 during the over-etching process, and will not be etched to the light-transmitting substrate 100. Compared with simply increasing the thickness of the silicon dioxide layer, for example, setting a silicon dioxide layer with a large thickness (for example, 2 um), it is more beneficial to the miniaturization and integration of the device. Preferably, H1 < H2. More preferably, H1 + H2 > 1 um. Preferably, 0.1-0.2 um of PE-CVD SiO2 is deposited as the second protective layer 203, and 0.8-0.9 um of HDP-CVD SiO2 is deposited as the first protective layer 202. Of course, in other embodiments, other deposition techniques can also be used to compare the deposition structure of the first protective layer 202, such as SACVD technology, FCVD technology, etc.

[0059] Of course, the same process can also be used to prepare the second protective layer 200-2 between the first waveguide layer 300, the first cover layer 800-1 and the second waveguide layer 300B, thereby obtaining a pure SiO2 double-layer structure. That is, a third protective layer 204 with a thickness H3 is first deposited on the first waveguide layer 300 and the first cover layer 800-1 by using a first deposition process (i.e., S1041), and then a fourth protective layer 205 with a thickness H4 is deposited on the third protective layer 204 by using a second deposition process (i.e., S1042). Preferably, the thickness H4 of the fourth protective layer 205 is less than the thickness H3 of the third protective layer 204, and H3 + H4 > 1 um, more preferably, H3 + H4 > 5 um; and the third protective layer 204 with the first topography and the fourth protective layer 205 with the second topography complementarily form the second protective layer 200-2 with a flat topography.

[0060] Embodiment three: the present application also provides another method for hetero-integration of a thin film lithium niobate and a light-transmitting substrate waveguide system, which comprises the steps of the above-mentioned embodiments one or two, except that, referring to Figure 7In the embodiment, before the etching of the first waveguide layer 300, the method further includes the following step: S401, obtaining the width of the pattern structure 120 (i.e. the spacing between the waveguide structures 110) based on the pattern structure 120 corresponding to the waveguide structure 110 on the soft stamp 500. In some embodiments, different patterns are provided on the first waveguide layer 300 and the second waveguide layer 300B, and therefore, different soft stamps can be provided for the two waveguide layers. Then, the image acquisition device, such as a high-definition camera, is used to capture the embossed pattern on the soft stamp and perform image analysis to obtain the spacing L1 or L2 between the pattern structures 120 corresponding to the waveguide structures 110. See FIG. 4A. Figure 3 That is, the width L1 or L2 of the protruding pattern structure 120 on the soft stamp 500. See FIG. 4B. Figure 4 Of course, in other embodiments, the width (or spacing) of the pattern structure 120 can be directly obtained from the design drawing (such as GDSII layout) of the soft stamp 500, thereby obtaining the spacing between the waveguide structures.

[0061] S402, taking the designated pattern structure 120 as the center point, the first waveguide layer 300B is divided into multiple regions with a first preset side length R1 (in fact, the regions are divided according to the side of the soft stamp on which the pattern structure 120 is provided in the design drawing), and the pattern coverage ratio and the average width of the pattern structure of each region are calculated. If the pattern coverage ratio is greater than or equal to a first preset coverage ratio threshold (such as 55%) and the average width of the pattern structure in the corresponding region is less than a first preset width threshold, the region is marked as a first-level dense region. If the pattern coverage ratio is greater than the first preset coverage ratio threshold and the average width of the pattern structure in the corresponding region is greater than the first preset width threshold, the region is marked as a second-level dense region. If the pattern coverage ratio is less than the first preset coverage ratio threshold (such as 55%) and the average width of the pattern structure is less than the first preset width threshold, the corresponding region is marked as a first-level sparse region. If the pattern coverage ratio is less than the first preset coverage ratio threshold and the average width of the pattern structure is greater than the first preset width threshold, the corresponding region is marked as a second-level sparse region. That is, the sparse and dense division is first performed based on the image coverage ratio, and then the sparse level division and the dense level division are further performed based on the width, thereby obtaining sparse regions of different levels and dense regions of different levels.

[0062] Of course, in other embodiments, the division of dense areas and sparse areas can also be made only according to the pattern duty cycle. For example, if the pattern duty cycle is greater than or equal to a first preset duty cycle threshold, it is divided into a dense area, and if it is less than the first preset duty cycle threshold, it is divided into a sparse area. Accordingly, step S103 specifically includes: for the sparse area, performing over-etching based on a first preset etching parameter; and for the dense area, performing over-etching based on a second preset etching parameter; wherein the first preset etching parameter includes a first particle concentration or a first etching time, and the second preset etching parameter includes a second ion concentration or a second etching time, the second ion concentration being greater than the first particle concentration, or the second etching time being greater than the second etching time. Of course, for different levels of sparse areas and different levels of dense areas, different preset etching parameters can be pre-set, and the higher the level of the same type of area, the smaller the corresponding preset etching parameter. For example, the preset etching parameter of I-level dense area is greater than the preset etching parameter of II-level dense area.

[0063] In a specific example, taking etching a silicon carbide waveguide layer as an example, the initial etching parameters set in advance according to actual needs include: ICP power: 1000W (control plasma ion concentration); etching mixed gas: CHF3 / CF4 / O2; etching time: 20s. When the pattern duty cycle of a certain area is 70%, which is greater than the first preset threshold of 55%, the ICP power of the dense area is increased to 1200W (i.e. the second preset etching parameter) accordingly, thereby increasing the ion concentration. When the image duty cycle of a certain area is 35% and less than 55%, the ICP power of the sparse area is kept at 1000W accordingly.

[0064] In another specific example, if the pattern duty cycle of a certain region on the first waveguide layer 300 is 70%, which is greater than the first preset threshold 55%, and the average width of the pattern structure is less than or equal to the preset width threshold, the region is marked as a first-level dense region, and the ICP power 1000W in the initial preset etching parameter is adjusted to 1200W (i.e., the second preset etching parameter). If the average width of the pattern structure is greater than or equal to the preset width threshold, the region is marked as a second-level dense region, and the ICP power 1000W in the initial preset etching parameter is adjusted to 1100W (i.e., the fourth preset etching parameter). Similarly, when the image duty cycle of a certain region on the first waveguide layer 300 is 35% and is less than 55%, and the average width of the pattern structure 120 is less than the preset width threshold, the ICP power of the first-level sparse region is maintained at 1000W (i.e., the first preset etching parameter). If the average width of the pattern structure 120 is greater than or equal to the preset width threshold, the ICP power of the second-level sparse region is maintained at 900W (i.e., not maintaining the first preset etching parameter, but reducing the first preset etching parameter to obtain the third preset etching parameter). That is, by adjusting the ion concentration during etching, the difference in global waveguide etching time is minimized. That is, different preset etching parameters are set for different levels of dense regions.

[0065] Preferably, when adjusting the ion concentration, a high-end etching machine supporting partition control can be used to set the corresponding etching parameters, such as ICP power, for the corresponding regions, and then use the high-end etching machine to over-etch all regions (i.e., the etching time of all regions is the same). When adjusting the etching time, a traditional shielding partition etching can be used, that is, the sparse and dense regions are etched separately. Specifically, when etching the sparse region, the dense region is shielded, and when etching the dense region, the sparse region is shielded. Similarly, the waveguide structure on the second waveguide layer 300B will also have sparse and dense regions. Therefore, based on the same principle as above, before over-etching the second waveguide layer 300B, the above steps S401-S402 are also used for partitioning, and the pattern duty cycle and the average width of the pattern structure of each region are obtained. The difference is that the preset edge length for dividing the region is different. For example, the second preset edge length R2 is used to divide the region with the specified pattern structure 120 as the center point, and the pattern duty cycle and the average width of the pattern structure of each region are calculated. The second preset edge length R2 is greater than the first preset edge length R1. Since the thin film lithium niobate waveguide layer is brittle, the density of the waveguide structure on the thin film lithium niobate is smaller than that of the first waveguide layer 300 made of other materials, so the scale of the preset edge length can be appropriately enlarged.

[0066] Correspondingly, if the graphic duty cycle is greater than or equal to a second preset duty cycle threshold (e.g., 60%), the corresponding region is marked as a dense region; if the graphic duty cycle is less than the second preset duty cycle threshold, the corresponding region is marked as a sparse region; the second preset duty cycle threshold is greater than the first preset duty cycle threshold. Correspondingly, step S105 specifically includes: for the sparse region, performing over-etching based on a seventh preset etching parameter; and for the dense region, performing over-etching based on an eighth preset etching parameter; wherein the seventh preset etching parameter includes a seventh ICP power, and the eighth preset etching parameter includes an eighth ICP power, the eighth ICP power being greater than the seventh ICP power.

[0067] Of course, further, each region can be further classified based on the average width of the region. For example, if the graphic duty cycle is greater than or equal to the second preset duty cycle threshold, and the average width of the graphic structure in the corresponding region is less than a second preset width threshold, the region is marked as a first-level dense region; if the graphic duty cycle is greater than the second preset duty cycle threshold, and the average width of the graphic structure in the corresponding region is greater than the second preset width threshold, the region is marked as a second-level dense region; if the graphic duty cycle is less than the second preset duty cycle threshold, and the average width of the graphic structure is less than the second preset width threshold, the corresponding region is marked as a first-level sparse region; and if the graphic duty cycle is less than the second preset duty cycle threshold, and the average width of the graphic structure is greater than the second preset width threshold, the corresponding region is marked as a second-level sparse region.

[0068] Correspondingly, based on the same principle described above, the higher the level of the same type of region, the smaller the corresponding preset etching parameter. Specifically, step S105 specifically includes: for the first-level sparse region, performing over-etching based on the seventh preset etching parameter; for the second-level sparse region, performing over-etching after reducing the seventh preset etching parameter by a preset decrement; for the first-level dense region, performing over-etching based on the eighth preset etching parameter; and for the second-level dense region, performing over-etching after reducing the eighth preset etching parameter by a preset decrement.

[0069] In some other embodiments, since the distribution of the waveguide structure on the first waveguide layer 300 is not only dense and sparse in the two-dimensional plane, but also has a height in the three-dimensional direction, which determines the etching depth, the method further comprises the following step: S501, obtaining the height of each pattern structure in the dense area (preferably, the height is obtained from the GDSII layout; the height actually maps the etching depth of the groove between the waveguide structures 110), and further performing partitioning; specifically, for each dense area, taking any designated pattern structure as the center, a third preset side length R3 (R3 < R1) is used to divide the dense area into at least two sub-areas (i.e., rectangular areas), and the average height of the pattern structure 120 in each sub-area is calculated; if the average height is less than or equal to a first preset height threshold and greater than or equal to a second preset height threshold, the second etching parameter corresponding to the corresponding sub-area is adjusted, such as increasing the initial etching time by a first preset increment or increasing the initial ICP power, so as to increase the ion concentration; if the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, the second etching parameter corresponding to the corresponding sub-area is adjusted, such as increasing the initial etching time by a second preset increment or increasing the initial ICP power, so as to increase the ion concentration; wherein the second preset increment is less than the first preset increment; if the average height is less than the third preset height threshold, the current second etching parameter is maintained. Furthermore, if the ion concentration is increased, the thickness of the second protective layer 203 is increased accordingly.

[0070] In a specific example, in combination with the above example, when the average height of any sub-area in any dense area is equal to or less than a first preset height threshold (preferably, the first preset height threshold is the maximum one among the average heights of all sub-areas) and greater than or equal to a second preset height threshold, and the ICP power in the second etching parameter is adjusted from 1200W to 1250W, the average height is less than the second preset height threshold and greater than or equal to a third preset height threshold, and the ICP power in the second etching parameter corresponding to the corresponding sub-area is adjusted from 1200W to 1230W; if the average height is less than the third preset height threshold, the current second etching parameter is maintained.

[0071] Of course, in other embodiments, the preset increments are different for each level of dense region, i.e. the level of dense region is identified first, and then the preset increments are adjusted based on the average height. For example, when the average height of any sub-region in any I-level dense region is equal to or less than the first preset height threshold, and greater than or equal to the second preset height threshold, and the ICP power 1200W in the second preset etching parameter is adjusted to 1250W, the average height is less than the second preset height threshold, and greater than or equal to the third preset height threshold, the ICP power 1200W in the corresponding second etching parameter of the corresponding sub-region is adjusted to 1230W. And for the average height of any sub-region in any II-level dense region, equal to or less than the first preset height threshold, and greater than or equal to the second preset height threshold, and the ICP power 1200W in the second preset etching parameter is adjusted to 1240W, the average height is less than the second preset height threshold, and greater than or equal to the third preset height threshold, the ICP power 1200W in the corresponding second etching parameter of the corresponding sub-region is adjusted to 1220W.

[0072] Of course, in order to further reduce the difference, in other embodiments, each sparse region can also be further divided into sub-regions based on the height of the graphic structure 120, and the division principle is the same as that of the above-mentioned dense region. For example, for each dense region, a fourth preset side length R4 (R4 is greater than R2) is used to divide the dense region into at least two sub-regions (i.e. rectangular regions) with any specified graphic structure 120 as the center, and the average height of the graphic structure 120 in each sub-region is calculated; if the average height is less than or equal to a fourth preset height threshold (the fourth preset height threshold is greater than the first preset height threshold), and greater than or equal to a fifth preset height threshold (the fifth preset height threshold is less than the second preset height threshold), the corresponding first etching parameter is adjusted, such as increasing the ion concentration according to the corresponding preset increment; if the average height is less than the fifth preset height threshold, and greater than or equal to a sixth preset height threshold (the sixth preset height threshold is greater than the third preset height threshold), the corresponding first etching parameter is adjusted, such as increasing the ICP power according to the corresponding preset increment, so as to increase the ion concentration; if the average height is less than the sixth preset height threshold, the current first etching parameter is maintained.

[0073] Compared with a complex multi-layer structure (for example, an optical waveguide with a double waveguide layer and a double-layer cover layer) that is more suitable for the experimental stage, in the present embodiment, the ion concentration in the etching parameters is set based on the sparse and dense regions of the waveguide structure 110 and the average height of the waveguide structure in the region, so as to reduce the difficulty of controlling the etching depth / etching time of the first waveguide layer 300 due to uneven imprint structure, uneven residual layer thickness, and etching ratio difference (even if the etching time difference between different waveguide structures is large, part of the waveguide structure is not smooth or serious lateral etching occurs, thereby affecting the performance of the optical waveguide), without using a covering deposition process and etching process. Not only is the cost lower, but the complexity of the entire preparation process of the optical waveguide is also reduced, and industrialization is achieved.

[0074] The present embodiment analyzes the graphical information of the imprint template, predicts the non-uniformity (micro-loading effect and depth effect) in the etching process in advance, and dynamically compensates different regions by applying different process parameters during etching, so as to finally ensure global uniform etching of a large area.

[0075] Of course, in other embodiments, the same principle can also be adopted when the second waveguide layer 300B is patterned by using the nano-imprint lithography process. That is, based on the width of the pattern structure 120 of the corresponding waveguide structure 110 on the pre-prepared imprint soft template 500 for the second waveguide layer 300B, the width is divided into sparse areas and dense areas, and then different etching parameters are set for the sparse areas and the dense areas, respectively. For example, for the sparse areas, over-etching is performed based on the seventh preset etching parameters; and for the dense areas, over-etching is performed based on the eighth preset etching parameters; wherein the seventh preset etching parameters include the seventh ion concentration (or the seventh ICP power) or the seventh etching time, the eighth preset etching parameters include the eighth ion concentration (or the eighth ICP power) or the eighth etching time, the eighth ion concentration is greater than the seventh ion concentration, or the eighth etching time is greater than the seventh etching time. Of course, further, based on the same principle, the height of each pattern structure in the dense area (preferably, obtained from the GDSII layout; the height actually maps the etching depth of the groove between the waveguide structures 110) can also be obtained, and further partitioned; specifically, for each dense area, taking any specified pattern structure as the center, the fifth preset side length R5 (R5 is less than R2) is used to partition the dense area to obtain at least two sub-areas (i.e., rectangular areas), and the average height of the pattern structure 120 in each sub-area is calculated; if the average height is less than or equal to the seventh preset height threshold and greater than or equal to the eighth preset height threshold, the eighth etching parameters corresponding to the corresponding sub-area are adjusted, such as increasing the initial etching time by the third preset increment, or increasing the initial ICP power, so as to increase the ion concentration; if the average height is less than the eighth preset height threshold and greater than or equal to the ninth preset height threshold, the eighth etching parameters corresponding to the corresponding sub-area are adjusted, such as increasing the initial etching time by the fourth preset increment, or increasing the initial ICP power, so as to increase the ion concentration; wherein the fourth preset increment is less than the third preset increment; if the average height is less than the ninth preset height threshold, the current eighth etching parameters are maintained. Further, if the ion concentration is increased, the thickness of the third protective layer 204 is increased accordingly.

[0076] Embodiment four: the present application also provides another method for heterogeneous integration of thin film lithium niobate and light-transmitting substrate waveguide system, which comprises the steps of embodiment three, except that the second waveguide layer 300B is made of thin film lithium niobate material, and due to the consideration of the properties of thin film lithium niobate, sometimes the waveguide structure 110 on the second waveguide layer 300B is not designed to be too dense, but a waveguide structure 110 with a large height difference can be designed, so in this embodiment, the etching parameters are configured from the two angles of the width and height (related to the etching depth) of the waveguide structure 110. That is, the first waveguide layer 300 still adopts the method of dividing the dense and sparse areas based on the duty cycle in embodiment three, and adjusting the etching parameters based on the width and height, and different from the etching parameter configuration method of the first waveguide layer 300, the etching parameters of the second waveguide layer 300B in this embodiment are not based on the duty cycle to distinguish the dense and sparse areas, but based on the height or depth of the pattern structure 120 to distinguish the deep etching area and the shallow etching area (here, the deep etching and the shallow etching refer to the etching depth corresponding to different waveguide structures 110 when the second waveguide layer 300B is etched through, and the etching depth greater than or equal to the preset height threshold is deep etching, and the etching depth less than the preset height threshold is shallow etching), then the average width of the pattern structure 120 or the waveguide structure 110 in each area is graded, and the corresponding process parameters are configured for each level area. Referring to Figure 8, specifically comprising steps: S601, acquiring the width and height of each graphic structure 120 (preferably, from the GDSII layout; the height actually maps the etching depth of the groove between the waveguide structures 110); S602, taking any designated graphic structure as the center, the second preset side length R2 is used to divide the second waveguide layer 300B into regions (actually, the regions are differentiated according to the side of the graphic structure provided on the soft stamp in the design drawing), thereby obtaining a plurality of regions (i.e., rectangular regions), and calculating the average height and average width of the graphic structure 120 in each region; S603, judging whether the average height of each region is greater than or equal to the tenth preset height threshold, and whether the average width is greater than or equal to the first preset width threshold; if the average height is less than or equal to the tenth preset height threshold, the corresponding region is marked as a shallow etching region; if the average height is greater than the tenth preset height threshold, the corresponding region is marked as a deep etching region; if the average width of any shallow etching region is less than the first preset width threshold, the region is marked as a first-level shallow etching region; if the average width is greater than or equal to the first preset width threshold, the region is marked as a second-level shallow etching region; if the average width of any deep etching region is less than the first preset width threshold, the region is marked as a first-level deep etching region; if the average width is greater than or equal to the first preset threshold, the region is marked as a second-level deep etching region. The higher the height and the greater the width of the graphic structure in a certain region, the greater the distance between the waveguide structures, although the etching depth is deep; the higher the height and the smaller the width of the graphic structure in a certain region, the smaller the distance between the waveguide structures, and the etching depth is deep, therefore, compared to the former region, if the same etching parameters are used, the etching rate of the latter region is slower, so as to reduce the difference in etching time and thus reduce the overall over-etching time, the etching parameters of the latter region can be greater than those of the former region.

[0077] Correspondingly, step S105 specifically comprises: for the first-level shallow etching region, over-etching based on the ninth preset etching parameter; for the second-level shallow etching region, over-etching based on the tenth preset etching parameter; for the first-level deep etching region, over-etching based on the eleventh preset etching parameter; for the second-level deep etching region, over-etching based on the twelfth preset etching parameter. Wherein, the ninth preset etching parameter comprises a ninth ICP power, the tenth preset etching parameter comprises a tenth ICP power, the eleventh preset etching parameter comprises an eleventh ICP power; the twelfth preset etching parameter comprises a twelfth ICP power. Preferably, the twelfth ICP power < the eleventh ICP power, the ninth ICP power < the twelfth ICP power, and the tenth ICP power < the ninth ICP power.

[0078] Embodiment five: referring to FIG. 1, a structural schematic diagram of an embodiment of a heterogeneous integrated structure of a thin film lithium niobate and light-transmitting substrate waveguide system of the present application, which is prepared based on the method of Embodiment one or Embodiment three or four. Specifically, the heterogeneous integrated structure specifically comprises: a light-transmitting substrate 100, a first shield layer 200-1 located on the light-transmitting substrate 100, and a first waveguide layer 300 located on the first shield layer 200-1, and a first cover layer 800-1 surrounding the first waveguide layer 300, and a second shield layer 200-2 located on the upper surface of the first cover layer 800-1 and the upper surface of the first waveguide layer 300, and a second waveguide layer 300B located on the second shield layer 200-2; wherein the upper surface of the first cover layer 800-1 is flush with the upper surface of the first waveguide layer 300.

[0079] Further, the first shield layer 200-1 and the second shield layer 200-2 are both patterned. Specifically, as described in Embodiment one, since the first waveguide layer 300 and the second waveguide layer 300B are respectively subjected to etching, the first shield layer 200-1 located on the light-transmitting substrate 100 is also patterned; similarly, the second shield layer 200-2 is also patterned.

[0080] In other embodiments, the first shield layer 200-1 is a double-layer structure, specifically comprising: a first protective layer 202 located on the first surface 101 of the light-transmitting substrate 100, and a second protective layer 203 located between the first protective layer 202 and the first waveguide layer 300, wherein the first protective layer 202 is obtained by depositing silicon dioxide with a thickness of H1 on the first surface 101 of the light-transmitting substrate 100 using a first deposition process such as HDP-CVD technology, and has a first topography; the second protective layer 203 is obtained by depositing silicon dioxide with a thickness of H2 on the upper surface of the first protective layer 202 using a second deposition process such as PECVD technology, and has a second topography, and the first topography and the second topography are complementary, so that the first protective layer and the second protective layer form a first shield layer with flat upper and lower surfaces.

[0081] In some other embodiments, the second mask layer 200-2 also adopts a double-layer structure, specifically, it comprises: a third protective layer 204 located on the upper surface of the first waveguide layer 300 and the upper surface of the first cover layer 800-1, and a fourth protective layer 205 located between the third protective layer 204 and the second waveguide layer 300B, wherein the third protective layer 204 is obtained by depositing silicon dioxide with a thickness of H3 on the upper surface of the first waveguide layer 300 and the upper surface of the first cover layer 800-1 by using a first deposition process such as HDP-CVD technology, and has a first topography; the fourth protective layer 205 is obtained by depositing silicon dioxide with a thickness of H4 on the upper surface of the third protective layer 204 by using a second deposition process such as PECVD technology, and has a second topography, and the first topography and the second topography are complementary, so that the third protective layer and the fourth protective layer form the second mask layer 200-2 with flat upper and lower surfaces. Specifically, the first mask layer 200-1 and the second mask layer 200-2 of the double-layer structure are both prepared in the manner of Embodiment 2. Correspondingly, the second protective layer 203 and the fourth protective layer 205 are both patterned.

[0082] Preferably, the thickness H2 of the second protective layer 203 is less than the thickness H1 of the first protective layer 202. Preferably, H1+H2≥1um (i.e. the thickness of the mask layer 200 is greater than or equal to 1um). Preferably, the thickness H4 of the fourth protective layer 205 is less than the thickness H3 of the third protective layer 204. Preferably, H3+H4≥5um (i.e. the thickness of the second mask layer 200-2 is greater than or equal to 5um).

[0083] In some other embodiments, the hetero-integrated structure further comprises a second cover layer 800-2 covering the second waveguide layer 300B.

[0084] It should be noted that in this document, the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or inherent to such a process, method, article or device. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

[0085] The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the specific embodiments described above, which are only illustrative rather than limiting, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. A method for heterogeneous integration of a thin-film lithium niobate and a transparent substrate waveguide system, characterized in that, Including the following steps: S101, a first masking layer (200-1) is deposited on the first surface (101) of the light-transmitting substrate (100), the first masking layer (200-1) being used to protect the light-transmitting substrate (100) during subsequent etching. S102, deposit a first waveguide layer (300) on the second surface (201) of the first shielding layer (200-1). S103, a first capping layer (800-1) is deposited around the first waveguide layer (300), the upper surface of the first capping layer (800-1) being flush with the upper surface of the first waveguide layer (300); S104, deposit a second shielding layer (200-2) on the upper surface of the first waveguide layer (300) and the upper surface of the first cover layer (800-1). S105, deposit a second waveguide layer (300B) on the second shielding layer (200-2); wherein the second waveguide layer (300B) is a thin film lithium niobate layer.

2. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 1, characterized in that, The light-transmitting substrate (100) is a glass substrate.

3. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 1 or 2, characterized in that, In step S102, a patterned first waveguide layer (300) is fabricated on the first masking layer (200-1) using nanoimprint lithography. And / or, in step S105, a patterned second waveguide layer (300B) is prepared on the first capping layer (800-1) and the first waveguide layer (300) using nanoimprint lithography.

4. A heterogeneous integration method for a thin-film lithium niobate and transparent substrate waveguide system according to claim 1 or 2, characterized in that, Step S101 specifically includes: S1011, a first protective layer (202) with a thickness of H1 and a first morphology is deposited on the first surface (101) using a first deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD. S1012, a second deposition process is used to deposit a silicon dioxide layer (203) with a thickness of H2 and a second morphology on the upper surface of the first protective layer (202); the second deposition process includes PECVD; Wherein, the sum of the thickness H2 of the second protective layer (203) and the thickness H1 of the first protective layer (202) is greater than or equal to 1 μm; and the first protective layer (202) of the first morphology and the second protective layer (203) of the second morphology complement each other to form a flat first protective layer (200-1).

5. A heterogeneous integration method for a thin-film lithium niobate and transparent substrate waveguide system according to claim 1 or 2, characterized in that, Step S104 specifically includes the following steps: S1041, a third protective layer (204) with a first morphology is deposited on the upper surface of the first waveguide layer (300) and the upper surface of the first cover layer (800-1) using a first deposition process. S1042, a fourth protective layer (205) with a second morphology is deposited on the third protective layer (204) using a second deposition process. Wherein, the sum of the thickness H3 of the fourth protective layer (205) and the thickness H4 of the third protective layer (204) is greater than or equal to 5 μm; and the third protective layer (204) of the first morphology and the fourth protective layer (205) of the second morphology complement each other to form a flat second protective layer (200-2).

6. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 3, characterized in that, Before fabricating the patterned first waveguide layer (300) and / or the patterned second waveguide layer (300B) using nanoimprint lithography, the following steps are also included: S401, the width of the graphic structure (120) on the imprinting soft template (500) corresponding to the waveguide structure (110) in the first waveguide layer (300) and / or the width of the graphic structure (120) corresponding to the waveguide structure (110) in the second waveguide layer (300B) is obtained in advance; S402, for the first waveguide layer (300), with the specified graphic structure as the center point, the first waveguide layer (300) is divided into regions by a first preset side length R1 to obtain multiple regions, and the graphic duty cycle of each region is calculated, and step S403 is executed; and / or, for the second waveguide layer (300B), with the specified graphic structure as the center, the second waveguide layer (300B) is divided into regions by a second preset side length R2 to obtain multiple regions, and the image duty cycle of each region is calculated, and step S403 is executed; S403, for the first waveguide layer (300), determine whether the pattern duty cycle of each region is greater than or equal to the first preset duty cycle threshold. If the pattern duty cycle is greater than or equal to the first preset duty cycle threshold, mark the corresponding region as a dense region. If the duty cycle of the graphic is less than the first preset duty cycle threshold, the corresponding region will be marked as a sparse region. And / or, for the second waveguide layer (300B), determine whether the pattern duty cycle of each region is greater than or equal to a second preset duty cycle threshold. If the pattern duty cycle is greater than or equal to the second preset duty cycle threshold, mark the corresponding region as a dense region. If the duty cycle of the graphic is less than the second preset duty cycle threshold, the corresponding region will be marked as a sparse region. Accordingly, during etching in step S102, sparse regions are over-etched based on a first preset etching parameter; while dense regions are over-etched based on a second preset etching parameter; wherein the first preset etching parameter includes a first ICP power, the second preset etching parameter includes a second ICP power, and the second ICP power is greater than the first ICP power; and / or, during etching in step S105, sparse regions are over-etched based on a seventh preset etching parameter; while dense regions are over-etched based on an eighth preset etching parameter; wherein the seventh preset etching parameter includes a seventh ICP power, the eighth preset etching parameter includes an eighth ICP power, and the eighth ICP power is greater than the seventh ICP power.

7. The heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system according to claim 3, characterized in that, Before fabricating the patterned second waveguide layer (300B) using nanoimprint lithography, the following steps are also included: S601, obtain the width and height of each graphic structure (120) on the imprinted soft template (500) corresponding to the waveguide structure (110) in the second waveguide layer (300B); S602, with any specified graphic structure as the center, the second waveguide layer (300B) is divided into regions by the second preset side length R2 to obtain multiple regions, and the average height and average width of the graphic structure (120) in each region are calculated; S603, determine whether the average height of each region is greater than or equal to the tenth preset height threshold, and whether the average width is greater than or equal to the first preset width threshold; If the average height is less than or equal to the tenth preset height threshold and the average width is less than the first preset width threshold, the area is marked as a Class I shallow etching area. If the average height is less than or equal to the tenth preset height threshold and the average width is greater than or equal to the first preset width threshold, the area is marked as a Level II shallow etching area. If the average height is greater than the tenth preset height threshold and the average width is less than the first preset width threshold, the area is marked as a Level I deep area. If the average height is greater than the tenth preset height threshold and the average width is greater than or equal to the first preset threshold, the area is marked as a Class II deep erosion area. Accordingly, step S105 specifically includes: for the Class I shallow etched area, over-etching is performed based on the ninth preset etch parameter; for the Class II shallow etched area, over-etching is performed based on the tenth preset etch parameter; for the Class I deep etched area, over-etching is performed based on the eleventh preset etch parameter; for the Class II deep etched area, over-etching is performed based on the twelfth preset etch parameter; wherein, the ninth preset etch parameter includes the ninth ICP power, the tenth preset etch parameter includes the tenth ICP power, the eleventh preset etch parameter includes the eleventh ICP power, and the twelfth preset etch parameter includes the twelfth ICP power.

8. A heterogeneous integrated structure of a thin-film lithium niobate and a transparent substrate waveguide system, characterized in that, It is prepared using a heterogeneous integration method of a thin-film lithium niobate and transparent substrate waveguide system as described in any one of claims 1 to 7, comprising: A light-transmitting substrate (100), a first masking layer (200-1) on the light-transmitting substrate (100), and a patterned first waveguide layer (300) on the first masking layer (200-1); a first cover layer (800-1) surrounding the first waveguide layer (300), and a second masking layer (200-2) on the upper surface of the first cover layer (800-1) and the upper surface of the first waveguide layer (300), and a second waveguide layer (300B) on the second masking layer (200-2); the upper surface of the first cover layer (800-1) is flush with the upper surface of the first waveguide layer (300); The first shielding layer (200-1) and the second shielding layer (200-2) are both deposited using pure silicon dioxide material, and the thickness of the first shielding layer (200-1) and the second shielding layer (200-2) is greater than or equal to 1 μm.

9. The heterogeneous integrated structure of a thin-film lithium niobate and transparent substrate waveguide system according to claim 8, characterized in that, The first shielding layer (200-1) includes: a first protective layer (202) with a thickness of H1 on a first surface (101) of the light-transmitting substrate (100); and a second protective layer (203) with a thickness of H2 deposited on the upper surface of the first protective layer (202); H1+H2≥1um; and / or, the second shielding layer (200-2) includes: a third protective layer (204) with a thickness of H3 on the first cover layer (800-1) and the first waveguide layer (300); and a fourth protective layer (205) with a thickness of H4 on the upper surface of the third protective layer (204); H3+H4≥5um.

10. The heterogeneous integrated structure of a thin-film lithium niobate and transparent substrate waveguide system according to claim 9, characterized in that, The first protective layer (202) or the third protective layer (204) is a silicon dioxide layer with a first morphology deposited using a first deposition process; the first deposition process includes HDP-CVD, SACVD, or FCVD. The second protective layer (203) or the fourth protective layer (205) is a silicon dioxide layer with a second morphology deposited using a second deposition process; the second deposition process includes PECVD; wherein the first protective layer (202) of the first morphology and the second protective layer (203) of the second morphology complement each other to form a flat first protective layer (200-1), or the third protective layer (204) of the first morphology and the fourth protective layer (205) of the second morphology complement each other to form a flat second protective layer (200-2).

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