Transistor selection method, apparatus, and computer equipment for loss balancing

Abstract

This invention discloses a transistor selection method, apparatus, and computer device for loss equalization. The method includes: acquiring multiple first rise times, multiple second rise times, and a target number of transistors for parallel circuits for each of multiple transistors; selecting the target number of transistors from the multiple transistors, iterating through all selection combinations to obtain multiple transistor parallel groups; determining an average difference coefficient for each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times; and selecting multiple transistors in the parallel groups whose average difference coefficients satisfy a preset condition as multiple target transistors, wherein the multiple target transistors are used in the parallel circuit. This invention solves the technical problems of high complexity and poor dynamic response in current transistor switching loss equalization control techniques for parallel circuits.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a transistor selection method, apparatus, and computer device for balancing losses. Background Technology

[0002] In today's power electronics field, silicon carbide (SiC) MOSFETs have gradually become core components for building high-power, high-frequency application systems due to their excellent electrical performance and high-temperature resistance. However, when multiple chips are used in parallel, due to limitations in manufacturing processes and individual differences in chip parameters, the switching losses experienced by each MOSFET during switching are not the same. This directly leads to instability and reduced efficiency in the parallel system. In particular, chips with higher switching losses are prone to excessively high junction temperatures, posing a risk of thermal failure and consequently affecting the reliability and lifespan of the entire system.

[0003] Traditional solutions, such as static sorting and parameter matching, typically evaluate and adjust the static characteristics of MOSFETs during the design phase, aiming to reduce performance differences between chips. However, this approach falls short when dealing with dynamic changes in real-world operating environments. Instantaneous load fluctuations, temperature variations, and even minor voltage changes can significantly alter switching losses, drastically reducing effectiveness. Furthermore, temperature-compensated switching loss control strategies have emerged. These strategies monitor MOSFET temperature in real time and adjust switching control accordingly to reduce switching loss imbalances. While theoretically, this approach can compensate for temperature-induced loss differences to some extent, its effectiveness is often unsatisfactory under complex and variable real-world load conditions. It also places high demands on hardware, increasing system complexity and cost.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This invention provides a transistor selection method, apparatus, and computer device for balancing losses, to at least solve the technical problems of high complexity and poor dynamic response in current switching loss balancing control techniques for transistors in parallel circuits.

[0006] According to one aspect of the present invention, a transistor selection method for balancing losses is provided, comprising: obtaining a plurality of first rise times corresponding to a plurality of transistors, a plurality of second rise times corresponding to a plurality of transistors, and a target number of transistors for a parallel circuit, wherein the first rise time is the time required for the drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to a corresponding preset current measurement point during the turn-on process; selecting the target number of transistors from the plurality of transistors, traversing all selection combinations to obtain a plurality of transistor parallel groups; determining an average difference coefficient corresponding to each of the plurality of transistor parallel groups based on the plurality of first rise times and the plurality of second rise times corresponding to the plurality of transistors, wherein the average difference coefficient characterizes the average difference degree of turn-on and turn-off characteristics among the plurality of transistors in the corresponding transistor parallel group; and selecting the plurality of transistors in the transistor parallel group whose average difference coefficient satisfies a preset condition as a plurality of target transistors, wherein the plurality of target transistors are used in a parallel circuit.

[0007] Optionally, obtaining multiple first rise times corresponding to each of the multiple transistors includes: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions of each of the multiple transistors; simulating the turn-off process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curves between the drain-source voltage and time of the multiple transistors during the turn-off process, wherein the preset test circuit has a symmetrical structure; and determining multiple first rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset voltage measurement points.

[0008] Optionally, obtaining multiple second rise times corresponding to each of the multiple transistors includes: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions of each of the multiple transistors; simulating the turn-on process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curve of the current flowing through the transistors versus time during the turn-on process, wherein the preset test circuit has a symmetrical structure; and determining multiple second rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset current measurement points.

[0009] Optionally, based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, an average difference coefficient corresponding to each of the multiple parallel transistor groups is determined. The average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding parallel transistor group. This includes: determining the total difference coefficient between any two transistors in the multiple parallel transistor group based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, where the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors; and calculating the average value of the multiple total difference coefficients corresponding to each of the multiple parallel transistor groups, using the average value as the average difference coefficient.

[0010] Optionally, based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, a total difference coefficient between any two transistors in the parallel group of multiple transistors is determined, wherein the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors, including: determining a first difference coefficient between any two transistors in the parallel group of multiple transistors based on the multiple first rise times, wherein the first difference coefficient characterizes the difference in the turn-off characteristics between the two transistors; determining a second difference coefficient between any two transistors in the parallel group of multiple transistors based on the multiple second rise times, wherein the second difference coefficient characterizes the difference in the turn-on characteristics between the two transistors; and weighting the multiple first difference coefficients with the corresponding multiple second difference coefficients based on preset weights to obtain the total difference coefficient between any two transistors in the parallel group of multiple transistors.

[0011] Optionally, based on multiple first rise times, a first difference coefficient between any two transistors in a plurality of parallel transistor groups is determined. The step of calculating the first difference coefficient between the first transistor and the second transistor is as follows, where the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the first rise times of the first transistor and the second transistor at multiple preset voltage measurement points; determining the average time difference based on the difference; and determining the first difference coefficient between the first transistor and the second transistor based on the average time difference.

[0012] Optionally, based on multiple second rise times, a second difference coefficient between any two transistors in multiple parallel transistor groups is determined. The step of calculating the second difference coefficient between the first transistor and the second transistor is as follows, where the first transistor and the second transistor are any two transistors in any group of multiple parallel transistor groups, including: calculating the difference between the second rise times corresponding to the first transistor and the second transistor at multiple preset current measurement points; determining the average time difference based on the difference; and determining the second difference coefficient between the first transistor and the second transistor based on the average time difference.

[0013] According to another aspect of the present invention, a transistor selection device for balancing losses is also provided, comprising: an acquisition module, configured to acquire a plurality of first rise times corresponding to a plurality of transistors, a plurality of second rise times corresponding to a plurality of transistors, and a target number of transistors for a parallel circuit, wherein the first rise time is the time required for the drain-source voltage of a transistor to rise to a corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to a corresponding preset current measurement point during the turn-on process; a traversal module, configured to select the target number of transistors from the plurality of transistors, traversing all selection combinations to obtain a plurality of transistor parallel groups; a determination module, configured to determine an average difference coefficient corresponding to each of the plurality of transistor parallel groups based on the plurality of first rise times and the plurality of second rise times corresponding to a plurality of transistors, wherein the average difference coefficient characterizes the average difference degree of turn-on and turn-off characteristics among the plurality of transistors in the corresponding transistor parallel group; and a selection module, configured to select the plurality of transistors in the transistor parallel group whose average difference coefficient satisfies a preset condition as a plurality of target transistors, wherein the plurality of target transistors are used in a parallel circuit.

[0014] According to another aspect of the present invention, a non-volatile storage medium is also provided, the non-volatile storage medium including a stored program, wherein, when the program is running, it controls the device where the non-volatile storage medium is located to execute any of the above-described transistor selection methods for balancing losses.

[0015] According to another aspect of the present invention, a computer device is also provided, the computer device including a processor, the processor being configured to run a program, wherein the program, when running, executes any of the transistor selection methods described above for balancing losses.

[0016] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements any of the above-described transistor selection methods for balancing losses.

[0017] In this embodiment of the invention, a transistor selection method for balancing losses is employed. This involves acquiring multiple first rise times and multiple second rise times corresponding to each transistor, as well as a target number of transistors for parallel circuits. The first rise time is the time required for the drain-source voltage of a transistor to rise to a corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to a corresponding preset current measurement point during the turn-on process. The target number of transistors is selected from the multiple transistors, and all selected combinations are iterated to obtain multiple transistor parallel groups. Based on the multiple first rise times and multiple second rise times corresponding to each transistor, an average difference coefficient is determined for each of the multiple transistor parallel groups. The average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the transistors in the corresponding parallel group. Multiple transistors in the parallel groups whose average difference coefficients meet preset conditions are selected as target transistors for use in the parallel circuit. This achieves the goal of selecting the transistor combination with the lowest switching losses during parallel connection, thereby improving system efficiency and reducing the risk of thermal failure. This solves the technical problems of high complexity and poor dynamic response in current transistor switching loss balancing control techniques used in parallel circuits. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0019] Figure 1 A hardware block diagram of a computer terminal for implementing a transistor selection method for balancing losses is shown.

[0020] Figure 2 This is a schematic flowchart of a transistor selection method for balancing losses provided in an embodiment of the present invention;

[0021] Figure 3 This is a flowchart illustrating the construction of a silicon carbide MOSFET dynamic characteristic testing platform according to an optional embodiment of the present invention;

[0022] Figure 4 This is a flowchart of a turn-off voltage rise curve test and sorting method provided by an optional embodiment of the present invention;

[0023] Figure 5 This is a flowchart of a turn-on current rise curve test and sorting method provided by an optional embodiment of the present invention;

[0024] Figure 6This is a flowchart of the calculation and weighted sorting of switching loss difference coefficients according to an optional embodiment of the present invention;

[0025] Figure 7 This is a structural block diagram of a transistor selection device for balancing losses provided in an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] According to an embodiment of the present invention, a transistor selection method for balancing losses is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0029] The method embodiment provided in Embodiment 1 of this application can be executed on a mobile terminal, computer terminal, or similar computing device. Figure 1 A hardware block diagram of a computer terminal for implementing a transistor selection method for balancing losses is shown. Figure 1As shown, the computer terminal 10 may include one or more processors (shown as 102a, 102b, ..., 102n in the figure) (the processor may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of a BUS bus), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, computer terminal 10 may also include... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0030] It should be noted that the aforementioned one or more processors and / or other data processing circuits are generally referred to herein as "data processing circuits". These data processing circuits may be embodied, in whole or in part, in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuits may be a single, independent processing module, or may be integrated, in whole or in part, into any other element within the computer terminal 10. As involved in the embodiments of this application, the data processing circuits serve as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0031] The memory 104 can be used to store software programs and modules for application software, such as the program instructions / data storage device corresponding to the transistor selection method for balancing losses in this embodiment of the invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 104, thereby implementing the transistor selection method for balancing losses in the aforementioned application program. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor, and these remote memories can be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0032] The display can be, for example, a touchscreen liquid crystal display (LCD) that allows the user to interact with the user interface of the computer terminal 10.

[0033] Figure 2 This is a flowchart illustrating a transistor selection method for loss balancing provided by an embodiment of the present invention, as shown below. Figure 2As shown, the method includes the following steps:

[0034] Step S201: Obtain multiple first rise times corresponding to multiple transistors, multiple second rise times corresponding to multiple transistors, and the target number of transistors for parallel circuits. The first rise time is the time required for the drain-source voltage of the transistor to rise to the corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to the corresponding preset current measurement point during the turn-on process.

[0035] In this step, in this embodiment of the invention, the transistor can be a silicon carbide MOSFET. The first rise time refers to the time required for the drain-source voltage to rise from zero to a preset voltage measurement point during the turn-off process of the silicon carbide MOSFET. The preset voltage measurement point is pre-set based on the characteristics of the transistor and is usually selected within the range where its change is most significant. The voltage rise time during the turn-off process reflects the speed of transistor turn-off; a longer time means a slower turn-off process, which may lead to an unbalanced current distribution between the transistor and other parallel transistors during the turn-off phase, thereby increasing switching losses during the turn-off process.

[0036] The second rise time, relative to the first rise time, is measured during the transistor's turn-on process. Specifically, it refers to the time required for the current flowing through the transistor to rise from zero to a preset current measurement point. The preset current measurement point is also set based on the transistor's dynamic characteristics and is typically chosen within the range where the current rises sharply. The length of the turn-on current rise time directly affects the transistor's turn-on speed; a shorter time indicates rapid turn-on and has a direct impact on the system's transient response and switching losses. If some transistors in a parallel circuit turn on significantly slower than others, then during turn-on, the current will tend to flow more towards the faster-turning transistors, leading to current imbalance and additional switching losses.

[0037] Step S202: Select the target number of transistors from multiple transistors, traverse all selection combinations, and obtain multiple transistor parallel groups.

[0038] In this step, after determining the target number, combinations can be selected from all transistors (i.e., multiple transistors) whose dynamic characteristics have been measured on the test platform, according to the target number. This process is called "traversal." Traversing all possible selection combinations means that each possible chip combination must be evaluated to find the optimal combination that achieves balanced switching losses. During the traversal, each selection combination is analyzed in detail, comparing the consistency of the first and second rise times among the transistors, and weighting the switching loss difference coefficients, thereby identifying the transistor combination that can achieve minimized switching losses and balanced current distribution.

[0039] Step S203: Based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, determine the average difference coefficient corresponding to each of the multiple parallel transistor groups, wherein the average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding parallel transistor group.

[0040] In this step, after obtaining the first and second rise times of each transistor, these dynamic parameters can be further processed to determine the average difference coefficient of the parallel group. This coefficient is an important indicator for evaluating the consistency of dynamic characteristics of transistors within a parallel group, characterizing the average difference in turn-on and turn-off characteristics among multiple transistors in the parallel group. As a quantitative indicator for evaluating dynamic performance consistency, the average difference coefficient is crucial for the optimal selection of parallel groups. Through this coefficient, the dynamic characteristic consistency of different parallel groups can be systematically compared, thereby selecting the most suitable transistor combination as part of the parallel circuit. In practical applications, selecting the parallel group with the smallest average difference coefficient means that switching losses in the parallel circuit will be minimized, and current distribution will be more balanced. This directly improves the overall efficiency and reliability of the system, reduces overheating and circulating current problems, and extends the service life of the equipment.

[0041] Step S204: Select multiple transistors in the parallel group of transistors whose average difference coefficient meets the preset condition as multiple target transistors, wherein the multiple target transistors are used in the parallel circuit.

[0042] In this step, after obtaining the average difference coefficient of all parallel groups, these coefficients can be compared with preset conditions. The preset condition can be to minimize the average difference coefficient. Once the parallel groups that meet the preset conditions are identified, the multiple transistors in these parallel groups are defined as "multiple target transistors". These target transistors will be the core components for building the parallel system. They have the smallest difference in switching losses and the most consistent dynamic response characteristics, which can effectively reduce current imbalance and local overheating problems during system operation, thereby improving the overall performance of the system.

[0043] Through the above steps, the goal of selecting the transistor combination with the lowest switching loss when connected in parallel is achieved, thereby realizing the technical effects of improving system efficiency and reducing the risk of thermal failure. This solves the technical problems of high complexity and poor dynamic response of the current switching loss equalization control technology for transistors used in parallel circuits.

[0044] As an optional embodiment, obtaining multiple first rise times corresponding to each of the multiple transistors includes: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions corresponding to each of the multiple transistors; simulating the turn-off process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curves between the drain-source voltage and time of the multiple transistors during the turn-off process, wherein the preset test circuit has a symmetrical structure; and determining the multiple first rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset voltage measurement points.

[0045] Optionally, the dual-pulse signals are generated to simulate the switching conditions faced by the MOSFET during actual operation, including the turn-on and turn-off processes. The amplitude, time interval, and duration of these signals are preset according to the operating conditions of the silicon carbide transistor, aiming to ensure that the test conditions are as close as possible to real-world applications, thereby obtaining data that reflects the true dynamic characteristics. The test circuit is designed with a symmetrical structure, meaning that the left and right sides or upstream and downstream sections of the circuit are electrically identical. The symmetrical structure of the test circuit helps to eliminate external interference during the testing process, ensuring that each transistor is tested under the same conditions, thereby obtaining comparable dynamic performance data.

[0046] During testing, when the first part of the dual-pulse signal (i.e., the turn-off pulse) is applied to the corresponding transistor in the test circuit, the change of the drain-source voltage (Vds) of the transistor over time can be recorded in real time using a high-precision measurement system or oscilloscope. The acquired data will be plotted as a curve, i.e., the relationship between drain-source voltage and time. Based on this relationship curve, multiple preset voltage measurement points can be selected. These points are usually located within the range where Vds changes most significantly, and are used to evaluate the dynamic characteristics of transistor turn-off. The first rise time refers to the time required for the transistor to rise from the start of turn-off to a certain preset voltage measurement point.

[0047] As an optional embodiment, obtaining multiple second rise times corresponding to each of the multiple transistors includes: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions corresponding to each of the multiple transistors; simulating the turn-on process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curve of the current flowing through the transistors versus time during the turn-on process, wherein the preset test circuit has a symmetrical structure; and determining the multiple second rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset current measurement points.

[0048] Optionally, each dual-pulse signal consists of two pulses: the first pulse simulates the MOSFET's turn-off process, while the second pulse simulates the turn-on process. The amplitude, time interval, and duration of these signals are precisely matched according to the specific operating conditions of the transistor. The test circuit employs a symmetrical structure to eliminate the effects of asymmetry during the testing process, ensuring that all transistors are tested under the same electrical environment. The use of symmetrical circuitry helps obtain accurate and comparable test data, avoids measurement errors introduced by differences in circuit structure, and guarantees the reliability and validity of the test results.

[0049] During dynamic testing, when the second part of the dual-pulse signal (the turn-on pulse) is applied to the transistor in the test circuit, the current change of the transistor is measured in real time by a current sensor. This process records the relationship between current and time, forming a current-time curve. The second rise time refers to the time required for the transistor to rise from the initial stage of the turn-on process to the preset current measurement point. The preset current measurement point is pre-set based on the rated current of the transistor and system requirements, and is usually selected in the range where the current change is most significant. By measuring the second rise time of multiple transistors and combining it with the current-time curve, we can quantitatively evaluate and compare the turn-on response characteristics of different transistors. This is a key basis for selecting transistors with high consistency for parallel connection.

[0050] As an optional embodiment, based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, an average difference coefficient corresponding to each of the multiple parallel transistor groups is determined. The average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding parallel transistor group. This includes: determining the total difference coefficient between any two transistors in the multiple parallel transistor group based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, where the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors; and calculating the average value of the multiple total difference coefficients corresponding to each of the multiple parallel transistor groups, using the average value as the average difference coefficient.

[0051] Optionally, for any two transistors in the parallel group, the difference between their first rise time and second rise time is calculated. Considering that the turn-on and turn-off processes have equally significant effects on switching losses, the differences in the first and second rise times of the two transistors are weighted, typically assigned equal weights (e.g., 0.5). The total difference coefficient between the two transistors is obtained by summing these differences; this coefficient summarizes the degree of difference in their turn-on and turn-off characteristics. For each pair of transistors in the parallel group, the first stage operation described above is repeated to calculate their total difference coefficient. The average difference coefficient of the parallel group is obtained by averaging all total difference coefficients within the parallel group. A smaller average difference coefficient indicates better consistency in the dynamic characteristics of the transistors in the parallel group, smaller differences in switching losses, and a more balanced current distribution.

[0052] As an optional embodiment, based on multiple first rise times corresponding to multiple transistors and multiple second rise times corresponding to multiple transistors, a total difference coefficient between any two transistors in a parallel group of multiple transistors is determined, wherein the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors. This includes: determining a first difference coefficient between any two transistors in a parallel group of multiple transistors based on multiple first rise times, wherein the first difference coefficient characterizes the difference in the turn-off characteristics between the two transistors; determining a second difference coefficient between any two transistors in a parallel group of multiple transistors based on multiple second rise times, wherein the second difference coefficient characterizes the difference in the turn-on characteristics between the two transistors; and weighting the multiple first difference coefficients with their corresponding multiple second difference coefficients based on preset weights to obtain the total difference coefficient between any two transistors in a parallel group of multiple transistors.

[0053] Optionally, for any two transistors in the parallel group, their first rise time during the turn-off process (i.e., the time from the initial value to the preset voltage measurement point) is compared. This time difference reflects the difference in the transistor's response speed and dynamic performance during the turn-off process. This difference is quantified as a first difference coefficient to measure the consistency of the turn-off characteristics of the two transistors. The smaller the first difference coefficient, the higher the similarity of the two transistors in their turn-off characteristics. Similarly, during the turn-on process, by comparing the second rise time (i.e., the time from zero to the preset current measurement point) of any two transistors in the parallel group, their dynamic performance difference during the turn-on process can be quantified. This difference quantification result is the second difference coefficient. The smaller the second difference coefficient, the higher the similarity of the two transistors in their turn-on characteristics.

[0054] After obtaining the first and second difference coefficients, they can be weighted and summed based on preset weights to calculate the total difference coefficient between any two transistors. The preset weights reflect the relative importance of turn-off and turn-on characteristics in balancing switching losses. Typically, the impact of turn-off and turn-on characteristics on switching losses is considered equal, so the weights are usually set to equal values ​​(e.g., 0.5 to 0.5). The formula for calculating the total difference coefficient can be expressed as: Total Difference Coefficient = Weight × First Difference Coefficient + Weight × Second Difference Coefficient. This calculation integrates the dynamic characteristic differences of transistors during turn-off and turn-on processes, providing a comprehensive perspective for evaluating the consistency of transistor performance in parallel groups.

[0055] As an optional embodiment, a first difference coefficient between any two transistors in a plurality of parallel transistor groups is determined based on multiple first rise times. The step of calculating the first difference coefficient between the first transistor and the second transistor is as follows, where the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the first rise times of the first transistor and the second transistor at multiple preset voltage measurement points; determining the average time difference based on the difference; and determining the first difference coefficient between the first transistor and the second transistor based on the average time difference.

[0056] Optionally, for any two transistors in the parallel group, such as the first transistor and the second transistor, the difference between their first rise times at various preset voltage measurement points can be calculated first. This difference reflects the difference in response speed between the first transistor and the second transistor in terms of turn-off dynamic characteristics. Based on the difference in the first rise time of the first transistor and the second transistor at multiple preset voltage measurement points, the average of these differences is calculated, i.e., the average time difference. The average time difference is a comprehensive quantitative indicator of the consistency of the dynamic response of the first transistor and the second transistor at different voltage measurement points during the turn-off process. Specifically, all differences are summed and then divided by the total number of voltage measurement points; the quotient is the average time difference between the first transistor and the second transistor. The average time difference between the first transistor and the second transistor is used as the first difference coefficient between them. This coefficient directly measures the difference in the dynamic characteristics of the two transistors during the turn-off process, i.e., the degree of consistency between the first transistor and the second transistor in the drain-source voltage rise response. The smaller the first difference coefficient, the smaller the difference in the turn-off characteristics of the two transistors, and the more uniform the current distribution during the turn-off process, which helps to reduce switching losses and the risk of local overheating.

[0057] As an optional embodiment, a second difference coefficient between any two transistors in a plurality of parallel transistor groups is determined based on a plurality of second rise times. The step of calculating the second difference coefficient between the first transistor and the second transistor is as follows, wherein the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the second rise times corresponding to the first transistor and the second transistor at a plurality of preset current measurement points; determining the average time difference based on the difference; and determining the second difference coefficient between the first transistor and the second transistor based on the average time difference.

[0058] Optionally, for any two transistors in the parallel group, such as the first transistor and the second transistor, the difference between their second rise times at various preset current measurement points can be calculated first. This difference reflects the difference in current response speed between the first transistor and the second transistor during the turn-on process. Based on the difference in the second rise times of the first transistor and the second transistor at multiple preset current measurement points, the average of these differences is calculated, i.e., the average time difference. The average time difference is a comprehensive quantitative indicator of the consistency of the dynamic response of the first transistor and the second transistor at different current measurement points during the turn-on process. Specifically, the calculation method is to add up all the differences in the second rise times and then divide by the total number of current measurement points; the quotient is the average time difference between the first transistor and the second transistor. The average time difference between the first transistor and the second transistor is used as the second difference coefficient between them. This coefficient directly measures the difference in the dynamic characteristics of the two transistors during the turn-on process, i.e., the degree of consistency between the first transistor and the second transistor in terms of drain current response time. The smaller the second difference coefficient, the closer the current response speed of the two transistors is during the turn-on process. This can reduce the switching losses caused by uneven current distribution in parallel circuits, reduce the risk of thermal failure, and improve the overall efficiency and reliability of the system.

[0059] As an optional embodiment, a method for equalizing and controlling the switching losses of parallel multi-chip silicon carbide MOSFETs based on dynamic parameter sorting is also provided. This method achieves equalization of switching losses by precisely controlling the consistency of the turn-on and turn-off currents of the parallel chips. Specific steps may include:

[0060] Step 1: Construct a silicon carbide MOSFET dynamic characteristic testing platform. The main function of this platform is to test the dynamic performance of the chips using a dual-pulse signal and accurately acquire the current and voltage change curves of each chip during turn-on and turn-off. Optionally, Figure 3 This is a flowchart illustrating the construction of a silicon carbide MOSFET dynamic characteristic testing platform according to an optional embodiment of the present invention, as shown below. Figure 3 As shown, the specific process may include:

[0061] S1: Dual-pulse signal generation. The platform generates dual-pulse signals and simulates the switching process of the chip under different operating states by precisely controlling the amplitude, time interval, and duration of the pulses.

[0062] S2: High-precision measurement system. The platform is equipped with high-precision current and voltage acquisition devices to ensure that the dynamic response characteristics of the chip can be captured in real time and accurately.

[0063] S3: Real-time data processing and analysis. Measurement data is processed in real time by a high-speed processing unit to generate turn-on current rise curves and turn-off voltage rise curves, providing a data basis for subsequent chip sorting.

[0064] Step 2: Turn-off voltage rise curve testing and sorting. By testing the turn-off voltage rise curve of the parallel chips, the consistency of current during the turn-off process of the parallel chips is ensured, thereby achieving a balanced distribution of turn-off current. Figure 4 This is a flowchart of a turn-off voltage rise curve test and sorting method provided by an optional embodiment of the present invention, such as... Figure 4 As shown, the specific process may include:

[0065] S4: Apply the first pulse signal. In the first part of the double pulse signal, the first pulse is applied to control the chip's shutdown process. Through the control of the pulse, the chip begins to enter the shutdown state.

[0066] S5: Voltage rise curve measurement. A high-precision voltage sensor is used to measure the voltage rise characteristics of the chip during the turn-off process in real time.

[0067] S6: Turn-off Voltage Rise Curve Characteristic Analysis. The turn-off characteristics of the chip are evaluated by analyzing the voltage rise curve. If the chip's voltage rise curve changes slowly or exhibits significant hysteresis, it indicates that the voltage is inconsistent during the turn-off process, thus triggering circulating current.

[0068] S7: Turn-off voltage rise curve sorting criteria. Chips are sorted based on the consistency of their voltage rise curves. Chips with significantly different turn-off voltage rise curves should be discarded, and chips with consistent voltage rise curves should be selected for parallel connection to achieve a balanced distribution of turn-off current.

[0069] Step 3: Turn-on Current Rise Curve Testing and Sorting. This step focuses on the turn-on process of the second pulse to accurately test the turn-on current rise curve of the chip. The turn-on current rise curve directly affects the current distribution in the parallel branches, and is therefore crucial for balancing switching losses. Figure 5 This is a flowchart of a turn-on current rise curve test and sorting method provided by an optional embodiment of the present invention, such as... Figure 5 As shown, the specific process may include:

[0070] S8: Apply a second pulse signal. In the dual-pulse signal, a second pulse is applied for the MOSFET turn-on process. Ensure the pulse amplitude and timing are set appropriately to test the chip's current response during actual turn-on.

[0071] S9: Current Rise Curve Measurement. A high-precision current sensor is used to acquire the current rise curve of each chip in real time under the turn-on pulse. This curve reflects the current change characteristics when the chip is turned on, including the current rise rate and amplitude.

[0072] S10: Turn-on current rise curve characteristic analysis. Analyze the shape, rise rate, and peak current of the current rise curve to determine the differences in the turn-on current characteristics of the chips.

[0073] S11: Turn-on current rise curve sorting criteria. If the current rise curves of multiple chips differ significantly, it indicates that their current change characteristics during the turn-on process are different, which may lead to current differences between parallel branches. Chips are sorted based on the consistency of their current rise curves, selecting chips with consistent current rise curve characteristics and assigning these chips to the same group of parallel branches.

[0074] Step 4: Calculation and Weighted Sorting of Switching Loss Difference Coefficient. When sorting by turn-on current and turn-off voltage curves, it may be impossible to achieve perfect consistency between the two. Therefore, a method for calculating the difference coefficient can be designed, using weighted calculations to balance the impact of switching losses and ensure optimal chip sorting results. Figure 6 This is a flowchart of the calculation and weighted sorting of switching loss difference coefficients according to an optional embodiment of the present invention, such as... Figure 6 As shown, the specific process may include:

[0075] S12: Difference Coefficient Calculation. For each chip's turn-on current rise curve and turn-off voltage rise curve, calculate their difference coefficients compared to other chips. The smaller the difference coefficient, the closer the turn-on current and turn-off current are during the switching process.

[0076] S13: Weighting coefficient setting. A weighted calculation method can be designed, assigning equal weights (0.5) to the difference coefficients of the turn-on current rise curve and the turn-off voltage rise curve. This means that the impact of both on switching losses is considered equally important.

[0077] S14: Calculate the switching loss difference coefficient. The difference coefficients of the two are weighted and calculated to obtain the switching loss difference coefficient for each chip.

[0078] S15: Select the optimal chip. Select the chip with the smallest switching loss difference coefficient for parallel connection. By selecting the chip with the smallest loss difference coefficient, the switching losses of the parallel chips can be minimized, achieving system switching loss balance.

[0079] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0080] Through the above description of the embodiments, those skilled in the art can clearly understand that the transistor selection method for balancing losses according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0081] According to embodiments of the present invention, a transistor selection apparatus for implementing the above-described transistor selection method for equalizing losses is also provided. Figure 7 This is a structural block diagram of a transistor selection device for balancing losses provided in an embodiment of the present invention, such as... Figure 7 As shown, the transistor selection device for balancing losses includes: an acquisition module 71, a traversal module 72, a determination module 73, and a selection module 74. The transistor selection device for balancing losses will be described below.

[0082] The acquisition module 71 is used to acquire multiple first rise times corresponding to multiple transistors, multiple second rise times corresponding to multiple transistors, and the target number of transistors for parallel circuits. The first rise time is the time required for the drain-source voltage of the transistor to rise to the corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to the corresponding preset current measurement point during the turn-on process.

[0083] The traversal module 72, connected to the acquisition module 71, is used to select a target number of transistors from multiple transistors, traverse all selection combinations, and obtain multiple transistor parallel groups.

[0084] The determination module 73, connected to the traversal module 72, is used to determine the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors. The average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding transistor parallel group.

[0085] Selection module 74, connected to determination module 73, is used to select multiple transistors in a parallel group of transistors whose average difference coefficient meets a preset condition as multiple target transistors, wherein the multiple target transistors are used in a parallel circuit.

[0086] It should be noted that the acquisition module 71, traversal module 72, determination module 73, and selection module 74 mentioned above correspond to steps S201 to S204 in the embodiments. Multiple modules implement the same instances and application scenarios as their corresponding steps, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules, as part of the device, can run on the computer terminal 10 provided in the embodiments.

[0087] Embodiments of the present invention may provide a computer device. Optionally, in this embodiment, the computer device may be located in at least one of a plurality of network devices in a computer network. The computer device includes a memory and a processor.

[0088] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the transistor selection method and apparatus for balancing losses in this embodiment of the invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the aforementioned transistor selection method for balancing losses. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0089] The processor can invoke information and application programs stored in memory via a transmission device to perform the following steps: acquiring multiple first rise times corresponding to multiple transistors, multiple second rise times corresponding to multiple transistors, and a target number of transistors for parallel circuits, wherein the first rise time is the time required for the drain-source voltage of a transistor to rise to a corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to a corresponding preset current measurement point during the turn-on process; selecting the target number of transistors from the multiple transistors, traversing all selection combinations to obtain multiple transistor parallel groups; determining the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to the multiple transistors, wherein the average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding transistor parallel group; and selecting multiple transistors in the transistor parallel groups whose average difference coefficients meet preset conditions as multiple target transistors, wherein the multiple target transistors are used in parallel circuits.

[0090] Optionally, the processor may also execute program code with the following steps: obtaining multiple first rise times corresponding to each of the multiple transistors, including: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions corresponding to each of the multiple transistors; simulating the turn-off process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curve between the drain-source voltage and time of the multiple transistors during the turn-off process, wherein the preset test circuit has a symmetrical structure; and determining the multiple first rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset voltage measurement points.

[0091] Optionally, the processor may also execute program code for the following steps: obtaining multiple second rise times corresponding to each of the multiple transistors, including: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions corresponding to each of the multiple transistors; simulating the turn-on process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curve of the current flowing through the transistors versus time during the turn-on process, wherein the preset test circuit has a symmetrical structure; and determining the multiple second rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset current measurement points.

[0092] Optionally, the processor may also execute program code with the following steps: determining the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, wherein the average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding parallel group, including: determining the total difference coefficient between any two transistors in the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, wherein the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors; calculating the average value of the multiple total difference coefficients corresponding to each of the multiple transistor parallel groups, and using the average value as the average difference coefficient.

[0093] Optionally, the processor may also execute program code with the following steps: determining the total difference coefficient between any two transistors in the parallel group of multiple transistors based on the multiple first rise times and the multiple second rise times corresponding to each of the multiple transistors, wherein the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors, including: determining the first difference coefficient between any two transistors in the parallel group of multiple transistors based on the multiple first rise times, wherein the first difference coefficient characterizes the difference in the turn-off characteristics between the two transistors; determining the second difference coefficient between any two transistors in the parallel group of multiple transistors based on the multiple second rise times, wherein the second difference coefficient characterizes the difference in the turn-on characteristics between the two transistors; and weighting the multiple first difference coefficients with the corresponding multiple second difference coefficients based on preset weights to obtain the total difference coefficient between any two transistors in the parallel group of multiple transistors.

[0094] Optionally, the processor may also execute program code with the following steps: determining a first difference coefficient between any two transistors in a plurality of parallel transistor groups based on multiple first rise times, wherein the step of calculating the first difference coefficient between the first transistor and the second transistor is as follows, wherein the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the first rise times of the first transistor and the second transistor at multiple preset voltage measurement points; determining an average time difference based on the difference; and determining the first difference coefficient between the first transistor and the second transistor based on the average time difference.

[0095] Optionally, the processor may also execute program code with the following steps: determining a second difference coefficient between any two transistors in a plurality of parallel transistor groups based on a plurality of second rise times, wherein the step of calculating the second difference coefficient between the first transistor and the second transistor is as follows, wherein the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the second rise times corresponding to the first transistor and the second transistor at a plurality of preset current measurement points; determining the average time difference based on the difference; and determining the second difference coefficient between the first transistor and the second transistor based on the average time difference.

[0096] The present invention provides a transistor selection method for balancing losses. By acquiring multiple first rise times and multiple second rise times corresponding to each of multiple transistors, as well as the target number of transistors for parallel circuits, where the first rise time is the time required for the drain-source voltage of the transistor to rise to the corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to the corresponding preset current measurement point during the turn-on process; selecting the target number of transistors from the multiple transistors, and iterating through all selected combinations to obtain multiple transistor parallel groups; determining the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, where the average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding transistor parallel group; and selecting multiple transistors in the transistor parallel group whose average difference coefficient meets the preset condition as multiple target transistors, where the multiple target transistors are used in the parallel circuit, thereby achieving the purpose of selecting the transistor combination with the lowest switching loss when connected in parallel, thus realizing the technical effect of improving system efficiency and reducing the risk of thermal failure, and thus solving the technical problems of high complexity and poor dynamic response of the current switching loss equalization control technology for transistors used in parallel circuits.

[0097] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a non-volatile storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0098] Embodiments of the present invention also provide a non-volatile storage medium. Optionally, in this embodiment, the aforementioned non-volatile storage medium can be used to store the program code executed by the transistor selection method for balancing losses provided in the above embodiments.

[0099] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a group of computer terminals in a computer network, or in any mobile terminal in a group of mobile terminals.

[0100] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: obtaining multiple first rise times corresponding to multiple transistors, multiple second rise times corresponding to multiple transistors, and a target number of transistors for parallel circuits, wherein the first rise time is the time required for the drain-source voltage of the transistor to rise to the corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to the corresponding preset current measurement point during the turn-on process; selecting the target number of transistors from the multiple transistors, traversing all selection combinations to obtain multiple transistor parallel groups; determining the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to the multiple transistors, wherein the average difference coefficient characterizes the average difference degree of turn-on and turn-off characteristics among the multiple transistors in the corresponding transistor parallel group; and selecting multiple transistors in the transistor parallel group whose average difference coefficient meets the preset condition as multiple target transistors, wherein the multiple target transistors are used in parallel circuits.

[0101] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: obtaining multiple first rise times corresponding to each of the multiple transistors, including: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions corresponding to each of the multiple transistors; simulating the turn-off process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curve between the drain-source voltage and time of the multiple transistors during the turn-off process, wherein the preset test circuit has a symmetrical structure; and determining the multiple first rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset voltage measurement points.

[0102] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: obtaining multiple second rise times corresponding to each of the multiple transistors, including: generating multiple double-pulse signals based on a signal generator, wherein the amplitude, time interval, and duration of each of the multiple double-pulse signals are matched one-to-one with the operating conditions corresponding to each of the multiple transistors; simulating the turn-on process of the multiple transistors based on a preset test circuit and the multiple double-pulse signals, and determining the relationship curve of the current flowing through the transistors versus time during the turn-on process, wherein the preset test circuit has a symmetrical structure; and determining the multiple second rise times corresponding to each of the multiple transistors based on the relationship curves corresponding to each of the multiple transistors and multiple preset current measurement points.

[0103] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: determining the average difference coefficient corresponding to each of the multiple parallel transistor groups based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, wherein the average difference coefficient characterizes the average difference in the turn-on and turn-off characteristics among the multiple transistors in the corresponding parallel transistor group, including: determining the total difference coefficient between any two transistors in the multiple parallel transistor group based on the multiple first rise times and multiple second rise times corresponding to each of the multiple transistors, wherein the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors; calculating the average value of the multiple total difference coefficients corresponding to each of the multiple parallel transistor groups, and using the average value as the average difference coefficient.

[0104] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: determining the total difference coefficient between any two transistors in a parallel group of multiple transistors based on the multiple first rise times and the multiple second rise times corresponding to each of the multiple transistors, wherein the total difference coefficient characterizes the total difference in the turn-on and turn-off characteristics between the two transistors, including: determining the first difference coefficient between any two transistors in a parallel group of multiple transistors based on the multiple first rise times, wherein the first difference coefficient characterizes the difference in the turn-off characteristics between the two transistors; determining the second difference coefficient between any two transistors in a parallel group of multiple transistors based on the multiple second rise times, wherein the second difference coefficient characterizes the difference in the turn-on characteristics between the two transistors; and weighting the multiple first difference coefficients with the corresponding multiple second difference coefficients based on preset weights to obtain the total difference coefficient between any two transistors in a parallel group of multiple transistors.

[0105] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: determining a first difference coefficient between any two transistors in a plurality of parallel transistor groups based on a plurality of first rise times, wherein the step of calculating the first difference coefficient between the first transistor and the second transistor is as follows, wherein the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the first rise times corresponding to the first transistor and the second transistor at a plurality of preset voltage measurement points; determining an average time difference based on the difference; and determining the first difference coefficient between the first transistor and the second transistor based on the average time difference.

[0106] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: determining a second difference coefficient between any two transistors in a plurality of parallel transistor groups based on a plurality of second rise times, wherein the step of calculating the second difference coefficient between the first transistor and the second transistor is as follows, wherein the first transistor and the second transistor are any two transistors in any group of parallel transistor groups, including: calculating the difference between the second rise times corresponding to the first transistor and the second transistor at a plurality of preset current measurement points; determining an average time difference based on the difference; and determining the second difference coefficient between the first transistor and the second transistor based on the average time difference.

[0107] Embodiments of the present invention also provide a computer program product, including a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, it can perform the following: obtaining multiple first rise times corresponding to multiple transistors, multiple second rise times corresponding to multiple transistors, and a target number of transistors for parallel circuits, wherein the first rise time is the time required for the drain-source voltage of the transistor to rise to a corresponding preset voltage measurement point during the turn-off process, and the second rise time is the time required for the current flowing through the transistor to rise to a corresponding preset current measurement point during the turn-on process; selecting the target number of transistors from the multiple transistors, traversing all selected combinations to obtain multiple transistor parallel groups; determining the average difference coefficient corresponding to each of the multiple transistor parallel groups based on the multiple first rise times and multiple second rise times corresponding to the multiple transistors, wherein the average difference coefficient characterizes the average difference degree of turn-on and turn-off characteristics among the multiple transistors in the corresponding transistor parallel group; and selecting multiple transistors in the transistor parallel groups whose average difference coefficients meet preset conditions as multiple target transistors, wherein the multiple target transistors are used in parallel circuits.

[0108] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0109] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0110] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0111] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0112] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0113] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0114] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A transistor selection method for equalizing losses, characterized by, The method comprises the following steps: obtaining a plurality of first rise times corresponding to a plurality of transistors respectively, a plurality of second rise times corresponding to the plurality of transistors respectively, and a target number of transistors for a parallel circuit, wherein the first rise time is a time required for a drain-source voltage of a transistor to rise to a corresponding preset voltage measurement point during a turn-off process, and the second rise time is a time required for a current flowing through the transistor to rise to a corresponding preset current measurement point during a turn-on process; selecting the target number of transistors from the plurality of transistors, and traversing all selected combinations to obtain a plurality of parallel groups of transistors; determining an average difference coefficient corresponding to each of the plurality of parallel groups of transistors based on the plurality of first rise times corresponding to the plurality of transistors respectively and the plurality of second rise times corresponding to the plurality of transistors respectively, wherein the average difference coefficient represents an average difference degree of turn-on and turn-off characteristics between the plurality of transistors in the corresponding parallel group of transistors; taking the plurality of transistors in a parallel group of transistors whose average difference coefficient meets a preset condition as a plurality of target transistors, wherein the plurality of target transistors are used for the parallel circuit; wherein the determining of the average difference coefficient corresponding to each of the plurality of parallel groups of transistors based on the plurality of first rise times corresponding to the plurality of transistors respectively and the plurality of second rise times corresponding to the plurality of transistors respectively comprises: determining a first difference coefficient between any two transistors in the plurality of parallel groups of transistors respectively based on the plurality of first rise times, wherein the first difference coefficient represents a difference degree of turn-off characteristics between the two transistors; determining a second difference coefficient between any two transistors in the plurality of parallel groups of transistors respectively based on the plurality of second rise times, wherein the second difference coefficient represents a difference degree of turn-on characteristics between the two transistors; weighting and adding the plurality of first difference coefficients and the corresponding plurality of second difference coefficients respectively based on a preset weight to obtain a total difference coefficient between any two transistors in the plurality of parallel groups of transistors; and calculating an average value of the plurality of total difference coefficients corresponding to the plurality of parallel groups of transistors respectively, and taking the average value as the average difference coefficient; The first difference coefficient between the first transistor and the second transistor is calculated as follows: the first transistor and the second transistor are any two transistors in any one of the plurality of parallel groups of transistors, and the calculation comprises: calculating a difference value between the first rise time corresponding to the first transistor and the second rise time corresponding to the second transistor at a plurality of preset voltage measurement points; determining an average time difference based on the difference value; and determining the first difference coefficient between the first transistor and the second transistor according to the average time difference. The step of calculating the second difference coefficient between the first transistor and the second transistor, the first transistor and the second transistor being any two transistors in any one of the plurality of parallel transistor groups, comprises: calculating a difference value between the first transistor and the second transistor in the second rising time corresponding to a plurality of preset current measurement points; determining an average time difference based on the difference value; and determining the second difference coefficient between the first transistor and the second transistor according to the average time difference.

2. The method of claim 1, wherein, The method further comprises: generating a plurality of double-pulse signals based on a signal generator, wherein the amplitude, time interval and duration of each of the plurality of double-pulse signals are matched with the working conditions of the plurality of transistors one by one; simulating the turn-off process of the plurality of transistors based on the plurality of double-pulse signals and a preset test circuit to determine the relationship curve between the drain-source voltage and the time of the plurality of transistors in the turn-off process, wherein the structure of the preset test circuit is a symmetrical structure; determining the plurality of first rising times of the plurality of transistors based on the relationship curve corresponding to each of the plurality of transistors and a plurality of preset voltage measurement points.

3. The method of claim 1, wherein, The method further comprises: generating a plurality of double-pulse signals based on a signal generator, wherein the amplitude, time interval and duration of each of the plurality of double-pulse signals are matched with the working conditions of the plurality of transistors one by one; simulating the turn-on process of the plurality of transistors based on the plurality of double-pulse signals and a preset test circuit to determine the relationship curve between the current flowing through the transistor and the time of the plurality of transistors in the turn-on process, wherein the structure of the preset test circuit is a symmetrical structure; determining the plurality of second rising times of the plurality of transistors based on the relationship curve corresponding to each of the plurality of transistors and a plurality of preset current measurement points.

4. A transistor selection device for equalizing losses, characterized by The method further comprises: an acquisition module configured to acquire a plurality of first rising times corresponding to the plurality of transistors, a plurality of second rising times corresponding to the plurality of transistors, and a target number of transistors for a parallel circuit, wherein the first rising time is the time required for the drain-source voltage of a transistor to rise to a corresponding preset voltage measurement point in a turn-off process, and the second rising time is the time required for the current flowing through the transistor to rise to a corresponding preset current measurement point in a turn-on process; a traversal module configured to select the target number of transistors from the plurality of transistors, traverse all selected combinations, and obtain a plurality of parallel transistor groups; a determination module configured to determine an average difference coefficient corresponding to each of the plurality of parallel transistor groups based on the plurality of first rising times corresponding to the plurality of transistors and the plurality of second rising times corresponding to the plurality of transistors, wherein the average difference coefficient represents the average difference degree of the turn-on and turn-off characteristics between the plurality of transistors in the corresponding parallel transistor group. The selection module is configured to select a plurality of transistors in a parallel transistor group with an average difference coefficient satisfying a preset condition as a plurality of target transistors, wherein the plurality of target transistors are used in a parallel circuit. The determination module is further configured to determine a first difference coefficient between any two transistors in the plurality of parallel transistor groups based on the plurality of first rise times, wherein the first difference coefficient represents a difference degree of turn-off characteristics between the two transistors; determine a second difference coefficient between any two transistors in the plurality of parallel transistor groups based on the plurality of second rise times, wherein the second difference coefficient represents a difference degree of turn-on characteristics between the two transistors; and add the plurality of first difference coefficients and the plurality of second difference coefficients corresponding to the first difference coefficients by weighting based on a preset weight, to obtain a total difference coefficient between any two transistors in the plurality of parallel transistor groups; and calculate an average value of the total difference coefficients corresponding to the plurality of parallel transistor groups respectively, and take the average value as the average difference coefficient. The first difference coefficient between the first transistor and the second transistor is calculated as follows, the first transistor and the second transistor being any two transistors in any one of the plurality of parallel transistor groups, including: calculating a difference value between the first rise times corresponding to the first transistor and the second transistor at a plurality of preset voltage measurement points; determining an average time difference based on the difference value; and determining the first difference coefficient between the first transistor and the second transistor according to the average time difference. The second difference coefficient between the first transistor and the second transistor is calculated as follows, the first transistor and the second transistor being any two transistors in any one of the plurality of parallel transistor groups, including: calculating a difference value between the second rise times corresponding to the first transistor and the second transistor at a plurality of preset current measurement points; determining an average time difference based on the difference value; and determining the second difference coefficient between the first transistor and the second transistor according to the average time difference.

5. A non-volatile storage medium, characterized by, The non-volatile storage medium includes a stored program, wherein the program controls a device in which the non-volatile storage medium is located to perform the transistor selection method for balancing loss according to any one of claims 1 to 3 when the program is running.

6. A computer device, comprising: Comprise: a memory and a processor, the memory stores a computer program; the processor is configured to execute the computer program stored in the memory, and the computer program makes the processor execute the transistor selection method for balancing loss according to any one of claims 1 to 3 when running.

7. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the transistor selection method for balancing loss according to any one of claims 1 to 3.

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