High-density bridging packaging methods and packaging structures

Abstract

This application provides a high-density bridging packaging method and packaging structure, relating to the field of semiconductor packaging technology. The high-density bridging packaging method includes providing a carrier having a first chip and a first metal pillar; the first chip and the first metal pillar are disposed on the same side of the carrier and spaced apart from each other. The first chip has a first pad. The first chip has a protective layer with a first groove exposing the first pad. A first molding compound covering the first chip and the first metal pillar is formed on the carrier. A second groove exposing the first pad is formed on the first molding compound. A first conductive pillar electrically connected to the first pad is formed in the second groove. A first wiring layer is formed on the first molding compound; the first wiring layer is electrically connected to the first metal pillar and the first conductive pillar respectively. This avoids voids caused by insufficient filling of the molding compound due to excessively small gaps between the first conductive pillars, and ensures uniform gaps between the first conductive pillars, improving the reliability of the connection with the wiring layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a high-density bridging packaging method and packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, chiplet technology employs a new design approach to package small chips with different functions together, forming a heterogeneous integrated chip package structure. Silicon bridge technology achieves electrical connections between chips by embedding small bridge chips with multiple RDL (redistribution layers) in the substrate, effectively reducing manufacturing costs while maintaining high-density interconnect capabilities. However, during the molding process, if the gaps between the copper pillars of the small bridge chips are too small, it can easily lead to insufficient filling of the molding compound, resulting in voids. Furthermore, thermal stress from molding warpage can cause gap shifts between the copper pillars of the small bridge chips, or between the copper pillars and the metal pillars of the substrate, ultimately affecting the contact area between the subsequent wiring layers and the metal pillars, thus impacting their conductivity. Summary of the Invention

[0003] The purpose of this invention is to provide a high-density bridging packaging method and packaging structure, which can avoid insufficient filling of the molding compound due to excessively small gaps between the first conductive pillars, and prevent voids in the structure. It ensures uniform gaps between the first conductive pillars, improves wiring accuracy, and enhances the conductivity of the wiring layer and the first conductive pillars.

[0004] In a first aspect, the present invention provides a high-density bridging packaging method, comprising:

[0005] A carrier having a first chip and a first metal pillar is provided; wherein the first chip and the first metal pillar are disposed on the same side of the carrier and there is a gap between the first chip and the first metal pillar; the first chip has a first pad.

[0006] The surface of the first chip away from the carrier is provided with a protective layer, and the protective layer has a first groove that exposes the first pad;

[0007] A first molding compound is formed on one side of the carrier having the first chip and the first metal pillar; the first molding compound covers the first chip and the first metal pillar;

[0008] A second groove is formed on the first molding compound to expose the first solder pad;

[0009] A first conductive post electrically connected to the first pad is formed in the second groove;

[0010] A first wiring layer is formed on the first molding compound; the first wiring layer is electrically connected to the first metal pillar and the first conductive pillar, respectively.

[0011] In an optional embodiment, the opening of the second groove is larger than the opening of the first groove.

[0012] In an optional implementation, the step of providing a carrier having a first chip and a first metal pillar includes: providing the first chip;

[0013] The first chip includes a second conductive post, which is connected to the side of the first pad away from the first wiring layer.

[0014] In an optional implementation, the step of providing the first chip further includes:

[0015] An active wiring layer is formed on the first pad; the active wiring layer is electrically connected to the first pad;

[0016] In the step of creating a second groove on the first molding compound to expose the first pad, the second groove exposes the active wiring layer;

[0017] A first conductive post electrically connected to the active wiring layer is formed in the second groove.

[0018] In an optional embodiment, the step of forming a first conductive post electrically connected to the first pad in the second groove includes:

[0019] A first metal layer electrically connected to the first pad is formed in the second groove; the first metal layer covers the surface of the first pad and the surface of the protective layer exposed from the second groove;

[0020] The first conductive pillar is formed on the first metal layer.

[0021] In an optional embodiment, after the step of forming the first wiring layer on the first molding compound, the method further includes:

[0022] Remove the vehicle;

[0023] A second wiring layer is formed on the side of the first encapsulation away from the first wiring layer; the second wiring layer is electrically connected to at least the first metal pillar.

[0024] In an optional embodiment, after the step of forming a first molding compound on the side of the carrier having the first chip and the first metal pillar, the method further includes:

[0025] The first molding compound is ground to make the surface of the first metal pillar flush with the surface of the first molding compound; wherein the height of the first metal pillar is greater than the height of the first chip.

[0026] In an optional embodiment, the step of creating a second groove on the first molding compound to expose the first solder pad includes:

[0027] The second groove is formed using laser grooving.

[0028] Alternatively, the second groove can be formed using an exposure and development method.

[0029] In an optional embodiment, after the step of forming a first molding compound on the side of the carrier having the first chip and the first metal pillar, the method further includes:

[0030] A second photoresist is formed on the first molding compound;

[0031] A third groove is formed on the second photoresist;

[0032] The first pad and the first metal pillar are etched along the third groove to form a fourth groove;

[0033] A third conductive post is formed in the fourth groove; the third conductive post is electrically connected to the first metal post and the first pad respectively.

[0034] Secondly, the present invention provides a packaging structure, comprising:

[0035] A substrate, wherein a first metal pillar is provided through the substrate; a first wiring layer connected to the first metal pillar is provided on one side of the substrate, and a second wiring layer connected to the first metal pillar is provided on the other side;

[0036] A first chip is embedded in the substrate; the first chip has a first pad; a first conductive post is connected to the first pad; the first conductive post is electrically connected to the first wiring layer or the second wiring layer.

[0037] A second conductive post is provided on the side of the first pad away from the first wiring layer; the second conductive post and the second wiring layer are electrically connected.

[0038] In an optional implementation, the first chip is provided with an active wiring layer; the two ends of the active wiring layer are electrically connected to the first pad and the first conductive post, respectively.

[0039] In an optional embodiment, a second pad is provided between the first conductive post and the first wiring layer; and / or, a second pad is provided between the second conductive post and the second wiring layer.

[0040] In an optional embodiment, at least one end of the first metal pillar is provided with a third pad, which is electrically connected to the first wiring layer or the second wiring layer.

[0041] In an optional implementation, a second chip and a second molding compound are also included;

[0042] The second chip is disposed on one side of the first wiring layer and electrically connected to the first wiring layer, and / or the second chip is disposed on one side of the second wiring layer and electrically connected to the second wiring layer;

[0043] The second molding compound encapsulates the second chip.

[0044] In an optional embodiment, the substrate is a first encapsulation body, the thickness of which is less than the thickness of the second encapsulation body.

[0045] The high-density bridging packaging method and packaging structure provided in this invention have the following advantages:

[0046] The high-density bridging packaging method provided in this invention first forms a first molding compound on a carrier, then forms a second groove in the first molding compound, and forms a first conductive post within the second groove. The first molding compound is formed before the first conductive post, which avoids insufficient filling of the molding compound due to excessively small gaps between the first conductive posts, and prevents voids in the first molding compound. Furthermore, the second groove can release molding stress, preventing the first conductive post from being affected by molding thermal stress, ensuring uniform gaps between the first conductive posts, thereby improving wiring accuracy and enhancing the conductivity of the wiring layer and the first conductive post.

[0047] The packaging structure provided in this invention is reliable and not easily delaminated. It can mitigate the impact of warpage on the gap between the first conductive pillars, and offers high wiring accuracy and good conductivity. Attached Figure Description

[0048] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0049] Figure 1 This is one of the first process schematic diagrams of the high-density bridging packaging method provided in the embodiments of the present invention;

[0050] Figure 2This is a schematic diagram of a first structure of the first chip in the high-density bridging packaging method provided in an embodiment of the present invention.

[0051] Figure 3 A second schematic diagram of the first process of the high-density bridging packaging method provided in an embodiment of the present invention;

[0052] Figure 4 for Figure 3 A magnified view of a portion of point A in the middle;

[0053] Figure 5 for Figure 3 A magnified view of a portion of point B in the middle;

[0054] Figure 6 This is the third schematic diagram of the first process of the high-density bridging packaging method provided in the embodiments of the present invention;

[0055] Figure 7 Fourth schematic diagram of the first process of the high-density bridging packaging method provided in the embodiments of the present invention;

[0056] Figure 8 This is one of the second process schematic diagrams of the high-density bridging packaging method provided in the embodiments of the present invention;

[0057] Figure 9 This is a second process schematic diagram of the high-density bridging packaging method provided in the embodiments of the present invention;

[0058] Figure 10 This is a schematic diagram of the third process of the high-density bridging packaging method provided in an embodiment of the present invention.

[0059] Figure 11 This is a process diagram illustrating the structure of mounting a second type of first chip on a carrier in the high-density bridging packaging method provided in an embodiment of the present invention.

[0060] Figure 12 This is a schematic diagram of a second structure of the first chip in the high-density bridging packaging method provided in an embodiment of the present invention.

[0061] Figure 13 This is a schematic diagram of the process for mounting dummy chips in the high-density bridging packaging method provided in this embodiment of the invention;

[0062] Figure 14 A schematic diagram of the structure of a dummy chip in the high-density bridging packaging method provided in this embodiment of the invention;

[0063] Figure 15 This is a schematic diagram of a first type of packaging structure provided in an embodiment of the present invention;

[0064] Figure 16This is a schematic diagram of a second type of packaging structure provided in an embodiment of the present invention;

[0065] Figure 17 This is a schematic diagram of a third type of packaging structure provided in an embodiment of the present invention.

[0066] Icons: 110 - Carrier; 111 - Debonding adhesive layer; 112 - Second metal layer; 113 - First metal pillar; 120 - First chip; 121 - First pad; 122 - Second conductive pillar; 123 - Protective layer; 124 - First groove; 125 - Active wiring layer; 126 - First adhesive layer; 130 - First molding compound; 131 - Second groove; 140 - First conductive pillar; 141 - First metal layer; 150 - First wiring layer; 151 - First dielectric layer; 152 - Second dielectric layer; 15 3-First solder ball; 160-Second chip; 161-Bottom filler; 162-Second molding compound; 170-Second wiring layer; 171-Second solder ball; 181-Second photoresist; 182-Third groove; 183-Fourth groove; 184-Third conductive post; 190-Dummy chip; 191-Connector post; 192-Buffer section; 1921-Connector peripheral wall; 193-Force-bearing membrane; 194-Buffer cavity; 200-Packaging structure; 220-Second pad; 230-Third pad. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0068] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0069] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0070] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0071] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0072] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0073] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0074] The high-density bridging packaging method proposed in this invention can alleviate warping deformation and avoid voids in the structure. It can also ensure uniform gaps between the first conductive pillars on the first chip, improving wiring accuracy and conductivity.

[0075] This high-density bridging packaging method mainly includes the following steps:

[0076] Please combine Figure 1 and Figure 2 S1. A carrier 110 is provided having a first chip 120 and a first metal pillar 113. The first chip 120 and the first metal pillar 113 are located on the same side of the carrier 110, and there is a gap between them. The first chip 120 has a first pad 121. A protective layer 123 is provided on the surface of the first chip 120 away from the carrier 110, and the protective layer 123 has a first groove 124 exposing the first pad 121.

[0077] Optionally, a debonding adhesive layer 111 is coated on the surface of the carrier 110. The debonding adhesive layer 111 can be separated by irradiation with ultraviolet light or laser debonding. A second metal layer 112 is formed on the surface of the debonding adhesive layer 111. The second metal layer 112 can be formed by metal sputtering or other methods, which are not specifically limited here. The second metal layer 112 can be a single layer, such as a titanium layer or a copper layer. The second metal layer 112 can also be a multilayer structure, such as including two layers, a copper layer and a titanium layer, or it can be more than one layer.

[0078] After coating the surface of the second metal layer 112 with a first photoresist using a coating process, a first opening is formed on the first photoresist using an exposure and development method. A first metal pillar 113 is then formed on the first opening using an electroplating process. In this electroplating process, the second metal layer 112 can serve as a seed layer for electroplating. After forming the first metal pillar 113, the first photoresist is removed using a photoresist stripper. This completes the fabrication of the first metal pillar 113.

[0079] Optionally, a first chip 120 is mounted on the carrier 110. The first chip 120 can be adhered to the carrier 110 via a first adhesive layer 126, such as a DAF adhesive layer. The first pad 121 of the first chip 120 faces upward, that is, the first pad 121 is located on the side of the first chip 120 away from the carrier 110. The DAF adhesive layer is cured using a baking process, so that the first chip 120 is fixedly adhered to the carrier 110.

[0080] In this embodiment, the first chip 120 further includes a second conductive post 122 connected to the first pad 121. The second conductive post 122 extends from the first pad 121 to the surface of the first chip 120 away from the first pad 121. In some embodiments, the first pad 121 and the second conductive post 122 can be integrated, that is, the end face of the second conductive post 122 can serve as the first pad 121. In this way, the fabrication process of the first pad 121 can be omitted, the process is simpler, and the production efficiency is higher.

[0081] Optionally, the protective layer 123 may be made of polyimide, benzocyclobutene, silicon carbide, or silicon oxide.

[0082] S2. A first molding compound 130 is formed on one side of the carrier 110 having the first chip 120 and the first metal pillar 113; the first molding compound 130 covers the first chip 120 and the first metal pillar 113. Optionally, the first molding compound 130 is formed on the carrier 110 using injection molding or stencil printing processes.

[0083] Please combine Figures 3 to 5Optionally, the first molding compound 130 can be thinned using mechanical grinding, so that the end face of the first metal pillar 113 is exposed from the surface of the first molding compound 130. That is, the end face of the first metal pillar 113 is flush with the surface of the first molding compound 130. In this embodiment, the height of the first chip 120 is less than the height of the first metal pillar 113. After grinding the first molding compound 130, the first chip 120 is still completely embedded in the first molding compound 130. It is worth noting that thinning the first molding compound 130 can reduce the overall thickness of the first molding compound 130 and also reduce the height of the first metal pillar 113, thereby shortening the electrical connection path in the packaging structure and improving transmission efficiency. Optionally, the height of the first metal pillar 113 is 100 micrometers to 350 micrometers, which is also the thickness of the first molding compound 130 after thinning. Furthermore, thinning the first molding compound 130 shortens the distance between its surface and the first pad 121, thereby reducing the groove depth of the second groove 131 and improving grooving efficiency. If the second groove 131 is grooved using laser technology, a smaller groove depth requires less laser energy, reducing heat radiation and minimizing the thermal impact of laser heat radiation on the first molding compound 130 surrounding the second groove 131, preventing cracking or softening of the first molding compound 130. Optionally, the depth of the second groove 131 can be between 5 micrometers and 50 micrometers.

[0084] S3. A second groove 131 is formed on the first molding compound 130 to expose the first solder pad 121.

[0085] The second groove 131 can be formed on the first molding compound 130 using laser grooving, dry etching, or exposure and development. It should be noted that the opening diameter D1 of the second groove 131 is larger than the opening diameter D2 of the first groove 124. In this embodiment, the opening diameter D2 of the first groove 124 is approximately 5 micrometers to 120 micrometers. Thus, the second groove 131 exposes not only the first pad 121 but also a portion of the protective layer 123.

[0086] S4. A first conductive post 140 is formed in the second groove 131, which is electrically connected to the first pad 121.

[0087] Optionally, a first metal layer 141 electrically connected to the first pad 121 is first formed in the second groove 131. The first metal layer 141 covers the surface of the first pad 121 and the surface of the protective layer 123 exposed from the second groove 131. The first metal layer 141 can be formed by electroplating, sputtering, or chemical plating. It should be noted that, since the protective layer 123 is provided in advance, when preparing the first metal layer 141, the first metal layer 141 can extend from the first pad 121 to the surface of the protective layer 123, thereby improving the adhesion.

[0088] A first conductive pillar 140 is then formed on the first metal layer 141. The first conductive pillar 140 can be prepared by electroplating. The first metal layer 141 can serve as a seed layer for electroplating the first conductive pillar 140, which is beneficial for improving the electroplating quality. The first metal layer 141 can also enhance the bonding force between the first conductive pillar 140 and the first pad 121.

[0089] In this embodiment, the first molding compound 130 is formed before the first conductive post 140, avoiding voids caused by insufficient filling of the first molding compound 130 due to the small gap between the first conductive posts 140, thus improving structural reliability. Furthermore, the design of the first metal layer 141 and the protective layer 123 further enhances structural bonding and reliability. In particular, the protective layer 123 can disperse thermal stress, preventing stress concentration in the connection area between the first pad 121 and the first conductive post 140, significantly improving the resistance to thermal cycling in the connection area, and enhancing the insulation performance around the first pad 121, reducing reliability failures during long-term use.

[0090] Please combine Figure 6 S5. A first wiring layer 150 is formed on the first molding compound 130; the first wiring layer 150 is electrically connected to the first metal pillar 113 and the first conductive pillar 140 respectively.

[0091] Optionally, a first dielectric layer 151 is formed on the first encapsulant 130 using a spin coating process, such as spin coating or spray coating. The material of the first dielectric layer 151 can be polyimide or benzocyclobutene, etc. A photomask with a patterned layer is placed over the first dielectric layer 151, and an exposure and development process is used to form patterned layer openings on the first dielectric layer 151. Metal is then filled into the patterned layer openings using electroplating, sputtering, or chemical plating to form a first wiring layer 150.

[0092] A second dielectric layer 152 is formed on a first dielectric layer 151 using a spin coating or spray coating process. The material of the second dielectric layer 152 includes, but is not limited to, polyimide or benzocyclobutene. A photomask with a patterned layer is placed over the second dielectric layer 152. A first opening is formed on the second dielectric layer 152 using an exposure and development process, exposing the first wiring layer 150. Metal is filled into the first opening using electroplating, sputtering, or chemical plating to form a first solder ball 153. Specifically, metal is first electroplated into the first opening to form a first bump, which is electrically connected to the first wiring layer 150. Optionally, the first bump is a copper pillar. Formic acid is used as a reducing agent, and high temperature and chemical reaction are used to remove oxides from the surface of the first bump, which helps to promote the bonding force between the first bump and the solder. Then, at least one of titanium, titanium-tungsten, nickel, tin-silver, tin-silver-copper, and tin-bismuth is electroplated onto the surface of the first bump to form the first solder ball 153.

[0093] S6, mount the second chip 160.

[0094] Optionally, the second chip 160 is mounted on one side of the second dielectric layer 152 using a hot-press bonding process or a flip-chip mounting process, and the second chip 160 is electrically connected to the first solder ball 153. An underfill adhesive 161 is formed using a dispensing process. The underfill adhesive 161 protects the solder structure at the first solder ball 153. A second molding compound 162 is formed on the second dielectric layer 152 to encapsulate the second chip 160. The thickness of the second molding compound 162 is greater than the thickness of the first molding compound 130, which prevents the first molding compound 130 from warping after the carrier 110 is removed during debonding, thus improving the packaging quality.

[0095] S7. A second wiring layer 170 is formed on the side of the first molding compound 130 away from the first wiring layer 150. The second wiring layer 170 is electrically connected to at least the first metal post 113.

[0096] Remove the carrier 110. Optionally, the carrier 110 and the first encapsulation body 130 can be separated by irradiating with ultraviolet light to debond them. It should be noted that after removing the carrier 110, the first chip 120 can provide support to prevent the first encapsulation body 130 and the second encapsulation body 162 from warping due to stress contraction after the carrier 110 is removed.

[0097] Please combine Figure 7 The product is flipped so that the second metal layer 112 faces upwards, allowing the second molding compound 162 to provide support. The second metal layer 112 and the DAF adhesive layer on the back of the first chip 120 are removed by grinding, exposing the first metal pillar 113 and the second conductive pillar 122 on the surface of the first molding compound 130, both on the same plane. It is easy to understand that during the removal of the DAF adhesive layer, the first molding compound 130 is also thinned by grinding, and the first metal pillar 113 is also subject to some grinding. The grinding process changes the surface roughness of the first molding compound 130, thereby improving the adhesion between the second wiring layer 170 and the first metal pillar 113 and the second conductive pillar 122, as well as improving the adhesion between the first molding compound 130 and the dielectric layer.

[0098] A third dielectric layer, a second wiring layer 170, a fourth dielectric layer, and a second solder ball 171 are formed on the side of the first molding compound 130 away from the first wiring layer 150. The process steps are similar to those in step S5 described above, and will not be repeated here.

[0099] Optionally, the second wiring layer 170 is electrically connected to the first metal post 113 and the second conductive post 122, respectively.

[0100] S8. Using a cutting process, the packaged product is cut and separated into individual products, completing the manufacturing process.

[0101] It should be noted that in some embodiments, the second chip 160 may also be mounted on one side of the second wiring layer 170, or the second chip 160 may be mounted on one side of the first wiring layer 150 and one side of the second wiring layer 170 respectively, without specific limitations.

[0102] Please combine Figure 8 and Figure 9 Optionally, in some embodiments, after forming the first molding compound 130 in step S2, a second photoresist 181 can be coated on the first molding compound 130, and a third groove 182 can be formed by exposure and development on the second photoresist 181. The first pad 121 and the first metal pillar 113 are etched along the third groove 182 to expose them, forming a fourth groove 183. The opening of the fourth groove 183 is larger than the opening of the first groove 124. The third groove 182 can be formed by dry etching. This improves the grooving accuracy, thereby improving the subsequent wiring accuracy and conductivity.

[0103] A first metal layer 141 is formed within the fourth groove 183, and a third conductive pillar 184 is formed by electroplating metal on the first metal layer 141. The third conductive pillar 184 is electrically connected to the first metal pillar 113 and the first pad 121, respectively. The second photoresist 181 is then removed. Subsequently, the first wiring layer 150 is fabricated, and the process is similar to that described above, so it will not be repeated here.

[0104] Compared with traditional processes, there is no need to grind the first molding compound 130, which can avoid cracks and other phenomena caused by grinding shear force on the first metal pillar 113 and the third conductive pillar 184, thus improving conductivity.

[0105] Please combine Figure 10 In other embodiments, the second groove 131 can be formed directly by exposure development or dry etching on the first molding compound 130. The groove opening size of the second groove 131 is larger than that of the first groove 124. This eliminates the need for coating the second photoresist 181, simplifying the process. It also avoids problems such as residue and incomplete removal of the second photoresist 181. Incomplete removal can lead to uneven wiring layers, affecting the conductivity of the wiring layer.

[0106] The second groove 131 is formed by direct exposure and development or dry etching on the first molding compound 130. The first molding compound 130 can be made of a film, and the molding compound is filled by vacuum lamination, thereby forming the first molding compound 130 on the carrier 110. The material of the first molding compound 130 includes, but is not limited to, high molecular polymer materials such as polyurethane resin, epoxy resin or polyimide.

[0107] Please combine Figure 11 and Figure 12In some embodiments, the first chip 120 in this embodiment includes a first pad 121, an active wiring layer 125, and a second conductive post 122. The second conductive post 122 is connected to the side of the first pad 121 away from the first wiring layer 150.

[0108] Optionally, an active wiring layer 125 is formed on the first pad 121; the active wiring layer 125 is electrically connected to the first pad 121. By setting the active wiring layer 125, the first pad 121 can be redistributed, which helps to increase the gap between the first conductive pillars 140, thereby improving the fluidity and filling properties of the molding compound when forming the first molding compound 130, and avoiding voids caused by insufficient filling.

[0109] In the step of forming the second recess 131 on the first molding compound 130, the second recess 131 exposes the active wiring layer 125. A first conductive post 140 electrically connected to the active wiring layer 125 is formed in the second recess 131. The first chip 120 may be a device such as an inductor, a voltage regulator, a resistor, a capacitor, a transistor, or a diode.

[0110] Of course, in some other embodiments, the active wiring layer 125 in the first chip 120 may be selectively omitted or retained.

[0111] Please combine Figure 13 and Figure 14 In some embodiments, during the step of mounting the first chip 120 to the carrier 110, a dummy chip 190 may be mounted on the carrier 110; the dummy chip 190 is located between the first metal post 113 and the dicing channel, or on the dicing channel. The dummy chip 190 is removed during the later cutting and separation into individual products, without altering the final structure of the product.

[0112] The dummy chip 190 includes a buffer portion 192 and connecting posts 191. The connecting posts 191 are respectively disposed on both sides of the buffer portion 192. One connecting post 191 is attached to a carrier, and the end face of the other connecting post 191 is flush with the end face of the first metal post 113. The buffer portion 192 has a hollow structure, meaning it has a deformation-adaptable buffer cavity 194. The connecting posts 191 can be made of metal or other materials. The buffer portion 192 includes a connecting peripheral wall 1921 and two opposing force-bearing membranes 193, which are respectively connected to both sides of the connecting peripheral wall 1921. Thus, the force-bearing membranes 193 can tear under thermal stress to absorb more thermal stress. Optionally, the product may experience significant thermal stress during the formation of the first molding compound 130 and the second molding compound 162, and after the removal of the carrier 110. In this embodiment, the dummy chip 190 can absorb these thermal stresses, causing more thermal stress to concentrate at the dummy chip 190. When the stress-bearing membrane 193 is torn under thermal stress, the buffer cavity 194 of the buffer portion 192 can provide deformation space to alleviate and release some of the thermal stress, thereby protecting the first metal pillar 113 from deformation or breakage due to stress.

[0113] Please combine Figure 15This invention also provides a packaging structure 200, which can be manufactured using the aforementioned high-density bridging packaging method. The packaging structure 200 includes a substrate and a first chip 120 embedded within the substrate. A first metal pillar 113 penetrating the substrate is provided within the substrate; a first wiring layer 150 connected to the first metal pillar 113 is provided on one side of the substrate, and a second wiring layer 170 connected to the first metal pillar 113 is provided on the other side. The first chip 120 has a first pad 121; a first conductive pillar 140 is connected to the first pad 121; the first conductive pillar 140 and the first wiring layer 150 are electrically connected. A second conductive pillar 122 is connected to the side of the first pad 121 away from the first wiring layer 150. The second conductive pillar 122 is electrically connected to the second wiring layer 170. This achieves both high-density packaging and reduces substrate warpage. The first chip 120 can be an inductor, voltage regulator, resistor, capacitor, transistor, or diode, etc., which facilitates high-density interconnection and the formation of an integrated circuit (IC) package. The first chip 120 serves as the IC chip in the IC package. The IC chip can be a System-on-a-Chip (SoC). The IC chip is electrically coupled to other IC chips and / or other components within the IC package via wiring layers electrically coupled to the substrate. The IC chip can also be electrically coupled to other circuitry outside the IC package via electrical connections through external metal interconnects. For example, one or more embedded capacitors can provide decoupling capacitance for the power distribution network (PDN) within the IC package to reduce current resistance (IR) drop. As another example, the active wiring layer 125 of the embedded capacitor is disposed between the IC chip and the package substrate to minimize the distance between the embedded capacitor and the IC chip. This reduces parasitic inductance in the wiring between the embedded capacitor and the IC chip, thereby reducing IR drop in the PDN and also helps reduce PDN noise.

[0114] Optionally, the first chip 120 has a protective layer 123 on one side where the first pad 121 is located. The protective layer 123 has a first groove 124 exposing the first pad 121. A first conductive post 140 is located in the first groove 124 and electrically connected to the first pad 121. A first metal layer 141 is provided between the first conductive post 140 and the first pad 121. This can improve the reliability of the connection between the first pad 121 and the first conductive post 140, resulting in better bonding and conductivity. The protective layer 123 can disperse thermal stress, avoid stress concentration in the connection area between the first pad 121 and the first conductive post 140, significantly improve the resistance to thermal cycling in the connection area, and improve the insulation performance around the first pad 121, reducing reliability failures during long-term use.

[0115] Please combine Figure 16Optionally, the first chip 120 is provided with an active wiring layer 125; the two ends of the active wiring layer 125 are electrically connected to the first pad 121 and the first conductive post 140, respectively. The design of the active wiring layer 125 can redistribute the pads, increase the gap between the pads, and thus increase the gap between the first conductive posts 140, avoiding bridging short circuits between the first metal post 113 and the active wiring layer 125 during the polishing process. Of course, in some embodiments, the active wiring layer 125 can be directly disposed on the second conductive post 122, omitting the structure of the first pad 121; this is not specifically limited here.

[0116] Please combine Figure 17 Optionally, a second pad 220 is provided between the first conductive post 140 and the first wiring layer 150; and / or, a second pad 220 is provided between the second conductive post 122 and the second wiring layer 170. The second pad 220 can be provided on either side of the first chip 120, or on both sides of the first chip 120, thereby increasing the contact area between the first conductive post 140 and the first wiring layer 150, or increasing the contact area between the second conductive post 122 and the second wiring layer 170, improving conductivity and connection reliability. The cross-sectional dimension of the second pad 220 is greater than or equal to the cross-sectional dimension of the first conductive post 140. If the cross-sectional dimension of the second pad 220 is greater than the cross-sectional dimension of the first conductive post 140, the contact area with the wiring layer can be increased, improving conductivity and connection reliability. If the cross-sectional dimension of the second pad 220 is equal to the cross-sectional dimension of the first conductive post 140, the conductivity of the first conductive post 140 can be increased.

[0117] Optionally, at least one end of the first metal pillar 113 is provided with a third pad 230, which is electrically connected to the first wiring layer 150 or the second wiring layer 170. The third pad 230 can be located on either side of the first metal pillar 113 or on both sides of the first metal pillar 113, thereby increasing the contact area between the first metal pillar 113 and the first wiring layer 150 or the second wiring layer 170, improving conductivity and connection reliability. Similarly, the cross-sectional dimension of the third pad 230 is greater than or equal to the cross-sectional dimension of the first metal pillar 113.

[0118] Optionally, the system also includes a second chip 160 and a second molding compound 162. The second chip 160 is disposed on one side of the first wiring layer 150 and electrically connected to the first wiring layer 150, or the second chip 160 is disposed on one side of the second wiring layer 170 and electrically connected to the second wiring layer 170. Alternatively, the second chip 160 is disposed on both sides of the substrate. The second molding compound 162 covers the second chip 160. This further increases the chip integration density. Optionally, the substrate uses a first molding compound 130, and the thickness of the first molding compound 130 is less than the thickness of the second molding compound 162. This effectively mitigates warpage caused by thermal stress after removing the carrier 110, improving the quality of the package structure 200.

[0119] The high-density bridging packaging method and packaging structure 200 provided in this invention have the following beneficial effects, including:

[0120] The high-density bridging packaging method provided in this embodiment of the invention first forms a first molding compound 130 on a carrier 110, then forms a second groove 131 on the first molding compound 130, and forms a first conductive post 140 within the second groove 131. The first molding compound 130 is formed before the first conductive post 140, which avoids insufficient filling of the molding compound due to excessively small gaps between the first conductive posts 140, and prevents voids in the first molding compound 130. Furthermore, the second groove 131 can release molding stress, preventing the first conductive posts 140 from being affected by molding thermal stress, ensuring uniform gaps between the first conductive posts 140, thereby improving wiring accuracy and enhancing the conductivity of the wiring layer and the first conductive post 140.

[0121] The packaging structure 200 provided in this embodiment of the invention is reliable and not easily delaminated. It can mitigate the impact of warpage on the gap of the first conductive post 140, has high wiring accuracy, and good conductivity. Furthermore, its compact structure facilitates high-density integrated packaging.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A high-density bridge package method, characterized by, The application relates to a manufacturing method of a chip package. The application provides a carrier with a first chip and a first metal column; wherein the first chip and the first metal column are arranged on the same side of the carrier, and the first chip and the first metal column are spaced apart; the first chip is provided with a first pad; The first chip is provided with a protective layer away from the side surface of the carrier; the protective layer is provided with a first groove exposing the first pad; A first plastic package is formed on the side of the carrier with the first chip and the first metal column; the first plastic package covers the first chip and the first metal column; A second groove exposing the first pad is formed on the first plastic package; A first conductive column electrically connected with the first pad is formed in the second groove; A first wiring layer is formed on the first plastic package; the first wiring layer is electrically connected with the first metal column and the first conductive column respectively.

2. The high-density bridge package method of claim 1, wherein, The opening diameter of the second groove is larger than the opening diameter of the first groove.

3. The high-density bridge package method of claim 1, wherein, In the step of providing the carrier with the first chip and the first metal column, the first chip is provided. The first chip comprises a second conductive column connected with the first pad away from the first wiring layer.

4. The high-density bridge package method of claim 3, wherein, The step of providing the first chip further comprises: An active wiring layer is formed on the first pad; the active wiring layer is electrically connected with the first pad; In the step of forming the second groove exposing the first pad on the first plastic package, the second groove exposes the active wiring layer; A first conductive column electrically connected with the active wiring layer is formed in the second groove.

5. The high-density bridge package method of claim 1, wherein, The step of forming the first conductive column electrically connected with the first pad in the second groove comprises: A first metal layer electrically connected with the first pad is formed in the second groove; the first metal layer covers the surface of the first pad and the surface of the protective layer exposed from the second groove; The first conductive column is formed on the first metal layer.

6. The high-density bridge package method of claim 1, wherein, After the step of forming the first wiring layer on the first plastic package, the step further comprises: The carrier is removed; A second wiring layer is formed on the side of the first plastic package away from the first wiring layer; the second wiring layer is electrically connected with at least the first metal column.

7. The high-density bridge package method of claim 1, wherein, After the step of forming the first plastic package on the side of the carrier with the first chip and the first metal column, the step further comprises: The first plastic package is polished so that the surface of the first metal column is flush with the surface of the first plastic package; wherein the height of the first metal column is larger than the height of the first chip.

8. The high-density bridge package method of claim 1, wherein, The step of forming the second groove exposing the first pad on the first plastic package comprises: The second groove is formed by a laser slotting method; Or, the second groove is formed by an exposure and development method.

9. The high-density bridge package method of claim 1, wherein, After the step of forming the first plastic package on the side of the carrier with the first chip and the first metal column, the step further comprises: A second photoresist is formed on the first plastic package; A third groove is formed on the second photoresist; The first pad and the first metal column are etched to expose the first pad and the first metal column along the third groove, and a fourth groove is formed; The first pad and the first metal column are etched to expose the first pad and the first metal column along the third groove, and a fourth groove is formed; A third conductive column is formed in the fourth groove; the third conductive column is electrically connected with the first metal column and the first pad respectively.

10. The high-density bridge package method of claim 1, wherein, Before the step of forming a first plastic package on one side of the carrier with the first chip and the first metal column, the method further comprises: A dummy chip is attached on the carrier; the dummy chip is located between the first metal column and the cutting path, or on the cutting path; The dummy chip comprises a buffer part and connecting columns; the connecting columns are respectively arranged on both sides of the buffer part; one side of the connecting column is attached to the carrier, and the end face of the other side of the connecting column is flush with the end face of the first metal column; the buffer part adopts a hollow structure.

11. The high-density bridge package method of claim 10, wherein, The buffer part comprises a connecting peripheral wall and two layers of stress films arranged oppositely; the two layers of stress films are respectively connected to both sides of the connecting peripheral wall; the stress films can be torn to absorb more thermal stress under the condition of thermal stress.

12. A package structure, characterized by, The packaging structure is made by the high-density bridge connection packaging method of any one of claims 1 to 11, and comprises: a substrate, the substrate is provided with a first metal column penetrating through the substrate; one side of the substrate is provided with a first wiring layer connected with the first metal column, and the other side is provided with a second wiring layer connected with the first metal column; a first chip, the first chip is embedded in the substrate; the first chip is provided with a first pad; the first pad is connected with a first conductive column; the first conductive column is electrically connected with the first wiring layer or the second wiring layer; the first pad is provided with a second conductive column away from one side of the first wiring layer; the second conductive column is electrically connected with the second wiring layer.

13. The package structure of claim 12, wherein, The first chip is provided with an active wiring layer; both ends of the active wiring layer are respectively electrically connected with the first pad and the first conductive column.

14. The package structure of claim 12, wherein, The first conductive column and the first wiring layer are provided with a second pad therebetween; and / or, the second conductive column and the second wiring layer are provided with a second pad therebetween.

15. The package structure of claim 12, wherein, At least one end of the first metal column is provided with a third pad, and the third pad is electrically connected with the first wiring layer or the second wiring layer.

16. The package structure of claim 12, wherein, Further comprising a second chip and a second plastic package; The second chip is arranged on one side of the first wiring layer and electrically connected with the first wiring layer, and / or the second chip is arranged on one side of the second wiring layer and electrically connected with the second wiring layer; The second plastic package covers the second chip.

17. The package structure of claim 16, wherein, The substrate adopts a first plastic package, and the thickness of the first plastic package is less than the thickness of the second plastic package.

18. The package structure of claim 12, wherein, One side of the first chip provided with the first pad is provided with a protective layer, the protective layer is provided with a first groove exposing the first pad; the first conductive column is arranged in the first groove and electrically connected with the first pad.

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