Parallel inverter system and synchronization method thereof

Abstract

The invention relates to the field of parallel inverters, and discloses a parallel inverter system and a synchronization method thereof. The synchronization method of the parallel inverter system comprises the steps that a main inverter generates a synchronization signal and outputs the synchronization signal to a synchronization signal bus through a synchronization signal output port, the synchronization signal is a PWM signal, and the period value of the synchronization signal is a preset output voltage period value; and the slave inverter receives the synchronization signal from the synchronization signal bus through the synchronization signal receiving port, calculates an output voltage period reference according to a first preset jump edge of the synchronization signal, performs output voltage phase synchronization, and performs carrier synchronization according to a second preset jump edge of the synchronization signal. Therefore, output voltage frequency, phase synchronization and carrier synchronization among a plurality of inverters can be realized only by using a single synchronization signal line, interconnection wiring among the inverters can be simplified, and the output voltage frequency, phase synchronization and carrier synchronization multiplex the same synchronization signal in a time division manner, so that time sequence conflicts can be avoided.

Description

Technical Field

[0001] This invention relates to the field of parallel inverters, and more particularly to a parallel inverter system and its synchronization method. Background Technology

[0002] With the development of power electronics technology and the increasing complexity of energy application scenarios, inverters, as the core equipment for converting DC to AC, face increasingly higher requirements in terms of performance and system architecture. Traditional single-unit high-power inverter solutions are gradually showing limitations when dealing with certain critical application scenarios. Inverter parallel technology connects multiple standard power module inverters together in AC to jointly supply power to the load or grid, thereby achieving a smooth expansion of the total system power in an economical and flexible manner.

[0003] To achieve excellent parallel operation performance, it is necessary to ensure the synchronization of the output voltage amplitude, frequency, and phase of each individual inverter in the parallel system, while also suppressing circulating currents between multiple inverters. Existing technology achieves synchronization among multiple inverters by adding two synchronization signals: a power frequency signal and a carrier signal. The power frequency synchronization is used to synchronize the frequency and phase of the inverter outputs, while the carrier synchronization is used to maintain the consistency of the PWM carrier phase among multiple inverters, thereby suppressing high-frequency circulating currents between them. However, this increases the number of interconnecting lines between modules, significantly increasing system complexity and potential failure risks. Summary of the Invention

[0004] The present invention aims to provide a parallel inverter system and its synchronization method, which can solve the problem that the existing parallel inverter system synchronization scheme has a large number of interconnections between modules, thus significantly increasing system complexity and potential failure risks.

[0005] To address the aforementioned technical problems, the first aspect of this invention provides a synchronization method for a parallel inverter system, applicable to a parallel inverter system, wherein the parallel inverter system includes a master inverter and at least one slave inverter connected in parallel with the master inverter, the master inverter and the slave inverter being communicatively connected via a synchronization signal bus; the synchronization method includes: The main inverter generates a synchronization signal and outputs the synchronization signal to the synchronization signal bus through the synchronization signal output port. The synchronization signal is a PWM signal (Pulse Width Modulation), and the period value of the synchronization signal is a preset output voltage period value. The slave inverter receives the synchronization signal from the synchronization signal bus through the synchronization signal receiving port, calculates the output voltage period reference based on the first preset transition edge of the synchronization signal and performs output voltage phase synchronization, and performs carrier synchronization based on the second preset transition edge of the synchronization signal.

[0006] Optionally, the main inverter generates a synchronization signal including: When the synchronization timer value of the main inverter is equal to zero, the first preset transition edge of the synchronization signal is generated. When the synchronization timer value of the main inverter is equal to the synchronization pulse width of the current cycle, a second preset transition edge of the synchronization signal is generated. The synchronization pulse width of the current cycle is calculated as follows: when the synchronization timer value of the main inverter in the current cycle is equal to zero, its carrier timer count value is taken as the second count value. The second count value is subtracted from the preset inverter carrier cycle value by N times. The difference is taken as the synchronization pulse width of the current cycle. N is a positive integer less than the quotient obtained by dividing the synchronization signal cycle value by the preset inverter carrier cycle value.

[0007] Optionally, the first preset transition edge for generating the synchronization signal when the synchronization timer value of the main inverter is equal to zero includes: When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at this time is recorded as the second count value, and the first preset transition edge of the synchronization signal is generated.

[0008] Optionally, when the synchronization timer value of the main inverter is not equal to zero for the first time, the second count value is calculated as follows: take the carrier timer count value when the synchronization timer value of the main inverter in the previous cycle is equal to zero as the first count value, divide the sum of the synchronization signal period value and the first count value by the preset inverter carrier period value, and the remainder is the second count value.

[0009] Optionally, calculating the output voltage period reference based on the first preset transition edge of the synchronization signal includes: The interval between consecutive first preset transition edges of the synchronization signal is captured, and the interval is used as the reference for the output voltage period.

[0010] Optionally, output voltage phase synchronization based on the first preset transition edge of the synchronization signal includes: Phase-locking is performed at the first preset transition edge of the synchronization signal to achieve phase synchronization of the output voltage.

[0011] Optionally, the carrier synchronization based on the second preset transition edge of the synchronization signal includes: Capture the second preset transition edge of the synchronization signal and record the carrier timer count value from the inverter at this time; Determine whether the carrier timer count value of the slave inverter is zero; If the carrier timer count value of the slave inverter is zero, then carrier synchronization is complete; If the carrier timer count value of the slave inverter is not zero, then the carrier timer count value of the slave inverter is used as the carrier phase error of the slave inverter, the carrier phase error is multiplied by the preset adjustment coefficient, and the product is used as the periodic adjustment amount; Determine whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value; If the carrier phase error is greater than or equal to half of the preset inverter carrier period value, then the sum of the preset inverter carrier period value and the period adjustment amount is taken as the carrier period of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal. If the carrier phase error is less than half of the preset inverter carrier period value, then the difference between the preset inverter carrier period value and the period adjustment amount is taken as the carrier period of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal.

[0012] Optionally, before determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value, the method further includes: Determine whether the carrier phase error is less than or equal to the maximum adjustment step size; If the carrier phase error is less than or equal to the maximum adjustment step size, then the step of determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value is executed. If the carrier phase error is greater than the maximum adjustment step size, the maximum adjustment step size is first used as the period adjustment amount, and then the step of determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value is executed.

[0013] Optionally, the first preset transition edge is a rising edge and the second preset transition edge is a falling edge, or the first preset transition edge is a falling edge and the second preset transition edge is a rising edge.

[0014] Accordingly, a second aspect of the present invention also provides a parallel inverter system, the parallel inverter system including a master inverter and at least one slave inverter connected in parallel with the master inverter, the master inverter and the slave inverter being communicatively connected via a synchronization signal bus, for implementing the steps of the synchronization method of the parallel inverter system as described in the first aspect.

[0015] Compared to existing technologies, this invention provides a parallel inverter system and its synchronization method. The synchronization method involves the main inverter generating a synchronization signal and outputting it to a synchronization signal bus via a synchronization signal output port. The synchronization signal is a PWM signal with a preset output voltage period. The slave inverter receives the synchronization signal from the synchronization signal bus via a synchronization signal receiving port, calculates the output voltage period reference based on the first preset transition edge of the synchronization signal, performs output voltage phase synchronization, and performs carrier synchronization based on the second preset transition edge of the synchronization signal. Thus, output voltage frequency, phase, and carrier synchronization among multiple inverters can be achieved using only a single synchronization signal line. This simplifies the interconnection wiring between inverters, reduces communication costs, and, by time-division multiplexing the same synchronization signal for output voltage frequency, phase, and carrier synchronization, avoids timing conflicts and improves the reliability of the parallel inverter system. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a flowchart illustrating a synchronization method for a parallel inverter system provided by the present invention. Figure 2 This is a schematic diagram of the synchronous signal bus structure of a parallel inverter system provided by the present invention; Figure 3 This is a schematic diagram of the process for generating a synchronization signal by a main inverter, provided by the present invention. Figure 4 This is a schematic diagram illustrating the principle of a main inverter generating a synchronization signal, provided by the present invention. Figure 5 This is a schematic diagram illustrating the principle of synchronizing the frequency and phase of the inverter output voltage provided by the present invention. Figure 6 This is a schematic diagram of a process for inverter carrier synchronization provided by the present invention; Figure 7 This is a schematic diagram of an inverter carrier synchronization process provided by the present invention; Figure 8 This is another schematic diagram of the process for inverter carrier synchronization provided by the present invention; Figure 9 This is a schematic diagram of a parallel inverter system provided by the present invention. Detailed Implementation

[0018] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0020] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0021] In one embodiment, the present invention provides a synchronization method for a parallel inverter system, applicable to a parallel inverter system including a master inverter and at least one slave inverter connected in parallel with the master inverter. The master inverter and the slave inverter are communicatively connected via a synchronization signal bus SYN_BUS. Figure 1 As shown, Figure 1 This is a flowchart illustrating a synchronization method for a parallel inverter system provided by the present invention. The synchronization method includes: S1. The main inverter generates a synchronization signal PWMsyn and outputs the synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through the synchronization signal output port SYN_OUT. The synchronization signal PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value. S2. The inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through the synchronization signal receiving port SYN_CAP, calculates the output voltage period reference according to the first preset transition edge of the synchronization signal and performs output voltage phase synchronization, and performs carrier synchronization according to the second preset transition edge of the synchronization signal.

[0022] In this embodiment, considering the problem in the prior art that using two synchronization signals (power frequency and carrier) between inverters to synchronize multiple inverters results in a large number of interconnecting lines between modules, significantly increasing system complexity and potential failure risks, this embodiment provides a synchronization method for a parallel inverter system. The main inverter generates a synchronization signal PWMsyn and outputs it to the synchronization bus SYN_BUS through the synchronization signal output port SYN_OUT. Here, PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value. The slave inverter receives the synchronization signal PWMsyn from the synchronization bus SYN_BUS through the synchronization signal receiving port SYN_CAP, calculates the output voltage period reference based on the first preset transition edge of the synchronization signal, performs output voltage phase synchronization, and performs carrier synchronization based on the second preset transition edge of the synchronization signal. Thus, output voltage frequency, phase, and carrier synchronization among multiple inverters can be achieved using only a single synchronization signal line. This simplifies the interconnection wiring between inverters, saves communication costs between inverters, and the time-division multiplexing of the same synchronization signal for output voltage frequency, phase, and carrier synchronization avoids timing conflicts and improves the reliability of parallel inverter systems.

[0023] The above steps will be described in detail below with reference to specific implementation methods.

[0024] In step S1, the main inverter generates a synchronization signal PWMsyn and outputs the synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through the synchronization signal output port SYN_OUT. The synchronization signal PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value.

[0025] For details, please refer to Figure 2 , Figure 2This is a schematic diagram of the synchronization signal bus structure of a parallel inverter system provided by the present invention. Taking a parallel inverter system comprising three inverters in parallel—INV1# (INV, inverter), INV2#, and INV3#—as an example, inverter INV1# is designated as the master inverter, and inverters INV2# and INV3# as slave inverters. The master inverter outputs a synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through its synchronization signal output port SYN_OUT. The period value Tinv of this synchronization signal is a preset output voltage period value. The synchronization signal PWMsyn is a PWM signal; its first preset transition edge contains output voltage phase information, and its second preset transition edge contains carrier phase information. Therefore, the rising and falling edges of this PWM-type synchronization signal can be used to transmit the phase information of both signals.

[0026] In step S2, the slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through the synchronization signal receiving port SYN_CAP, calculates the output voltage period reference based on the first preset transition edge of the synchronization signal and performs output voltage phase synchronization, and performs carrier synchronization based on the second preset transition edge of the synchronization signal.

[0027] For details, please refer to Figure 2 The inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through its synchronization signal receiving port SYN_CAP. It calculates the output voltage period reference based on the first preset transition edges of the synchronization signal PWMsyn, performs phase synchronization processing on the output voltage based on the first preset transition edge of the synchronization signal, and performs carrier synchronization based on the second preset transition edge of the synchronization signal. Thus, output voltage frequency, phase, and carrier synchronization among multiple inverters can be achieved using only a single synchronization signal line. This simplifies the interconnection wiring between inverters, saves communication costs, and, by time-division multiplexing the same synchronization signal for output voltage frequency, phase, and carrier synchronization, avoids timing conflicts and improves the reliability of the parallel inverter system.

[0028] Optionally, the first preset transition edge is a rising edge and the second preset transition edge is a falling edge, or the first preset transition edge is a falling edge and the second preset transition edge is a rising edge.

[0029] Specifically, the first preset transition edge is a rising edge and the second preset transition edge is a falling edge. That is, the synchronization signal PWMsyn is a high-level synchronization pulse between the first and second preset transition edges. In this case, the rising edge of the synchronization signal PWMsyn contains the output voltage phase information, and the falling edge contains the carrier phase information. Therefore, the phase information of two signals can be transmitted using the rising and falling edges of the same synchronization signal. Alternatively, the first preset transition edge is a falling edge and the second preset transition edge is a rising edge. That is, the synchronization signal PWMsyn is a low-level synchronization pulse between the first and second preset transition edges. In this case, the falling edge of the synchronization signal PWMsyn contains the output voltage phase information, and the rising edge contains the carrier phase information. Similarly, the phase information of two signals can be transmitted using the rising and falling edges of the same synchronization signal.

[0030] In one implementation, please refer to Figure 3 , Figure 3 This is a schematic diagram of a process for generating a synchronization signal by a main inverter according to the present invention. The generation of the synchronization signal PWMsyn by the main inverter specifically includes: S101. When the synchronous timer value of the main inverter is equal to zero, the first preset transition edge of the synchronous signal PWMsyn is generated.

[0031] S102. When the synchronization timer value of the main inverter is equal to the synchronization pulse width Tpulse of the current period, a second preset transition edge of the synchronization signal PWMsyn is generated. The synchronization pulse width Tpulse of the current period is calculated as follows: when the synchronization timer value of the main inverter in the current period is equal to zero, its carrier timer count value is taken as the second count value T2. The second count value T2 is subtracted from the preset inverter carrier period value Tpwm by N times. The difference is taken as the synchronization pulse width Tpulse of the current period. N is a positive integer less than the quotient obtained by dividing the synchronization signal period value Tinv by the preset inverter carrier period value Tpwm.

[0032] In this embodiment, please refer to Figure 4 , Figure 4This is a schematic diagram illustrating the principle of a main inverter generating a synchronization signal according to the present invention. The explanation uses a first preset transition edge as the rising edge, a second preset transition edge as the falling edge, and N equal to 2 as an example. The dashed line represents the synchronization timer value of the main inverter, the solid line represents the carrier timer count value of the main inverter, and PWMsyn is the synchronization signal. Because the synchronization signal period value Tinv is the preset output voltage period value, when the synchronization timer value of the main inverter equals the synchronization signal period value Tinv and returns to zero, the rising edge of the synchronization signal PWMsyn is generated. This allows the preset output voltage period value to be transmitted to the slave inverter through continuous rising edges of the synchronization signal PWMsyn, and also enables the slave inverter to synchronize its output voltage phase based on the phase of the main inverter's output voltage at the time of that rising edge. When the synchronization timer value of the main inverter in the current cycle is equal to zero, its carrier timer count value is taken as the second count value T2. Twm, twice the preset inverter carrier cycle value, is subtracted from the second count value T2, and the difference is taken as the synchronization pulse width Tpulse of the current cycle. When the synchronization timer value of the main inverter is equal to the synchronization pulse width Tpulse of the current cycle, a falling edge of the synchronization signal PWMsyn is generated. This falling edge corresponds to the second zeroing moment of the carrier timer after the synchronization timer value of the main inverter is zeroed. Therefore, the slave inverter can determine whether its carrier phase is synchronized with the main inverter based on whether its carrier timer count value is zero at the falling edge. If it is zero, the slave inverter is carrier synchronized with the main inverter. If it is not zero, the carrier of the slave inverter is adjusted so that its carrier timer count value is zero at the falling edge, thus achieving carrier phase synchronization with the main inverter. In this embodiment, the high-level range of the synchronization signal PWMsyn is [0, Tpulse), and the low-level range is [Tpulse, Tinv]. The value of N is determined by the falling edge of the synchronization signal PWMsyn and the zeroing time of the carrier timer after the synchronization timer value of the main inverter is zeroed. For example, if the falling edge of the synchronization signal PWMsyn corresponds to the second zeroing time of the carrier timer after the synchronization timer value of the main inverter is zeroed, then the value of N is 2. If the falling edge of the synchronization signal PWMsyn corresponds to the fifth zeroing time of the carrier timer after the synchronization timer value of the main inverter is zeroed, then the value of N is 5.

[0033] In one implementation, the first preset transition edge for generating the synchronization signal when the synchronization timer value of the main inverter is equal to zero includes: When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at this time is recorded as the second count value T2, and the first preset transition edge of the synchronization signal is generated.

[0034] In this embodiment, please refer to Figure 4When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter is recorded at this time. The carrier timer count value of the main inverter at this time is used as the second count value T2, and the synchronization pulse width Tpulse of the first synchronization signal cycle is calculated accordingly.

[0035] In one implementation, when the synchronization timer value of the main inverter is not equal to zero for the first time, the second count value T2 is calculated as follows: the carrier timer count value when the synchronization timer value of the main inverter in the previous cycle is equal to zero is taken as the first count value T1, and the sum of the synchronization signal period value Tinv and the first count value T1 is divided by the preset inverter carrier period value Tpwm, and the remainder is the second count value T2.

[0036] In this embodiment, please refer to Figure 4 When the synchronization timer value of the main inverter is not equal to zero for the first time, there will be a carrier timer count value when the synchronization timer value of the main inverter was equal to zero in the previous cycle. This count value is used as the first count value T1. For example, when the synchronization timer value of the main inverter is equal to zero for the second time, there will be a carrier timer count value when the synchronization timer value of the main inverter was equal to zero in the previous cycle (i.e., the first synchronization signal cycle). This count value is used as the first count value T1. The sum of the synchronization signal cycle value Tinv and the first count value T1 is divided by the preset inverter carrier cycle value Tpwm, and the remainder is the second count value T2. This process is repeated to calculate the second count value T2 for each synchronization signal cycle, and the synchronization pulse width Tpulse for each synchronization signal cycle is calculated accordingly.

[0037] In one implementation, calculating the output voltage period reference based on the first preset transition edge of the synchronization signal includes: The interval between consecutive first preset transitions of the synchronization signal PWMsyn is captured, and the interval is used as the reference for the output voltage period.

[0038] In this embodiment, please refer to Figure 5 , Figure 5This is a schematic diagram illustrating the principle of frequency and phase synchronization of inverter output voltage provided by the present invention. Taking a first preset rising edge and a second preset falling edge as an example, the upper part represents the synchronization signal PWMsyn captured by the slave inverter, and the lower part represents the sinusoidal signal generated by the slave inverter based on the captured synchronization signal PWMsyn. Because the synchronization signal period value Tinv is the preset output voltage period value, the master inverter generates the rising edge of the synchronization signal PWMsyn when its synchronization timer value equals the synchronization signal period value Tinv and returns to zero. Therefore, the slave inverter can capture consecutive rising edges of the synchronization signal PWMsyn, calculate the interval time between consecutive rising edges, and use this interval time as the reference for the output voltage period.

[0039] In one embodiment, output voltage phase synchronization based on a first preset transition edge of the synchronization signal includes: Phase-locking is performed at the first preset transition edge of the synchronization signal to achieve phase synchronization of the output voltage.

[0040] In this embodiment, please refer to Figure 5 Because the synchronization signal period value Tinv is the preset output voltage period value, when the main inverter's synchronization timer value equals the synchronization signal period value Tinv and returns to zero, it generates the rising edge of the synchronization signal PWMsyn. Therefore, the slave inverter can synchronize its own output voltage phase based on the phase of the main inverter's output voltage at the rising edge.

[0041] In one implementation, please refer to Figure 6 , Figure 6 This is a schematic diagram of a process for inverter carrier synchronization provided by the present invention. The step of performing carrier synchronization according to the second preset transition edge of the synchronization signal includes: S201. Capture the second preset transition edge of the synchronization signal and record the carrier timer count value Tcarry from the inverter at this time; S202. Determine whether the carrier timer count value Tcarry of the slave inverter is zero; S203. If the carrier timer count value Tcarry of the slave inverter is zero, then carrier synchronization is completed. S204. If the carrier timer count value Tcarry of the slave inverter is not zero, then the carrier timer count value Tcarry of the slave inverter is used as the carrier phase error e of the slave inverter, and the carrier phase error e is multiplied by the preset adjustment coefficient Kp, and the product is used as the periodic adjustment amount ΔTadjust. S205. Determine whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm; S206. If the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm, then the sum of the preset inverter carrier period value Tpwm and the period adjustment amount ΔTadjust is taken as the carrier period Tprd of the slave inverter, and the step of capturing the second preset transition edge of the synchronization signal is returned. S207. If the carrier phase error e is less than half of the preset inverter carrier period value Tpwm, then the difference between the preset inverter carrier period value Tpwm and the period adjustment amount ΔTadjust is taken as the carrier period Tprd of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal.

[0042] In this embodiment, please refer to Figure 4 Because the falling edge of the synchronization signal PWMsyn corresponds exactly to the second zeroing moment of the carrier timer after the synchronization timer value of the main inverter is zeroed, the slave inverter can determine whether its carrier phase is synchronized with the main inverter based on whether its carrier timer count is zero at the falling edge. If it is zero, the slave inverter is carrier synchronized with the main inverter. If it is not zero, the carrier of the slave inverter is adjusted so that its carrier timer count is zero at the falling edge of the synchronization signal PWMsyn, thus achieving carrier phase synchronization with the main inverter. The process of adjusting the carrier from the inverter is as follows: The carrier timer count value Tcarry of the slave inverter is used as the carrier phase error e of the slave inverter. The carrier phase error e is multiplied by a preset adjustment coefficient Kp, and the product is used as the period adjustment amount ΔTadjust. When the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm, the sum of the preset inverter carrier period value Tpwm and the period adjustment amount ΔTadjust is used as the carrier period Tprd of the slave inverter. When the carrier phase error e is less than half of the preset inverter carrier period value Tpwm, the difference between the preset inverter carrier period value Tpwm and the period adjustment amount ΔTadjust is used as the carrier period Tprd of the slave inverter. This process is repeated until the carrier timer count value Tcarry of the slave inverter is zero at the falling edge of the synchronization signal PWMsyn, thus achieving carrier phase synchronization. The value of the preset adjustment coefficient Kp can be determined based on empirical values, pre-calculated experimental values, or estimated values. In this embodiment, its specific value is not limited.

[0043] For example, please refer to Figure 7 , Figure 7This is a schematic diagram of the inverter carrier synchronization process provided by the present invention, wherein the explanation is based on the example of a first preset transition edge being a rising edge and a second preset transition edge being a falling edge. In the figure, the first dashed line from the left indicates that the carrier of the slave inverter and the carrier of the master inverter are not synchronized, and the second dashed line from the left indicates that the carrier synchronization of the master and slave inverters is achieved through gradual dynamic adjustment of the carrier period of the slave inverter.

[0044] In one implementation, please refer to Figure 8 , Figure 8 This is another schematic diagram of the process for inverter carrier synchronization provided by the present invention. Before determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm, the method further includes: S208. Determine whether the carrier phase error e is less than or equal to the maximum adjustment step size ΔTmax; S209. If the carrier phase error e is less than or equal to the maximum adjustment step size ΔTmax, then the step of determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm is executed. S210. If the carrier phase error e is greater than the maximum adjustment step size ΔTmax, then the maximum adjustment step size ΔTmax is first used as the period adjustment amount ΔTadjust, and then the step of determining whether the carrier phase error e is greater than or equal to half of the preset inverter carrier period value Tpwm is executed.

[0045] In this embodiment, by setting a maximum adjustment step size ΔTmax, when the carrier phase error e is greater than the maximum adjustment step size ΔTmax, the maximum adjustment step size ΔTmax is used as the periodic adjustment amount ΔTadjust, so that the adjustment amplitude is not too large each time, ensuring that the parallel inverter system can operate stably during the inverter carrier synchronization process.

[0046] To facilitate understanding of the above-mentioned inventive concept of the present invention, the following description is in conjunction with the appendix. Figures 1-8 Taking a parallel inverter system with an output voltage frequency of 60 Hz, an inverter switching frequency of 10 kHz, and an inverter main control unit clock frequency of 10 MHz as an example, the synchronization method of a parallel inverter system according to the present invention will be described in more detail. The inverter synchronization signal period value Tinv = 166667 (specifically 10 MHz / 60 Hz) is calculated based on the output voltage frequency, inverter switching frequency, and inverter main control unit clock frequency. The preset inverter carrier period value Tpwm = 1000 (specifically 10 MHz / 10 kHz).

[0047] Inverter #1 is designated as the master inverter in the parallel inverter system, and the remaining inverters are designated as slave inverters. If the initial parameter T1 = 200, to prevent the short interval between the synchronization timer and the carrier timer from affecting the slave inverters' capture of the synchronization signal edge, the synchronization pulse width is defined as Tpulse = 2Tpwm - Tx (Tx represents the carrier timer count value corresponding to the master inverter's synchronization timer returning to zero in the current cycle). Therefore, the synchronization pulse width for this cycle is Tpulse = 1800 (specifically, 2Tpwm - Tx = 2Tpwm - 200). Figure 4 We can see that by taking the remainder of (Tinv + T1) / Tpwm, we can calculate T2 = 867. We can further calculate the synchronization pulse width of the next cycle, Tpulse = 1133 (specifically, 2Tpwm - T2 = 2Tpwm - 867).

[0048] The specific process for generating the main inverter synchronization signal is as follows: The main control unit of the INV1# inverter (main inverter) performs the following cyclic operation to generate the synchronization signal PWMsyn: a) When the synchronization timer count of the main control unit returns to zero, the synchronization signal output port SYN_OUT is controlled to output a high level.

[0049] b. When the count value of the synchronization timer reaches the pulse width value Tpulse set for this period (e.g., initial value 1800), the synchronization signal output port SYN_OUT is controlled to output a low level.

[0050] c. When the synchronous timer count returns to zero again, the following operations are performed simultaneously: Control the synchronization signal output port SYN_OUT to output a high level again (i.e., start a new cycle), and update the pulse width: load the synchronization pulse width Tpulse (e.g., 1133) calculated for the next cycle as the pulse width value Tpulse used in the next cycle in step b of this article.

[0051] d. Repeat steps a to c. Through this cyclic process, inverter #1 continuously generates a synchronization signal PWMsyn with a period of Tinv (166667) and a pulse width dynamically updated to Tpulse (e.g., 1800, 1133, ...).

[0052] The process of capturing the synchronization signal from the inverter is as follows: Output voltage frequency and phase synchronization: The continuous rising edges of the synchronization signal PWMsyn are captured from the inverter, and the interval time (166667) between the continuous rising edges is calculated. Dividing the time base clock frequency of the main control unit by the interval time gives a period of 60 Hz. At the same time, phase-locked adjustment is performed on the rising edge moment. When the phase error between the phase-locked phase of the slave inverter and the rising edge phase of the synchronization signal is 0, output voltage phase synchronization is achieved as Figure 5 shown.

[0053] Carrier synchronization control: When the falling edge of the synchronization signal PWMsyn is captured from the inverter, the carrier timer count value Tcarry of the slave inverter is recorded. Define the carrier phase error e = Tcarry, calculate the period adjustment amount ΔTadjust = Kp × e, and define ΔTmax as the maximum adjustment step ΔTmax. When Tcarry >= Tpwm / 2, the carrier period value Tprd of the slave inverter is Tprd = Tpwm + ΔTadjust. When Tcarry < Tpwm / 2, the carrier period value Tprd of the slave inverter is Tprd = Tpwm - ΔTadjust. Dynamically adjust the carrier timer period value Tprd of the slave inverter until Tcarry = 0 to achieve carrier phase synchronization, as Figure 7 shown.

[0054] The synchronization method of the parallel inverter system in this embodiment generates a synchronization signal PWMsyn through the main inverter and outputs the synchronization signal PWMsyn to the synchronization signal bus SYN_BUS through the synchronization signal output port SYN_OUT. Among them, the synchronization signal PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value; the slave inverter receives the synchronization signal PWMsyn from the synchronization signal bus SYN_BUS through the synchronization signal receiving port SYN_CAP, calculates the output voltage period reference according to the first preset transition edge of the synchronization signal and performs output voltage phase synchronization, and performs carrier synchronization according to the second preset transition edge of the synchronization signal. Thus, only by using a single synchronization signal line, output voltage frequency, phase synchronization, and carrier synchronization between multiple inverters can be achieved, which can simplify the interconnection wiring between inverters, save the communication cost between inverters. Moreover, output voltage frequency, phase synchronization, and carrier synchronization multiplex the same synchronization signal分时复用同一同步信号, which can avoid timing conflicts and improve the reliability of the parallel inverter system.

[0055] Based on the same concept, in another embodiment, please refer to Figure 9 , Figure 9This is a schematic diagram of a parallel inverter system provided by the present invention. The parallel inverter system 100 includes one master inverter 110 and two slave inverters 120 as an example for illustration. The present invention also provides a parallel inverter system 100, which includes a master inverter 110 and at least one slave inverter 120 connected in parallel with the master inverter. The master inverter 110 and the slave inverter 120 are communicatively connected via a synchronization signal bus SYN_BUS to implement the steps of the synchronization method for the parallel inverter system described in the above embodiments.

[0056] This embodiment provides a parallel inverter system. The main inverter generates a synchronization signal PWMsyn and outputs it to the synchronization bus SYN_BUS via the synchronization signal output port SYN_OUT. The synchronization signal PWMsyn is a PWM signal, and the synchronization signal period value Tinv is a preset output voltage period value. The slave inverter receives the synchronization signal PWMsyn from the synchronization bus SYN_BUS via the synchronization signal receiving port SYN_CAP. It calculates the output voltage period reference based on the first preset transition edge of the synchronization signal and performs output voltage phase synchronization. It then performs carrier synchronization based on the second preset transition edge of the synchronization signal. Thus, output voltage frequency, phase, and carrier synchronization among multiple inverters can be achieved using only a single synchronization signal line. This simplifies the interconnection wiring between inverters, saves communication costs, and, by time-division multiplexing the same synchronization signal for output voltage frequency, phase, and carrier synchronization, avoids timing conflicts and improves the reliability of the parallel inverter system.

[0057] It should be noted that the above-described parallel inverter system embodiment and the parallel inverter system synchronization method embodiment belong to the same concept. For details of the specific implementation process, please refer to the parallel inverter system synchronization method embodiment. Furthermore, the technical features of the parallel inverter system synchronization method embodiment are all applicable to the above-described parallel inverter system embodiment, and will not be repeated here.

[0058] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0059] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A synchronization method for a parallel inverter system, characterized in that, The parallel inverter system includes a master inverter and at least one slave inverter connected in parallel with the master inverter. The master inverter and the slave inverter are communicatively connected via a synchronization signal bus. The synchronization method includes: The main inverter generates a synchronization signal and outputs the synchronization signal to the synchronization signal bus through the synchronization signal output port. The synchronization signal is a PWM signal, and the period value of the synchronization signal is a preset output voltage period value. The slave inverter receives the synchronization signal from the synchronization signal bus through the synchronization signal receiving port, calculates the output voltage period reference based on the first preset transition edge of the synchronization signal and performs output voltage phase synchronization, and performs carrier synchronization based on the second preset transition edge of the synchronization signal.

2. The synchronization method according to claim 1, characterized in that, The main inverter generates a synchronization signal including: When the synchronization timer value of the main inverter is equal to zero, the first preset transition edge of the synchronization signal is generated. When the synchronization timer value of the main inverter is equal to the synchronization pulse width of the current cycle, a second preset transition edge of the synchronization signal is generated. The synchronization pulse width of the current cycle is calculated as follows: when the synchronization timer value of the main inverter in the current cycle is equal to zero, its carrier timer count value is taken as the second count value. The second count value is subtracted from the preset inverter carrier cycle value by N times. The difference is taken as the synchronization pulse width of the current cycle. N is a positive integer less than the quotient obtained by dividing the synchronization signal cycle value by the preset inverter carrier cycle value.

3. The synchronization method according to claim 2, characterized in that, The first preset transition edge for generating the synchronization signal when the synchronization timer value of the main inverter is equal to zero includes: When the synchronization timer value of the main inverter is equal to zero for the first time, the carrier timer count value of the main inverter at this time is recorded as the second count value, and the first preset transition edge of the synchronization signal is generated.

4. The synchronization method according to claim 2, characterized in that, When the synchronization timer value of the main inverter is not equal to zero for the first time, the second count value is calculated as follows: take the carrier timer count value when the synchronization timer value of the main inverter in the previous cycle is equal to zero as the first count value, divide the sum of the synchronization signal period value and the first count value by the preset inverter carrier period value, and the remainder is the second count value.

5. The synchronization method according to any one of claims 2-4, characterized in that, The output voltage period reference is calculated based on the first preset transition edge of the synchronization signal, including: The interval between consecutive first preset transition edges of the synchronization signal is captured, and the interval is used as the reference for the output voltage period.

6. The synchronization method according to any one of claims 2-4, characterized in that, The output voltage phase synchronization based on the first preset transition edge of the synchronization signal includes: Phase-locking is performed at the first preset transition edge of the synchronization signal to achieve phase synchronization of the output voltage.

7. The synchronization method according to any one of claims 2-4, characterized in that, The carrier synchronization based on the second preset transition edge of the synchronization signal includes: Capture the second preset transition edge of the synchronization signal and record the carrier timer count value from the inverter at this time; Determine whether the carrier timer count value of the slave inverter is zero; If the carrier timer count value of the slave inverter is zero, then carrier synchronization is complete; If the carrier timer count value of the slave inverter is not zero, then the carrier timer count value of the slave inverter is used as the carrier phase error of the slave inverter, the carrier phase error is multiplied by the preset adjustment coefficient, and the product is used as the periodic adjustment amount; Determine whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value; If the carrier phase error is greater than or equal to half of the preset inverter carrier period value, then the sum of the preset inverter carrier period value and the period adjustment amount is taken as the carrier period of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal. If the carrier phase error is less than half of the preset inverter carrier period value, then the difference between the preset inverter carrier period value and the period adjustment amount is taken as the carrier period of the slave inverter, and the process returns to the step of capturing the second preset transition edge of the synchronization signal.

8. The synchronization method according to claim 7, characterized in that, Before determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value, the method further includes: Determine whether the carrier phase error is less than or equal to the maximum adjustment step size; If the carrier phase error is less than or equal to the maximum adjustment step size, then the step of determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value is executed. If the carrier phase error is greater than the maximum adjustment step size, the maximum adjustment step size is first used as the period adjustment amount, and then the step of determining whether the carrier phase error is greater than or equal to half of the preset inverter carrier period value is executed.

9. The synchronization method according to any one of claims 1-4, characterized in that, The first preset transition edge is a rising edge and the second preset transition edge is a falling edge, or the first preset transition edge is a falling edge and the second preset transition edge is a rising edge.

10. A parallel inverter system, characterized in that, The parallel inverter system includes a master inverter and at least one slave inverter connected in parallel with the master inverter. The master inverter and the slave inverter are connected in communication via a synchronization signal bus to implement the synchronization method of the parallel inverter system as described in any one of claims 1-9.

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