A silicon capacitor, a photolithography mask plate and a manufacturing method of a silicon capacitor

Abstract

The application discloses a silicon capacitor, comprising: a groove arranged on a silicon substrate; the groove is used for arranging a capacitor structure; the groove is arranged in the surface direction of the silicon substrate as follows: the groove comprises a plurality of longitudinally distributed first-type grooves and a plurality of transversely distributed second-type grooves; wherein, at least part of the first-type grooves and part of the second-type grooves are connected through. The silicon capacitor provided by the application has the advantages of large effective area, high yield, simple structure and reliable performance, and can achieve a larger capacitance value.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a silicon capacitor, a photomask, and a method for manufacturing a silicon capacitor. Background Technology

[0002] With rapid economic development and accelerated localization of semiconductor production, silicon capacitors are widely used in communications, automotive electronics, medical equipment, and aerospace due to their advantages such as high stability, excellent high-frequency performance, and compatibility with integrated circuit processes, resulting in continuous growth in market demand.

[0003] With limited chip size, maximizing the effective area of ​​the device's electrodes becomes crucial for improving capacitor performance. Existing technologies propose a regularly arranged trench structure to increase the effective area of ​​the electrodes, thereby increasing the capacitance value. To further improve the capacitance value, the trench depth needs to be increased; however, this approach requires thicker epitaxial silicon wafers, leading to increased costs.

[0004] Therefore, there is an urgent need for a silicon capacitor that has a high capacitance value at a given cost. Summary of the Invention

[0005] This application provides a silicon capacitor and its manufacturing method to solve the problem of low substrate area utilization in the manufacturing process of silicon capacitors in the prior art. The specific solution is as follows:

[0006] In a first aspect, this application provides a silicon capacitor, comprising:

[0007] Trenches formed on a silicon substrate;

[0008] The trench is used to set up the capacitor structure;

[0009] The trenches are arranged on the surface of the silicon substrate as follows:

[0010] The trenches include a plurality of longitudinally distributed first-type trenches and a plurality of transversely distributed second-type trenches;

[0011] Among them, at least some of the first type of trenches and some of the second type of trenches are connected through each other.

[0012] Optionally, the at least a portion of the first type of trench and a portion of the second type of trench are connected in a continuous manner, including:

[0013] The tail end of the first type of trench is connected to the head end of the second type of trench, and the tail end of the second type of trench is connected to the head end of another first type of trench.

[0014] Optionally, the at least a portion of the first type of trench and a portion of the second type of trench are connected in a continuous manner, including:

[0015] The tail end of the second type of trench is connected to the head end of the first type of trench.

[0016] Optionally, the at least a portion of the first type of trench and a portion of the second type of trench are connected in a continuous manner, including:

[0017] The ends of a plurality of second-type grooves are connected to a first-type groove.

[0018] Alternatively, the ends of a plurality of first-type grooves are connected through a second-type groove.

[0019] Optionally, the tail end of the first type of trench is connected to the head end of the second type of trench, and the tail end of the second type of trench is connected to the head end of another first type of trench, including: the trench combination formed by the connected first type of trench and the second type of trench, with its two ends respectively close to the edge of the lateral edge of the capacitor region of the silicon substrate.

[0020] Optionally, the tail end of the second type of trench is connected to the head end of the first type of trench, including: in the trench combination formed by the first type of trench and the second type of trench connected through, the head end of the second type of trench is close to the edge of the longitudinal side of the capacitor region, and the tail end of the first type of trench is close to the edge of the transverse side of the capacitor region.

[0021] Optionally, the ends of the plurality of second-type trenches are connected through a first-type trench, or the ends of the plurality of first-type trenches are connected through a second-type trench, including: the trench combination formed by the above-mentioned through connection method occupies the corner position of the capacitor region.

[0022] Optionally, each adjacent trench has an equal spacing distance.

[0023] Optionally, the ends of the trenches are 0.5 micrometers away from each edge of the silicon substrate.

[0024] Optionally, the aspect ratio of the trench is 9:1.

[0025] Optionally, the lengths of the first type of trench and the second type of trench are 4-17 micrometers.

[0026] Optionally, the point where the first type of trench and the second type of trench connect is a rounded corner.

[0027] Optionally, the ends of the first type of groove and the second type of groove are rounded.

[0028] Optionally, the total length of the first type of trenches is equal to the total length of the second type of trenches.

[0029] Secondly, this application also provides a photomask, on which a pattern for forming a silicon capacitor is disposed, the pattern including:

[0030] A plurality of vertically distributed first-class strip patterns and a plurality of horizontally distributed second-class strip patterns;

[0031] Among them, at least some of the first type of strip patterns and some of the second type of strip patterns are connected through each other; the area where the pattern is located is a light-transmitting area or a light-blocking area.

[0032] Optionally, the connection between at least a portion of the first type of strip pattern and a portion of the second type of strip pattern includes: the tail end of the first type of strip pattern is connected to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected to the head end of another first type of strip pattern.

[0033] And / or,

[0034] The at least part of the first type of strip pattern and part of the second type of strip pattern are connected through each other, including: the tail end of the second type of strip pattern is connected through to the head end of the first type of strip pattern.

[0035] And / or,

[0036] The at least some of the first type of strip pattern and some of the second type of strip pattern are connected through each other, including: the ends of a plurality of second type of strip patterns are connected through each other to a first type of strip pattern, or the ends of a plurality of first type of strip patterns are connected through each second type of strip pattern.

[0037] Optionally, the tail end of the first type of strip pattern is connected to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected to the head end of another first type of strip pattern, including: forming a strip-shaped zigzag pattern formed by the first type of strip pattern and the second type of strip pattern that are connected through each other, with both ends close to the edge of the longitudinal edge of the photomask.

[0038] And / or, the tail end of the second type of strip pattern is connected through to the head end of the first type of strip pattern, including: forming a pattern combination of the first type of strip pattern and the second type of strip pattern that are connected through, wherein the head end of the second type of strip pattern is close to the edge of the longitudinal edge of the photomask, and the tail end of the first type of strip pattern is close to the edge of the transverse edge of the photomask.

[0039] And / or, the ends of the plurality of second-type strip patterns are connected through to a first-type strip pattern, or the ends of the plurality of first-type strip patterns are connected through to a second-type strip pattern, including: the pattern combination formed by the above-mentioned through connection method occupies the corner position of the photomask.

[0040] Optionally, each adjacent strip has an equal spacing.

[0041] Thirdly, this application also provides a method for manufacturing a silicon capacitor, comprising:

[0042] Provide silicon substrates;

[0043] A trench pattern is formed on a mask layer of the silicon substrate using a photolithography process. The trench pattern includes a plurality of vertically distributed first-type strip patterns and a plurality of horizontally distributed second-type strip patterns; wherein at least some of the first-type strip patterns and some of the second-type strip patterns are connected through each other.

[0044] Etching forms trenches corresponding to the trench pattern, including first-type trenches corresponding to the first type of strip pattern and second-type trenches corresponding to the second type of strip pattern; and a capacitor structure is formed in the trenches.

[0045] Compared with the prior art, this application has the following advantages:

[0046] The silicon capacitor provided in this application includes trenches formed on a silicon substrate; the trenches are used to form a capacitor structure; the trenches are arranged on the surface of the silicon substrate as follows: the trenches include a plurality of longitudinally distributed first-type trenches and a plurality of laterally distributed second-type trenches; wherein at least some of the first-type trenches and some of the second-type trenches are connected through each other.

[0047] The silicon capacitor provided in this application includes trenches formed on a silicon substrate. While maintaining the same substrate dimensions, this increases the surface area of ​​the capacitor, thereby increasing the capacitance. Furthermore, because these trenches have varying shapes but are arranged in a relatively balanced and symmetrical manner, they can resist the effects of etching and stress generated during the deposition process, effectively preventing chip cracking and resulting in a high yield rate. In addition, this trench arrangement ensures that the trench ends are as close as possible to the edge of the capacitor region, maximizing the utilization of the capacitor area. The through-type trench structure simplifies the electrode filling process and improves the reliability of the silicon capacitor. Therefore, the silicon capacitor provided in this application can provide a larger usable area while maintaining the same trench depth. With the same area, it offers higher capacitor redundancy and has the advantages of simple structure and high reliability. Attached Figure Description

[0048] Figure 1This is a top view of the trench of a conventional silicon capacitor provided by existing technology.

[0049] Figure 2 This is a top view of the trench of a capacitor region of a silicon capacitor provided in an embodiment of this application.

[0050] Figure 3 This is a top view of the trench of another capacitance region of the silicon capacitor provided in the embodiments of this application.

[0051] Figure 4 This is a flowchart of a method for manufacturing a silicon capacitor provided in an embodiment of this application.

[0052] Figure 5 This is a schematic diagram of the structure of the silicon capacitor in the manufacturing method of the silicon capacitor provided in this application embodiment. Detailed Implementation

[0053] To enable those skilled in the art to better understand the technical solutions of this application, the application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. However, this application can be implemented in many other ways different from those described below. Therefore, based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0054] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described in this application. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0055] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0056] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0057] To facilitate understanding of the various embodiments of this application, the application background of the embodiments will be explained.

[0058] With sustained economic growth and the deep integration of industrialization and informatization, the process of domestic production of semiconductors is accelerating. Silicon capacitors, due to their high stability, excellent high-frequency characteristics, and compatibility with integrated circuit processes, are widely used in communications, automotive electronics, medical equipment, smartphones, and aerospace, leading to continuously expanding market demand.

[0059] Existing silicon capacitors mostly employ planar or regular trench structures, limiting the effective electrode area and resulting in low capacitance density. Furthermore, in actual manufacturing, densely packed deep trenches generate significant stress, easily causing wafer edge deformation and affecting yield. Therefore, current technologies increase electrode area by deepening the trenches. However, this method has significant problems: First, deeper trenches require thicker epitaxial wafers, leading to increased procurement costs; second, the increased trench aspect ratio places higher demands on etching uniformity and the filling capacity of the dielectric and electrode materials, significantly increasing process difficulty; in addition, thicker epitaxial layers introduce greater wafer stress, causing increased edge curling of the epitaxial wafer, affecting subsequent processing yield and device reliability.

[0060] For example, please refer to the conventional silicon capacitor in the existing technology. Figure 1 , Figure 1 This is a top view of a conventional capacitor trench in the prior art. The conventional capacitor includes four regions, and the upper surface of the silicon substrate in each region is provided with strip trenches arranged in a horizontal or vertical array. Each trench has equal length and width, and the arrangement direction of the strip trenches in any adjacent region is perpendicular to each other. This arrangement helps to balance stress in different directions, but because the trench design is the same, it is limited by the etching effect, resulting in a low area utilization rate.

[0061] To address the above issues, this application provides a silicon capacitor and its manufacturing method. The aim is to effectively increase the effective surface area of ​​the capacitor within a given area by optimizing the trench structure design, without increasing production and procurement costs, thereby achieving a higher capacitance value and superior performance compared to conventional designs.

[0062] Example 1

[0063] Please refer to Figure 2 and Figure 3 Understand the silicon capacitor of Embodiment 1 of this application. Figure 2 A top view of a trench in a capacitance region of a silicon capacitor provided in an embodiment of this application. Figure 3 A top view of the trench in another capacitance region of the silicon capacitor provided in an embodiment of this application.

[0064] Embodiment 1 of this application provides a silicon capacitor, comprising:

[0065] Trenches formed on a silicon substrate;

[0066] The trench is used to set up the capacitor structure;

[0067] The trenches are arranged on the surface of the silicon substrate as follows:

[0068] The trench includes a plurality of longitudinally distributed first-type trenches 21 and a plurality of transversely distributed second-type trenches 22;

[0069] Among them, at least some of the first type of trenches and some of the second type of trenches are connected through each other.

[0070] The capacitor structure in this embodiment is formed on a silicon substrate. A silicon substrate is a basic silicon wafer used to manufacture semiconductor devices, possessing good crystal integrity and mechanical support capabilities, and is a fundamental material for integrated circuit manufacturing. In some embodiments, the silicon substrate may further include an epitaxially grown single-crystal silicon layer (i.e., an epitaxial substrate) to optimize the electrical performance of the device, such as increasing breakdown voltage or reducing parasitic effects.

[0071] On the surface of a silicon substrate, one or more capacitor regions are defined through dielectric deposition and patterning processes. Each capacitor region contains multiple trenches arranged in a specific shape and manner. The trench cross-section can be rectangular, trapezoidal, or U-shaped, and the depth is typically between hundreds of nanometers and several micrometers. The inner wall surface of the trenches can be further grown or deposited with a dielectric layer and covered with a conductive material as the lower electrode, thereby expanding the effective area of ​​the capacitor from a two-dimensional plane to a three-dimensional space, increasing the effective electrode area and improving the capacitance density per unit area.

[0072] A capacitor formed on a silicon substrate includes at least a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is typically formed on the silicon substrate or an epitaxial layer and can be doped polycrystalline silicon or a metal (such as TiN or TaSi2). The dielectric layer is located above the lower electrode. In one embodiment, the dielectric layer is an insulating dielectric layer with alternating "ONO" layers, specifically including a first silicon oxide film, a silicon nitride film, and a second silicon oxide film (ONO) stacked sequentially from bottom to top. The upper electrode is typically a metal (such as Al, Cu, or W) or polycrystalline silicon, covering the dielectric layer and capacitively coupled to the lower electrode. In another embodiment, the capacitor may include one or more capacitor regions, each containing a three-dimensional structure composed of multiple alternating layers of lower electrodes and dielectric layers to form a multi-level capacitor structure in the vertical direction. Each lower electrode layer and its overlying dielectric layer constitute a unit cell. Finally, a continuous conductive layer is formed above the uppermost dielectric layer as a common upper electrode. The upper electrode and all lower electrodes are capacitively coupled through their respective dielectric layers, thereby increasing the total capacitance density per unit area. To increase capacitance while balancing stacking effect and deposition difficulty, the number of alternating stacking operations can be 4-6 times.

[0073] Taking a square capacitor region as an example, a trench can be a single vertically distributed first-type trench 21, or a single horizontally distributed second-type trench 22. A trench can also be a combination of trenches formed by connecting first-type and second-type trenches. This trench configuration allows for the balanced arrangement of not entirely identical trenches on the silicon substrate, maximizing the area occupancy of the trenches on the silicon substrate, thereby increasing the area available for subsequent capacitor placement.

[0074] The following uses the top-left corner of the capacitor region in the figure as the origin of the coordinate system, with the rightward direction as the positive x-axis (horizontal direction) and the downward direction as the positive y-axis (vertical direction). The morphology and arrangement of the trenches are described in detail below:

[0075] The top view of both types of grooves is nearly elongated. Type I grooves are parallel to the y-axis, and their length is not fixed. Figure 2 In the capacitor region, the lower end of the first type of trench is the tail end, and the upper end is the head end; the second type of trench is a trench parallel to the x-axis, and its length is not fixed. Figure 2 In the capacitor region, the right end of the second type of trench is the tail end of the second type of trench, and the left end is the head end; the tail end and the head end can be collectively referred to as the end.

[0076] In one embodiment, the at least part of the first type of trench and part of the second type of trench are connected through each other, including: the tail end of the first type of trench is connected through to the head end of the second type of trench, and the tail end of the second type of trench is connected through to the head end of another first type of trench. Figure 2 The groove 24 in the text refers to a groove formed by connecting two first-type grooves and one second-type groove end to end. In one embodiment, it can also be... Figure 3 In the middle, there is a groove 23 consisting of two second-class grooves and one first-class groove connected end to end.

[0077] In one embodiment, the at least part of the first type of trench and the part of the second type of trench are connected through each other, including: the tail end of the second type of trench is connected through to the head end of the first type of trench. Figure 2 The groove 25 in the text is a groove in which a second type of groove and a first type of groove are connected head to head. Figure 3 The groove 25 in the middle is also a groove in which a second type of groove and a first type of groove are connected head to head.

[0078] In one embodiment, the at least some of the first type of trenches and some of the second type of trenches are connected through each other, including: the ends of a plurality of second type of trenches are connected through to a first type of trench, or the ends of a plurality of first type of trenches are connected through to a second type of trench. Figure 2 Groove 26 in the text is a groove that connects three second-type grooves and one first-type groove. Figure 3 The groove 27 in the text is a groove in which three first-class grooves and one second-class groove are connected.

[0079] The width and depth of each of the above trenches are preferably equal, with a depth-to-width ratio of 9:1. For example, the width is 1 micrometer and the depth is 9 micrometers.

[0080] In one implementation, the lengths of the first type of trench and the second type of trench in each trench may not be the same, but their respective lengths may range from 4 to 17 micrometers (inclusive of the end value).

[0081] In one embodiment, the position where the first type of trench and the second type of trench in each trench are connected can be a right angle or a rounded corner.

[0082] In one embodiment, the ends of the first type of groove and the second type of groove are right-angled or rounded.

[0083] In order to balance stress and resist the effects of etching, in one embodiment, the total length of the first type of trenches forming trenches in a capacitor region is equal to the total length of the second type of trenches.

[0084] To better balance stress, different types of grooves should be arranged in a certain way. The following arrangement is an optimal arrangement of grooves.

[0085] In one embodiment, the tail end of the first type of trench is connected through to the head end of the second type of trench, and the tail end of the second type of trench is connected through to the head end of another first type of trench, including: the trench combination formed by the connected first type of trench and the second type of trench, with its two ends respectively close to the edge of the lateral edge of the capacitor region of the silicon substrate. Figure 2 In the trench 24, the upper end of the first first-type trench constituting the trench 24 is designated as the beginning end of the trench 24, and the lower end of the second first-type trench constituting the trench 24 is designated as the end end of the trench 24; the beginning end of the trench 24 is close to the top edge of the capacitor region, and the end end of the trench 24 is close to the bottom edge of the capacitor region; for example... Figure 3 Correspondingly, the left end of the first second type of trench constituting the trench 23 is taken as the beginning end of the trench 23, and the right end of the second second type of trench constituting the trench 23 is taken as the end end of the trench 23; the beginning end of the trench 23 is close to the left side of the capacitor region, and the end end of the trench 23 is close to the right side of the capacitor region.

[0086] In one embodiment, the tail end of the second type of trench is connected through to the head end of the first type of trench, including: in the trench combination formed by the connected first type of trench and the second type of trench, the head end of the second type of trench is located near the edge of the longitudinal side of the capacitor region, and the tail end of the first type of trench is located near the edge of the transverse side of the capacitor region. Figure 2 In the trench 25, the lower end of the first type of trench constituting the trench 25 is designated as the tail end of the trench 25, and the left end of the second type of trench constituting the trench 25 is designated as the head end of the trench 25; the head end of the trench 25 is close to the left side of the capacitor region, and the tail end is close to the bottom edge of the capacitor region; for example... Figure 3 In the groove 28, the lower end of the first type of groove in the groove 28 is taken as the first end of the groove 28, and the right end of the second type of groove in the groove 28 is taken as the tail end of the groove 28; the first end of the groove 28 is close to the bottom edge of the capacitor region, and the tail end of the groove 28 is close to the right side of the capacitor region.

[0087] In one embodiment, the ends of the plurality of second-type trenches are connected through a first-type trench, or the ends of the plurality of first-type trenches are connected through a second-type trench, including: the trench combination formed by the above-described through connection method occupies a corner position of the capacitor region. For example, Figure 2 The trench 26 in the middle is formed by the tail ends of three second-type trenches connecting to the side of one first-type trench. The beginning ends of the three second-type trenches in the trench 26 are aligned and close to the left side of the capacitor region. The entire trench 26 is located at the lower left corner of the capacitor region. For example... Figure 3The groove 27 is formed by the tail ends of three first-type grooves and the lower edge of a second-type groove. The tail ends of the three first-type grooves of the groove 27 are aligned and close to the bottom edge of the capacitor region. The entire groove 27 is located in the lower right corner of the capacitor region.

[0088] In one embodiment, each adjacent trench has an equal spacing distance, which may be 1 micrometer.

[0089] In one embodiment, the ends of the trenches near any one of the top, bottom, left, and right edges of the capacitor region are aligned, such as... Figure 2 Since the beginnings of the trenches 24, 25, and 26 shown are all close to the left side of the capacitor region, the beginnings of the trenches 24, 25, and 26 should be equidistant from the left side of the capacitor region, which can be reduced to 0.5 micrometers.

[0090] To intuitively demonstrate the significant improvement in area utilization of the silicon capacitor provided in this application embodiment, specific data are used as examples below. The data below are intended to illustrate the size relationship and are not unique.

[0091] Assuming the square side length of the capacitor region is 18 micrometers and the trench depth is the same in both methods, no increase in surface area due to depth is introduced.

[0092] Provided by existing technology Figure 1 In the silicon capacitor, the spacing between the trenches is 1 micrometer, the width of each trench is 1 micrometer, the length is 7 micrometers, the distance between adjacent positions of the transverse trench and the longitudinal trench is 2 micrometers, and the distance from the trench end to the four edges of the capacitor region is 1 micrometer. The surface area of ​​each region obtained in this way is 42 square micrometers, and the total surface area is 168 square micrometers.

[0093] In comparison, in the silicon capacitor provided in this application embodiment, the spacing between trenches is also 1 micrometer, the width of each trench is 1 micrometer, and the distance from the end of the trench to the four edges of the capacitor region is 0.5 micrometers. The surface area obtained in this way can reach 259 square micrometers, which is much larger than the surface area in the prior art.

[0094] The silicon capacitor provided in this application includes trenches formed on a silicon substrate. These trenches are used to form a capacitor structure. The trenches are arranged on the surface of the silicon substrate as follows: the trenches include a plurality of longitudinally distributed first-type trenches and a plurality of laterally distributed second-type trenches; wherein at least some of the first-type trenches and some of the second-type trenches are connected through each other. Using the silicon capacitor provided in this application, the distance from the end of the trench to each edge of the silicon substrate can be reduced to 0.5 micrometers, which is smaller than the distance in the prior art, directly increasing the area utilization of the silicon substrate surface. This trench configuration increases the utilization of the horizontal surface of the silicon substrate. For trenches of the same depth, the trenches in this application have a larger accommodating area, providing more contact area for the silicon capacitor, thereby increasing the capacitance of the silicon capacitor. Correspondingly, if the required area or capacitance value provided by the trench is the same, the depth of the trenches in this application is shallower than that in the prior art. This characteristic facilitates trench etching and subsequent filling processes. Therefore, the process of this silicon capacitor is simple, and obviously, the silicon capacitor provided in this application has a higher yield.

[0095] Example 2

[0096] The second embodiment of this application also provides a photolithographic mask corresponding to the silicon capacitor embodiment provided in the first embodiment. Since the embodiment of the photolithographic mask is basically similar to the structural embodiment, it is described simply. For details of the related technical features and their effects, please refer to the corresponding description of the silicon capacitor embodiment provided above.

[0097] In this embodiment, the photolithography mask can be used in the process of manufacturing silicon capacitors. The trenches formed by the photolithography mask serve as the physical basis for the subsequent capacitor structure. Its sidewalls and bottom will be used to deposit the lower electrode, dielectric layer and upper electrode to realize a high-density three-dimensional integrated capacitor device.

[0098] The photomask includes a transparent substrate and a patterned light-shielding layer formed thereon. The light-shielding layer constitutes the graphic structure of the mask and is used to control the exposure area. By adjusting the geometry, size, and arrangement density of the light-transmitting / light-shielding areas on the mask, the width, spacing, and aspect ratio of the trenches can be precisely controlled, thereby optimizing the effective surface area and capacitance density of the capacitor.

[0099] The photomask has a pattern for forming a silicon capacitor, the pattern including:

[0100] A plurality of vertically distributed first-class strip patterns and a plurality of horizontally distributed second-class strip patterns;

[0101] Among them, at least some of the first type of strip patterns and some of the second type of strip patterns are connected through each other; the area where the pattern is located is a light-transmitting area or a light-blocking area.

[0102] The pattern on the photomask corresponds to the trenches in the silicon capacitor of Embodiment 1, and the pattern can be used to form the trenches on the silicon capacitor. The first type of vertically distributed strip pattern corresponds to the first type of trench in Embodiment 1, and the second type of horizontally distributed strip pattern corresponds to the second type of trench in Embodiment 1.

[0103] In processes using positive photoresist, the light-transmitting areas correspond to the trench locations to be etched on the silicon substrate. Specifically, light passes through the light-transmitting areas of the photomask, exposing the underlying photoresist. After development, the exposed photoresist is removed, revealing the silicon substrate surface. Trench locations are then formed in the exposed areas using dry etching. Therefore, the light-transmitting areas on the photomask correspond one-to-one with the final trench locations. These light-transmitting areas can be designed with a shape corresponding to the trench shape to match the structural requirements of silicon capacitors. This approach achieves high-precision trench patterning resolution and is suitable for sub-micron level fine structures.

[0104] In processes using negative photoresist, the light-shielding area corresponds to the trench location to be etched on the silicon substrate. After exposure, the negative photoresist undergoes a cross-linking reaction, becoming insoluble in the developer. Therefore, light cannot pass through the light-shielding area of ​​the mask, resulting in the photoresist beneath that area remaining unexposed and being removed during development, thus exposing the silicon substrate. Subsequent etching processes then form trenches in this area. This approach achieves high-precision trench patterning with good adhesion, is suitable for thick photoresist or high aspect ratio structures, and is commonly found in power devices.

[0105] In one embodiment, the photomask further includes alignment marks for high-precision overlay with the previous layer structure on the wafer, ensuring that the trench position is consistent with the overall circuit layout.

[0106] In one embodiment, the at least part of the first type of strip pattern and the part of the second type of strip pattern are connected through to each other, including: the tail end of the first type of strip pattern is connected through to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected through to the head end of another first type of strip pattern.

[0107] And / or,

[0108] The at least part of the first type of strip pattern and part of the second type of strip pattern are connected through each other, including: the tail end of the second type of strip pattern is connected through to the head end of the first type of strip pattern.

[0109] And / or,

[0110] The at least some of the first type of strip pattern and some of the second type of strip pattern are connected through each other, including: the ends of a plurality of second type of strip patterns are connected through each other to a first type of strip pattern, or the ends of a plurality of first type of strip patterns are connected through each second type of strip pattern.

[0111] The adjacent strip patterns on the photomask have equal spacing.

[0112] In one embodiment, the tail end of the first type of strip pattern is connected through to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected through to the head end of another first type of strip pattern, including: forming a strip-shaped zigzag pattern formed by the first type of strip pattern and the second type of strip pattern that are connected through to each other, with both ends close to the edge of the longitudinal edge of the photomask.

[0113] And / or, the tail end of the second type of strip pattern is connected through to the head end of the first type of strip pattern, including: forming a pattern combination of the first type of strip pattern and the second type of strip pattern that are connected through, wherein the head end of the second type of strip pattern is close to the edge of the longitudinal edge of the photomask, and the tail end of the first type of strip pattern is close to the edge of the transverse edge of the photomask.

[0114] And / or, the ends of the plurality of second-type strip patterns are connected through to a first-type strip pattern, or the ends of the plurality of first-type strip patterns are connected through to a second-type strip pattern, including: the pattern combination formed by the above-mentioned through connection method occupies the corner position of the photomask.

[0115] The dimensions of the pattern on the photomask correspond to the dimensions of the target trench. Under ideal conditions, the width, length, and spacing of the light-transmitting or light-blocking areas on the mask are consistent with the top-view dimensions of the trench to be formed. However, in actual manufacturing processes, factors such as optical proximity effects, etching offsets, and process variations must be considered. Therefore, optical proximity correction or dimensional compensation can be performed on the mask pattern to ensure that the actual dimensions of the final trench meet the design specifications.

[0116] The photomask provided in Embodiment 2 of this application has precisely designed geometric shapes and arrangements of light-transmitting or light-shielding regions, enabling accurate control of the position, size, and array density of trenches on the silicon substrate. This ensures the pattern consistency and process repeatability of subsequent capacitor structures. This mask design is applicable to both positive and negative photoresist processes. This dual adaptability enhances process flexibility and can meet the manufacturing requirements of different device structures. By optimizing the pattern arrangement on the mask, a high-density trench structure can be formed within a unit area, significantly increasing the effective electrode surface area of ​​the capacitor and thus improving the capacitance per unit area. Therefore, the photomask provided in this embodiment not only achieves high-precision, high-density patterning of silicon capacitor trenches but also possesses process compatibility and scalability, providing reliable technical support for the large-scale manufacturing of high-performance, three-dimensional integrated silicon capacitors.

[0117] Example 3

[0118] The third embodiment of this application also provides an embodiment of a method for manufacturing a silicon capacitor corresponding to the silicon capacitor provided in the first embodiment. The following description of the method embodiment for manufacturing a silicon capacitor is merely illustrative. For details of the relevant technical features and the effects achieved, please refer to the corresponding description of the silicon capacitor embodiment provided above.

[0119] Please refer to Figure 4 , Figure 4 A flowchart illustrating a method for manufacturing a silicon capacitor as provided in an embodiment of this application.

[0120] The method for manufacturing a silicon capacitor provided in this application includes:

[0121] S401 provides a silicon substrate;

[0122] S402, a trench pattern is formed on the mask layer of the silicon substrate by photolithography. The trench pattern includes a plurality of vertically distributed first-type strip patterns and a plurality of horizontally distributed second-type strip patterns; wherein at least some of the first-type strip patterns and some of the second-type strip patterns are connected through each other.

[0123] S403, etching to form trenches corresponding to the trench pattern, including a first type of trench corresponding to the first type of strip pattern and a second type of trench corresponding to the second type of strip pattern; and forming a capacitor structure in the trenches.

[0124] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of the silicon capacitor in the manufacturing method of the silicon capacitor provided in the embodiments of this application.

[0125] The bottom layer of the silicon capacitor is a highly doped N-type silicon wafer 501, which serves as a low-resistance drain contact layer to provide good electrical contact and a low-resistance path. An epitaxial layer 502 is formed on the top layer. Trenches can be etched to the epitaxial layer 502, and the structure of the silicon capacitor, such as the lower electrode 51, the dielectric layer 52, and the upper electrode 53, is deposited on the epitaxial layer 502.

[0126] The formation of trench patterns on the mask layer of the silicon substrate using photolithography can be achieved as follows: one or more mask layers are sequentially formed on the surface of the epitaxial layer; photoresist is coated on the surface of the mask layers; the photoresist is exposed using the photolithographic mask provided in Example 2, where the light-transmitting or light-blocking areas on the mask correspond to the trenches to be etched. The photoresist in the exposed areas is removed, exposing the surface of the mask layer below, thereby forming a pattern window in the photoresist that matches the target trench. Subsequently, the pattern on the photoresist is transferred to the mask layer below using a dry etching process. For example, a silicon nitride / silicon oxide mask layer is etched using a fluorine-containing gas such as CF4 or CHF3 to form a hard mask pattern composed of SiO2 / Si3N4, the opening area of ​​which corresponds to the top view shape, size, and arrangement of the trenches in the silicon capacitor in Example 1.

[0127] In the preceding steps, a patterned structure corresponding to the target capacitor trenches has been formed on a mask layer on the surface of the silicon substrate using photolithography. Based on this, an etching process is further performed to etch a deep trench structure consistent with the trench pattern into the epitaxial layer of the silicon substrate, providing a physical basis for the subsequent construction of a three-dimensional silicon capacitor. Specifically, dry etching technology is used to directionally etch the exposed silicon areas. The etching gas can be fluorine- or chlorine-containing gases such as SF6, CF4, or Cl2, achieving selective removal of single-crystal silicon through the synergistic effect of physical bombardment and chemical reaction. During etching, the mask layer acts as a hard mask, protecting the silicon surface in non-trench areas from etching. The deep trenches have a rectangular or U-shaped cross-section with a flat bottom, meeting the requirements of subsequent ALD deposition of dielectric layers and electrode filling. The width, spacing, and arrangement of the trenches are precisely controlled by the preceding photolithography pattern. After etching, the residual mask layer is removed, exposing the complete deep trench structure.

[0128] In one embodiment, a stacked capacitor structure can be formed on a silicon substrate. For example, a first lower electrode layer and a first dielectric layer are deposited in a trench, and the lower electrode layer and dielectric layer are deposited alternately in sequence, with a total of 4-6 depositions. An upper electrode layer is then deposited on the top dielectric layer. This stacked structure does not excessively increase the processing difficulty and can improve the capacitance. The dielectric layer includes a first silicon oxide film, a silicon nitride film, and a second silicon oxide film (ONO) stacked sequentially from bottom to top. The upper electrode layer is preferably made of metal or AlSiCu. In one embodiment, the lower electrode layer is deposited using an ALD-CVD (Atomic Layer Deposition-Chemical Vapor Deposition) process, and the deposition thickness of the lower electrode layer can be 20 nanometers.

[0129] The silicon capacitor manufacturing method provided in this application provides an irregular trench structure formed by etching in a silicon substrate. The shape and arrangement of the trenches improve the surface area utilization of the silicon substrate. Electrodes and dielectric layers are constructed on the sides and bottom of the trenches, significantly increasing the effective area of ​​the electrodes and breaking through the limitations of capacitor area in the prior art. When the required area or capacitance value is fixed, the trenches of the silicon capacitor obtained by this manufacturing method are shallower. This characteristic is beneficial to the etching of the trenches and subsequent filling processes. Therefore, the process of this silicon capacitor is simple. Obviously, the silicon capacitor manufacturing method provided in this application can achieve a higher yield.

[0130] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0131] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0132] 1. Computer-readable media includes both permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined in this application, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0133] 2. Those skilled in the art will understand that embodiments of this application can provide methods, systems, or computer program products. Therefore, embodiments of this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0134] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A silicon capacitor, characterized in that, include: Trenches formed on a silicon substrate; The trench is used to set up the capacitor structure; The trenches are arranged on the surface of the silicon substrate as follows: The trenches include a plurality of longitudinally distributed first-type trenches and a plurality of transversely distributed second-type trenches; Wherein, at least a portion of the first type of trench and a portion of the second type of trench are connected through each other, including: The tail end of the first type of trench is connected to the head end of the second type of trench, and the tail end of the second type of trench is connected to the head end of another first type of trench. The ends of a plurality of second-type trenches are connected through a first-type trench, or the ends of a plurality of first-type trenches are connected through a second-type trench, including: the trench combination formed by the above-mentioned through connection method occupies a corner position of the capacitor region.

2. The silicon capacitor according to claim 1, characterized in that, The at least part of the first type of trench and part of the second type of trench are connected through each other, including: The tail end of the second type of trench is connected to the head end of the first type of trench.

3. The silicon capacitor according to claim 1, characterized in that, The tail end of the first type of trench is connected to the head end of the second type of trench, and the tail end of the second type of trench is connected to the head end of another first type of trench, including: the trench combination formed by the connected first type of trench and the second type of trench, with its two ends respectively close to the edge of the lateral edge of the capacitor region of the silicon substrate.

4. The silicon capacitor according to claim 2, characterized in that, The tail end of the second type of trench is connected to the head end of the first type of trench, including: in the trench combination formed by the first type of trench and the second type of trench connected through, the head end of the second type of trench is close to the edge of the longitudinal side of the capacitor region, and the tail end of the first type of trench is close to the edge of the transverse side of the capacitor region.

5. The silicon capacitor according to claim 1, characterized in that, Each adjacent trench has an equal spacing.

6. The silicon capacitor according to claim 1, characterized in that, The ends of the trenches are 0.5 micrometers away from each edge of the silicon substrate.

7. The silicon capacitor according to claim 1, characterized in that, The trench has a depth-to-width ratio of 9:

1.

8. The silicon capacitor according to claim 1, characterized in that, The lengths of the first type of trench and the second type of trench are 4-17 micrometers.

9. The silicon capacitor according to claim 1, characterized in that, The joint between the first type of trench and the second type of trench is rounded.

10. The silicon capacitor according to claim 1, characterized in that, The ends of the first type of groove and the second type of groove are rounded.

11. The silicon capacitor according to claim 1, characterized in that, The total length of the first type of trenches is equal to the total length of the second type of trenches.

12. A photolithographic mask, characterized in that, The photomask has a pattern for forming a silicon capacitor, the pattern including: A plurality of vertically distributed first-class strip patterns and a plurality of horizontally distributed second-class strip patterns; Among them, at least some of the first type of strip patterns and some of the second type of strip patterns are connected through each other; the area where the pattern is located is a light-transmitting area or a light-blocking area; The at least some of the first type of strip pattern and some of the second type of strip pattern are connected through each other, including: The tail end of the first type of strip pattern is connected to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected to the head end of another first type of strip pattern. The ends of a plurality of second-type strip patterns are connected through to a first-type strip pattern, or the ends of a plurality of first-type strip patterns are connected through to a second-type strip pattern, including: the pattern combination formed by the above-mentioned through connection method occupies the corner position of the photomask.

13. The photomask according to claim 12, characterized in that, The at least some of the first type of strip pattern and some of the second type of strip pattern are connected through each other, including: The connection between at least a portion of the first type of strip pattern and a portion of the second type of strip pattern includes: the tail end of the second type of strip pattern being connected to the head end of the first type of strip pattern.

14. The photomask according to claim 13, characterized in that, The tail end of the first type of strip pattern is connected to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected to the head end of another first type of strip pattern, including: forming a strip-shaped zigzag pattern formed by the first type of strip pattern and the second type of strip pattern that are connected through each other, with both ends close to the edge of the longitudinal edge of the photomask. And / or, the tail end of the second type of strip pattern is connected through to the head end of the first type of strip pattern, including: forming a pattern combination of the first type of strip pattern and the second type of strip pattern that are connected through, wherein the head end of the second type of strip pattern is close to the edge of the longitudinal edge of the photomask, and the tail end of the first type of strip pattern is close to the edge of the transverse edge of the photomask.

15. The photomask according to claim 14, characterized in that, Each adjacent bar has an equal spacing.

16. A method for manufacturing a silicon capacitor, characterized in that, include: Provide silicon substrates; A trench pattern is formed on a mask layer of the silicon substrate using a photolithography process. The trench pattern includes a plurality of vertically distributed first-type strip patterns and a plurality of horizontally distributed second-type strip patterns; wherein at least some of the first-type strip patterns and some of the second-type strip patterns are connected through each other. Etching forms trenches corresponding to the trench pattern, including first-type trenches corresponding to the first type of strip pattern and second-type trenches corresponding to the second type of strip pattern; and a capacitor structure is formed in the trenches; Wherein, the at least a portion of the first type of strip pattern and a portion of the second type of strip pattern are connected through each other, including: The tail end of the first type of strip pattern is connected to the head end of the second type of strip pattern, and the tail end of the second type of strip pattern is connected to the head end of another first type of strip pattern. The ends of a plurality of second-type strip patterns are connected through to a first-type strip pattern, or the ends of a plurality of first-type strip patterns are connected through to a second-type strip pattern, including: the pattern combination formed by the above-mentioned through connection method occupies the corner position of the capacitor region.

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