Method, device, equipment, medium and product for quality inspection of printed circuit board

Abstract

The application discloses a printed circuit board quality inspection method, device, equipment, medium and product, relates to the double data rate hardware design technical field, and comprises the following steps: automatically analyzing a design file to replace manual sampling inspection, realizing batch and rapid signal line and target connecting piece identification, and improving detection efficiency; after extracting signal line information and identifying the target connecting piece, obtaining design parameters thereof and performing full-parameter verification based on a reference rule, so that key parameters are ensured not to be missed; automatically performing design file analysis, parameter extraction and rule judgment throughout the whole process, so that missing problems caused by fatigue and negligence during manual one-by-one auditing can be avoided; and through automatic comparison of the target connecting piece design parameters and the reference rule, efficient and accurate comparison is realized, manual comparison is replaced, and the result accuracy is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of double data rate hardware design, and particularly relates to a printed circuit board quality inspection method, device, equipment, medium and product. BACKGROUND

[0002] In the field of double data rate (DDR) hardware design, the tabbed routing (Tab) as a key structure to make up for the insufficient length of the wire, undertakes the core functions of signal shielding, enhanced grounding and optimized impedance matching, and directly determines the performance of DDR signal transmission.

[0003] However, in actual design, problems such as deviation of the number of Tab copper skins, size inconsistency, unreasonable layout and the like often occur, which threatens the normal operation of the hardware. The traditional inspection methods mainly rely on manual sampling inspection and single parameter verification, which is low in efficiency, incomplete in parameter coverage, easy to miss and lacks automatic comparison, and is difficult to meet the large-scale design requirements. SUMMARY

[0004] The present application provides a printed circuit board quality inspection method, device, equipment, medium and product to at least solve the problems of strong subjectivity, low efficiency, insufficient coverage and easy to miss in quality inspection in the related art.

[0005] The present application provides a printed circuit board quality inspection method, comprising: obtaining a design file of a printed circuit board; analyzing the design file to extract signal line information; identifying a target tab from the design file according to the signal line information; the target tab is attached to the signal line and is used to adjust the electromagnetic characteristics and impedance parameters of the signal line to optimize the signal transmission performance; obtaining the design parameters of the target tab, and judging whether the design parameters meet the reference rules; and generating a quality inspection report of the target tab according to the judgment result.

[0006] The present application also provides a printed circuit board quality inspection device, comprising:

[0007] An obtaining module is configured to obtain a design file of a printed circuit board;

[0008] An analyzing module is configured to analyze the design file to extract signal line information;

[0009] An identifying module is configured to identify a target tab from the design file according to the signal line information; the target tab is attached to the signal line and is used to adjust the electromagnetic characteristics and impedance parameters of the signal line to optimize the signal transmission performance;

[0010] A judging module is configured to obtain the design parameters of the target tab, and judge whether the design parameters meet the reference rules;

[0011] generating a quality inspection report of the target connecting piece according to the judgment result.

[0012] The application further provides an electronic device, comprising a memory for storing a computer program and a processor for executing the computer program to realize the steps of the quality inspection method of the printed circuit board.

[0013] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the steps of the quality inspection method of the printed circuit board.

[0014] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to realize the steps of the quality inspection method of the printed circuit board.

[0015] The application realizes batch and rapid signal line and target connecting piece identification by automatically analyzing the design file and replacing manual sampling inspection, and improves detection efficiency; after extracting the signal line information and identifying the target connecting piece, the design parameters thereof are acquired and full-parameter verification is performed based on the reference rules, so that the key parameters are ensured not to be missed; the design file analysis, parameter extraction and rule judgment are automatically performed throughout the whole process, so that the missed problems caused by fatigue and negligence during manual one-by-one auditing can be avoided; by automatically comparing the design parameters of the target connecting piece with the reference rules, efficient and accurate comparison is realized, manual comparison is replaced, and the result accuracy is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A schematic diagram of a specific hardware architecture relied on by the execution of the quality inspection method of the printed circuit board provided by the embodiments of the application;

[0018] Figure 2 A flowchart of the quality inspection method of the printed circuit board provided by the embodiments of the application;

[0019] Figure 3 A schematic diagram of a standard public board library provided by the embodiments of the application;

[0020] Figure 4 A schematic diagram of a quality inspection report provided by the embodiments of the application;

[0021] Figure 5Another schematic diagram of a quality inspection report provided by an embodiment of the present application is shown in FIG. 6.

[0022] Figure 6 A schematic diagram of a quality inspection device for a printed circuit board provided by an embodiment of the present application is shown in FIG. 5.

[0023] Figure 7 A schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0025] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0026] In order to more clearly illustrate the embodiments of the present application, the technical terms needed in the embodiments will be briefly introduced as follows:

[0027] Double Data Rate (DDR) is a data transmission technology for computer memory, and the core is that data can be transmitted on both the rising edge and the falling edge of the clock signal, realizing double rate.

[0028] Tabbed Routing (Tab) is an innovative Printed Circuit Board (PCB) routing technology for high-speed signal transmission optimization, and its core definition is: on one side or both sides of the signal transmission line (such as microstrip line, stripline), through the addition of regularly arranged small copper foil protruding structures (i.e. connection tabs), the electromagnetic characteristics and impedance parameters of the transmission line are adjusted, so as to realize the signal integrity optimization routing scheme in the limited routing space scene.

[0029] Electronic Design Automation (EDA) tools refer to a collection of software tools that assist engineers in completing the entire process of integrated circuits (IC), printed circuit boards and electronic systems from design, simulation to manufacturing.

[0030] In the field of double data rate hardware design, in order to make up for the problem of insufficient DDR wiring length, a connecting sheet structure is usually used for design optimization. Among them, Tab as the key accessory structure in the signal transmission path of the connecting sheet DDR connecting sheet, plays an indispensable role, its core functions include realizing signal shielding to reduce external interference, enhancing grounding performance to guarantee circuit stability and optimizing impedance matching to ensure signal transmission quality, therefore, the design quality of Tab connecting sheet copper sheet directly determines the transmission rate, transmission stability and anti-interference ability of the connecting sheet DDR connecting sheet signal, which has a crucial influence on the performance of the entire connecting sheet DDR connecting sheet hardware system.

[0031] However, in the actual process of designing the copper sheet of the tab, due to factors such as design complexity and operation standardization, problems such as copper sheet quantity deviation, size not meeting the design standard, and unreasonable position layout are prone to occur. If these problems are not discovered and corrected in time, they will directly affect the normal operation of the tab hardware. In the related art, there are obvious deficiencies in the inspection method for the design quality of the copper sheet of the tab. Mainly using manual sampling inspection or single parameter verification method, such as only checking the number of copper sheets. However, this inspection method has many defects: first, the inspection efficiency is very low. Manual sampling inspection requires a lot of manpower and time, and it is difficult to meet the batch detection needs in large-scale tab PCB (printed circuit board) design scenarios. Second, the parameter coverage is not comprehensive. The related inspection method often ignores the verification of key parameters such as the position accuracy and size specification of the copper sheet of the tab, which leads to the fact that some potential design defects cannot be discovered in time, thereby causing hidden dangers to the subsequent signal transmission performance of the tab. Third, manual inspection is prone to missing problems. In large-scale tab hardware design, the number of copper sheets of the tab can reach tens of thousands. During the manual review process, it is inevitable that some abnormal copper sheets will be missed due to fatigue, negligence and other factors. Fourth, it cannot be efficiently compared and confirmed with the artwork (standard template). The related inspection method lacks an automatic comparison mechanism with the artwork, and can only rely on manual comparison. Not only is the workload huge, but the comparison accuracy is also easily affected by human factors, making it difficult to ensure the accuracy of the inspection results. Fifth, in the process of engineers copying the artwork for design reuse, it is easy to cause the copper sheet of the tab to be repeatedly copied. The related inspection method cannot identify such repeated problems in time, which leads to analysis errors due to abnormal copper sheet quantity when performing signal equivalent length analysis, further affecting the reliability and accuracy of the tab hardware design.

[0032] To solve all or part of the above technical problems, the embodiments of the present application provide a quality inspection method for a printed circuit board. The method automatically analyzes design files, replaces manual sampling inspection, realizes batch and rapid signal line and target tab identification, improves detection efficiency, meets the batch detection needs of large-scale PCB design, extracts signal line information and identifies target tabs, obtains their design parameters (covering quantity, size, position, etc.), and performs full-parameter verification based on reference rules to ensure that key parameters such as position accuracy and size specification are not missed. The design file analysis, parameter extraction and rule judgment are automatically performed throughout the process to avoid missing problems caused by fatigue and negligence during manual review. By automatically comparing the design parameters of the target tab with the reference rules, efficient and accurate comparison with the artwork is realized, manual comparison is replaced, and the accuracy of the results is ensured.

[0033] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1 The diagram illustrates the specific hardware architecture upon which the quality inspection method for printed circuit boards (PCBs) relies. This specific hardware architecture includes a hardware support layer, a software core layer, and an interactive presentation layer.

[0035] The hardware support layer provides the physical operating environment for the quality inspection methods, serving as the physical foundation for method execution. Its core components include computing devices, dedicated PCB design hardware peripherals, and data storage devices. The computing devices support the parsing of PCB design files and the extraction and processing of tab copper data. The dedicated PCB design hardware peripherals include display devices and input devices. The display devices present multi-layered PCB design views, problem annotation layers, and inspection reports. The input devices allow engineers to select target areas in the design files and locate problem tab copper areas. The data storage devices store the original PCB design files, benchmark rule bases, intermediate processing data, and the final quality inspection report.

[0036] The core software layer automates the entire process from design file parsing to report generation through modular software functions. Core modules include: a PCB design file parsing module, supporting the reading and parsing of mainstream PCB design file formats and extracting layer information, signal line information, and tab copper information; a data association and mapping module, responsible for constructing key data mapping relationships to achieve precise binding of signals to tab copper and components; a multi-dimensional inspection execution module, broken down into multiple sub-modules according to inspection requirements, performing compliance judgments in different dimensions, including determining whether tab copper is bound to valid signal lines; counting the number of tab copper designs, judging overlap, calculating the valid number and comparing it with a benchmark; verifying the matching degree of tab copper dimensions with the benchmark through area difference calculation or shape intersection operation; calculating individual scores based on the judgment results of each dimension, and generating a comprehensive quality score based on weights; and a problem annotation and report generation module, used to create an independent problem annotation layer, visually marking non-compliant tab copper coordinates and dimensions; and integrating problem information, annotation layers, and original design files to generate a structured quality inspection report.

[0037] The interactive display layer provides an interactive interface for engineers to realize controllability of the inspection process and intuitive presentation of the results. The core functions include: a parameter configuration interface that supports engineers to select an inspection platform, specify a PCB layer, set an inspection range, and adjust reference rule parameters; a PCB design view display interface that synchronously presents an original PCB design view and a problem marking layer, supports layer switching, zooming, and panning, and enables engineers to intuitively view the location and marking of non-compliant Tab copper skins; an inspection result display interface that presents inspection result details in a table form, including signal network name, Tab copper skin quantity / size data, compliance judgment result, quality score, and the like, and supports data filtering and exporting; and an operation control interface that provides an inspection triggering button, a result clearing button (Clear), and a report exporting button (Export) to support engineers to execute the inspection process as needed.

[0038] Embodiments of the present application provide a quality inspection method for printed circuit boards. The method is described in detail in combination with the execution process of the quality inspection method for printed circuit boards.

[0039] As shown in Figure 2 , the method comprises the following steps:

[0040] S201, obtaining a design file of a printed circuit board.

[0041] The design file of the printed circuit board contains the physical structure of the printed circuit board, including but not limited to layer distribution, via hole position, and device packaging layout, etc. The design file also records complete design information of the DDR signal line, including but not limited to the topology structure of the DDR signal network, the physical properties of each signal line, and the spacing specification between signal lines, etc. S202, analyzing the design file and extracting signal line information.

[0042] The signal line information is the information of the relevant signal lines between the DDR controller and the device, including data lines (Data Queue, DQ), address lines (Address, ADDR), clock lines (Clock, CLK), strobe signals (Data Strobe, DQS), power ground, etc. The data line is mainly used to transmit actual data between the DDR memory and the controller; the address line is used to specify the storage address of the data in the memory to ensure that the controller can accurately find the location of the target data; the clock line is used to provide a synchronous clock signal to make data transmission, address selection, and the like operate according to a unified rhythm to ensure timing consistency; the strobe signal is synchronized with data transmission to help the controller accurately identify the valid time of the data to reduce data transmission errors.

[0043] The signal line information is a physical attribute of the signal line, including line identification, length, board layer, impedance parameter and the like of each signal line. The signal line information can be extracted by analyzing the design file of the printed circuit board through an EDA tool.

[0044] In some embodiments, the design board layer of the printed circuit board is determined from the design file, and a plurality of signal lines of the design board layer are obtained. Target signal lines carrying a target keyword in line identification are filtered from the plurality of signal lines, and signal line information of the target signal lines is determined.

[0045] The design board layer of the printed circuit board in the design file is taken as a check layer, and board layers that do not need to participate in the check are excluded. Then, a plurality of signal lines of the design board layer are obtained, line identifications of the signal lines are extracted, and the signal line identifications are integrated to construct a signal line list netlist. Target signal lines containing a target keyword "DDR" are filtered from the signal line list netlist, line identifications of the target signal lines are summarized, and a DDR signal line list DDRnetlist is constructed.

[0046] The above embodiments first determine the design board layer, and then obtain the signal lines in the board layer, so as to accurately focus the check range, avoid indiscriminate analysis of all lines on the whole board, reduce the interference of irrelevant line data, and improve the overall efficiency of the quality check process. The target signal lines are filtered based on the line identification carrying the target keyword, so as to accurately lock the core object to be checked, and avoid the check deviation caused by irrelevant lines. The determined target signal line information can ensure accurate association to the target connecting piece attached to each target line, so as to avoid the missed detection or misjudgment of the target connecting piece caused by line matching error, and ensure the reliability and accuracy of the quality check.

[0047] In some embodiments, the target signal line list is traversed to obtain the device reference designations of the devices connected to each line in the list, and a list of device reference designations for each signal line is generated. If the target device reference designation is in the list of device reference designations for a signal line, then the signal line is a target signal line for the target device. For example, if a user wants to inspect the target connection pads associated with the DDR signal lines of a CPU, the reference designation of the CPU device can be obtained and denoted as cpurefdes. A list of DDR signals connected to the CPU can be declared and denoted as cpunetList. Each element (i.e., each net item) in the DDRnetlist obtained above is then processed one by one. For each item, a list of reference designations of the devices connected to the pins of the item is obtained, and if cpurefdes is in the list of reference designations, then the item is a DDR signal connected to the CPU. The item is then stored in cpunetList. After such filtering, cpunetList is a list of DDR signals for the selected CPU.

[0048] In complex printed circuit board designs, a signal line can be connected to multiple devices. The above embodiments clearly define the ownership of each line by sorting the device reference designations, and avoid interference from cross-device lines. The target signal lines for the target device are filtered out based on whether the target device reference designation is in the list, for example, in DDR designs, the DQ, ADDR, and other signal lines associated with the CPU can be quickly located based on the reference designation of the CPU, rather than other devices (e.g., memory chips). This allows independent inspection of the target connection pads corresponding to different devices, and meets the needs of fine quality control of local areas in complex hardware designs.

[0049] In some embodiments, a target area selected by a user from a design file is obtained, and the target area is analyzed to extract signal line information of the target area.

[0050] In the present application, the design view of the design file of the printed circuit board can be displayed in a user interface, and the user can select a target area for quality inspection from the design file. The target area in the design file is then analyzed to obtain a plurality of signal lines belonging to the target area, and target signal lines having a target keyword in the line designations are filtered out from the plurality of signal lines, and the signal line information of the target signal lines is determined.

[0051] In large-scale PCB design, engineers may only need to focus on checking the quality of the Tab copper skin in a specific area, rather than checking the whole board. The above embodiment allows the user to directly select the target area, avoiding redundant analysis of the whole board data, reducing data processing, and focusing inspection resources on key areas to improve the efficiency of local problem troubleshooting. By selecting the target area, only the signal line information in the area is extracted, effectively excluding irrelevant line interference, ensuring that the Tab copper skin identified later belongs to the core signal line of the target area, reducing false positives or missed detections caused by mixed data.

[0052] S203, identifying a target connecting piece from the design file according to the signal line information.

[0053] The target connecting piece is attached to the signal line and used to adjust the electromagnetic characteristics and impedance parameters of the signal line to optimize the signal transmission performance, such as the Tab copper skin used to compensate for the length of the trace. It should be noted that the target connecting piece, as an auxiliary optimization structure of the DDR number line, contains the shape, size, and board layer of each connecting piece in the design file, as well as the DDR signal line it belongs to. For example, the design file will mark that "DDR data line DQ<0> needs to be attached with two copper skin Tabs of a specific size on a certain segment of the trace on the L3 board layer", thereby binding the Tab with the specific DDR signal line.

[0054] Each signal element (denoted as neti) in the previously determined DDR signal list DDRnetlist is processed one by one: for each neti, all shape elements associated with it are obtained, and these shape elements are sorted into a list named l_getshapei. Then, from the l_getshapei list, elements whose board layer is consistent with the currently specified inspection board layer are selected, and these selected elements are stored in the previously created empty table L_ddrTab. After this step of selection, L_ddrTab becomes a list of Tab elements corresponding to the DDR signal in the selected inspection area and belonging to the current inspection board layer.

[0055] A mapping relationship table TableDDRTab can also be constructed, including: taking the line identification (denoted as netiname) corresponding to each neti as the key, taking the l_getshapei list corresponding to this neti (i.e. all shape elements associated with this network) as the value, and storing it in TableDDRTab in the format TableDDRTab[netiname]=l_getshapei. TableDDRTab presents a one-to-one correspondence between each DDR signal and all its attached Tabs (i.e. shape elements), becoming a mapping relationship table between DDR signals and attached Tabs.

[0056] In a complex PCB design, a large number of DDR signals (such as DQ, ADDR, etc.) are each attached to multiple Tabs, and it is difficult for traditional manual inspection to quickly confirm which signal line a certain Tab belongs to. In the above implementation, TableDDR Tab directly establishes a corresponding relationship between the line identifier as the key and the corresponding Tab list as the value, so that all the attached Tabs of an arbitrary DDR signal can be located by the line identifier of the DDR signal, avoiding the mismatch or ambiguity of the Tabs and the signals. In addition, subsequent Tab quantity statistics, size verification, and overlap judgment can quickly retrieve target data based on TableDDR Tab, reducing the time for data query and screening and improving the overall inspection efficiency.

[0057] S204, obtain the design parameters of the target connecting sheet, and determine whether the design parameters meet the reference rule.

[0058] The design parameters of the target connecting sheet include network attribute, design quantity, design size, and design position.

[0059] The reference rule includes: having a network attribute, being consistent with the reference quantity, matching the reference size, and matching the reference position. The reference rule is constructed according to industry standards and enterprise specifications, supports customization, and can obtain the reference rule from a pre-constructed rule library.

[0060] In some embodiments, detecting whether the target connecting sheet has a network attribute includes: first determining whether the design area of the target connecting sheet meets the reference area range, and if so, obtaining the line identifier of the signal line corresponding to the target connecting sheet; if the line identifier is empty, it is determined that the target connecting sheet has no network attribute. The reference area range can be the area interval of the standard Tab copper sheet.

[0061] Specifically, first, the identification information of all copper sheets in the current analysis area needs to be extracted, and these identifications are integrated to form a list, denoted as shaplist. Then, according to the standard Tab area maximum threshold and the standard Tab area minimum threshold pre-set in the rule library, the copper sheet elements in shaplist are subjected to first layer screening to retain the copper sheets with areas within the range of the two thresholds; then, second layer screening is performed: from the copper sheets after the first layer screening, further screen out the elements with empty line identifiers, which means that there is no network attribute bound, and these copper sheets belong to Tabs without network attributes.

[0062] In addition, the Tab without network attributes obtained after two screenings is stored in a special error Tab list, recorded as errorTab. Then, all Tabs in errorTab are highlighted to be displayed in a conspicuous manner in the design interface, facilitating the staff to quickly identify them. Meanwhile, the specific location information (such as coordinates) of each Tab without network attributes in the design file is recorded. In actual operation, when the user clicks on the highlighted Tabs in the interface, the system can directly locate the specific location of the Tab in the design diagram, without the user manually searching, thereby improving the efficiency of problem troubleshooting. The whole process not only realizes the accurate screening of Tabs without network attributes, but also simplifies the subsequent processing flow through highlighting and positioning functions, ensuring that the abnormal Tabs in the design can be quickly discovered and corrected.

[0063] In the PCB design, there are various copper skins for non-Tab purposes (such as ground copper skin and shielding copper skin). If the network attributes of all copper skins are directly checked, irrelevant objects may be mixed in, leading to misjudgment. The above embodiment first takes the reference area range as the screening condition, and includes the copper skin meeting the Tab size characteristics in the subsequent detection, avoiding invalid detection of non-Tab copper skin, and improving the detection efficiency and accuracy; the Tab copper skin without network attributes is accurately locked by judging whether the line signal identifier is empty. The Tab copper skin without network attributes is a potential design defect, which may affect the integrity of the surrounding DDR signals if not timely removed or re-bound with the line. Through the above embodiment, such defects are identified, and in the subsequent process, the Tab copper skin without network attributes can be bound with the correct line or deleted, avoiding signal interference or functional failure caused by missing attributes, and further ensuring the reliability of the DDR hardware design.

[0064] In some embodiments, detecting whether the design quantity of the target connection piece matches the reference quantity includes: obtaining a mapping relationship table between the signal line and the corresponding target connection piece according to the signal line information, then determining the design quantity of the target connection piece according to the mapping relationship table, and then performing overlap judgment on the target connection piece other than the first target connection piece to determine the overlap quantity of the target connection piece; then calculating the effective quantity of the target connection piece according to the design quantity and the overlap quantity of the target connection piece; and comparing whether the effective quantity and the reference quantity are the same, if yes, determining that the design quantity of the target connection piece matches the reference quantity.

[0065] Specifically, according to the previously constructed TableDDRTab (which records the mapping relationship between all network ids and corresponding Tabs), the total number of networks contained in TableDDRTab is first counted and recorded as nettotal, an empty list L_overlapTab is initialized for subsequent storage of overlapping Tabs, a count variable N is set and assigned a value of 1 for marking the entry serial number in the check result table.

[0066] Next, each network element (denoted as netitem) in TableDDRTab is analyzed one by one: First, all tabs corresponding to the network are extracted from netitem to form a tab list netitemTablist, and the number of elements in this list is counted as the actual number of tabs for the network, denoted as actTabcount; Second, the first tab is taken from netitemTablist and denoted as firstTab, and an equivalent tab list L_filerTab is initialized based on it. In the initial state, L_filerTab only contains firstTab.

[0067] Next, overlap is checked for each tab element (denoted as netitemTabi) in netitemTablist except for firstTab: First, an overlap flag is initialized and assigned a value of 0, where 0 represents no overlap and 1 represents overlap; then, each tab element (denoted as fileritemTabi) in the equivalent tab list L_filerTab is traversed; for each pair of netitemTabi and fileritemTabi, their shapes are obtained (denoted as polynetTab and polyflierTab respectively), and the intersection operation is performed on these two shapes. If there is an intersection, it means that the two tabs have an overlapping area, so the flag is set to 1; if there is no intersection, it means that the two tabs do not overlap, so the flag is kept at 0.

[0068] If flag=0, it means that the current netitemTabi does not overlap with any tabs in L_filerTab, and it is added to L_filerTab. At this time, L_filerTab records the non-overlapping tabs in this network. If flag=1, it means that the current netitemTabi overlaps with a certain tab in L_filerTab, and it is added to the overlapping tab list L_overlapTab.

[0069] After all Tab elements in netitemTablist have been analyzed, L_filerTab is processed: empty elements in the list are removed, and the number of remaining elements is counted, denoted as eqTabcount. This value is the equivalent number of Tabs (i.e., the number of valid Tabs without overlap) corresponding to the netitem network. At the same time, L_overlapTab stores all overlapping Tabs under the network, and the number of elements in L_overlapTab is counted, denoted as overlapTabcount, which is the number of overlapping Tabs in the network.

[0070] Finally, an inspection result table, `checkTable`, is initialized. The relevant information for the current netitem is stored in the Nth entry of `checkTable` according to a fixed format: `checkTable[N] = {netitem (network element), netitem's line identifier, actual number of tabs `actTabcount`, equivalent number of tabs `eqTabcount`, board layer, overlapping tab list `L_overlapTab`}. After completing one record, the value of N is incremented by 1, and the analysis continues for the next netitem until all networks in `TableDDRTab` have been traversed, ultimately forming a complete inspection result table.

[0071] In actual design, target connectors may overlap (e.g., due to repeated copying during PCB layout). Overlapping connectors cannot perform their normal signal optimization function. If only the surface design quantity is counted, invalid overlaps may be mistakenly included in the valid quantity, rendering the comparison with the baseline quantity meaningless. The above embodiment retrieves data from an established mapping table of signal lines and target connectors to accurately obtain the design quantity of target connectors for each signal line. For each connector other than the first one, the overlap situation is judged one by one. After counting the overlaps, invalid overlaps are removed from the design quantity to calculate the truly effective quantity. By directly comparing the effective quantity with the baseline quantity, the hidden problem of insufficient effective quantity despite meeting the design quantity standard can be accurately identified. This avoids the situation where the quantity meets the standard in form but fails to meet the signal optimization requirements, further ensuring the compliance and practicality of the target connector quantity design.

[0072] In some embodiments, detecting whether the design quantity of the target connector matches the reference quantity further includes: obtaining a mapping table between signal lines and corresponding target connectors based on signal line information, and then determining the design quantity of the target connector based on the mapping table; obtaining the reference quantity from the standard reference board library, comparing whether the design quantity and the reference quantity are the same, and if so, determining that the design quantity of the target connector matches the reference quantity.

[0073] Standard public board library such as Figure 3 As shown, column A records the line identifier of the DDR signal, such as "MFCPU0.SB.DQ". <24> “MNCPU0.SB.DQS.DN” <3> "etc." covers different types of DDR signals such as data lines (DQ) and strobe signals (DQS); column B records the board layer where these DDR signals and their associated tabs are located, such as "ETCH / L16"; column C records the tab copper and quantity corresponding to each DDR signal network, with values ​​ranging from 0 to 9, reflecting the different requirements of different signals for tab optimization.

[0074] Specifically, firstly, from the TableDDRTab mapping table (which maps all DDR networks to their corresponding tabs) in the current PCB file, the name, board layer, and actual number of attached tabs for each DDR network are extracted. Then, referring to the DDRTabBZInfo format, this is organized into a unified list DDRTabInfo with the fixed format of "Netname (NETNAME), Tab Count (TabCOUT), Board Layer (LAYER)". Simultaneously, the DDRTabBZInfo obtained from the standard reference library records the standard number of copper tabs that each DDR network (such as data lines and address lines) should have on its corresponding PCB layer, i.e., the baseline number. Next, the organized DDRTabInfo (current design) and DDRTabBZInfo (standard library) are compared line by line to identify "difference lines" where the number of tabs is inconsistent. These difference lines are uniformly recorded in the checkresult list, with the record format clearly indicating key information: "Netname, Tab Count in the Current Design, Tab Count in the Standard Reference Library, Board Layer".

[0075] Afterwards, this discrepancy information will be displayed on the front-end list page. When an engineer clicks on a problematic network record, the system will automatically switch to the PCB board layer where the network is located and highlight the network. Engineers no longer need to manually search for the board layer and network, which improves the efficiency of locating problems and facilitates subsequent targeted modifications.

[0076] In some embodiments, detecting whether the design size of the target connector matches the reference size includes: firstly calculating a first area difference between the design area of ​​the target connector and the reference area; then determining whether the first area difference is less than or equal to a first area difference threshold; if not, determining that the design size of the target connector does not match the reference size.

[0077] The process for determining the reference area (referarea) is as follows: First, extract the area of ​​each tab element from L_ddrTab and integrate these areas into an area list L_area. Next, take the first element from L_area as the initial comparison value, denoted as firstarea, and remove firstarea from the original L_area, resulting in a new area list still named L_area. Then, initialize two counter variables n and m (both 0), and evaluate each area element item in the new L_area one by one. If the difference between item and firstarea is less than the tab size set in the rule base... If the size threshold is reached, n is incremented by 1 (indicating that the element is similar in size to the firstarea). If the difference exceeds the threshold, m is incremented by 1, and the current item is assigned to the temporary variable temparea. This process continues until all elements have been traversed. Finally, the reference area is determined based on the values ​​of n and m: if n ≤ m, it means that there are few elements similar in size to the firstarea, and the firstarea may not be representative, so the reference area refererarea = temparea; if n > m, it means that most elements are similar in size to the firstarea, and the firstarea is more representative, so the reference area refererarea = firstarea.

[0078] The specific steps for filtering and recording tabs whose dimensions do not meet the requirements are as follows: First, obtain the size difference threshold range (i.e., the first area difference threshold) from the rule base, denoted as areaol. At the same time, initialize two empty lists L_errorTab (to store tab elements that do not meet the requirements) and L_errorTabResult (to store detailed inspection result descriptions). Then, process each tab element item2 in L_ddrTab one by one: first extract the area of ​​item2, denoted as itemrea, and calculate the difference disarea between itemrea and the reference area referencerea. If disarea is greater than the threshold areaol, it means that the tab size does not meet the design requirements.

[0079] At this point, the corresponding inspection result status can be retrieved from the rule base. Then, information such as item2 itself, the netname of the line to which item2 belongs, the center coordinates (xy) of item2, the layer to which it belongs, the actual area (actarea, i.e., itemmarea), the difference (disarea) between the actual area and the baseline area, and the inspection result status type are recorded in L_errorTabResult in the format {item2netnamexylayeractareadisareatype}. At the same time, item2 is added to L_errorTab. This process is repeated until all elements in L_ddrTab have been traversed, and finally, a complete list of non-compliant Tabs, L_errorTab, and the corresponding list of inspection result descriptions, L_errorTabResult, are obtained.

[0080] The dimensions of the tab copper layer directly affect its effect on adjusting the electromagnetic characteristics and impedance parameters of signal lines. In PCB design, the shape of the tab copper layer may be an irregular polygon. Directly comparing multiple dimensions such as side length and outline one by one would increase the computational complexity and difficulty of judgment. However, the above embodiment transforms the dimensional difference of irregular shapes into a single quantitative indicator by calculating the first area difference between the designed area and the reference area, reducing the computational cost of dimensional inspection and improving the judgment efficiency. Using a quantitative threshold as the judgment basis, if the value exceeds the threshold, the size is judged to be mismatched, avoiding the interference of subjective factors and ensuring the objectivity and consistency of dimensional inspection results.

[0081] In some embodiments, detecting whether the design size of the target connecting piece matches the reference size includes: drawing a reference shape of the connecting piece on a preset plate according to the reference size, and drawing a design shape of the target connecting piece on the preset plate according to the design size of the target connecting piece; performing an intersection operation on the reference shape and the design shape to obtain the intersection area; calculating a second area difference between the intersection area and the reference area; and determining that the design size of the target connecting piece does not match the reference size if the second area difference is greater than a second area difference threshold.

[0082] The size of the intersection area directly reflects the degree of overlap between the design shape and the reference shape: the larger the intersection area, the higher the fit between the two contours; the smaller the intersection area, the more obvious the shape deviation. The second area difference threshold is a threshold requirement set in the rule base.

[0083] Specifically, first, a temporary worksheet layer is created and named Tabchecktemp. An empty list L_erroTabByBZ is initialized to store tab elements whose dimensions do not meet the requirements. Next, the area corresponding to a predefined baseline tab size is extracted from the rule base and denoted as L_BZTabarea, serving as the benchmark for subsequent comparisons.

[0084] Then, based on the specific size parameters of the reference Tab in the rule base, a reference Tab shape is drawn on the newly created temporary layer Tabchecktemp, and this reference shape is denoted as Tabshape.

[0085] Next, each element (denoted as item3) in the previously obtained DDR signal Tab list L_ddrTab is checked one by one: First, on the temporary board layer Tabchecktemp, the design shape corresponding to item3 is drawn in the same direction as the reference shape Tabshape, and denoted as item3shpe; then, the intersection operation of item3shpe (design shape) and Tabshape (reference shape) is performed, and the area corresponding to this intersection region is calculated and denoted as jiaojiarea; then, the difference between jiaojiarea and the reference area L_BZTabarea in the rule base is calculated. If this difference meets the threshold requirement set in the rule base (i.e., the difference is within the allowable range), it means that the size of item3 conforms to the design rules; if the difference exceeds the threshold requirement of the rule base, it is determined that the size of item3 does not conform to the design rules.

[0086] For item3 that is determined to be non-compliant, the corresponding inspection result status (such as size exceeding the limit or shape mismatch) needs to be retrieved from the rule base first. Then, the item3 itself, the netname of the line to which the item3 belongs, the center coordinates (xy) of the item3, the layer to which the item3 belongs, the actual area (actarea) of the item3, the difference (disarea) between the actual area and the reference area, and the corresponding inspection result status (type) are recorded in detail in the inspection result description list L_errorTabResult in the format L_errorTabResult={item2netnamexylayeractareadisareatype}. At the same time, this non-compliant item3 is added to the previously initialized L_erroTabByBZ list. The above inspection, judgment and recording operation for each item3 is repeated until all elements in L_ddrTab are traversed, finally obtaining the complete list of tabs with non-compliant sizes, L_erroTabByBZ, and the corresponding list of inspection result descriptions, L_errorTabResult.

[0087] The shape and contour of the tab copper directly affect its coupling effect with signal lines, thus determining the accuracy of impedance adjustment. The above embodiment, by drawing two shapes on the same preset board layer, can intuitively reflect the dual differences in size and contour, avoiding hidden design defects caused by area compliance but shape deviation. Intersection area is obtained through intersection calculation, accurately quantifying the overlap of shapes. Then, based on the difference between the intersection area and the reference area (the second area difference), the degree of deviation between the designed shape and the reference is objectively presented. By setting a second area difference threshold, it is possible to accurately identify area compliance but shape deviation, avoiding the misjudgment risk of traditional single area judgment and ensuring that the size design of the target connector meets the area requirements.

[0088] It should be noted that the above-mentioned embodiments for checking whether the design dimensions of the target connecting piece match the reference dimensions can be combined in combination to further ensure the accuracy of the dimension inspection.

[0089] In some embodiments, the compliance assessment progress is displayed on the user interface. Specifically, this includes: counting the total number of all elements in the target connection chip list L_ddrTab corresponding to the DDR signal, and recording this as total, which represents the total number of tab copper layers that need to be checked. Simultaneously, two variables are initialized: the current progress value per (initially 0) displayed by the progress bar and the number of elements that have been checked (initially 0).

[0090] When iterating through the elements in L_ddrTab, the completed count cn is incremented by 1 for each element checked (i.e., cn = cn + 1). Then, the current progress percentage per1 is calculated based on the completed count and the total count. The formula is per1 = (100 × cn) / total, and this value reflects the completion rate of the checks up to now.

[0091] To ensure the progress bar scrolls smoothly and updates in real time, a condition can be set: if the difference between the currently calculated per1 and the per currently displayed on the progress bar is greater than or equal to 1, a loop starts from i=1, driving the progress bar to scroll by the corresponding amount and displaying the latest progress value in real time. Simultaneously, the current per1 is assigned to per as the baseline for the next calculation, until the difference between per1 and per is less than 1, at which point the current progress update loop ends.

[0092] In this way, the progress bar can be dynamically updated as the inspection progresses, allowing engineers to intuitively understand the real-time progress of the inspection and improving the user experience.

[0093] S205. Generate a quality inspection report for the target connecting piece based on the judgment result.

[0094] When the design dimensions of the target connector do not match the reference dimensions, obtain the center coordinates, board layer, and corresponding target signal line of the target connector; generate a quality inspection report based on the difference between the design area and the first area of ​​the target connector, as well as the center coordinates, board layer, and corresponding target signal line of the target connector.

[0095] Specifically, the core information of each problematic tab is extracted, including its specific coordinates on the PCB board, design dimensions, differences from standard dimensions, and the reasons for non-compliance (such as exceeding the size threshold, overlap, lack of net attributes, etc.). This information is organized into a clear list and displayed on the front-end interface, allowing engineers to directly see the key details of all problematic tabs without having to check them one by one, and quickly understand the type and severity of the problem.

[0096] like Figure 4As shown, the left side displays the circuit layout of the printed circuit board. The green wavy lines are DDR signal lines, and the irregular green shapes distributed along these lines are the tab copper areas used to optimize signal transmission. Some tab copper areas are highlighted or specially displayed, indicating potential design issues in these areas, requiring further confirmation based on the inspection results on the right. The right side presents the TabDimensionCheck page, which includes an inspection configuration area, operation button area, inspection result area, and progress bar. The inspection configuration area allows selection of different platforms and specification of the board layer to be inspected (e.g., L3 layer), as well as setting the total number of inspections. The operation button area provides Manual, AllCheck, and Clear functions, allowing engineers to perform inspections as needed. The inspection result area lists information on non-compliant tab copper areas, including center coordinates (e.g., [4558.0 6650.505]), the board layer (e.g., ETCH / L3), the reason for non-compliance (e.g., sizeerror), and area difference (e.g., 21.46), enabling engineers to quickly locate and analyze problems. The progress bar displays the completion rate of the inspection (e.g., 100%), intuitively reflecting the execution status of the inspection task.

[0097] When the above embodiment detects a size mismatch in the target connector, it does not merely record a single size deviation, but simultaneously acquires the center coordinates of the target connector, its board layer, the corresponding target signal line, and the difference between the designed area and the first area. The center coordinates are used to determine the physical location of the target connector, the board layer is used to locate the PCB layer, the corresponding target signal line is used to associate the target connector with the core signal, and the first area difference is used to quantify the degree of deviation. This clear and intuitive presentation of the target connector information allows engineers to quickly understand, through the report, the location (center coordinates) of a DDR signal line on a specific board layer, and the extent of a tab copper size deviation. Based on the center coordinates and board layer in the report, the physical location of the problematic connector can be instantly found in the PCB design drawing; through the corresponding target signal line, it is possible to analyze whether the overall impedance design of the signal is affected by this size deviation; and by combining the design area and the first area difference, the magnitude of the deviation can be quickly determined and a correction plan can be formulated.

[0098] After verifying that the design quantity of the target connector matches the baseline quantity, a quality inspection report for the target connector is generated based on this result. This includes: First, obtaining the total number of rows in the inspection result table CheckTable[N], denoted as sizerow. This row number corresponds to the total number of DDR signal networks to be displayed. Then, starting from the first row, iterates through all rows up to sizerow, extracting the data from each row and denoting it as rowlist. In each row, information is stored in fixed positions: the second element is the line identifier, the third is the actual number of tabs for the network, and the fourth is the equivalent number of tabs calculated after removing overlaps. Comparing these two quantities, if the actual number of tabs and the equivalent number of tabs are different, it indicates that the network has tab overlap. In this case, the contents of the actual number of tabs and the equivalent number of tabs in this row will be highlighted in red, allowing engineers to easily notice networks with abnormal quantities. Simultaneously, the fifth element of each row stores the list of overlapping tabs for the network. The tabs corresponding to this list are highlighted, making it easier for engineers to quickly locate overlapping tab positions in the PCB layout. Furthermore, when an engineer clicks on this row of data, the system will automatically highlight the corresponding DDR signal network in the PCB diagram, further helping engineers to accurately locate the problematic network without the need for manual searching, thus improving troubleshooting efficiency.

[0099] like Figure 5As shown, the left side displays the circuit layout of the printed circuit board. Different colored wavy lines represent different DDR signal lines (such as yellow and blue lines), and the irregular shapes distributed along the lines are tab copper areas used to optimize signal transmission. Some areas of tab copper areas or lines are displayed differently, indicating potential quantity design issues in these areas, requiring further analysis based on the inspection results on the right. The right side presents the Tab CountCheck page, used to analyze the compliance of the number of DDR signal-related tabs. The Tab CountCheck page includes a check configuration area, an operation button area, a check result area, and a progress bar. The check configuration area allows setting the number of tabs to be checked (TabCount, e.g., 14) and the layer (e.g., L20). The operation button area provides function buttons such as CPU Selection, AllCPUCheck, NetSelect, AllNetCheck, Export Results, and Clear Results to meet the quality inspection needs of different scenarios. The inspection results area lists detailed information for each DDR signal network in tabular form, including netname, layer, actual number of tabs (ActCount), and equivalent number of tabs (EQCount). Among these, "M_P_CPU0_SB_DQ" is listed. <21> "The actual number of networks (5) is inconsistent with the equivalent number (3), and the data is highlighted in red, indicating that there is a tab overlap problem in the network; "M_P_CPU0_SB_DQ <23> "Network data highlighted in blue may represent currently selected or key areas requiring close monitoring. The progress bar indicates the current inspection progress is 100%."

[0100] In some embodiments, at least one result score is calculated based on at least one judgment result; then, a quality-weighted score for the target connector is calculated, and a quality inspection report for the target connector is generated based on the quality-weighted score. The quality inspection report includes a design document on the target connector annotated with the quality-weighted score. The weights can be set according to the degree of influence of different indicators on signal performance, such as network attribute weights being higher than size deviations.

[0101] Specifically, for each non-compliant tab copper layer identified in the previous inspection, a corresponding deduction value is assigned according to a preset scoring rule, such as deducting X points for exceeding size limits, deducting Y points for overlap, and deducting Z points for lacking net attributes. Then, the deduction values ​​for all non-compliant items are summed to obtain the total deduction value. This total deduction value will serve as one of the important standards for evaluating the quality of the tab copper layer in the current PCB design, directly reflecting the compliance level of the tab copper layer design. In the design files accompanying the report, each target connector is marked with its corresponding weighted quality score; for example, a copper layer is marked with "75 points".

[0102] The above embodiments first calculate a score for each judgment result (such as size matching degree, quantity compliance, network attribute integrity, etc.), and then integrate them into a quality weighted score through a weighted algorithm. The specific score quantifies the overall quality level of the Tab copper sheet, accurately reflecting the design quality. Combined with the weighted score, a quality inspection report is generated, realizing the structured and hierarchical presentation of quality information. This makes the report not only include the score details of each individual judgment result, but also uses the final weighted score as the core indicator to clearly show the comprehensive quality of the Tab copper sheet.

[0103] Based on the assessment results, determine whether the target connector is compliant. Obtain the center coordinates, design dimensions, and reasons for non-compliance of the non-compliant target connectors. Then, create a problem annotation layer and mark the non-compliant target connectors in the problem annotation layer according to their center coordinates and design dimensions. Based on the marked problem annotation layer, the reasons for non-compliance, and the printed circuit board design documents, generate a quality inspection report for the target connectors. Reasons for non-compliance include dimensional deviations, quantity mismatches, and missing network attributes.

[0104] This application records the inspection results (such as circuit identification, area, board layer, compliance status, and deduction value) of all tab copper surfaces (including compliant and non-compliant ones) in a unified Excel list. The Excel format facilitates engineers' long-term storage of inspection data and allows for flexible subsequent filtering, sorting, and statistical processing, or for other purposes such as design review and cross-departmental collaboration, thereby improving the practicality of the results.

[0105] For each non-compliant tab copper, its key information will be recorded in detail, including the copper's specific coordinates in the PCB diagram (for accurate positioning), the reason for non-compliance (such as size exceeding the maximum threshold of the rule library, overlap with other tab copper, lack of network attributes, etc.), and the corresponding suggested modification methods, such as adjusting the area to the range of XX-XX square millimeters, moving it to a non-overlapping area and binding the corresponding DDR network, etc., so that engineers can clearly understand the essence of the problem and quickly formulate a modification plan.

[0106] Visual markers for problematic tab copper areas in PCB layouts are implemented as follows: First, create a dedicated layer in the PCB design file named `checkclass` for problem annotation. This layer is independent and will not affect the original design. Then, based on the dimensions of each non-compliant tab copper area, draw corresponding marker lines on the `checkclass` layer, such as border lines around the problematic copper area or prominent warning lines. This way, when engineers need to check for problems, they can simply enable the `checkclass` layer and visually locate the specific position of each problematic tab on the board through the highlighted marker lines. Combined with information from the front-end list, they can quickly identify and accurately locate the problem, avoiding the need to manually search for problem points in a complex PCB layout and improving modification efficiency.

[0107] After determining that the target connector is non-compliant, the above embodiments simultaneously acquire its center coordinates, design dimensions, and reasons for non-compliance. This information comprehensively outlines "where the problem is, what it is, and why it is non-compliant," avoiding the predicament of only knowing that a problem exists but being unable to trace its root cause. By creating an independent problem annotation layer and marking non-compliant connectors, the distribution of all non-compliant connectors can be quickly and intuitively seen in the PCB design view, improving problem identification efficiency. The final generated quality inspection report not only includes a textual list of non-compliance reasons but also links the marked problem annotation layer and the original design file, shortening the cycle of problem location, analysis, and correction, and providing efficient support for batch rectification of non-compliant connectors and ensuring DDR signal transmission performance.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0109] like Figure 6 As shown, embodiments of this application also provide a quality inspection device for printed circuit boards, the device comprising:

[0110] The acquisition module 601 is used to acquire the design files of the printed circuit board;

[0111] Analysis module 602 is used to analyze design documents and extract signal line information;

[0112] The identification module 603 is used to identify the target connector from the design file based on the signal line information; the target connector is attached to the signal line and is used to adjust the electromagnetic characteristics and impedance parameters of the signal line to optimize the signal transmission performance.

[0113] The judgment module 604 is used to obtain the design parameters of the target connecting piece and determine whether the design parameters meet the benchmark rules.

[0114] The generation module 605 is used to generate a quality inspection report for the target connector based on the judgment results.

[0115] As an optional implementation provided in this application, the analysis module 602 is specifically used for: determining the design board layer of the printed circuit board from the design file; obtaining multiple signal lines of the design board layer; filtering the target signal lines whose line identifiers carry target keywords from the multiple signal lines; and determining the signal line information of the target signal lines.

[0116] As an optional implementation method provided in this application embodiment, the analysis module 602 is specifically used for: obtaining the target area selected by the user from the design file; analyzing the target area and extracting the signal line information of the target area.

[0117] As an optional implementation provided in this application, the judgment module 604 is specifically used for: detecting whether the target connecting piece has network attributes; detecting whether different target connecting pieces overlap; detecting whether the design quantity of the target connecting pieces matches the reference quantity; detecting whether the design size of the target connecting piece matches the reference size; and detecting whether the design position of the target connecting piece matches the reference position.

[0118] As an optional implementation provided in this application, the judgment module 604 detects whether the design size of the target connecting piece matches the reference size, specifically used for: calculating a first area difference between the design area of ​​the target connecting piece and the reference area; wherein, the reference area is determined based on the area difference between multiple connecting pieces and the first connecting piece; determining whether the first area difference is less than or equal to a first area difference threshold; if the first area difference is greater than the first area difference threshold, then determining that the design size of the target connecting piece does not match the reference size.

[0119] As an optional implementation provided in this application, the generation module 605 is used to: obtain the center coordinates, board layer, and line identifier of the target connecting piece when the design size of the target connecting piece does not match the reference size; and generate a quality inspection report based on the design area of ​​the target connecting piece and the first area difference, as well as the center coordinates, board layer, and line identifier of the target connecting piece.

[0120] As an optional implementation provided in this application, the judgment module 604 detects whether the design size of the target connecting piece matches the reference size. Specifically, it is used to: draw the reference shape of the connecting piece on a preset plate according to the reference size; draw the design shape of the target connecting piece on the preset plate according to the design size of the target connecting piece; perform an intersection operation on the reference shape and the design shape to obtain the intersection area; calculate the second area difference between the intersection area and the reference area; and determine that the design size of the target connecting piece does not match the reference size if the second area difference is greater than the second area difference threshold.

[0121] As an optional implementation provided in this application, the judgment module 604 detects whether the design quantity of the target connector pieces matches the reference quantity. Specifically, it is used to: obtain a mapping relationship table between the signal line and the corresponding target connector piece according to the signal line information; determine the design quantity of the target connector piece according to the mapping relationship table; perform overlap judgment on the target connector pieces other than the first target connector piece to determine the overlap quantity of the target connector pieces; determine the effective quantity of the target connector pieces according to the design quantity and the overlap quantity; and determine that the design quantity of the target connector pieces matches the reference quantity when the effective quantity is the same as the reference quantity.

[0122] As an optional implementation provided in this application, the judgment module 604 detects whether the target connecting piece has network attributes. Specifically, it is used to: determine whether the design area of ​​the target connecting piece meets the reference area range, the reference area range includes the preset maximum and minimum area of ​​the connecting piece; if so, obtain the line identifier of the signal line corresponding to the target connecting piece; if the line identifier is empty, determine that the target connecting piece has no network attributes.

[0123] As an optional implementation provided in this application, the generation module 605 is specifically used for: calculating at least one result score based on at least one judgment result; calculating the quality weighted score of the target connector based on the at least one result score; and generating a quality inspection report based on the quality weighted score, wherein the quality inspection report includes a design document on the target connector in which the quality weighted score is marked.

[0124] As an optional implementation provided in this application, the generation module 605 is specifically used for: determining whether the target connecting piece is compliant based on the judgment result; obtaining the center coordinates, design dimensions, and reasons for non-compliance of the non-compliant target connecting piece; creating a problem annotation layer, and marking the non-compliant target connecting piece in the problem annotation layer according to the center coordinates and design dimensions; and generating a quality inspection report based on the marked problem annotation layer, reasons for non-compliance, and design documents.

[0125] For a description of the features in the embodiment of the printed circuit board quality inspection device, please refer to the relevant description of the embodiment of the printed circuit board quality inspection method, which will not be repeated here.

[0126] like Figure 7 As shown, embodiments of this application also provide an electronic device, including a memory 701 and a processor 702. The memory 701 stores a computer program, and the processor 702 is configured to run the computer program to perform the steps in any of the above-described embodiments of the printed circuit board quality inspection method.

[0127] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the printed circuit board quality inspection method when it is run.

[0128] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0129] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the printed circuit board quality inspection method.

[0130] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described embodiments of the printed circuit board quality inspection method.

[0131] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0132] The foregoing has provided a detailed description of a method, apparatus, equipment, medium, and product for quality inspection of printed circuit boards. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A method of inspecting the quality of a printed circuit board, characterized by, The method comprises: obtaining a design file of a printed circuit board; analyzing the design file to extract signal line information; identifying a target pad from the design file according to the signal line information; the target pad is attached to a signal line and is used to adjust electromagnetic characteristics and impedance parameters of the signal line to optimize signal transmission performance; obtaining design parameters of the target pad and determining whether the design parameters meet a reference rule; generating a quality inspection report of the target pad according to the determination result; wherein the determination of whether the design parameters meet the reference rule comprises: calculating a first area difference between a design area of the target pad and a reference area; determining whether the first area difference is less than or equal to a first area difference threshold; if the first area difference is greater than the first area difference threshold, it is determined that the design size of the target pad does not match the reference size; the determination process of the reference area is as follows: from a list of pad elements corresponding to double data rate signals of a board layer to which the target pad belongs, the area of each pad element is extracted, and then the area of the first pad element is taken as an initial comparison value; for the areas of the remaining pad elements, it is determined whether the difference between the area and the initial comparison value is less than a preset pad size threshold, the number n of differences less than the preset pad size threshold is counted, and the number m of differences greater than the preset pad size threshold is counted; if the number n is less than or equal to the number m, the reference area is equal to the area of the current pad element, and if the number n is greater than the number m, the reference area is equal to the initial comparison value; the generation of the quality inspection report of the target pad according to the determination result comprises: in the case where the design size of the target pad does not match the reference size, obtaining the center coordinates of the target pad, the board layer to which the target pad belongs, and the line identifier of the corresponding target signal line; generating the quality inspection report according to the design area of the target pad and the first area difference, and the center coordinates of the target pad, the board layer to which the target pad belongs, and the line identifier.

2. The method of claim 1, wherein, The analysis of the design file to extract signal line information comprises: determining a design board layer of the printed circuit board from the design file; obtaining a plurality of signal lines of the design board layer; screening a target signal line carrying a target keyword from the plurality of signal lines; determining signal line information of the target signal line.

3. The method of claim 1, wherein, The analysis of the design file to extract signal line information comprises: obtaining a target area selected by a user from the design file; analyzing the target area to extract signal line information of the target area.

4. The method of claim 1, characterized in that, The determination of whether the design parameters meet the reference rule further comprises at least one of the following: detecting whether the target pad has a network attribute; detecting whether different target pads overlap; detecting whether the design number of the target pad matches a reference number; detecting whether the design position of the target pad matches a reference position.

5. The method of claim 4, characterized in that, The detection of whether the design number of the target pad matches the reference number comprises: According to the signal line information, a mapping relationship table between the signal line and the corresponding target connection piece is obtained; According to the mapping relationship table, the design quantity of the target connection piece is determined; For other target connection pieces except the first target connection piece, overlap judgment is performed to determine the overlap quantity of the target connection piece; According to the design quantity and the overlap quantity, the effective quantity of the target connection piece is determined; In the case that the effective quantity is the same as the reference quantity, it is determined that the design quantity of the target connection piece matches the reference quantity.

6. The method of claim 4, characterized in that, The detection of whether the target connection piece has a network attribute includes: Judging whether the design area of the target connection piece meets a reference area range, the reference area range containing a pre-set maximum connection piece area and a minimum connection piece area; If yes, the line identifier of the signal line corresponding to the target connection piece is obtained; If the line identifier is empty, it is determined that the target connection piece has no network attribute.

7. The method of claim 4, wherein, According to the judgment result, the quality inspection report of the target connection piece is generated, including: According to at least one judgment result, at least one result score is calculated; According to the at least one result score, a quality weighted score of the target connection piece is calculated; According to the quality weighted score, the quality inspection report is generated, the quality inspection report containing a design file in which the quality weighted score is labeled on the target connection piece. According to the judgment result, the quality inspection report of the target connection piece is generated, including:

8. The method of claim 1, wherein, According to the judgment result, it is determined whether the target connection piece is compliant; The center coordinates, design size and non-compliance reason of the non-compliant target connection piece are obtained; A problem annotation layer is created, and the non-compliant target connection piece is marked in the problem annotation layer according to the center coordinates and the design size; According to the marked problem annotation layer, the non-compliance reason and the design file, the quality inspection report is generated. It includes: An acquisition module is used to acquire a design file of a printed circuit board; 9. A quality inspection apparatus for printed circuit boards, characterized by An analysis module is used to analyze the design file and extract signal line information; An identification module is used to identify a target connection piece from the design file according to the signal line information; The target connection piece is attached to the signal line and is used to adjust the electromagnetic characteristics and impedance parameters of the signal line to optimize the signal transmission performance; A judgment module is used to acquire design parameters of the target connection piece and judge whether the design parameters meet reference rules; A generation module is used to generate a quality inspection report of the target connection piece according to the judgment result; The judgment module is used to calculate a first area difference value between the design area of the target connection piece and a reference area; It is judged whether the first area difference value is less than or equal to a first area difference threshold value; If the first area difference value is greater than the first area difference threshold value, it is determined that the design size of the target connection piece does not match the reference size; ​ ​ The determination procedure of the reference area is as follows: extracting the area of each connecting pad element from the connecting pad element list corresponding to the double data rate signal of the board layer to which the target connecting pad belongs, and then taking the area of the first connecting pad element as an initial comparison value; For the areas of the remaining connecting pad elements, judging whether the difference between each area and the initial comparison value is less than a preset connecting pad size threshold, counting the number n of the connecting pad elements whose difference is less than the preset connecting pad size threshold, and counting the number m of the connecting pad elements whose difference is greater than the preset connecting pad size threshold; If the number n is less than or equal to the number m, the reference area is equal to the area of the current connecting pad element, and if the number n is greater than the number m, the reference area is equal to the initial comparison value; The generation module is configured to, in a case where the design size of the target connecting pad does not match the reference size, acquire the center coordinates of the target connecting pad, the board layer to which the target connecting pad belongs, and the line identifier of the corresponding target signal line; According to the design area of the target connecting pad, the first area difference, the center coordinates of the target connecting pad, the board layer to which the target connecting pad belongs, and the line identifier, the quality inspection report is generated.

10. An electronic device, comprising: Comprise: A memory for storing a computer program; A processor for implementing the steps of the quality inspection method of the printed circuit board according to any one of claims 1 to 8 when executing the computer program.

11. A computer readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium, and when the computer program is executed by the processor, the steps of the quality inspection method of the printed circuit board according to any one of claims 1 to 8 are implemented.

12. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor, and the steps of the quality inspection method of the printed circuit board according to any one of claims 1 to 8 are implemented.

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