A display motherboard and a leakage test method, and a display panel

Abstract

The present disclosure provides a display mother board and a leakage test method, and a display panel, and relates to the technical field of display, and comprises a first area and a second area, the first area comprises a plurality of areas for arranging the display panel, and the second area comprises a test transistor and a test capacitor, a plurality of switching transistors in the display panel are manufactured by using the same process as the test transistor; a first plate of the test capacitor receives a fixed potential, a second plate is connected to a first node, an output end of the test transistor and a test signal line are connected to the first node, and the test signal line is configured to transmit an electrical signal of the first node in a detection stage; and the test transistor is cut off in the detection stage. By arranging the test capacitor, the charge stored in the test capacitor can increase the leakage current effect of the test transistor in the detection stage, and the leakage current size of the test transistor can be accurately characterized.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display motherboard and a leakage current testing method, and a display panel. Background Technology

[0002] With the development of display technology, display devices are becoming increasingly common and are gradually being applied to people's daily work and life. Among them, OLED (Organic Light-Emitting Diode) display devices have become the mainstream trend in display panels due to their superior characteristics such as high contrast, thinness, wide viewing angle, fast response speed, wide operating temperature range, and relatively simple structure and manufacturing process.

[0003] OLED display devices typically include a bezel area with a driving circuit and a display area with multiple pixel units. Each pixel unit includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit is electrically connected to the driving circuit in the bezel area, and the driving circuit provides enable signals to the pixel circuit to control the pixel circuit to provide driving current to the light-emitting element. However, due to leakage current, the pixel circuits in current display devices experience unstable driving current output, affecting the brightness of the light-emitting element. In particular, with the application of frequency conversion driving technology in display devices, the leakage current problem in the pixel circuit can cause flickering when displaying images, impacting the user experience. Furthermore, due to limitations in the measurement accuracy of equipment, it is impossible to accurately characterize the leakage current effect of transistors. Summary of the Invention

[0004] To address the aforementioned technical issues, this disclosure provides a display motherboard, a leakage current testing method, and a display panel for accurately characterizing the leakage current effect of transistors and exploring the correlation between product performance and transistor performance.

[0005] In a first aspect, this disclosure provides a display motherboard, comprising: a first region and a second region surrounding the first region, the first region including a plurality of areas for setting a display panel, the second region including test transistors and test capacitors, wherein the plurality of switching transistors in the display panel are manufactured using the same process as the test transistors; The first plate of the test capacitor receives a fixed potential, the second plate of the test capacitor is connected to the first node, the output terminal of the test transistor and the test signal line are connected to the first node, and the test signal line is configured to transmit the electrical signal of the first node during the detection phase. During the detection phase, the test transistor is turned off.

[0006] Secondly, based on the same inventive concept, this disclosure provides a leakage current testing method for a display motherboard, using the display motherboard as described above for testing, including: Control the transistor to turn off; Obtain the voltage data of the first node.

[0007] Thirdly, based on the same inventive concept, this disclosure also provides a display panel, which is cut from the display motherboard as described above.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure provides a display motherboard, comprising: a first region and a second region surrounding the first region. The first region includes multiple areas for mounting a display panel, and the second region includes test transistors and test capacitors. Multiple switching transistors in the display panel are manufactured using the same process as the test transistors. The first plate of the test capacitor receives a fixed potential, and the second plate of the test capacitor is connected to a first node. The output terminal of the test transistor and a test signal line are connected to the first node, and the test signal line is configured to transmit an electrical signal from the first node during the detection phase. During the detection phase, the test transistors are turned off. By setting the test transistors and test capacitors in the second region of the display motherboard, the charge stored in the test capacitors can increase the leakage current effect of the test transistors during the detection phase. This increases the leakage current signal, which is previously low and difficult to measure accurately, to a range that can be measured with precision by the testing equipment. This is beneficial for accurately characterizing the leakage current magnitude of the test transistors, exploring the correlation between display product performance and the leakage current characteristics of the switching transistors, and provides a reference and basis for studying the reliability of the switching transistors. Since the test transistor and the switching transistor in the display panel are manufactured using the same process at the same time, the test results of the leakage current of the test transistor in this embodiment can accurately reflect the leakage current characteristics of the switching transistor in the actual display product. This can detect and eliminate defective products in the early stages of manufacturing, reduce waste in subsequent processing steps, and effectively improve the yield of the final product.

[0009] The display panel provided in this disclosure has the same technical effects as the display motherboard provided in this disclosure. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 The figure shown is a plan view of a display motherboard provided in an embodiment of this disclosure; Figure 2 As shown Figure 1 Equivalent circuit diagram of region A1 in the middle; Figure 3 As shown Figure 1 A schematic diagram of a cross-section along B-B'; Figure 4 As shown Figure 1 Another cross-sectional diagram along B-B'; Figure 5 As shown Figure 1 A schematic diagram of the connections of the devices in region A1; Figure 6 As shown Figure 1 A schematic diagram of a connection for a mid-pixel driving circuit; Figure 7 The diagram shown is a flowchart of a method for testing leakage current in a display motherboard according to an embodiment of this disclosure; Figure 8 As shown Figure 7 A detailed flowchart of the first step in the process; Figure 9 As shown Figure 7 Detailed flowchart of the second step; Figure 10 The figure shown is a plan view of a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0013] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0014] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0015] Figure 1 The figure shown is a plan view of a display motherboard provided in an embodiment of this disclosure. Figure 2 As shown Figure 1 Equivalent circuit diagram of region A1 in the middle. Figure 3 As shown Figure 1 Please refer to the schematic diagram of a cross-section along B-B'. Figures 1 to 3This disclosure provides a display motherboard 100, including a first region 10 and a second region 20 surrounding the first region 10. The first region 10 includes a plurality of areas for mounting a display panel 200. It is understood that the display motherboard 100 provided in the embodiments of this disclosure may have a plurality of first regions 10 and a plurality of second regions 20, and this disclosure does not limit it in this way. Figure 1 The illustration is based on the example of a display motherboard 100 comprising a second zone 20 surrounding a first zone 10. Figure 1 The number of display panels 200 is for illustrative purposes only. This disclosure does not limit the number, size, or arrangement of the display panels 200 in the display motherboard 100.

[0016] Please combine Figure 2 The second region 20 includes a test transistor T0 and a test capacitor C1. The plurality of switching transistors T11 in the display panel 200 are manufactured using the same process as the test transistor T0. The display motherboard 100 provided in this embodiment may include a pixel driving circuit 70, which may be located in the area where the display panel 200 is located. The pixel driving circuit 70 may include at least one switching transistor T11. The pixel driving circuit 70 may be arranged in an array and may also include capacitors and other devices. Figure 1 The position and arrangement of the pixel driving circuit 70 and the switching transistor are for illustrative purposes only, and this disclosure does not limit them. It can be understood that the display panel 200 includes sub-pixels arranged in an array, and each sub-pixel corresponds to a pixel driving circuit 70.

[0017] Since the test transistor T0 and the switching transistor T11 are fabricated using the same process at the same time, the leakage current characteristics of the test transistor T0 are highly consistent with those of the switching transistor T11 in the display panel 200, making the test results more representative. By characterizing the leakage current characteristics of the test transistor T0, the leakage current characteristics of each switching transistor T11 in the display panel 200 can be determined, which can indirectly characterize the performance of the display product under different process conditions, and further explore the correlation between the performance of the display product and the leakage current characteristics of the switching transistor T11.

[0018] Please refer to Figure 2 In this embodiment of the present disclosure, the first plate 01 of the test capacitor C1 receives a fixed potential, the second plate 02 of the test capacitor C1 is connected to the first node N0, the output terminal 11 of the test transistor T0 and the test signal line L1 are connected to the first node N0, and the test signal line L1 is configured to transmit the electrical signal of the first node N0 during the detection phase; during the detection phase, the test transistor T0 is turned off.

[0019] During the detection phase, test transistor T0 is set to the off state. Test capacitor C1 has the ability to store charge. By setting test capacitor C1, the leakage current effect of test transistor T0 can be increased, so as to accurately characterize the leakage current of test transistor T0. Test signal line L1 can transmit the electrical signal on the first node N0. Since test transistor T0 is in the off state, the current flowing to the first node N0 mainly comes from the charge of test capacitor C1. The weak leakage current output by test transistor T0 will cause the voltage of the first node N0 to change. By detecting the electrical signal on the first node N0, the leakage current characteristics of test transistor T0 can be characterized, and thus the leakage current characteristics of all switching transistors T11 on the same display motherboard 100 can be characterized.

[0020] Compared to traditional testing methods, the low leakage current of the test transistor T0 and the limitations of the measurement accuracy of the testing equipment make it impossible to accurately collect the low current, resulting in inaccurate measurement of the leakage current signal of the test transistor T0. The display motherboard 100 provided in this disclosure, by setting a test capacitor C1 in the second region 20, allows the charge stored in the test capacitor C1 to increase the leakage current effect of the test transistor T0 during the detection phase. This increases the low, inaccurately measurable leakage current signal to a range detectable by the testing equipment, thus facilitating accurate characterization of the leakage current magnitude of the test transistor T0. Since the test transistor T0 and the switching transistor T11 in the display panel 200 are manufactured using the same process, the test results of the leakage current of the test transistor T0 in this embodiment can accurately reflect the leakage current characteristics of the switching transistor T11 in the actual display product. Therefore, by integrating the test capacitor C1 connected to the test transistor T0 on the motherboard of the display panel 200, the charge storage capacity of the test capacitor C1 can increase the leakage current effect of the test transistor T0 during the detection phase, which is beneficial for accurately characterizing the leakage current characteristics of the switching transistor T11 within the display panel 200.

[0021] Understandably, after the display motherboard 100 is cut to form multiple display panels 200, the second region 20 will be removed and will not remain in the display panel 200. In this embodiment, the test transistor T0 and test capacitor C1 are placed in the second region 20, which does not occupy the space of the first region 10 in the display motherboard 100. After performing a leakage current test on the test transistor T0 in the display motherboard 100, the test transistor T0 and test capacitor C1 in the second region 20 can be directly removed. Performing leakage current detection on the test transistor T0 before cutting the display motherboard 100 can detect and reject defective products at an early stage, reduce waste in subsequent processing steps, and effectively improve the yield of the final product.

[0022] Please refer to Figure 3This disclosure provides a display motherboard 100, which includes a substrate 00, a test transistor T0 located on one side of the substrate 00, and a test capacitor C1 located between the substrate 00 and the test transistor T0 along a direction perpendicular to the plane of the substrate 00.

[0023] Specifically, the substrate 00 of the display motherboard 100 includes a rigid substrate and a flexible substrate. The rigid substrate includes glass, etc., and the flexible substrate includes polyimide, polyethylene terephthalate, etc. This disclosure does not limit the material of the substrate 00; it can be selected according to product requirements. The test transistor T0 is located on one side of the substrate 00, and the test transistor T0 and the switching transistor T11 in the display panel 200 are manufactured using the same process. Specifically, the test transistor T0 and the switching transistor T11 are typically thin-film transistors. The manufacturing process of the test transistor T0 and the switching transistor T11 is based on photolithography technology, forming each film layer through multiple deposition, exposure, development, and etching steps. Please refer to [reference needed]. Figure 3 The test transistor T0 includes a gate, an active layer 30, an input terminal 12 (source), and an output terminal 11 (drain). An insulating layer is also included between the gate and the active layer 30, and an insulating layer is also included between the active layer 30 and the source and drain. The source is electrically connected to the source region of the active layer 30 through a via, and the drain is electrically connected to the drain region of the active layer 30 through a via.

[0024] In this embodiment, the test capacitor C1 is located between the substrate 00 and the test transistor T0 along a direction perpendicular to the plane of the substrate 00. This structure, by stacking the test transistor T0 and the test capacitor C1 in the vertical direction, integrates the test transistor T0 and the test capacitor C1 into the same small area, which can significantly reduce the area occupied by the test transistor T0 and the test capacitor C1 on the substrate 00. More test capacitors C1 and test transistors T0 can be integrated in the limited space of the display motherboard 100, increasing the number of test points and improving test accuracy. This compact vertical structure can also effectively reduce parasitic effects such as resistance and capacitance caused by excessively long signal lines, ensuring a purer leakage current signal of the test transistor T0 during the detection stage, which is beneficial to improving the accuracy of detection. Furthermore, stacking the test transistor T0 and test capacitor C1 vertically reduces the area occupied by the display motherboard 100 while freeing up more space for the actual display panel 200, thus improving the space utilization of the display motherboard 100. This allows for the simultaneous fabrication of more display panels 200 on the same area of ​​the display motherboard 100, increasing production volume and reducing the manufacturing cost per display panel 200. It should be noted that multiple test transistors T0 and test capacitors C1 can also be introduced on the display motherboard 100, allowing for better characterization of leakage current through methods such as averaging. Additionally, when the display panel 200 includes different types of transistors, different test transistors T0 can be introduced for each type of transistor to perform leakage current testing on different types of transistors.

[0025] Thus, by placing the test capacitor C1 between the substrate 00 and the test transistor T0, the signal line length between the test transistor T0 and the test capacitor C1 can be shortened, reducing signal loss or other parasitic effects. The vertical stacking design of the test capacitor C1 and the test transistor T0 can reduce the space occupied by the display motherboard 100, improve the space utilization of the display motherboard 100, and increase the production volume of the display panel 200.

[0026] Please continue to refer to this. Figure 3 This disclosure provides a display motherboard 100, which further includes a first metal layer M1 and a capacitor metal layer MC. The first metal layer M1 is located on the side of the capacitor metal layer MC facing the substrate 00, and the capacitor metal layer MC is located between the first metal layer M1 and the test transistor T0. The first electrode 01 of the test capacitor C1 is located on the first metal layer M1, and the second electrode 02 of the test capacitor C1 is located on the capacitor metal layer MC. Understandably, an insulating layer is also included between the first metal layer M1 and the capacitor metal layer MC to achieve electrical isolation between the two.

[0027] Specifically, the first metal layer M1 is located on one side of the substrate 00, and the first electrode 01 of the test capacitor C1 is located on the first metal layer M1. In the manufacturing process, the first metal layer M1 can be formed by deposition (e.g., metal magnetron sputtering), and then photolithography is performed on the first metal layer M1 using a mask with a specific pattern, followed by etching to form the first electrode 01 of the test capacitor C1. The capacitor metal layer MC is located on the side of the first metal layer M1 facing away from the substrate 00. Furthermore, the capacitor metal layer MC is located between the first metal layer M1 and the test transistor T0. The second electrode 02 of the test capacitor C1 is disposed on the capacitor metal layer MC. Similarly, the second electrode 02 is also fabricated after the capacitor metal layer MC is formed by deposition, further processed by photolithography, etching, and other processes. That is, the first electrode 01 and the second electrode 02 of the test capacitor C1 can be fabricated simultaneously with the metal layers in the display motherboard 100 using existing processes in existing steps, without the need for additional processes or steps, which helps to reduce costs.

[0028] In this embodiment, by placing the two plates of the test capacitor C1 on two different metal layers, the size and spacing of the different plates in the test capacitor C1 can be controlled more precisely. This is beneficial for obtaining a stable and predictable capacitance value, and thus for improving the controllability of leakage current detection of the test transistor T0. The first plate O1 of the test capacitor C1 is located on the first metal layer M1, and the second plate O2 is located on the capacitor metal layer MC. The close distance between the first metal layer M1 and the capacitor metal layer MC can reduce signal loss and delay during transmission, which is beneficial for optimizing signal transmission during the detection process. The layered stacking design of the test capacitor C1 makes the test transistor T0 and the test capacitor C1 in the display motherboard 100 more compact in the direction perpendicular to the plane of the substrate 00, freeing up more space in the effective display panel 200 area of ​​the display motherboard 100, improving the space utilization of the display motherboard 100 and the production efficiency of the display panel 200.

[0029] Thus, by setting the first plate 01 of the test capacitor C1 in the first metal layer M1 and the second plate 02 in the capacitor metal layer MC, the test capacitor C1 can be manufactured using existing processes and procedures without the need for additional steps, which helps to reduce costs.

[0030] Please continue to refer to this. Figure 3 This disclosure provides a display motherboard 100, which includes a second metal layer M2, a fixed potential signal line L0, and an input terminal 12 and an output terminal 11 of a test transistor T0 located on the second metal layer M2. The fixed potential signal line L0 is connected to the first plate 01 of the test capacitor C1 through a via. The output terminal 11 of the test transistor T0 is connected to the second plate 02 of the test capacitor C1 through a via.

[0031] In one optional embodiment provided in this disclosure, the display motherboard 100 includes a substrate 00, a first metal layer M1, a capacitor metal layer MC, and a second metal layer M2. The first metal layer M1 is located between the substrate 00 and the capacitor metal layer MC, and the second metal layer M2 is located on the side of the capacitor metal layer MC facing away from the first metal layer M1. An insulating layer is included between adjacent metal layers to achieve electrical insulation between different metal layers. The input terminal 12 and output terminal 11 of the test transistor T0 are located on the second metal layer M2. Along a direction perpendicular to the plane of the display motherboard 100, the plate of the test capacitor C1 is located between the test transistor T0 and the substrate 00. The first plate 01 of the test capacitor C1 is located on the first metal layer M1. The fixed potential signal line L0 and the first plate 01 are located on different metal layers, and the fixed potential signal line L0 is connected to the first plate 01 of the test capacitor C1 through a via. The second plate 02 of the test capacitor C1 is located on the capacitor metal layer MC. The output terminal 11 of the test transistor T0 and the second plate 02 are located on different metal layers, and the output terminal 11 of the test transistor T0 is connected to the second plate 02 of the test capacitor C1 through a via. In this embodiment, the via serves as a conductive channel perpendicular to the plane of the display motherboard 100, and can be used to connect the test capacitor C1 and the test transistor T0, and the test capacitor C1 and the fixed potential signal line L0, with the shortest connection path, thereby reducing the signal transmission distance, reducing parasitic capacitance and resistance, and improving the accuracy of the detection results.

[0032] Compared to planar wiring, vias provide vertical and direct connections, resulting in a more robust connection and effectively reducing manufacturing defects such as open circuits and short circuits, thus improving electrical connection reliability. By placing the input terminal 12 and output terminal 11 of the test transistor T0 and the plates of the test capacitor C1 on different metal layers and connecting them separately vias, the planar space of the display motherboard 100 can be greatly saved, improving area utilization. Standardized via connections simplify automated alignment and connection in mass production, helping to improve production efficiency and reduce manufacturing costs.

[0033] Thus, by placing the test transistor T0, test capacitor C1, and fixed potential signal line L0 on different metal layers, and electrically connecting the test transistor T0 and test capacitor C1, and the test capacitor C1 and fixed potential signal line L0, respectively, through vias, the electrical connection problem in the three-dimensional stacked structure can be solved. The vertical vias can also optimize the signal path, improve connection reliability, and help improve the signal transmission stability during the leakage current detection process of the test transistor T0.

[0034] Figure 4 As shown Figure 1 Please refer to another cross-sectional diagram along line B-B'. Figure 3 and 4This disclosure provides a display motherboard 100, which includes a third metal layer M3 located on the side of the second metal layer M2 away from the substrate 00, and a fixed potential signal line L0 located in the second metal layer M2 and / or the third metal layer M3.

[0035] Please refer to Figure 3 In one optional embodiment provided in this disclosure, the display motherboard 100 includes a first metal layer M1, a capacitor metal layer MC, and a second metal layer M2. The first metal layer M1 is located on the side of the capacitor metal layer MC facing the substrate 00, and the second metal layer M2 is located on the side of the capacitor metal layer MC away from the first metal layer M1. The input terminal 12 and the output terminal 11 of the test transistor T0 are located on the second metal layer M2. The first plate 01 of the test capacitor C1 is located on the first metal layer M1, the second plate 02 is located on the capacitor metal layer MC, and the fixed potential signal line L0 is located on the second metal layer M2. The second plate 02 of the test capacitor C1 is electrically connected to the output terminal 11 of the test transistor T0 through a via, and the first plate 01 of the test capacitor C1 is electrically connected to the fixed potential signal line L0 through a via. In this embodiment, the fixed potential signal line L0 is located on the second metal layer M2. That is, the fixed potential signal line L0 is on the same layer as the input terminal 12 and the output terminal 11 of the test transistor T0. This effectively utilizes the wiring space of the second metal layer M2, eliminating the need for a separate metal layer to house the fixed potential signal line L0. By placing the fixed potential signal line L0 on the second metal layer M2, and since the second metal layer M2 is closer to the first metal layer M1 where the first electrode plate 01 of the test capacitor C1 is placed, the via length between the fixed potential signal line L0 and the first electrode plate 01 can be shortened, which helps reduce signal loss or interference during transmission.

[0036] Please refer to Figure 4In another optional embodiment provided in this disclosure, the display motherboard 100 includes a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, and a third metal layer M3. The capacitor metal layer MC is located between the first metal layer M1 and the second metal layer M2, and the third metal layer M3 is located on the side of the second metal layer M2 away from the capacitor metal layer MC. The input terminal 12 and the output terminal 11 of the test transistor T0 are located on the second metal layer M2. The first plate 01 of the test capacitor C1 is located on the first metal layer M1, and the second plate 02 is located on the capacitor metal layer MC. The second plate 02 of the test capacitor C1 is electrically connected to the output terminal 11 of the test transistor T0 through a via, and the first plate 01 of the test capacitor C1 is electrically connected to the fixed potential signal line L0 through a via. In this embodiment, the fixed potential signal line L0 is disposed on the third metal layer M3. It can be physically isolated from critical signal lines on the second metal layer M2 (such as the signal lines connecting the input terminal 12 and output terminal 11 of the test transistor T0) by using different metals. This effectively avoids signal crosstalk and electromagnetic interference, ensuring the signal purity of the test transistor T0 during the testing phase, thereby improving testing accuracy. This wiring method also optimizes the circuit layout, providing more space for complex circuit wiring and making the wiring method more flexible.

[0037] Thus, by setting the fixed potential signal line L0 in the second metal layer M2 or the third metal layer M3, more options and greater flexibility can be provided for the signal wiring on the display motherboard 100, making it easier to adapt to the manufacturing needs of display panels 200 of different sizes and types.

[0038] Figure 5 As shown Figure 1 Please refer to the connection diagram of each device in area A1. Figures 1 to 5 This disclosure provides a display motherboard 100, which includes a pad group P0 corresponding to a test transistor T0. The pad group P0 is located in the second region 20 and includes a first pad P1, a second pad P2, a third pad P3, and a fourth pad P4. The first pad P1 is connected to the gate of the test transistor T0, the second pad P2 is connected to the input terminal 12 of the test transistor T0, the third pad P3 is connected to the output terminal 11 of the test transistor T0, and the fourth pad P4 is connected to the first plate 01 of the test capacitor C1 through a fixed potential signal line L0.

[0039] In one optional embodiment provided in this disclosure, the second area 20 of the display motherboard 100 is provided with a pad group P0. The pad group P0 is used to perform external electrical connection and leakage current performance testing on the test transistor T0 during the production process. After the test is completed, the pad group P0 used for testing is cut off, leaving only the area on the display motherboard 100 used to make the display panel 200 for subsequent process manufacturing.

[0040] The pad group P0 includes four pads. The first pad P1 is connected to the gate of the test transistor T0, providing an on / off signal to the gate during the detection phase. The second pad P2 is connected to the input terminal 12 of the test transistor T0. The third pad P3 is connected to the output terminal 11 of the test transistor T0. Specifically, the third pad P3 is electrically connected to the output terminal 11 of the test transistor T0 and the second plate 02 of the test capacitor C1 via a test signal line L1, receiving the leakage current signal of the test transistor T0 during the detection phase. The fourth pad P4 is connected to the first plate 01 of the test capacitor C1 via a fixed potential signal line L0, outputting a fixed potential signal to the first plate 01 of the test capacitor C1 during the detection phase to detect the leakage current characteristics of the test transistor T0. By setting the pad group P0 in the second area 20 of the display motherboard 100, a standardized electrical interface can be provided for the leakage current detection of the test transistor T0, allowing external detection equipment to directly access each electrode of the test transistor T0 and each plate of the test capacitor C1. During the testing phase, testing equipment (such as a probe station) can quickly and accurately contact the pads in the pad group P0, thereby performing high-efficiency leakage current characteristic testing on the test transistor T0, which can greatly simplify the testing process.

[0041] The testing equipment is connected to the test transistor T0 and test capacitor C1 via pad group P0, which effectively reduces the probability of accidental contact between the testing equipment and other parts of the display motherboard 100, and reduces testing errors caused by improper connection. Simultaneously, the fixed pad group P0 helps ensure the consistency and repeatability of each test, thereby improving the reliability of the test results. Since the pads in the pad group P0 correspond to specific parts of the test transistor T0 and test capacitor C1, when a problem is found at a test node, the specific test area can be accurately located, facilitating rapid problem diagnosis and providing data support for subsequent process optimization. The standardized pad group P0 provided in this embodiment allows the testing equipment to quickly locate and contact the pads according to a preset program, achieving fully automated batch testing, thereby significantly improving production efficiency and reducing labor costs.

[0042] Thus, by setting the pad group P0 in the second area 20 of the display motherboard 100, an efficient, reliable and easily automated electrical interface can be provided for the test transistor T0 and test capacitor C1 on the display motherboard 100, which is beneficial to simplify the testing process; it is also beneficial to realize fully automatic batch testing of the display motherboard 100 by the testing equipment, improve the repeatability of the test, and thus improve the reliability of the test results.

[0043] Please refer to Figure 3This disclosure provides a display motherboard 100, and a test transistor T0 includes a top gate 40, an active layer 30 and a bottom gate 50. The top gate 40 is located on the side of the active layer 30 away from the substrate 00, and the bottom gate 50 is located on the side of the active layer 30 facing the substrate 00. The bottom gate 50 of the test transistor T0 is located in the capacitor metal layer MC.

[0044] In one optional embodiment provided in this disclosure, the test transistor T0 is a dual-gate transistor, comprising an active layer 30, a top gate 40, and a bottom gate 50. The bottom gate 50 and the top gate 40 are located on opposite sides of the active layer 30 along a direction perpendicular to the plane of the substrate 00. Specifically, the bottom gate 50 of the test transistor T0 is located in the capacitor metal layer MC, while the second electrode 02 of the test capacitor C1 is located in the capacitor metal layer MC. That is, the bottom gate 50 of the test transistor T0 can also serve as the second electrode 02 of the test capacitor C1, achieving efficient multi-functional integration. The bottom gate 50 of the test transistor T0 can be manufactured simultaneously with the test capacitor C1, thus simplifying the manufacturing process. It eliminates the need to separately place the second electrode 02 of the test capacitor C1 and the bottom gate 50 of the test transistor T0 in different metal layers, which helps reduce the thickness of the display motherboard 100, thereby facilitating the thinning of the display panel 200. It is not necessary to set the second plate 02 of the test capacitor C1 parallel to the bottom gate 50 of the test transistor T0 in the capacitor metal layer MC, which helps to reduce the occupation of the display motherboard 100, and thus facilitates the production of more display panels 200.

[0045] In this embodiment, the dual-gate test transistor T0 allows for more precise adjustment of its performance by simultaneously controlling the voltages of the top gate 40 and the bottom gate 50. Since the test transistor T0 and the switching transistor T11 in the display panel 200 are manufactured in the same process, it can be understood that the switching transistor T11 in the display panel 200 is also a dual-gate transistor, similarly allowing for precise control during the display process by simultaneously controlling the voltages of the top gate 40 and the bottom gate 50. This facilitates flexible optimization of the turn-on voltage, switching speed, and current output of the test transistor T0 during the testing phase, enabling the test transistor T0 to accurately simulate the real leakage current characteristics of the switching transistor T11 in the display panel 200 under different operating modes.

[0046] Furthermore, the bottom gate 50 of the test transistor T0 is located on the side of the active layer 30 facing the substrate 00, and can serve as a light-shielding layer or shielding layer, effectively reducing the influence of external light or electric field on the active layer 30 of the test transistor T0. Similarly, the bottom gate 50 of the switching transistor T11 in the display panel 200 can also serve as a light-shielding layer or shielding layer, effectively reducing the influence of external light or electric field on the active layer 30 of the switching transistor T11, which is beneficial to improving the long-term stability and reliability of the switching transistor T11, and is crucial for manufacturing a high-quality, long-life display panel 200.

[0047] Thus, by using the bottom gate 50 of the dual-gate test transistor T0 as the second plate 02 of the test capacitor C1, it is beneficial to simplify the manufacturing process, reduce the thickness of the display motherboard 100, facilitate the high-density integration of functional devices in the display motherboard 100, and improve the space utilization of the display motherboard 100.

[0048] Please refer to Figure 3 and Figure 4 This disclosure provides a display motherboard 100, in which the two plates of the test transistor T0 and the test capacitor C1 overlap along the thickness direction of the display motherboard 100.

[0049] In one optional embodiment provided in this disclosure, the test capacitor C1 includes a first electrode 01 and a second electrode 02. The first electrode 01 is located in the first metal layer M1 of the display motherboard 100, and the second electrode 02 is located in the capacitor metal layer MC of the display motherboard 100. In a direction perpendicular to the plane of the display motherboard 100, the two electrodes of the test capacitor C1 overlap with the test transistor T0. By setting the test transistor T0 and the test capacitor C1 to overlap in the thickness direction of the display motherboard 100, space is rationally utilized, the planar area occupied by the display motherboard 100 is reduced, and more space is left for the actual display panel 200 area within the limited size of the display motherboard 100. This allows more display panels 200 to be produced on a single display motherboard 100, which is beneficial for improving production efficiency and yield.

[0050] In this embodiment, the overlapping design of the test transistor T0 and the test capacitor C1 along the thickness direction of the display motherboard 100 breaks the traditional planar layout. Components that might otherwise need to be placed side-by-side are stacked vertically, making it possible to integrate more complex and powerful test circuits within micrometer or even nanometer-scale spaces. This provides a technological foundation for the manufacturing of more refined and intelligent display panels 200 in the future. In some cases, this overlapping design can also enable component sharing. For example, a layer of the bottom gate 50 of the dual-gate test transistor T0 can also serve as the second electrode plate 02 of the test capacitor C1, reducing manufacturing steps and material consumption, and further lowering production costs.

[0051] Thus, by setting the test transistor T0 and the test capacitor C1 to overlap in the thickness direction of the display motherboard 100, the space utilization rate can be improved, the high-density integration of functional devices in the display motherboard 100 can be achieved, the area occupied by the display motherboard 100 can be reduced, and the production efficiency of the display panel 200 can be improved.

[0052] Figure 6 As shown Figure 1 A connection diagram of a mid-pixel driving circuit is shown below. Figures 1 to 6This disclosure provides a display motherboard 100, and a display panel 200 including a pixel driving circuit 70. The display panel 200 is formed by cutting the display motherboard 100. The pixel driving circuit 70 includes a driving transistor T3, a threshold compensation transistor T4 and a first reset transistor T5. The threshold compensation transistor T4 and the first reset transistor T5 are both connected to the gate of the driving transistor T3. The switching transistor T11 is at least one of the threshold compensation transistor T4 or the first reset transistor T5.

[0053] In one optional embodiment provided in this disclosure, taking the 8T2C pixel driving circuit 70 as an example, the pixel driving circuit 70 includes a first light-emitting control transistor T1, a write transistor T2, a driving transistor T3, a threshold compensation transistor T4, a first reset transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a bias transistor T8, a first capacitor Cboost, and a second capacitor Cst; the two plates of the first capacitor Cboost are respectively connected to the third scan line SP and the third control node N3; the two plates of the second capacitor Cst are respectively connected to the power signal line PVDD and the third control node N3; the gate of the driving transistor T3 is connected to the third control node N3, the first terminal of the driving transistor T3 is connected to the first control node N1, and the second terminal of the driving transistor T3 is connected to the second control node N2; one terminal of the first reset transistor T5 is connected to the first reset signal line Vref1, the other terminal of the first reset transistor T5 is connected to the first capacitor Cboost, the third control node N3, and one terminal of the threshold compensation transistor T4, and the gate of the first reset transistor T5 is connected to the first scan line S1N. The other terminal of threshold compensation transistor T4 is connected to the second control node N2, and the gate of threshold compensation transistor T4 is connected to the second scan line S2N. The terminals of write transistor T2 are connected to the data signal line Vdata and the first control node N1, respectively, and the gate of write transistor T2 is connected to the third scan line SP and the first capacitor Cboost. The terminals of the first light-emitting control transistor T1 are connected to the power signal line PVDD and the first control node N1, respectively, and the gate is connected to the light-emitting control line EMIT. The terminals of the second light-emitting control transistor T6 are connected to the second control node N2 and the fourth control node N4, respectively, and the gate of the second light-emitting control transistor T6 is connected to the light-emitting control line EMIT. The terminals of the second reset transistor T7 are connected to the second reset signal line Vref2 and the fourth control node N4, respectively, and the fourth control node N4 is connected to the anode of the light-emitting element. The gate of the second reset transistor T7 is connected to the fourth scan line SP*. The terminals of the bias transistor T8 are connected to the bias signal line Vi3 and the first control node N1, respectively, and the gate is connected to the fourth scan line SP*. It should be noted that the type of transistor is not limited in the pixel driving circuit 70 of this embodiment. Furthermore, Figure 6 The structure of the pixel driving circuit 70 shown is for illustrative purposes only, and this disclosure is not limited thereto.

[0054] The driving transistor T3 controls the current flowing through the light-emitting element, thereby determining the brightness of the pixel. The threshold compensation transistor T4 and the first reset transistor T5 are electrically connected to the gate of the driving transistor T3. The threshold compensation transistor T4 compensates for the threshold voltage drift of the driving transistor T3. The threshold voltage of the driving transistor T3 can change due to uneven manufacturing processes or prolonged use, leading to inconsistent brightness among different pixels. Through compensation, even if the performance of the driving transistor T3 in different pixel driving circuits 70 differs, each pixel can receive a stable and uniform driving current, ensuring that different pixels emit the same brightness under the same driving signal, thus significantly improving the uniformity of the image. The first reset transistor T5 can quickly and effectively clear residual charge in the pixel driving circuit 70, ensuring that the pixel driving circuit 70 is reset to a preset state at the beginning of each display cycle to eliminate afterimages and improve image clarity and dynamic performance.

[0055] In this embodiment, the switching transistor T11 in the display panel 200, manufactured simultaneously and using the same process as the test transistor T0, can be the first reset transistor T5 in the pixel driving circuit 70, or it can be the threshold compensation transistor T4 in the pixel driving circuit 70, or it can be both the first reset transistor T5 and the threshold compensation transistor T4 in the pixel driving circuit 70. This disclosure does not limit this to any particular type. By performing leakage current characteristic tests on the test transistor T0 in the display motherboard 100 during the manufacturing process, this embodiment of the disclosure can obtain the leakage current characteristics and related performance parameters of the switching transistor T11 (e.g., the threshold compensation transistor T4 and the first reset transistor T5) in the display panel 200 based on the characterization of the leakage current characteristics of the test transistor T0. Since the threshold compensation transistor T4, the first reset transistor T5, and the driving transistor T3 are electrically connected to their gates, the leakage current of these two transistors may affect the current flowing through the driving transistor T3, thereby affecting the brightness of the light-emitting element. Obtaining the leakage current characteristics and related performance parameters of the threshold compensation transistor T4 and the first reset transistor T5 is beneficial for exploring the correlation between the performance of display products and the leakage current characteristics of the switching transistor T11, and provides a reference and basis for studying the reliability of the switching transistor T11.

[0056] Thus, by fabricating at least one of the threshold compensation transistor T4 or the first reset transistor T5 in the pixel driving circuit 70 in the same process as the test transistor T0, the leakage current characteristics and performance parameters of the threshold compensation transistor T4 or the first reset transistor T5 can be characterized based on the detected leakage current characteristics of the test transistor T0. This is beneficial for exploring the correlation between the performance of the display product and the leakage current characteristics of the switching transistor T11, and provides a solid technical foundation for manufacturing a high-quality, high-reliability display panel 200.

[0057] Please refer to Figures 1 to 6 This disclosure provides a display motherboard 100, wherein the test transistor T0 is an oxide transistor.

[0058] In one optional embodiment provided in this disclosure, the test transistor T0 and the switching transistor T11 in the display panel 200 are manufactured in the same process and using the same technology. That is, when at least one of the threshold compensation transistor T4 and the first reset transistor T5 in the pixel driving circuit 70 is an oxide transistor, the test transistor T0 is also an oxide transistor. Therefore, the detection of the test transistor T0 and the obtained leakage current performance parameters can represent the leakage current characteristics of the threshold compensation transistor T4 and the first reset transistor T5.

[0059] Oxide semiconductor materials have a much higher electron mobility than amorphous silicon, resulting in oxide transistors with faster switching speeds and higher current driving capabilities. In the pixel driving circuit 70, the oxide transistor, acting as a threshold compensation transistor T4 or a first reset transistor T5, can transmit the compensation signal or reset signal to the driving transistor T3 more quickly and accurately, facilitating rapid compensation of the threshold voltage drift of the driving transistor T3 or rapid release of residual charge.

[0060] Due to their high mobility and low power consumption, oxide transistors are widely used in high-resolution, high-refresh-rate OLED and LCD panels. Therefore, using oxide transistors as test transistors T0 allows for a more realistic simulation and testing of the performance of switching transistors T11 in these panels, providing stronger assurance for product quality control. However, oxide transistors have very low cutoff current, approaching that of ideal insulators. Therefore, when test transistor T0 is in the cutoff state, its leakage current is extremely weak. Due to limitations in the measurement accuracy of the testing equipment, the low leakage current signal of the oxide transistor cannot be accurately collected, resulting in inaccurate measurement of the leakage current. By using the display motherboard 100 provided in this disclosure, a test capacitor C1 and a test transistor T0 are set in the second region 20 of the display motherboard 100. The charge storage capacity of the test capacitor C1 increases the leakage current effect of the test transistor T0. Even when the test transistor T0 is an oxide transistor, the leakage current magnitude can be accurately characterized, improving the accuracy of the test results and thus enhancing the accurate characterization of the leakage current characteristics of the switching transistor T11 in the display panel 200.

[0061] Of course, in some other embodiments, the test transistor T0 can also be other types of transistors besides oxide transistors, such as low-temperature polysilicon transistors, etc. This disclosure does not limit this. When the test transistor T0 is other types of transistors, the technical solution provided by this disclosure can also detect its leakage current characteristics.

[0062] Figure 7 The diagram shown is a flowchart of a method for testing leakage current in a display motherboard according to an embodiment of this disclosure. Please refer to it. Figures 1 to 7 This disclosure provides a leakage current testing method for a display motherboard 100, which uses the display motherboard 100 as described above for testing, including: step S1, controlling the test transistor T0 to turn off; step S2, acquiring the voltage data of the first node N0.

[0063] Specifically, in step S1, by applying an appropriate gate voltage to the gate of the test transistor T0, the test transistor T0 can be turned off, that is, the test transistor T0 on the display motherboard 100 is completely turned off. Turning off the test transistor T0 ensures that the current flowing to the first node N0 is mainly leakage current, rather than normal conduction current, thereby making leakage current measurement more sensitive and accurate.

[0064] In step S2, with the test transistor T0 off, the voltage at the first node N0 is measured. The first node N0 is electrically connected to the second plate O2 of the test capacitor C1 and the output terminal 11 of the test transistor T0. Since the test transistor T0 is off, the current flowing to the first node N0 mainly originates from the charge of the test capacitor C1. The weak leakage current output from the output terminal 11 of the test transistor T0 causes a change in the voltage at the first node N0. By monitoring the rate of change of the voltage at the first node N0, combined with the fixed voltage input to the first plate O1 of the test capacitor C1, the magnitude of the leakage current can be assessed. Indirectly assessing the leakage current characteristics of the test transistor T0 by measuring the voltage change at the first node N0 is more feasible and accurate than directly measuring the weak leakage current.

[0065] Thus, during the testing phase, the leakage current data of the test transistor T0 can be obtained by controlling the turn-off of the test transistor T0 and acquiring the voltage data of the first node N0. The testing process is simple and easy to promote and apply in the production process.

[0066] Please continue to refer to this. Figures 1 to 7 This disclosure provides a leakage current testing method for a display motherboard 100, which further includes: adjusting the display motherboard 100 to a preset temperature and light source before conducting the test.

[0067] In one optional embodiment provided in this disclosure, the entire display motherboard 100 is adjusted to specific temperature and lighting conditions before the above measurements are performed. Optionally, the leakage current detection of the test transistor T0 can be performed in a dark indoor environment at room temperature, or in a bright outdoor environment at room temperature, to simulate the leakage current effect of the switching transistor T11 in different usage scenarios. Further, different temperature gradients can be set while keeping the lighting conditions constant, and the leakage current detection of the test transistor T0 can be performed with a single temperature variable. For example, the preset temperature is greater than or equal to 60°C and less than or equal to 80°C; or the preset temperature is greater than or equal to 70°C and less than or equal to 80°C; or the preset temperature is greater than or equal to 60°C and less than or equal to 70°C, etc., where the temperature gradient interval can be 1°C, 3°C, 5°C, etc., which are not listed here, as long as the preset temperature is within the range of greater than or equal to 60°C and less than or equal to 80°C. Similarly, under constant temperature conditions, different illumination gradients can be set to detect the leakage current of the test transistor T0 using a single illumination variable. For example, under indoor dark conditions, the screen illumination of the display motherboard 100 can be set to 200 nits, 300 nits, 400 nits, 500 nits, etc.; or, under outdoor bright light conditions, the screen illumination of the display motherboard 100 can be set to 1000 nits, 1200 nits, 1400 nits, 1800 nits, 2000 nits, etc. The illumination gradient interval can also be other values, and this disclosure does not limit this. The above are merely examples; the preset temperature and illumination can also be other values, and this disclosure does not limit this. Based on the final usage scenario of the display product, different temperature and illumination conditions can be simulated for testing, thereby more realistically reflecting the leakage current performance of the test transistor T0 in the actual working environment. This makes the test results of the test transistor T0 closer to the real usage scenario, thus achieving more reliable and accurate leakage current detection. This makes the test results more valuable, effectively filtering out products that are unstable in extreme environments, and improving the reliability and stability of the final product.

[0068] Figure 8 As shown Figure 7 For a detailed flowchart of the first step, please refer to [link / reference]. Figures 1 to 8This disclosure provides a leakage current testing method for a display motherboard 100. The display motherboard 100 includes a first pad P1, a second pad P2, a third pad P3, and a fourth pad P4. The first pad P1 is connected to the gate of a test transistor T0, the second pad P2 is connected to the input terminal 12 of the test transistor T0, the third pad P3 is connected to the output terminal 11 of the test transistor T0, and the fourth pad P4 is connected to the first plate O1 of the test capacitor C1 through a fixed potential signal line L0.

[0069] In step S1, controlling the test transistor T0 to turn off specifically involves: step S11: the voltage value of the voltage signal input to the first pad P1 is less than 0; step S12: the voltage value of the voltage signal input to the second pad P2 is less than 0.

[0070] Specifically, in step S11, the first pad P1 is electrically connected to the gate of the test transistor T0, and the voltage value of the voltage signal input to the first pad P1 is less than 0. In step S12, the threshold voltage Vth of the oxide transistor is approximately 0.3V, and the off state requires Vgs < |Vth|. That is, when the test transistor T0 is an oxide transistor, by applying a voltage signal to a specific pad and controlling Vgs within the range of less than 0V, the test transistor T0 can be kept in the off state, which can be used for accurate leakage current measurement. For example, the voltage value connected to the first pad P1 is -7V, and the voltage value connected to the second pad P2 is -4V. Of course, the voltage values ​​connected to the first pad P1 and the second pad P2 can also be other values, and this disclosure does not limit them. Setting the voltage value of the voltage signal input to the second pad P2 connected to the input terminal 12 of the test transistor T0 within the range of less than 0V ensures that the voltage at the input terminal 12 will not cause the test transistor T0 to turn on unexpectedly, which helps to ensure the accuracy of the detection process.

[0071] By setting the voltage value of the voltage signal connected to the first pad P1 to less than 0V and the voltage value of the voltage signal connected to the second pad P2 to less than 0V, it can be ensured that the test transistor T0 is in a more complete off state. Thus, the leakage current characteristics of the test transistor T0 in the display motherboard 100 can be determined according to the leakage current test method of the display motherboard 100 provided in this disclosure, so that the voltage change measured at the first node N0 comes almost entirely from the leakage current effect of the test transistor T0 itself, rather than the weak conduction current on the test transistor T0.

[0072] Thus, by applying a negative voltage to the gate and input terminal 12 of the test transistor T0, it can be ensured that the test transistor T0 is in the off state, achieving high-precision and high-reliability detection of leakage current of the test transistor T0 on the display motherboard 100. This not only helps to screen out defective products in the early stages of manufacturing, but also provides a strong guarantee for the production of high-quality, long-life display panels 200.

[0073] Figure 9 As shown Figure 7 For a detailed flowchart of the second step, please refer to [link / reference]. Figures 1 to 9 This disclosure provides a leakage current testing method for a display motherboard 100. The display motherboard 100 includes a test signal line L1 and a test capacitor C1. The test signal line L1 is connected to the output terminal 11 of the test transistor T0 and the second plate 02 of the test capacitor C1. In step S2, obtaining the voltage data of the first node N0 includes: step S21: the voltage value of the voltage signal input to the fourth pad P4 is equal to the voltage value of the operating power supply when the display panel 200 is displayed; step S22: obtaining the voltage data of the output terminal 11 of the test transistor T0 through the third pad P3 and the test signal line L1; step S23: changing the preset temperature and illumination, and comparing and analyzing the voltage data of the output terminal 11 under different test conditions.

[0074] Specifically, in step S21, the voltage value of the voltage signal input to the fourth pad P4 is equal to the operating power supply voltage of the display panel 200 during normal operation, which can provide a stable and realistic operating potential for the first plate O1 of the test capacitor C1. Further simulating real lighting and temperature allows the entire test environment to closely match the state of the display panel 200 in actual use, making the test results more accurate in predicting the product's performance in the hands of consumers and significantly improving the reliability of the test results.

[0075] In step S22, the third pad P3 is electrically connected to the output terminal 11 of the test transistor T0 and the second plate 02 of the test capacitor C1 via the test signal line L1. This is used to obtain the voltage data of the output terminal 11 of the test transistor T0 through the test signal line L1. Combined with the voltage value of the working power supply displayed on the display panel 200 input to the first plate 01 of the test capacitor C1 by the fourth pad P4, the leakage current data of the test transistor T0 can be obtained, which is used to characterize the leakage current characteristics of the test transistor T0.

[0076] In step S23, the preset temperature and illumination are changed. By conducting tests under different temperature and illumination conditions, the leakage current characteristics of the test transistor T0 can be comprehensively and realistically evaluated. This is crucial for screening out defective products whose performance will significantly degrade or fail under extreme environments. It is beneficial to efficiently eliminate potential environmentally sensitive defective products in the early stages of manufacturing, thereby significantly improving the yield of the final product and reducing after-sales maintenance costs. By comparing and analyzing the voltage data under different test conditions, it is helpful to diagnose the type of defect. For example, if the voltage data detected at the output terminal 11 of the test transistor T0 changes significantly at high temperatures, it may indicate that there is a heat-sensitive defect in the insulating layer of the test transistor T0; if the detected voltage data changes significantly under strong light, it may indicate that there is a light-sensitive defect in the active layer 30 of the test transistor T0. This in-depth analysis helps to optimize the manufacturing process and further explore the characteristics of the test transistor T0.

[0077] Figure 10 The diagram shown is a plan view of a display panel provided in an embodiment of this disclosure. Please refer to it. Figure 10 This disclosure provides a display panel 200, which is cut from the display motherboard 100 as described above. The display panel 200 provided in this disclosure embodiment can be a display panel 200 in any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display panel 200 provided in this disclosure embodiment has the beneficial effects of the display motherboard 100 provided in this disclosure embodiment. For details, please refer to the specific descriptions of the display motherboard 100 in the above embodiments; these will not be repeated here.

[0078] Understandable Figure 10 The rounded rectangle structure is used as an example to illustrate one shape of the display panel 200. In some other embodiments of this disclosure, the display panel 200 may also be square, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0079] In summary, this disclosure provides a display motherboard, a leakage current testing method, and a display panel, comprising: a first region and a second region surrounding the first region. The first region includes multiple areas for mounting the display panel, and the second region includes test transistors and test capacitors. Multiple switching transistors in the display panel are fabricated using the same process as the test transistors. The first plate of the test capacitor receives a fixed potential, and the second plate of the test capacitor is connected to a first node. The output terminal of the test transistor and a test signal line are connected to the first node. The test signal line is configured to transmit an electrical signal from the first node during the detection phase; during the detection phase, the test transistor is turned off. By integrating the test capacitor connected to the test transistors on the display panel motherboard, the leakage current effect of the test transistors during the detection phase can be increased through the charge storage capacity of the test capacitor, which is beneficial for accurately characterizing the leakage current characteristics of the switching transistors within the display panel. By placing the test capacitor between the substrate and the test transistors, the space occupied by the display motherboard can be reduced, improving the space utilization of the display motherboard and increasing the production volume of the display panel. By placing the first plate of the test capacitor in a first metal layer and the second plate in a capacitor metal layer, the fabrication of the test capacitor can be completed using existing processes and procedures without adding any new processes, which helps to reduce costs. By placing the fixed-potential signal lines on the second or third metal layer, more selectivity and greater flexibility can be provided for signal wiring on the display motherboard, facilitating adaptation to the manufacturing needs of display panels of different sizes and types. By setting pad groups in the second area of ​​the display motherboard, an efficient, reliable, and easily automated electrical interface can be provided for the test transistors and test capacitors on the display motherboard, enabling fully automated batch testing of the display motherboard by testing equipment and improving test repeatability. Using the bottom gate of the dual-gate test transistor as the second plate of the test capacitor simplifies the manufacturing process and reduces the thickness of the display motherboard. By fabricating at least one of the threshold compensation transistor or the first reset transistor in the pixel driving circuit in the same process as the test transistor, the leakage current characteristics and performance parameters of the threshold compensation transistor or the first reset transistor can be characterized based on the detected leakage current characteristics of the test transistor. This facilitates exploring the correlation between display product performance and the leakage current characteristics of switching transistors, providing a solid technical foundation for manufacturing high-quality, high-reliability display panels.

[0080] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display motherboard, characterized in that, include: A first region and a second region surrounding the first region, the first region including multiple areas for setting up a display panel, the second region including test transistors and test capacitors, the multiple switching transistors in the display panel being manufactured using the same process as the test transistors; The first plate of the test capacitor receives a fixed potential, the second plate of the test capacitor is connected to the first node, the display motherboard includes a pad group corresponding to the test transistor, the pad group is located in the second area, the pad group includes a first pad and a second pad, the first pad is connected to the gate of the test transistor, the second pad is connected to the input terminal of the test transistor, the output terminal of the test transistor and a test signal line are connected to the first node, and the test signal line is configured to transmit the electrical signal of the first node during the detection phase; During the detection phase, the test transistor is turned off.

2. The display motherboard as described in claim 1, characterized in that, The display motherboard includes a substrate, the test transistor is located on one side of the substrate along a direction perpendicular to the plane of the substrate, and the test capacitor is located between the substrate and the test transistor.

3. The display motherboard as described in claim 2, characterized in that, The display motherboard further includes a first metal layer and a capacitor metal layer. The first metal layer is located on the side of the capacitor metal layer facing the substrate, and the capacitor metal layer is located between the first metal layer and the test transistor. The first plate of the test capacitor is located in the first metal layer, and the second plate of the test capacitor is located in the capacitor metal layer.

4. The display motherboard as described in claim 3, characterized in that, The display motherboard includes a second metal layer and a fixed potential signal line, and the input terminal and the output terminal of the test transistor are located on the second metal layer; The fixed potential signal line is connected to the first plate of the test capacitor through a via. The output terminal of the test transistor is connected to the second plate of the test capacitor through a via.

5. The display motherboard as described in claim 4, characterized in that, The display motherboard includes a third metal layer located on the side of the second metal layer away from the substrate, and the fixed potential signal line is located in the second metal layer and / or the third metal layer.

6. The display motherboard as described in claim 4, characterized in that, The pad group includes a third pad and a fourth pad. The third pad is connected to the output terminal of the test transistor, and the fourth pad is connected to the first plate of the test capacitor through the fixed potential signal line.

7. The display motherboard as described in claim 3, characterized in that, The test transistor includes a top gate, an active layer, and a bottom gate. The top gate is located on the side of the active layer away from the substrate, and the bottom gate is located on the side of the active layer facing the substrate. The bottom gate of the test transistor is located in the capacitor metal layer.

8. The display motherboard as described in claim 1, characterized in that, Along the thickness direction of the display motherboard, the two plates of the test transistor overlap with those of the test capacitor.

9. The display motherboard as described in claim 1, characterized in that, The display panel includes a pixel driving circuit, which includes a driving transistor, a threshold compensation transistor, and a first reset transistor. The threshold compensation transistor and the first reset transistor are both connected to the gate of the driving transistor. The switching transistor is at least one of the threshold compensation transistor or the first reset transistor.

10. The display motherboard as described in claim 1, characterized in that, The test transistor is an oxide transistor.

11. A method for testing leakage current in a display motherboard, characterized in that, Testing is performed using the display motherboard as described in any one of claims 1-10, including: Control the transistor to turn off; Obtain the voltage data of the first node.

12. The leakage current testing method for the display motherboard as described in claim 11, characterized in that, Also includes: The display motherboard was tested after being adjusted to the preset temperature and light intensity.

13. The leakage current testing method for the display motherboard as described in claim 11, characterized in that, The display motherboard includes a first pad, a second pad, a third pad, and a fourth pad. The first pad is connected to the gate of the test transistor, the second pad is connected to the input terminal of the test transistor, the third pad is connected to the output terminal of the test transistor, and the fourth pad is connected to the first plate of the test capacitor through a fixed potential signal line. The control test transistor shutdown is specifically as follows: The voltage value of the voltage signal input to the first pad is less than 0; The voltage value of the voltage signal input to the second pad is less than 0.

14. The leakage current testing method for the display motherboard as described in claim 13, characterized in that, The display motherboard includes a test signal line and a test capacitor. The test signal line is connected to the output terminal of the test transistor and the second plate of the test capacitor. The process of obtaining the voltage data of the first node includes: The voltage value of the voltage signal input to the fourth pad is equal to the voltage value of the power supply when the display panel is displaying; The voltage data of the output terminal of the test transistor is obtained through the third pad and the test signal line; By changing the preset temperature and illumination, the voltage data at the output terminal under different test conditions are compared and analyzed.

15. A display panel, characterized in that, It is cut from the display motherboard as described in any one of claims 1-10.

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