Semiconductor process chamber and thin film deposition process

Abstract

The invention provides a semiconductor process chamber and a thin film deposition process, and relates to the technical field of semiconductors. The semiconductor process chamber comprises a chamber body, a bearing assembly and a shielding assembly, the shielding assembly comprises a driving structure, a first shielding ring and a second shielding ring, the first shielding ring comprises a plurality of arc-shaped shielding sections in the circumferential direction of the first shielding ring, and the driving structure is connected to the shielding sections and is configured to drive the shielding sections to move in the radial direction; the first shielding ring, the second shielding ring and the wafer are coaxially arranged and are configured as follows: the ring inner diameter of the second shielding ring is larger than that of the first shielding ring, two deposition periods can be continuously carried out, and in the first deposition period and the second deposition period, the first shielding ring and the second shielding ring are arranged coaxially; a first shielding structure and a second shielding structure which are formed by the first shielding ring, the second shielding ring and the film layers deposited on the inner walls of the corresponding rings sequentially shield the upper portion of the edge ineffective area of the wafer. According to the semiconductor process chamber, the cavity opening cleaning maintenance frequency of the semiconductor process chamber can be reduced, and the maintenance convenience and the productivity of the semiconductor process chamber are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor process chamber and thin film deposition process. Background Technology

[0002] Thin film deposition is an important process in the fabrication of semiconductor devices. During thin film deposition, the back side of the wafer must be kept clean to ensure wafer quality and reduce contact contamination from metrology tools and other equipment.

[0003] In related technologies, some process chambers have a shielding ring with an inner diameter less than or equal to the wafer diameter placed above the wafer. This shields the wafer edge to reduce deposition contamination on the back side of the wafer during thin film deposition. However, during thin film deposition, the inner wall of the shielding ring also deposits a film layer. As the process progresses, the film thickness gradually increases, and the shielding area on the wafer edge also increases. When the shielding area is large enough to exceed the ineffective area of ​​the wafer edge, it significantly affects the plasma distribution within the process chamber, thus affecting the uniformity of the thin film deposited on the front side of the wafer. Based on this, the process chambers in related technologies generally determine the duration of the deposition cycle (PK life) based on the thin film deposition rate. After each deposition cycle, the process chamber needs to be shut down and the shielding ring needs to be disassembled, cleaned, and replaced to ensure the uniformity of the thin film deposited on the front side of the wafer. However, this operation also increases the maintenance cost of the process chamber and reduces its throughput. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor process chamber and a thin film deposition process to solve the technical problem in related technologies that the thin film deposition process requires shutdown and opening of the chamber to disassemble, clean, and replace the shielding ring after each deposition cycle, resulting in high maintenance costs and low production capacity of the process chamber.

[0005] To address the above problems, the present invention provides a semiconductor process chamber, comprising:

[0006] The chamber body has an internal cavity;

[0007] A carrier component is disposed within the cavity, and the carrier component is configured to carry a wafer.

[0008] The shielding assembly includes a drive structure disposed on the chamber body and a first shielding ring and a second shielding ring disposed in the chamber. The first shielding ring includes a plurality of arc-shaped shielding segments along its circumference. The drive structure is connected to each of the shielding segments and is configured to drive the shielding segments to move radially away from the axis of the first shielding ring.

[0009] The first shielding ring, the second shielding ring and the wafer are coaxially arranged, and the inner diameter of the second shielding ring is greater than the inner diameter of the first shielding ring, and two deposition cycles can be continuously performed. In the first deposition cycle, the first shielding structure formed by the first shielding ring and the film layer deposited on the inner wall of the ring of the first shielding ring is shielded above the edge invalid area of the wafer; in the second deposition cycle, the second shielding structure formed by the second shielding ring and the film layer deposited on the inner wall of the ring of the second shielding ring is shielded above the edge invalid area of the wafer.

[0010] Optionally, the difference between the diameter of the wafer and the inner diameter of the first shielding ring is 0-1mm.

[0011] The second shielding ring is located above the first shielding ring, the difference between the inner diameter of the second shielding ring and the diameter of the wafer is 2d1, the thickness of the film layer deposited on the inner wall of the ring of the second shielding ring in the first deposition cycle is d2, and the difference between d2 and d1 is 0-0.5mm.

[0012] Or, the second shielding ring is located below the first shielding ring, and the inner diameter of the second shielding ring is smaller than the diameter of the wafer.

[0013] Optionally, the second shielding ring is located above the first shielding ring, and the outer edge of the second shielding ring is surrounded by a side plate extending upward, and the top end of the side plate is connected to the chamber body.

[0014] Optionally, the upper region of the cavity side wall of the cavity is surrounded by a lap joint seat, and the outer periphery of the top end of the side plate is surrounded by a top turning edge, and the top turning edge is lap jointed to the lap joint seat.

[0015] Optionally, the outer diameter of the first shielding ring is greater than the outer diameter of the second shielding ring.

[0016] Optionally, the carrier assembly comprises a base and a deposition ring arranged on the top of the base, the deposition ring comprises a ring-shaped receiving boss and a shielding edge surrounding the outer periphery of the bottom end of the receiving boss, and the outer diameter of the shielding edge is greater than the diameter of the wafer.

[0017] Optionally, the outer diameter of the shielding edge is greater than the outer diameter of the second shielding ring.

[0018] Optionally, in the abutting end portions of two adjacent shielding segments, the upper portion of one is an upper abutting groove, and the lower portion is a lower abutting step, the upper portion of the other is an upper abutting step, and the lower portion is a lower abutting groove, the upper abutting step is matched and inserted into the upper abutting groove, and the lower abutting step is matched and inserted into the lower abutting groove.

[0019] Optionally, the driving structure comprises a plurality of driving members, each of the plurality of driving members is connected to one of the shielding segments, and is configured to drive the corresponding shielding segment to move away from the axis of the first shielding ring in the radial direction.

[0020] The application further provides a thin film deposition process using the semiconductor process chamber, the thin film deposition process comprising:

[0021] A first deposition step: performing thin film deposition on a wafer carried by the carrier base for a first preset time length, wherein the film layer deposited on the first shielding ring and the inner wall thereof forms a first shielding structure, and the film layer deposited on the second shielding ring and the inner wall thereof forms a second shielding structure;

[0022] An adjusting step: adjusting the shielding segments of the first shielding structure to move away from the axis thereof in the radial direction until the inner region surrounded by the second shielding structure is avoided;

[0023] A second deposition step: performing thin film deposition on the wafer carried by the carrier base for a second preset time length.

[0024] The semiconductor process chamber provided by the application comprises a shielding assembly including a first shielding ring capable of moving outwardly and expanding in a spliced form and a second shielding ring, and the relationship between the inner diameters of the first shielding ring and the second shielding ring and the diameter of the wafer is set, so that the semiconductor process chamber can continuously perform two deposition periods and then needs to be opened to clean and replace the shielding assembly, the deposition process time is doubled compared with the related art, the opening and cleaning maintenance frequency of the semiconductor process chamber is reduced, the maintenance convenience and productivity of the process chamber are improved, and the waste of target material resources is reduced.

[0025] The thin film deposition process provided by the application uses the semiconductor process chamber, and can continuously perform two deposition periods and then needs to be opened to clean and replace the shielding assembly, the deposition process time is doubled compared with the related art, the opening and cleaning maintenance frequency of the semiconductor process chamber is reduced, the maintenance convenience and productivity of the process chamber are improved, and the waste of target material resources is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the related art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0027] Figure 1 An internal schematic view of a semiconductor process chamber in the related art;

[0028] Figure 2 An internal schematic view of a semiconductor process chamber provided by an embodiment of the present application;

[0029] Figure 3 An initial relative position schematic view of a wafer, a first shielding ring and a second shielding ring in a semiconductor process chamber provided by an embodiment of the present application;

[0030] Figure 4 A relative position schematic view of a wafer, a first shielding ring and a second shielding ring in a semiconductor process chamber provided by an embodiment of the present application after a first deposition period of a thin film deposition process;

[0031] Figure 5 A relative position schematic view of a wafer, a first shielding ring and a second shielding ring in a semiconductor process chamber provided by an embodiment of the present application after a second deposition period of a thin film deposition process;

[0032] Figure 6 A connection schematic view of a first shielding ring and a driving structure in a semiconductor process chamber provided by an embodiment of the present application;

[0033] Figure 7 A connection schematic view of a first shielding ring and a driving structure in a semiconductor process chamber provided by an embodiment of the present application after a first deposition period of a thin film deposition process;

[0034] Figure 8 An adaption schematic view of two adjacent shielding segments in a semiconductor process chamber provided by an embodiment of the present application;

[0035] Figure 9 A flow schematic view of a thin film deposition process provided by an embodiment of the present application.

[0036] Explanation of reference signs:

[0037] 10 - wafer; 11 - deposition zone; 12 - edge dead zone; 100 - chamber body; 110 - cavity; 120 - cavity sidewall; 200 - supporting assembly; 210 - susceptor; 220 - deposition ring; 221 - receiving boss; 222 - shielding edge; 300 - shielding assembly; 30A - first shielding structure; 30B - second shielding structure; 30C - inner liner; 310 - driving structure; 311 - driver; 312 - connecting rod; 320 - first shielding ring; 321 - shielding segment; 321a - upper engaging groove; 321b - lower engaging step; 321c - upper engaging step; 321d - lower engaging groove; 330 - second shielding ring; 340 - first shielding film layer; 350 - second shielding film layer; 360 - side wall; 370 - top flange; 380 - overlapping seat; 400 - target material; 500 - magnetron; 600 - shielding disc. DETAILED DESCRIPTION

[0038] The technical solutions of the present application will be described clearly and completely below in conjunction with the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0039] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0040] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0041] Figure 1 It is a schematic view of the interior of a semiconductor process chamber in the related art. As shown in FIG. 1, the semiconductor process chamber 100 includes a chamber body 110, a cavity 120, a supporting assembly 200, a deposition ring 220, a shielding assembly 300, and a target material 400. Figure 1As shown, the semiconductor process chamber includes a chamber body 100 internally surrounding a cavity 110, a lower region of the cavity 110 is provided with a susceptor 210, a top of the susceptor 210 is provided with a deposition ring 220; an upper region of the cavity 110 is provided with an inner liner 30C (Shield), an inner side of the inner liner 30C is overlapped with a first shielding ring 320, a bottom flange of the inner liner 30C serves as a second shielding ring 330. In use, a wafer 10 is carried on a middle region of a top surface of the deposition ring 220, wherein the wafer 10 includes a deposition area 11 located at a middle position requiring deposition of a thin film and an edge invalid area 12 located at an edge position of the wafer 10, the first shielding ring 320 is arranged approximately coaxially with the wafer 10, and an inner diameter of the first shielding ring 320 is less than or equal to a diameter of the wafer 10; when the susceptor 210 drives the deposition ring 220 and the wafer 10 to move upward until the edge of the deposition ring 220 pushes up the first shielding ring 320 to reach a deposition position, the first shielding ring 320 is located above the wafer 10 and can shield the outer periphery of the wafer 10 to prevent deposition material from reaching below the wafer 10 to contaminate the back surface formed by the wafer 10.

[0042] Subsequently, a thin film deposition process is performed on the wafer 10, and the length of time of a deposition period is determined according to a thin film deposition speed. As the thin film deposition proceeds, the deposition area 11 of the wafer 10 is deposited to form a thin film, at the same time, the inner wall of the first shielding ring 320 is also deposited to form a film layer and the thickness of the film layer gradually increases, then the inner diameter of the first shielding ring 320 and the film layer deposited on the inner wall thereof gradually decrease to form a first shielding structure 30A, which correspondingly shields the edge invalid area 12 and the shielding area gradually increases. At the end of a deposition period, the shielding area of the first shielding structure 30A to the edge invalid area 12 is close to the inner ring boundary of the edge invalid area 12. During the deposition period, the first shielding structure 30A has a smaller shielding area to the edge of the wafer 10, has a smaller influence on the distribution of plasma in the cavity 110, and can ensure uniform film formation of the front deposition area 11 of the wafer 10. If the thin film deposition continues, the shielding of the first shielding structure 30A to the edge of the wafer 10 exceeds the edge invalid area 12, has a greater influence on the distribution of plasma in the cavity 110, and causes the uniformity of the deposition thin film of the deposition area 11 of the wafer 10 to be affected. Therefore, after a deposition period, the process chamber needs to be stopped and opened to disassemble and clean or replace the first shielding ring 320 and other process components. Subsequently, the clean first shielding ring 320 is reloaded into the chamber body 100, and the next deposition period is continued. In this way, the uniformity of the deposition thin film of the front deposition area 11 of the wafer 10 is ensured, and at the same time, the frequent stop and opening of the process chamber and the frequent disassembly, cleaning and replacement of the first shielding ring 320 also lead to higher maintenance cost and lower productivity of the process chamber.

[0043] The embodiment provides a semiconductor process chamber, a shielding assembly 300 is arranged, the shielding assembly 300 comprises a second shielding ring 330 and a first shielding ring 320 in a spliced form and capable of outward expansion movement, considering the speed of film layer accumulated on the inner wall of the ring of the shielding assembly 300 during the process of depositing the film on the wafer 10, by arranging the relationship between the inner diameter of the first shielding ring 320 and the second shielding ring 330 and the diameter of the wafer 10, the semiconductor process chamber can continuously carry out two deposition periods and then stop and open the cavity to disassemble, clean and replace the shielding assembly 300, relative to the deposition process time length in the related art, the deposition process time length is doubled, so that the opening cavity cleaning and maintenance frequency of the semiconductor process chamber is reduced, the maintenance convenience and the production capacity of the process chamber are improved, and the waste of target material 400 resources is reduced. The semiconductor process chamber provided by the embodiment of the application will be further described in detail below with reference to the drawings.

[0044] The embodiment of the application provides a semiconductor process chamber, as shown in the drawings, Figure 2 The embodiment of the application provides a semiconductor process chamber, as shown in the drawings,

[0045] The embodiment of the application provides a semiconductor process chamber, as shown in the drawings, Figure 1 、 Figure 3 and Figure 6As shown, the first shielding ring 320 is in a spliced state under the restriction of the driving assembly, and the first shielding ring 320 and the second shielding ring 330 are arranged in sequence in the height direction and coaxially arranged; when the thin film deposition process needs to be performed, the wafer 10 is conveyed and carried on the carrying surface at the top of the carrying assembly 200, the first shielding ring 320 and the second shielding ring 330 are located above the wafer 10, and the first shielding ring 320, the second shielding ring 330 and the wafer 10 are coaxially arranged, the inner diameter of the first shielding ring 320 is smaller than the inner diameter of the second shielding ring 330, and at the same time, the inner diameter of the first shielding ring 320 is smaller than or equal to the diameter of the wafer 10 and greater than the diameter of the inner ring boundary of the ineffective area 12 of the wafer 10.

[0046] The embodiment also provides a thin film deposition process, which uses the above-mentioned semiconductor process chamber. On the basis of ensuring that the shielding assembly 300 forms effective shielding for the wafer 10, the back surface of the wafer 10 is not deposited with a thin film, and the uniformity of the thin film deposited on the front surface of the wafer 10 is ensured, the thin film deposition process can be continuously performed for two deposition periods, and then the shielding assembly 300 needs to be disassembled, cleaned and replaced after the chamber is opened. Figure 9 A flowchart of a thin film deposition process according to an embodiment of the present application is provided. Specifically, the thin film deposition process includes:

[0047] S102, a first deposition step: performing thin film deposition on the wafer 10 carried on the carrying base 210 for a first preset time length, wherein the film layer deposited on the first shielding ring 320 and the inner wall thereof forms a first shielding structure 30A, and the film layer deposited on the second shielding ring 330 and the inner wall thereof forms a second shielding structure 30B.

[0048] The semiconductor process chamber enters a first deposition period. In the deposition period, the first shielding ring 320 effectively shields the ineffective area 12 of the wafer 10, so as to reduce the deposition of the deposited material downward to the back surface of the wafer 10; as the thin film deposition on the front surface deposition area 11 of the wafer 10 proceeds, the top surface and the inner wall of the first shielding ring 320 are also simultaneously deposited to form a first shielding film layer 340, and the thickness of the first shielding film layer 340 gradually increases, so that the inner diameter of the first shielding structure 30A formed by the first shielding ring 320 and the first shielding film layer 340 gradually decreases, the shielding area of the first shielding structure 30A on the ineffective area 12 of the wafer 10 gradually increases, and the deposition time reaches the first preset time length, and the first deposition period ends.

[0049] In the first deposition period, the second shielding ring 330 can be located above or below the first shielding ring 320, for example, Figure 4As shown, when the second shielding ring 330 is located above the first shielding ring 320, the top surface and the inner wall of the second shielding ring 330 are simultaneously deposited to form a second shielding film layer 350, and the second shielding ring 330 and the second shielding film layer 350 jointly form a second shielding structure 30B; when the second shielding ring 330 is located below the first shielding ring 320, the second shielding ring 330 will not be deposited to form a film layer, and the second shielding ring 330 serves as the second shielding structure 30B. At the end of the first deposition period, the inner diameter of the second shielding structure 30B is less than or equal to the diameter of the wafer 10 and greater than the diameter of the inner ring boundary of the edge exclusion zone 12.

[0050] S104 adjustment step: adjust the shielding segments 321 of the first shielding structure 30A to move away from the axis in the radial direction until the inner area surrounded by the second shielding structure 30B is avoided.

[0051] Subsequently, the adjustment step is performed, as shown in Figure 5 and Figure 7 As shown, the adjustment driving structure 310 drives the plurality of shielding segments 321 of the first shielding ring 320 to move away from the axis of the second shielding ring 330 in the radial direction until the radial distance between each shielding segment 321 and the axis of the second shielding ring 330 is greater than the inner radius of the second shielding structure 30B, that is, each shielding segment 321 moves to an area outside the inner wall of the second shielding structure 30B in the radial direction, avoiding the inner area surrounded by the second shielding structure 30B.

[0052] S106 second deposition step: performing thin film deposition on the wafer 10 carried by the carrier base 210 for a second preset time period.

[0053] The second deposition step is continued, as shown in Figure 5 As shown, the semiconductor process chamber enters a second deposition period, in which the second shielding structure 30B effectively shields the edge exclusion zone 12 of the wafer 10 to continue to reduce the deposition of the deposition material downward to the back surface of the wafer 10; as the thin film deposition of the front surface of the wafer 10 proceeds, the front surface and the inner wall of the second shielding structure 30B are also simultaneously deposited to form a second shielding film layer 350, and the shielding area of the second shielding structure 30B on the edge exclusion zone 12 gradually increases until the shielding area of the second shielding structure 30B on the edge exclusion zone 12 approaches the inner ring boundary of the edge exclusion zone 12, the deposition time reaches the second preset time period, and the second deposition period ends.

[0054] Subsequently, the semiconductor process chamber is shut down and opened, the shielding component 300 is disassembled, removed, cleaned, and replaced. This ensures that the shielding component 300 effectively shields the wafer 10, prevents the deposition of thin film on the back side of the wafer 10, and guarantees the uniformity of the deposition film on the front side of the wafer 10. It allows for two consecutive deposition cycles before the chamber needs to be shut down and the shielding component 300 needs to be disassembled, cleaned, and replaced. This doubles the deposition process time compared to related technologies, thereby reducing the frequency of opening, cleaning, and maintenance of the semiconductor process chamber, improving the ease of maintenance and production capacity of the process chamber, and reducing the waste of target material 400 resources.

[0055] Specifically, such as Figure 2 As shown, a target material 400 is provided in the upper region of the cavity 110, and a magnetron 500 is provided above the target material 400. The magnetron 500 applies an action to the target material 400, causing a deposit to form below the target material 400 and deposit downwards onto the deposition region 11 of the wafer 10 to form a thin film. A shielding disk 600 may also be provided in the lower region of the cavity 110.

[0056] In embodiments of the present invention, such as Figure 8 As shown, in the connecting ends of two adjacent blocking segments 321, one has an upper connecting groove 321a at the top and a lower connecting step 321b at the bottom, while the other has an upper connecting step 321c at the top and a lower connecting groove 321d at the bottom. The upper connecting step 321c is inserted into the upper connecting groove 321a, and the lower connecting step 321b is inserted into the lower connecting groove 321d. The upper connecting step 321c and the lower connecting step 321b are arranged to overlap vertically, resulting in overlapping areas in both the radial and circumferential directions. During adjustment, the drive structure 310 drives each blocking segment 321 to move radially towards the cavity sidewall 120 of the corresponding area. This causes adjacent blocking segments 321 to move away from each other at a certain angle. Within the adjustable range, although the corresponding upper connecting step 321c and lower connecting step 321b move away from each other, they still have overlapping areas, allowing for adjustment of the radial... Each shielding segment 321, even as its size increases, remains a closed ring. This ensures that while the first shielding ring 320 can be radially adjusted to avoid obstructing the second shielding ring 330, the circumferential shielding of the first shielding ring 320 is maintained. Consequently, the leakage of light through the gap between two adjacent shielding segments 321 during the second deposition cycle is reduced. This ensures the isolation between the upper and lower cavities, reduces the deposition contamination caused by upper cavity deposits entering the lower cavity and affecting the cavity wall and the outer wall of the support assembly 200, and ensures the ease of maintenance and production capacity of the semiconductor process chamber.

[0057] Specifically, in the embodiments of the present invention, such as Figure 6 and Figure 7As shown, the driving structure 310 includes a plurality of driving members 311, each of which is connected to one of the shielding segments 321 and configured to drive the corresponding shielding segment 321 to move radially away from the axis of the first shielding ring 320. The number of the driving members 311 is equal to the number of the shielding rings, each of the driving members 311 is connected to the cavity side wall 120 of the chamber body 100, the plurality of driving members 311 are arranged at intervals along the circumferential direction of the cavity side wall 120, and each of the driving members 311 is connected to the middle position of the corresponding shielding segment 321 in the circumferential direction. When adjusting, each of the driving members 311 synchronously operates and drives the plurality of shielding segments 321 to move synchronously outward in the radial direction, so as to realize the synchronous driving of the plurality of shielding segments 321. Specifically, the driving member 311 can adopt a linear motor, and the driving end of the driving member 311 is connected to the corresponding shielding segment 321 through a connecting rod 312.

[0058] In the embodiment of the present application, the difference between the diameter of the wafer 10 and the inner diameter of the first shielding ring 320 is 0-1 mm. Therefore, at the beginning of the first deposition period, the shielding range of the first shielding ring 320 in the radial direction to the edge invalid area 12 is 0-0.5 mm. In the early stage of the first deposition period, the first shielding ring 320 can effectively shield the edge of the wafer 10 to prevent the deposition of the wafer 10 from causing deposition pollution on the back surface. On this basis, the inner wall of the first shielding ring 320 and the inner ring boundary of the edge invalid area 12 have a large radial distance, thereby ensuring that the first preset time length of the first deposition period is long, reducing the occurrence of the situation that the shielding range of the first shielding film layer 340 deposited on the first shielding ring 320 exceeds the inner ring boundary at the end of the first deposition period, and further ensuring the uniformity of the deposition film on the front surface of the wafer 10, ensuring the yield of the semiconductor devices produced by the semiconductor process chamber, and further reducing the opening cleaning and maintenance frequency of the semiconductor process chamber, improving the maintenance convenience and productivity of the process chamber.

[0059] In the embodiment of the present application, the second shielding ring 330 can be located above or below the first shielding ring 320. When the second shielding ring 330 is located above the first shielding ring 320, the difference between the inner diameter of the second shielding ring 330 and the diameter of the wafer 10 is 2d1, the thickness of the film layer deposited on the inner wall of the second shielding ring 330 in the first deposition period is d2, and the difference between d2 and d1 is 0-0.5 mm.

[0060] In the first deposition period, the second shielding ring 330 is located above the first shielding ring 320, and as the film deposition of the wafer 10 deposition area 11 proceeds, the top surface and the inner wall of the second shielding ring 330 are simultaneously deposited with a film layer to form a second shielding structure 30B, and the first shielding ring 320 radially extends outward from the top surface and the inner wall of the second shielding ring 330 to form a first shielding structure 30A, and the inner diameter of the first shielding structure 30A is always smaller than the inner diameter of the second shielding structure 30B, and the first shielding structure 30A maintains effective shielding of the wafer 10 edge invalid area 12; at the end of the first deposition period, the inner wall of the first shielding structure 30A approaches the inner ring boundary of the edge invalid area 12, and the inner diameter of the second shielding structure 30B is reduced by 2d2 compared to the inner diameter of the first shielding ring 320, and since the inner diameter of the second shielding ring 330 is greater than the diameter of the wafer 10, and the radial distance d1 between the inner wall of the second shielding ring 330 and the outer edge of the wafer 10 is 0-0.5mm less than d2, the second shielding structure 30B has a radial shielding range of 0-0.5mm to the edge invalid area 12.

[0061] Correspondingly, at the beginning of the second deposition period, the second shielding structure 30B has a radial shielding range of 0-0.5mm to the edge invalid area 12, and in the early stage of the second deposition period, the second shielding structure 30B effectively shields the edge of the wafer 10, prevents deposition from causing deposition pollution on the back of the wafer 10, and ensures that the inner wall of the second shielding structure 30B has a large radial distance from the inner ring boundary of the edge invalid area 12, thereby ensuring that the second predetermined length of the second deposition period is long, and reducing the occurrence of the second shielding film 350 deposited on the second shielding ring 330 exceeding the inner ring boundary at the end of the second deposition period, and further ensuring the uniformity of the deposition film on the front of the wafer 10, ensuring the yield of the semiconductor device produced by the semiconductor process chamber, and further reducing the opening cleaning and maintenance frequency of the semiconductor process chamber, and improving the maintenance convenience and productivity of the process chamber.

[0062] When the second shielding ring 330 is located below the first shielding ring 320, the inner diameter of the second shielding ring 330 is smaller than the diameter of the wafer 10, and the inner diameter of the second shielding ring 330 is larger than the inner diameter of the first shielding ring 320. In the first deposition period, as the film deposition of the deposition area 11 of the wafer 10 proceeds, the top surface and the inner wall of the first shielding ring 320 are simultaneously deposited with the first shielding film layer 340 to form the first shielding structure 30A, and the second shielding ring 330 is not formed with the film layer due to the shielding of the first shielding ring 320. Therefore, when the first deposition period ends, the inner wall of the first shielding structure 30A is close to the inner boundary of the edge ineffective area 12, and the second shielding ring 330 maintains the initial state to shield the edge ineffective area 12 in the radial direction and the shielding range is less than 0.5 mm. Correspondingly, when the second deposition period starts, the shielding range of the second shielding ring 330 to the edge ineffective area 12 in the radial direction is less than 0.5 mm, which can further ensure the uniformity of the film deposition on the front surface of the wafer 10, ensure the yield of the semiconductor device produced by the semiconductor process chamber, and further reduce the opening cleaning and maintenance frequency of the semiconductor process chamber, and improve the maintenance convenience and productivity of the process chamber.

[0063] In the embodiment of the present application, when the second shielding ring 330 is located above the first shielding ring 320, the outer edge of the second shielding ring 330 is surrounded by a side plate 360 extending upward, and the top end of the side plate 360 is connected to the chamber body 100. The second shielding ring 330 and the side plate 360 together form an inner liner 30C. When depositing the film, the inner liner 30C, the first shielding ring 320 and the wafer 10 together divide the cavity 110 into an upper cavity and a lower cavity, and the side plate 360 can shield and protect the cavity side wall 120 of the upper cavity. Therefore, on the basis of realizing the effective shielding effect of the second shielding ring 330 on the edge ineffective area 12 of the wafer 10 in the second deposition period, the functionality of the second shielding ring 330 is improved, the pollution caused by the film deposition on the cavity side wall 120, the carrier assembly 200 and the like is reduced, and the maintenance convenience and productivity of the semiconductor process chamber are further improved.

[0064] In the embodiment of the present application, as shown in Figure 2 The upper region of the cavity side wall 120 of the cavity 110 is surrounded by a lap seat 380, the outer periphery of the top end of the side plate 360 is surrounded by a top turning edge 370, and the top turning edge 370 is lapped on the lap seat 380. The inner liner 30C is connected to the chamber body 100 by lapping the top turning edge 370 on the lap seat 380, which is more convenient to disassemble and assemble, so as to ensure the convenience of cleaning and replacing the inner liner 30C, and accordingly ensure the maintenance convenience of the semiconductor process chamber.

[0065] In the embodiment of the present application, as shown in Figure 2As shown, the outer diameter of the first shielding ring 320 is greater than the outer diameter of the second shielding ring 330. The outer wall of the first shielding ring 320 and the cavity side wall 120 of the cavity 110 leave a radial position adjustment for the first shielding ring 320 during the adjustment step, and in the first deposition period, the inner wall of the first shielding ring 320 extends radially inward beyond the second shielding ring 330, and at the same time, the outer wall of the first shielding ring 320 extends radially outward beyond the second shielding ring 330, so that the first shielding ring 320 can be shielded between the upper cavity and the lower cavity with a larger area, and at the same time, the second shielding ring 330 is shielded above the first shielding ring 320; in the second deposition period, the first shielding ring 320 moves radially close to the cavity side wall 120, the second shielding ring 330 is staggered with the first shielding ring 320, and there is a large overlapping area, thereby ensuring the shielding comprehensiveness of the shielding assembly 300 to the upper cavity and the lower cavity in the two deposition periods, i.e. the entire deposition process, effectively reducing the deposition of the deposition material into the lower cavity, and the deposition pollution to the bearing assembly 200, the cavity wall, etc.

[0066] In the embodiment of the present application, as shown in the figure, Figure 2 As shown, the bearing assembly 200 includes a base 210 and a deposition ring 220 (Dep ring) arranged on the top of the base 210, the deposition ring 220 includes a ring-shaped receiving boss 221 and a shielding edge 222 arranged outside the bottom of the receiving boss 221, and the outer diameter of the shielding edge 222 is greater than the diameter of the wafer 10. The receiving boss 221 is arranged inside the shielding edge 222 and protrudes upward relative to the shielding edge 222, in the first deposition period, the receiving boss 221 bears the wafer 10, and the shielding edge 222 and the first shielding ring 320 have an overlapping area in the radial direction, the shielding edge 222 can perform secondary shielding on the gap between the first shielding ring 320 and the wafer 10, so as to increase the difficulty of the deposition material in the upper cavity entering the lower cavity through the gap between the first shielding ring 320 and the wafer 10, thereby further improving the isolation of the upper cavity and the lower cavity, reducing the deposition pollution of the deposition material in the upper cavity to the cavity wall and the outer wall of the bearing assembly 200, and correspondingly further improving the maintenance convenience and productivity of the semiconductor process chamber.

[0067] In the embodiment of the present application, as shown in the figure, Figure 2 As shown, the outer diameter of the shielding edge 222 is greater than the outer diameter of the second shielding ring 330. In the first deposition period and the second deposition period, the shielding edge 222 and the first shielding ring 320 and the second shielding ring 330 can ensure a large overlapping area in the radial direction, thereby ensuring the isolation of the upper cavity and the lower cavity, and correspondingly ensuring the cleanliness of the lower cavity during the entire deposition process, and further improving the maintenance convenience and productivity of the semiconductor process chamber.

[0068] Exemplarily, the diameter of the wafer 10 can be 300 mm, the radial size of the edge exclusion zone 12 of the wafer 10 is determined as 2 mm according to the size of the edge blank area of the wafer 10 and the axial distance between the first shielding ring 320, the second shielding ring 330 and the wafer 10; the first shielding ring 320 is arranged below the second shielding ring 330, and the inner diameter of the first shielding ring 320 is 299 mm, and the inner diameter of the second shielding ring 330 is 302 mm; a deposition cycle is accumulated on the inner wall of the first shielding ring 320 and the second shielding ring 330 to form a shielding film layer with a radial thickness of about 1.5 mm.

[0069] Firstly, a first deposition step is performed, as shown in FIG. 2A. Figure 3 As shown in FIG. 2A, the first shielding ring 320 effectively shields the wafer 10, and the radial shielding distance of the first shielding ring 320 to the edge exclusion zone 12 of the wafer 10 is 0.5 mm initially. Figure 4 As shown in FIG. 2B, the radial thickness of the first shielding film layer 340 deposited on the inner wall of the first shielding ring 320 gradually increases, and when the radial thickness of the first shielding film layer 340 reaches 1.5 mm, the deposition time reaches a first preset time, the inner diameter of the first shielding structure 30A formed by the first shielding ring 320 and the first shielding film layer 340 is reduced to 296 mm, the radial shielding distance of the first shielding structure 30A to the edge exclusion zone 12 reaches 2 mm, the shielding range approaches the inner ring boundary of the edge exclusion zone 12, and the first deposition cycle ends. In the first deposition cycle, the radial thickness of the second shielding film layer 350 formed on the inner wall of the second shielding ring 330 is also about 1.5 mm, and the inner diameter of the second shielding structure 30B formed by the second shielding ring 330 and the second shielding film layer 350 is reduced to 299 mm.

[0070] Subsequently, an adjustment step is performed, as shown in FIG. 2C. Figure 5 As shown in FIG. 2C, the driving structure 310 drives each shielding segment 321 of the first shielding ring 320 to move radially outward by a distance greater than 1.5 mm, so that each shielding segment 321 is located radially outside the inner area of the second shielding structure 30B, so that the second shielding structure 30B effectively shields the wafer 10.

[0071] Then, a second deposition step is continued, as shown in FIG. 2D. Figure 5As shown, the second shielding structure 30B effectively shields the wafer 10, and the radial shielding distance of the second shielding structure 30B to the edge ineffective area 12 of the wafer 10 is 0.5 mm. As the film deposition proceeds, the radial thickness of the second shielding film layer 350 deposited on the inner wall of the second shielding ring 330 continues to increase. When the radial thickness of the second shielding film layer 350 increases by 1.5 mm relative to the first deposition period, the deposition time reaches the second preset time, the inner diameter of the second shielding structure 30B is reduced to 296 mm, the radial shielding distance of the second shielding structure 30B to the edge ineffective area 12 reaches 2 mm, and the shielding range approaches the inner ring boundary of the edge ineffective area 12. The second deposition period ends.

[0072] Subsequently, the semiconductor process chamber is stopped and opened, the shielding assembly 300 is disassembled, removed and cleaned and replaced, so that the shielding assembly 300 can continuously perform two deposition periods before being stopped and opened for cleaning and replacement, while ensuring that the wafer 10 is effectively shielded, the back of the wafer 10 is not deposited with a film, and the uniformity of the film deposited on the front of the wafer 10 is guaranteed. The deposition process time of the related art is doubled, the cleaning and maintenance frequency of the semiconductor process chamber is correspondingly reduced, and the maintenance convenience and productivity of the process chamber are improved.

[0073] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor process chamber, comprising: The chamber body (100) has a cavity (110) inside; The carrier assembly (200) is arranged in the cavity (110) and is configured to carry a wafer (10); The shielding assembly (300) includes a driving structure (310) arranged on the chamber body (100) and a first shielding ring (320) and a second shielding ring (330) arranged in the cavity (110), the first shielding ring (320) includes a plurality of arc-shaped shielding segments (321) along the circumference thereof, and the driving structure (310) is connected to each shielding segment (321) and is configured to drive the shielding segment (321) to move radially away from the center of the first shielding ring (320). The first shielding ring (320), the second shielding ring (330), and the wafer (10) are coaxially arranged, and the inner diameter of the second shielding ring (330) is greater than the inner diameter of the first shielding ring (320), and two deposition periods can be continuously performed, wherein in the first deposition period, a first shielding structure (30A) formed by the first shielding ring (320) and the film layer deposited on the inner wall thereof shields the edge dead zone (12) of the wafer (10); in the second deposition period, a second shielding structure (30B) formed by the second shielding ring (330) and the film layer deposited on the inner wall thereof shields the edge dead zone (12) of the wafer (10). The difference between the diameter of the wafer (10) and the inner diameter of the first shielding ring (320) is 0-1 mm; 2. The semiconductor process chamber of claim 1, wherein, The second shielding ring (330) is located above the first shielding ring (320), the difference between the inner diameter of the second shielding ring (330) and the diameter of the wafer (10) is 2d1, the thickness of the film layer deposited on the inner wall of the second shielding ring (330) in the first deposition period is d2, and the difference between d2 and d1 is 0-0.5 mm; Or, the second shielding ring (330) is located below the first shielding ring (320), and the inner diameter of the second shielding ring (330) is smaller than the diameter of the wafer (10). The second shielding ring (330) is located above the first shielding ring (320), and the outer edge of the second shielding ring (330) is surrounded by a side panel (360) extending upward, and the top end of the side panel (360) is connected to the chamber body (100).

3. The semiconductor process chamber of claim 1, wherein, The upper region of the cavity side wall (120) of the cavity (110) is surrounded by a lap joint seat (380), and the outer periphery of the top end of the side panel (360) is surrounded by a top turning edge (370), and the top turning edge (370) is lap jointed to the lap joint seat (380).

4. The semiconductor process chamber of claim 3, wherein, The outer diameter of the first shielding ring (320) is greater than the outer diameter of the second shielding ring (330).

5. The semiconductor process chamber of any of claims 1-4, wherein, ​ 6. The semiconductor process chamber of any of claims 1-4, wherein, The carrier assembly (200) comprises a base (210) and a deposition ring (220) arranged on the top of the base (210), the deposition ring (220) comprises a ring-shaped receiving boss (221) and a shielding rim (222) arranged outside the receiving boss (221), and the outside diameter of the shielding rim (222) is greater than the diameter of the wafer (10).

7. The semiconductor process chamber of claim 6, wherein, The outside diameter of the shielding rim (222) is greater than the outside diameter of the second shielding ring (330).

8. The semiconductor process chamber of any of claims 1-4, wherein, The upper part of one of the abutting end portions of two adjacent shielding segments (321) is an upper abutting groove (321a) and the lower part is a lower abutting step (321b), and the upper part of the other is an upper abutting step (321c) and the lower part is a lower abutting groove (321d), the upper abutting step (321c) is fitted into the upper abutting groove (321a), and the lower abutting step (321b) is fitted into the lower abutting groove (321d).

9. The semiconductor process chamber of any of claims 1-4, wherein, The driving structure (310) comprises a plurality of driving members (311), and each driving member (311) is connected to one of the shielding segments (321) and is configured to drive the corresponding shielding segment (321) to move away from the axis of the first shielding ring (320) in the radial direction.

10. A thin film deposition process, characterized by, The semiconductor process chamber of any one of claims 1-9, wherein the thin film deposition process comprises: a first deposition step of depositing a thin film on the wafer (10) carried by the carrier base (210) for a first predetermined time period, wherein the first shielding ring (320) and the film deposited on the inner wall thereof form a first shielding structure (30A), and the second shielding ring (330) and the film deposited on the inner wall thereof form a second shielding structure (30B); an adjusting step of adjusting the shielding segments (321) of the first shielding structure (30A) to move away from the axis thereof in the radial direction until the second shielding structure (30B) is avoided; a second deposition step of depositing a thin film on the wafer (10) carried by the carrier base (210) for a second predetermined time period. a first deposition step of depositing a thin film on the wafer (10) carried by the carrier base (210) for a first predetermined time period, wherein the first shielding ring (320) and the film deposited on the inner wall thereof form a first shielding structure (30A), and the second shielding ring (330) and the film deposited on the inner wall thereof form a second shielding structure (30B);

Images