Data transmission method and system between electronic speed governor and flight control based on adaptive master-slave switching

Abstract

The application discloses a data transmission method and system between an electronic governor and a flight control based on adaptive master-slave switching, relates to the technical field of unmanned aerial vehicle flight control, and discloses the data transmission method and system between the electronic governor and the flight control based on adaptive master-slave switching, which solves the problems of high delay, time sequence drift and lagged response in an emergency scene of a traditional polling mechanism through dynamic generation of a time slot strategy, calibration of a local clock, priority allocation and an optimized retransmission mechanism, can improve data transmission real-time performance, reduce communication conflict probability and enhance control response capability in an emergency obstacle avoidance scene, and thus improves flight performance and safety of the unmanned aerial vehicle.

Description

Technical Field

[0001] This application relates to the field of unmanned aerial vehicle (UAV) flight control technology, and in particular to a method and system for data transmission between an electronic speed controller and a flight controller based on adaptive master-slave switching. Background Technology

[0002] In UAV flight control systems, real-time data interaction between the electronic speed controller (ESC) and the flight control unit (FCU) has a decisive impact on flight stability and dynamic response capabilities. Currently, the mainstream solution employs a master-slave polling mechanism using an RS485 bus. This mechanism has significant technical flaws: as the number of ESCs increases, the polling cycle grows linearly, leading to a significant increase in control command delay. This delay can cause attitude control lag in critical scenarios such as high-speed obstacle avoidance, and in severe cases, may lead to loss of control. Traditional master-slave switching protocols use a fixed timing design, which is prone to timing drift under vibration, temperature changes, or electromagnetic interference, causing signal overlap and conflict from multiple ESCs, resulting in a high data error rate. Furthermore, existing solutions fail to effectively integrate the real-time flight control load status with obstacle avoidance requirements. During emergency obstacle avoidance, critical motor data cannot be prioritized for transmission, leading to a disconnect between control decisions and sensor feedback, which restricts the flight performance and safety of UAVs in complex environments.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a data transmission method and system between an electronic speed controller and a flight controller based on adaptive master-slave switching, which aims to improve the safety of unmanned aerial vehicles (UAVs).

[0005] To achieve the above objectives, this application proposes a data transmission method between an electronic speed controller and a flight controller based on adaptive master-slave switching, employing RS485 bus communication. The method includes:

[0006] The flight controller, acting as the host, broadcasts control command frames containing real-time control parameters to all electronic speed controllers via the RS485 bus. After the control command frames are sent, it generates timestamp data and broadcasts time synchronization frames containing that timestamp data.

[0007] The flight controller acquires environmental monitoring data from the RS485 bus and reads CPU utilization data. Based on the environmental monitoring data, CPU utilization data, and the number of electronic speed controllers, it generates time slot strategy data.

[0008] Each electronic speed controller receives the time synchronization frame and time slot strategy data, calibrates its local clock based on the timestamp data, and performs a bus contention detection operation according to the time slot strategy data.

[0009] During bus contention testing, each electronic speed controller acts as a temporary host within the time slot window allocated based on the time slot strategy data, and sends status reporting data to the flight controller via the RS485 bus.

[0010] The flight controller receives the status report data and acquires obstacle distance data collected by the obstacle avoidance sensor. It then performs correlation analysis between the obstacle distance data and the status report data to generate flight control command data.

[0011] The flight controller performs verification calculations on the reported status data. If the verification fails, it generates retransmission command data containing the address of the electronic speed controller. Based on the flight control command data and the retransmission command data, it generates optimized time slot strategy data for use in the next communication cycle.

[0012] In one embodiment, the flight controller includes a radio frequency noise sensor and a system register; the step of the flight controller acquiring environmental monitoring data from the RS485 bus and reading CPU utilization data, and generating time slot strategy data based on the environmental monitoring data, CPU utilization data, and the number of electronic speed controllers includes:

[0013] The radio frequency noise sensor collects environmental monitoring data from the RS485 bus, and the noise impact coefficient is calculated based on the environmental monitoring data.

[0014] Read CPU utilization data from the system registers and calculate the load adjustment factor based on the CPU utilization data;

[0015] The time slot strategy data is generated by a dynamic allocation algorithm based on the number of electronic speed controllers, the noise impact coefficient, and the load adjustment coefficient.

[0016] In one embodiment, the step of generating the time slot strategy data based on the number of electronic speed controllers, the noise impact factor, and the load adjustment factor using a dynamic allocation algorithm includes:

[0017] Set the reference time slot length and adjust the reference time slot length according to the noise impact factor;

[0018] Set priority identifiers for electronic speed controllers based on load adjustment coefficients;

[0019] The time slot window for each electronic speed controller is assigned according to the priority identifier and the preset electronic speed controller number.

[0020] In one embodiment, the steps of each electronic speed controller receiving the time synchronization frame and time slot strategy data, calibrating its local clock based on the timestamp data, and performing a bus contention detection operation according to the time slot strategy data include:

[0021] The electronic speed governor extracts the time slot window from the time slot strategy data;

[0022] The local clock is calibrated based on the timestamp data;

[0023] When the local clock reaches the start time point of the time slot window, a random delay timer is started to perform a bus contention detection operation.

[0024] In one embodiment, the bus contention detection operation includes:

[0025] Generate a random delay seed value;

[0026] The bus detection time interval is determined based on the random delay seed value;

[0027] The bus level state is sampled according to the bus detection time interval to obtain the corresponding sampled value;

[0028] When the sampled value is lower than the preset level for a consecutive preset number of times, it is determined that the bus competition detection is passed.

[0029] In one embodiment, the flight controller receives the status report data and acquires obstacle distance data collected by the obstacle avoidance sensor. The step of correlating and analyzing the obstacle distance data with the status report data to generate flight control command data includes:

[0030] Read the safe distance threshold from the preset aircraft safety parameter library;

[0031] Compare and analyze the motor speed and obstacle distance data in the status report data;

[0032] When the obstacle distance data is less than the safe distance threshold, the corresponding electronic speed controller is marked as high priority;

[0033] Generate flight control command data containing high-priority tags.

[0034] In one embodiment, the step of marking the corresponding electronic speed controller as high priority when the obstacle distance data is less than a safe distance threshold includes:

[0035] Determine the physical address of the high-priority electronic speed controller;

[0036] Update the priority identifier of the physical address in the time slot policy data;

[0037] The first duration is preset for the start time of the time slot window corresponding to the high-priority physical address.

[0038] In one embodiment, the step of generating optimized time slot strategy data for the next communication cycle based on the flight control command data and the retransmission command data includes:

[0039] Extract the electronic speed controller physical address from the retransmission command data as the retransmission address;

[0040] A new time slot window is generated based on the high-priority identifier and retransmission address in the flight control command data.

[0041] The new time slot window is combined with the priority identifier to form the optimized time slot policy data.

[0042] In one embodiment, the step of generating a new time slot window based on the high-priority identifier and retransmission address in the flight control command data includes:

[0043] A dedicated transmission channel identifier is set for the retransmission address, a time slot window with a preset second duration is allocated to the physical address corresponding to the high priority identifier, and a parallel transmission path is created when the retransmission address conflicts with the high priority address.

[0044] Furthermore, to achieve the above objectives, this application also proposes a data transmission system between an electronic speed controller and a flight controller based on adaptive master-slave switching. The data transmission system includes a memory, a processor, and a data transmission program between the electronic speed controller and the flight controller based on adaptive master-slave switching, stored in the memory and executable on the processor. The data transmission program between the electronic speed controller and the flight controller is configured to implement the steps of the data transmission method between the electronic speed controller and the flight controller based on adaptive master-slave switching.

[0045] The data transmission method and system between the electronic speed controller and flight controller based on adaptive master-slave switching proposed in this application solves the problems of high latency, timing drift and delayed response in emergency scenarios of the traditional polling mechanism by dynamically generating time slot strategies, calibrating the local clock, prioritizing and optimizing the retransmission mechanism. It can improve the real-time performance of data transmission, reduce the probability of communication conflicts and enhance the control response capability in emergency obstacle avoidance scenarios, thereby improving the flight performance and safety of UAVs. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1This is a flowchart illustrating an embodiment of the data transmission method between an electronic speed controller and a flight controller based on adaptive master-slave switching, as provided in this application.

[0049] Figure 2 For this application Figure 1 A detailed flowchart of step S200;

[0050] Figure 3 For this application Figure 2 A detailed flowchart of step S230;

[0051] Figure 4 For this application Figure 1 Detailed flowchart of step S300;

[0052] Figure 5 For this application Figure 1 Detailed flowchart of step S500;

[0053] Figure 6 For this application Figure 1 A detailed flowchart of step S600;

[0054] Figure 7 This is a schematic diagram of a structural embodiment of the data transmission system between the electronic speed governor and flight control system based on adaptive master-slave switching, as provided in this application.

[0055] Explanation of icon numbers:

[0056] 10. Memory; 20. Processor.

[0057] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0058] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0059] It should be understood that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0060] In existing technologies, data interaction between the electronic speed controller (ESC) and the flight control unit (FCU) in UAV flight control systems typically employs a master-slave polling mechanism, where the FCU, as the master, queries multiple ESCs sequentially in a fixed order. As the number of ESCs increases, the polling cycle grows linearly, leading to a significant increase in control command issuance latency. In high-speed obstacle avoidance scenarios, this latency can cause attitude control lag or even loss of control. Furthermore, the fixed-timing master-slave switching protocol is susceptible to environmental interference, resulting in timing drift, signal conflicts, and a high data error rate. Existing solutions do not consider the linkage requirements between the flight control unit's real-time load and obstacle avoidance scenarios, and in emergency situations, critical data cannot be prioritized for transmission, causing a disconnect between control decisions and sensor feedback.

[0061] To address the aforementioned issues, the inventors discovered that the core flaw of the traditional polling mechanism lies in its static timing allocation and unidirectional transmission mode. Through analysis of the bus contention mechanism, they found that dynamically adjusting the time slot window can shorten the communication cycle; by introducing environmental monitoring and load assessment, they realized that real-time time slot adjustment strategies can adapt to complex operating conditions; and by combining obstacle avoidance sensor data correlation analysis, they found that dynamic priority allocation can improve the efficiency of critical data transmission. Based on this, they proposed a closed-loop optimized data transmission mechanism that combines dynamic switching of master / slave roles with adaptive time slot allocation, and achieves conflict avoidance through time synchronization calibration and bus contention detection.

[0062] Based on this, the embodiments of this application provide a data transmission method between an electronic speed governor and a flight controller based on adaptive master-slave switching, which adopts RS485 bus communication, as described above. Figure 1 The data transmission method between the electronic speed controller and the flight controller based on adaptive master-slave switching includes steps S100 to S600, wherein:

[0063] In step S100, the flight controller, acting as the host, broadcasts a control command frame containing real-time control parameters to all electronic speed controllers via the RS485 bus. After the control command frame is sent, it generates timestamp data and broadcasts a time synchronization frame containing the timestamp data.

[0064] Step S200: The flight controller acquires environmental monitoring data from the RS485 bus and reads CPU utilization data. Based on the environmental monitoring data, CPU utilization data, and the number of electronic speed controllers, it generates time slot strategy data.

[0065] In step S300, each electronic speed controller receives the time synchronization frame and time slot strategy data, calibrates its local clock based on the timestamp data, and performs a bus contention detection operation according to the time slot strategy data.

[0066] In step S400, during bus contention detection, each electronic speed controller acts as a temporary host within the time slot window allocated based on the time slot strategy data, and sends status reporting data to the flight controller via the RS485 bus.

[0067] In step S500, the flight controller receives the status report data and obtains the obstacle distance data collected by the obstacle avoidance sensor. It then performs correlation analysis between the obstacle distance data and the status report data to generate flight control command data.

[0068] In step S600, the flight controller performs verification calculations on the status reporting data. If the verification fails, it generates retransmission command data containing the address of the electronic speed controller. Based on the flight control command data and the retransmission command data, it generates optimized time slot strategy data for use in the next communication cycle.

[0069] In this embodiment, the time synchronization frame refers to a data packet containing reference time information indicating the completion time of the control command frame transmission. Specifically, it can be implemented using 32-bit timestamp encoding to unify the clock reference of each node. The time slot strategy data refers to a dynamically allocated set of communication time window parameters. Specifically, it can be implemented using a data structure containing start time, duration, and priority identifiers to coordinate the orderly access of multiple nodes to the bus. The bus contention detection operation refers to the detection mechanism for determining the bus idle state. Specifically, it can be implemented by continuously sampling the bus level after a random delay to avoid data conflicts caused by multiple nodes simultaneously transmitting data. Correlation analysis refers to the process of logically matching sensor data with the electronic speed controller state. Specifically, it can be implemented using data timestamp alignment and spatial location mapping algorithms to identify key nodes in emergency obstacle avoidance scenarios.

[0070] In this embodiment, the flight controller immediately sends a time synchronization frame after broadcasting control commands to ensure that all electronic speed controllers (ESCs) have a unified time reference. Bus interference intensity is collected by an RF noise sensor, and dynamic time slot allocation parameters are calculated based on the CPU load status. Before the allocated time slot window starts, each ESC performs random delay bus detection according to its calibrated local clock, and uploads status data after confirming the bus is idle. After receiving the data, the flight controller spatially correlates the obstacle distance collected by the obstacle avoidance sensor with the corresponding motor speed data to identify the ESC requiring priority control. When data verification fails, a retransmission command containing the target address is generated. In the next communication cycle, the time slot window is reallocated based on the priority adjustment results and retransmission requirements, forming an adaptively optimized transmission timing sequence.

[0071] In this embodiment, the solution shortens the response time in emergency scenarios through dynamic time slot allocation and priority adjustment; reduces the probability of multi-node conflicts through time synchronization and bus contention detection mechanisms; and improves data transmission reliability through closed-loop optimized time slot strategy. Furthermore, this solution achieves accurate generation of control commands through the mapping analysis of obstacle distance and motor state. Thus, this application effectively reduces the communication latency of the multi-electronic speed controller system and improves the real-time control performance in high-speed obstacle avoidance scenarios. Dynamic time slot allocation and priority adjustment ensure priority transmission of critical data, avoiding control decision lag. The combination of bus contention detection and time synchronization mechanisms reduces the probability of data conflicts and enhances communication stability in complex environments. The closed-loop optimized time slot strategy enables the system to adapt to load changes and operating condition requirements, improving overall communication efficiency.

[0072] In one feasible implementation, refer to Figure 2 The flight controller includes a radio frequency noise sensor and a system register; step S200 includes steps S210 to S230, wherein:

[0073] Step S210: Collect environmental monitoring data from the RS485 bus using the radio frequency noise sensor, and calculate the noise impact coefficient based on the environmental monitoring data;

[0074] Step S220: Read CPU utilization data from the system register and calculate the load adjustment coefficient based on the CPU utilization data;

[0075] Step S230: Based on the number of electronic speed controllers, the noise impact coefficient, and the load adjustment coefficient, the time slot strategy data is generated through a dynamic allocation algorithm.

[0076] In this embodiment, the radio frequency noise sensor is a device used to detect the intensity of electromagnetic interference on the bus. Specifically, it can be implemented using a broadband radio frequency receiving module, generating environmental monitoring data by capturing signal amplitude changes within a specific frequency band. The system register is a storage unit that stores processor operating status information. Specifically, it can read CPU utilization data through the operating system kernel interface to reflect the real-time computational load of the flight control system. The noise impact factor is a parameter that quantifies the degree of interference in the bus communication environment. Specifically, it can be calculated by weighted integration of the radio frequency signal amplitude and is used to evaluate the impact of channel quality on communication rate. The load adjustment factor is a dynamic parameter characterizing the flight control system's data processing capability. Specifically, it can be implemented by mapping the CPU utilization rate to a normalized value within the range of 0-1 and is used to adjust the calculation weights of the time slot allocation strategy. The dynamic allocation algorithm is a computational method that dynamically generates time slot allocation rules based on real-time parameters. Specifically, it can be implemented using a greedy algorithm based on priority sorting to balance communication efficiency and system stability.

[0077] In this embodiment, the RF noise sensor continuously monitors the operating frequency band of the RS485 bus, for example, acquiring RF signal strength within the 2.4GHz band. When increased electromagnetic interference is detected, the noise impact coefficient increases accordingly, triggering a time slot length adjustment mechanism. The system register reads the CPU utilization rate at fixed intervals, for example, acquiring processor load data every 10 milliseconds. When the CPU utilization rate exceeds a set threshold, the load adjustment coefficient decreases by a preset ratio. The dynamic allocation algorithm uses the number of electronic speed controllers as a basic parameter, combining the noise impact coefficient and the load adjustment coefficient for comprehensive calculation. For example, it calculates the priority weight of each node using a weighted summation formula, ultimately generating strategy data that includes time slot length and allocation order.

[0078] In this embodiment, by introducing a radio frequency noise sensor to monitor the communication environment in real time and combining it with a processor load status to dynamically adjust the time slot strategy, communication failures caused by channel quality deterioration or system overload can be effectively avoided. This solves the communication reliability problem of fixed time slot allocation in complex electromagnetic environments and high-load scenarios. By dynamically adjusting the time slot strategy, the optimal allocation of channel resources is achieved, ensuring the real-time transmission of key control commands, while reducing the probability of data conflicts and improving the robustness of the UAV flight control system.

[0079] In one feasible implementation, refer to Figure 3 Step S230 includes steps S231 to S233, wherein:

[0080] Step S231: Set the reference time slot length and adjust the reference time slot length according to the noise impact coefficient;

[0081] Step S232: Set a priority identifier for the electronic speed controller based on the load adjustment coefficient;

[0082] Step S233: Allocate time slot windows for each electronic speed controller according to the priority identifier and the preset electronic speed controller number.

[0083] In this embodiment, the reference time slot length refers to the pre-set initial time slot window length, which can be implemented using a fixed value or dynamically adjusted based on historical communication data, such as 5 milliseconds or 10 milliseconds, and is used to allocate initial communication time resources for each electronic speed controller. The noise impact factor is a quantitative indicator reflecting the current electromagnetic interference level of the RS485 bus. Specifically, it can be obtained by collecting signal amplitude fluctuation data from an RF noise sensor and calculating the standard deviation, and is used to dynamically adjust the time slot length to cope with changes in channel quality. The load adjustment factor is a parameter reflecting the real-time load status of the flight control CPU. Specifically, it can be obtained by reading the CPU utilization rate from the system register and normalizing it, and is used to prioritize the allocation of time slot resources when the flight control is under high load. The priority identifier is a mark used to distinguish the communication priority of the electronic speed controller, and can be implemented using binary flag bits or numerical levels. For example, electronic speed controllers in emergency obstacle avoidance scenarios are marked as high priority to ensure the timeliness of critical data transmission.

[0084] In this embodiment, the reference time slot length is initialized to a fixed value, such as 10 milliseconds, and then dynamically adjusted based on the noise impact factor calculated in real time. When the noise impact factor exceeds a preset threshold, the reference time slot length can be extended to increase communication reliability, for example, extending the time slot to 15 milliseconds in a strong interference environment. Simultaneously, a load adjustment factor is used to determine the priority of each electronic speed controller. For example, when the CPU utilization exceeds 80%, time slot windows are allocated only to electronic speed controllers marked as high priority. During the allocation process, the electronic speed controllers are sorted according to preset numbers, and the allocation order of time slot windows is determined based on priority identifiers. For example, if electronic speed controller number 1 is marked as high priority, its time slot window is allocated before that of the low-priority electronic speed controller number 2.

[0085] Understandably, existing solutions employ fixed time slot lengths and polling sequences, making it impossible to dynamically adjust communication resources based on environmental noise or flight control load. This solution utilizes a dual adjustment mechanism of noise impact factor and load adjustment factor to enable the time slot allocation strategy to adapt to changes in channel quality and system load fluctuations. Simultaneously, the introduction of priority identifiers addresses the issue of delayed critical data transmission in emergency obstacle avoidance scenarios. Through these technical solutions, this application can reduce the probability of data collisions in high electromagnetic interference environments by extending the time slot window, and prioritize the communication needs of critical electronic speed controllers under high flight control loads. The allocation method combining priority and numbering avoids timing chaos when multiple devices compete for the bus, ensuring stable data transmission order and timeliness even in complex environments.

[0086] In one feasible implementation, refer to Figure 4 Step S300 includes steps S310 to S330, wherein:

[0087] Step S310: The electronic speed controller extracts the time slot window from the time slot strategy data;

[0088] Step S320: Calibrate the local clock based on the timestamp data;

[0089] Step S330: When the local clock reaches the start time point in the time slot window, start the random delay timer to perform bus contention detection operation.

[0090] In this embodiment, the time slot window refers to the data transmission time period allocated to the electronic speed controller (ESC). This can be achieved by parsing the time interval field in the time slot strategy data, which limits the time range within which the ESC participates in bus contention. Local clock calibration refers to aligning the ESC's internal timing reference with the flight controller's timestamp data. An interpolation compensation algorithm can be used to adjust the local clock's counting frequency to eliminate accumulated clock errors between master and slave devices. The random delay timer is a timing module used to generate variable delay times. Specifically, it can generate pseudo-random numbers using a linear feedback shift register as the delay base, used to distribute the bus access request timing of multiple ESCs.

[0091] In this embodiment, after receiving the time slot strategy data, the electronic speed controller first parses the time slot window parameters assigned to itself, such as the start time and duration. Then, it calibrates the local clock based on the timestamp data broadcast by the flight control system. For example, it calculates the difference between the current count value of the local clock and the timestamp data, and achieves synchronization by adjusting the clock division factor. When the calibrated local clock reaches the start time of the time slot window, it triggers a random delay timer to start working, for example, generating a random delay value within the range of 0 to 50 microseconds. After the delay ends, the electronic speed controller begins to detect the bus level status, for example, by sampling the differential signal voltage of the RS485 bus three times consecutively. If the bus is detected to be idle, the data transmission process is initiated.

[0092] Understandably, existing technologies typically perform bus contention detection using a fixed delay mechanism, which can lead to multiple electronic speed controllers (ESCs) initiating access requests simultaneously, resulting in signal overlap and conflicts. This solution, however, introduces time slot window partitioning and a random delay mechanism to distribute the bus detection operations of different ESCs across different time periods. For example, by overlaying random delays within the time slot window, the bus access requests from each device are staggered in time, reducing the probability of conflicts. This solves the bus access conflict problem caused by timing drift in traditional master-slave switching protocols. Through time slot window constraints and random delay separation, multiple ESCs can perform bus contention detection in an orderly manner within dynamically allocated time intervals, thereby improving data transmission reliability and avoiding data retransmission errors caused by signal overlap.

[0093] In one feasible implementation, performing a bus contention detection operation includes: generating a random delay seed value; determining a bus detection time interval based on the random delay seed value; sampling the bus level state according to the bus detection time interval to obtain corresponding sample values; and determining that the bus contention detection has passed when the sample value is lower than a preset level for a preset number of consecutive times.

[0094] In this embodiment, the random delay seed value refers to the initial parameter used to initialize the delay calculation. Specifically, it can be implemented using a linear feedback shift register to generate pseudo-random numbers. Its purpose is to avoid contention caused by multiple electronic speed controllers simultaneously starting bus detection. The bus detection time interval refers to the interval between two level samples. Specifically, it can be dynamically adjusted by the counter module based on the seed value to distribute the detection timing of different devices. The preset number of times refers to the minimum threshold for continuously detecting the bus idle state, for example, it can be set to a range of 3 to 5 times. The continuous sampling results are recorded by the shift register to ensure the reliability of the bus idle state.

[0095] In this embodiment, after the electronic speed controller enters the allocated time slot window according to the time slot strategy, it first calls the random number generation module to generate a seed value. This seed value is input to the delay calculation unit to generate a non-fixed interval bus detection timing sequence. Under the control of the bus detection time interval, the level sampling module periodically reads the differential signal of the RS485 bus and stores the results in a buffer queue. When the continuously recorded sampled values ​​in the buffer queue are all lower than a preset voltage threshold, it is determined that the bus is in an idle state and data transmission is allowed. For example, during the flight of a UAV, if an electronic speed controller detects that the bus is idle three times in a row, it immediately starts the data transmission process, effectively avoiding multiple devices occupying the bus at the same time.

[0096] In this embodiment, by introducing a randomized delay mechanism, the detection time points of each device are discretely distributed. Combined with a multiple continuous sampling verification mechanism, the probability of false triggering caused by instantaneous interference or timing overlap is significantly reduced. This can effectively solve the signal conflict problem caused by fixed timing during bus competition among multiple electronic speed controllers. Through randomized delay and multi-condition verification mechanisms, the accuracy of bus status determination in complex electromagnetic environments is ensured, thereby improving the real-time performance and reliability of flight control command transmission.

[0097] In one feasible implementation, refer to Figure 5 Step S500 includes steps S510 to S540, wherein:

[0098] Step S510: Read the safe distance threshold from the preset aircraft safety parameter library;

[0099] Step S520: Compare and analyze the motor speed and obstacle distance data in the status report data;

[0100] Step S530: When the obstacle distance data is less than the safe distance threshold, mark the corresponding electronic speed controller as high priority;

[0101] Step S540: Generate flight control command data containing high priority markers.

[0102] In this embodiment, the safe distance threshold is a pre-set minimum safe interval parameter between the aircraft and the obstacle. Specifically, it can be accessed in real-time from stored data in the aircraft safety parameter library to determine whether an emergency obstacle avoidance operation needs to be triggered. The comparison analysis of motor speed and obstacle distance data refers to correlating the speed data reported by the electronic speed controller with the real-time distance data collected by the obstacle avoidance sensor. For example, it uses a mapping table or algorithm model to determine whether the current speed might prevent the aircraft from decelerating in time when the obstacle is too close. High-priority marking refers to identifying a specific electronic speed controller, allowing it to be preferentially allocated time slot windows in subsequent communication cycles. This can be achieved, for example, by modifying the priority identifier field in the time slot strategy data.

[0103] In this embodiment, after the flight controller receives the status data reported by the electronic speed controller, it simultaneously acquires obstacle distance data collected by obstacle avoidance sensors, such as distance values ​​obtained through ultrasonic or infrared sensors. By comparing the current motor speed with the obstacle distance, if the obstacle distance is lower than a safety threshold, the motor corresponding to the electronic speed controller is determined to be in a high-risk state, and its control parameters need to be adjusted first. At this time, the flight controller embeds a high-priority marker in the generated flight control command data, for example, by adding a specific identifier bit to the header of the data frame, so that the subsequent time slot allocation module can adjust the communication priority of the corresponding electronic speed controller according to the identifier.

[0104] In this embodiment, by real-time correlation of obstacle distance and motor status data, this solution can immediately mark high-priority devices when a safety risk is detected, thereby optimizing the allocation of communication resources and shortening the generation and issuance time of emergency control commands. This enables the rapid identification of high-risk electronic speed controllers during obstacle avoidance and priority processing of their control commands, avoiding control failures caused by communication delays. At the same time, the dynamic priority adjustment mechanism ensures the timeliness of critical data transmission, improving the safety and response efficiency of the aircraft in complex environments.

[0105] In one feasible implementation, the step of marking the corresponding electronic speed controller as high priority when the obstacle distance data is less than the safe distance threshold includes: determining the physical address of the high-priority electronic speed controller; updating the priority identifier of the physical address in the time slot strategy data; and pre-setting a first duration for the start time of the time slot window corresponding to the high-priority physical address.

[0106] In this embodiment, the physical address of the high-priority electronic speed controller is its unique identifier on the RS485 bus. It can be stored in a register using hexadecimal encoding for precise target device location during communication. The priority flag is a marker used to distinguish the data transmission priorities of different devices. It can be embedded in the time-slot strategy data frame as a binary flag, and priority can be dynamically adjusted through setting operations. The pre-setting of the time-slot window start time by a first duration means shifting the communication window start time of the high-priority device forward by a fixed amount of time. This can be configured using a preset time unit, ensuring that critical data can preferentially occupy bus resources.

[0107] In this embodiment, when the obstacle avoidance sensor detects that the distance to an obstacle is below a safe threshold, the flight control unit immediately parses the physical address information of the current electronic speed controller and modifies the priority flag bit of the corresponding address in the time slot policy data packet. After the priority flag is updated, the system automatically calculates the start time of the time slot window for the electronic speed controller in the next communication cycle and advances it by a preset first duration, for example, 3 milliseconds. This mechanism allows the electronic speed controller in emergency obstacle avoidance mode to preferentially occupy the bus transmission channel, ensuring that the generation and execution of flight control commands are not affected by the delay of the conventional data transmission queue.

[0108] In this embodiment, by dynamically adjusting priority flags and time slot windows, data transmission preemption for critical equipment in emergency situations is achieved, effectively shortening the response delay of control commands. This allows for rapid adjustment of communication strategies when the UAV approaches obstacles, prioritizing the processing of status data from high-risk motors and avoiding control command lag caused by bus contention. The flight control unit can generate adjustment commands in real time based on high-priority data to ensure the aircraft maintains a stable attitude during obstacle avoidance.

[0109] In one feasible implementation, refer to Figure 6 Step S600 includes steps S610 to S630, wherein:

[0110] Step S610: Extract the physical address of the electronic speed controller from the retransmission command data as the retransmission address;

[0111] Step S620: Generate a new time slot window based on the high priority identifier and retransmission address in the flight control command data;

[0112] Step S630: Combine the new time slot window with the priority identifier to form optimized time slot policy data.

[0113] In this embodiment, the electronic speed controller (ESC) physical address in the retransmission command data is data containing a unique identifier for a specific ESC, generated when the flight control system fails to verify the data. This can be implemented using hexadecimal values ​​stored in an address encoding register, used to locate the device requiring retransmission in the next communication cycle. The high-priority identifier is a marker signal generated by the flight control system based on a comparison of obstacle avoidance sensor data and a safety threshold. It can be identified using binary bits in the status register and used to elevate the transmission priority of critical devices during time slot allocation. The new time slot window refers to the data transmission period adjusted according to priority. Specifically, a dynamic time allocation algorithm can be used to recalculate the start time and duration, for example, advancing the start time of the window for high-priority devices or extending the transmission duration. The priority identifier refers to the weight parameter of the ESC in the time slot strategy. Specifically, it can be associated with the priority levels of different devices through an address mapping table, used to determine the transmission order during bus contention.

[0114] In this embodiment, when the flight controller detects a failure in the status reporting data verification, it extracts the physical address of the electronic speed controller from the verification failure frame and writes it into the retransmission command data. Simultaneously, the flight controller compares the obstacle distance collected by the obstacle avoidance sensor with a preset safety threshold. If a collision risk exists, a high-priority identifier is added to the associated electronic speed controller. When generating the time slot policy for the next cycle, the system prioritizes allocating an earlier time slot window start time to devices with high-priority identifiers, for example, advancing the start time to the beginning of the communication cycle. For device addresses requiring retransmission, the system allocates a separate time period in the time slot policy to avoid conflicts with other devices. If the time slot windows of high-priority devices and retransmission devices overlap, the system can create parallel transmission paths, for example, by enabling redundant communication channels or dividing the time slot window into multiple sub-segments. The final optimized time slot policy data includes updated priority identifiers and a time slot allocation table, and is broadcast to all electronic speed controllers for execution.

[0115] In this embodiment, the proposed solution establishes a dynamic priority adjustment mechanism by associating obstacle distance data with device status. This prioritizes the transmission of motor control data closer to obstacles. Simultaneously, a dedicated time slot window is created for retransmission requests, effectively preventing secondary retransmissions caused by data conflicts and improving communication reliability. Thus, this application solves the problem of delayed critical data transmission in emergency obstacle avoidance scenarios using traditional master-slave switching protocols, enabling immediate response to high-priority device data. By dynamically generating time slot windows and parallel paths, the probability of signal conflicts caused by multiple devices competing for the bus is reduced. The optimized time slot strategy data can adjust the transmission order in real time according to flight status, ensuring the synchronization of control commands and sensor feedback, thereby improving the control accuracy of the aircraft in complex environments.

[0116] In one feasible implementation, step S620 includes setting a dedicated transmission channel identifier for the retransmission address, allocating a time slot window with a preset second duration to the physical address corresponding to the high priority identifier, and creating a parallel transmission path when the retransmission address conflicts with the high priority address.

[0117] In this embodiment, the dedicated transmission channel identifier is an independent communication path identifier assigned to the electronic speed controller that needs to retransmit data. Specifically, this can be achieved by adding a channel number field to the time slot strategy data, used to isolate retransmitted data from regular data transmission to reduce interference. Extending the preset second time slot window refers to dynamically adjusting the communication time capacity of the high-priority electronic speed controller according to the urgency of the flight scenario. This can be implemented using a dynamic time slot expansion algorithm to ensure that critical data is transmitted with priority in obstacle avoidance scenarios. Parallel transmission paths refer to establishing auxiliary communication links through multiplexing technology when address conflicts occur. This can be achieved by configuring redundant bus interfaces or enabling backup communication protocols to avoid data loss due to address contention.

[0118] In this embodiment, when high-priority identifiers or retransmission command data are present in the flight control command data, a dedicated channel identifier is first assigned to the retransmission address to isolate its communication process and prevent signal conflicts with other devices. Simultaneously, the time slot window corresponding to the high-priority electronic speed controller is extended by a preset duration, for example, by adding a fixed proportion of time margin to the original time slot to ensure its status data is uploaded completely. If a time slot overlap is detected between the retransmission address and the high-priority address, a parallel transmission path is activated through the bus arbitration module, for example, by assigning conflicting devices to different physical channels or employing a time-division multiplexing mechanism to achieve parallel data transmission.

[0119] In some specific implementations, a dedicated transmission channel identifier can be added to the data frame header using channel encoding, while the creation of parallel transmission paths can be achieved using a double-buffering mechanism, automatically switching to a backup buffer for temporary data storage when an address conflict is detected. The extension of the time slot window can be achieved by adjusting the clock division factor, for example, by increasing the system clock's counting threshold by a certain percentage to expand the communication time window.

[0120] Understandably, existing solutions rely solely on fixed-priority queuing mechanisms when address conflicts occur, leading to delays in critical data transmission under high load scenarios. This proposed solution, however, dynamically allocates dedicated channels and parallel paths to maintain data transmission continuity even in the event of address conflicts. Particularly in obstacle avoidance scenarios, the status data of high-priority electronic speed controllers can be extended to allow sufficient transmission time, preventing control command delays caused by communication congestion. This solves the problem of low data retransmission efficiency due to address conflicts in traditional master-slave communication. In emergency obstacle avoidance scenarios, it prioritizes the status feedback channels for critical motors, while parallel transmission paths reduce the data error rate caused by bus contention, significantly improving the real-time response capability and communication reliability of the flight control system.

[0121] In this embodiment, the data transmission method between the electronic speed controller and the flight controller based on adaptive master-slave switching solves the problems of high latency, timing drift, and delayed response in emergency scenarios of the traditional polling mechanism by dynamically generating time slot strategies, calibrating the local clock, prioritizing and optimizing the retransmission mechanism. This method can improve the real-time performance of data transmission, reduce the probability of communication conflicts, and enhance the control response capability in emergency obstacle avoidance scenarios, thereby improving the flight performance and safety of the UAV.

[0122] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the data transmission method between the electronic speed governor and the flight controller based on adaptive master-slave switching. Any simple modifications based on this technical concept are within the protection scope of this application.

[0123] This application also provides a data transmission system between an electronic speed governor and a flight controller based on adaptive master-slave switching, referring to... Figure 7 The adaptive master-slave switching-based electronic speed controller and flight controller data transmission system includes: a memory 10, a processor 20, and an adaptive master-slave switching-based electronic speed controller and flight controller data transmission program stored in the memory 10 and executable on the processor 20. The adaptive master-slave switching-based electronic speed controller and flight controller data transmission program is configured to implement the steps of the adaptive master-slave switching-based electronic speed controller and flight controller data transmission method.

[0124] The adaptive master-slave switching-based electronic speed controller and flight controller data transmission system provided in this application, employing the adaptive master-slave switching-based electronic speed controller and flight controller data transmission method described in the above embodiments, can improve the safety of unmanned aerial vehicles (UAVs). Compared with the prior art, the beneficial effects of the adaptive master-slave switching-based electronic speed controller and flight controller data transmission system provided in this application are the same as those of the adaptive master-slave switching-based electronic speed controller and flight controller data transmission method provided in the above embodiments. Furthermore, other technical features of the adaptive master-slave switching-based electronic speed controller and flight controller data transmission system are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0125] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0126] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. All equivalent structural transformations made under the technical concept of this application using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of this application.

Claims

1. A data transmission method between an electronic speed controller and a flight controller based on adaptive master-slave switching, employing RS485 bus communication, characterized in that... The method includes: The flight controller, acting as the host, broadcasts control command frames containing real-time control parameters to all electronic speed controllers via the RS485 bus. After the control command frames are sent, it generates timestamp data and broadcasts time synchronization frames containing that timestamp data. The flight controller acquires environmental monitoring data from the RS485 bus and reads CPU utilization data. Based on the environmental monitoring data, CPU utilization data, and the number of electronic speed controllers, it generates time slot strategy data. Each electronic speed controller receives the time synchronization frame and time slot strategy data, calibrates its local clock based on the timestamp data, and performs a bus contention detection operation according to the time slot strategy data. During bus contention testing, each electronic speed controller acts as a temporary host within the time slot window allocated based on the time slot strategy data, and sends status reporting data to the flight controller via the RS485 bus. The flight controller receives the status report data and acquires obstacle distance data collected by the obstacle avoidance sensor. It then performs correlation analysis between the obstacle distance data and the status report data to generate flight control command data. The flight controller performs verification calculations on the reported status data. If the verification fails, it generates retransmission command data containing the address of the electronic speed controller. Based on the flight control command data and the retransmission command data, it generates optimized time slot strategy data for use in the next communication cycle. The flight controller includes a radio frequency noise sensor and a system register; the flight controller acquires environmental monitoring data from the RS485 bus and reads CPU utilization data, and the step of generating time slot strategy data based on the environmental monitoring data, CPU utilization data, and the number of electronic speed controllers includes: The radio frequency noise sensor collects environmental monitoring data from the RS485 bus, and the noise impact coefficient is calculated based on the environmental monitoring data. Read CPU utilization data from the system registers and calculate the load adjustment factor based on the CPU utilization data; Based on the number of electronic speed controllers, the noise impact coefficient, and the load adjustment coefficient, the time slot strategy data is generated through a dynamic allocation algorithm. The step of generating the time slot strategy data based on the number of electronic speed controllers, the noise impact factor, and the load adjustment factor using a dynamic allocation algorithm includes: Set the reference time slot length and adjust the reference time slot length according to the noise impact factor; Set priority identifiers for electronic speed controllers based on load adjustment coefficients; The time slot window for each electronic speed controller is assigned according to the priority identifier and the preset electronic speed controller number.

2. The data transmission method between the electronic speed controller and flight control system based on adaptive master-slave switching as described in claim 1, characterized in that, The steps of each electronic speed controller receiving the time synchronization frame and time slot strategy data, calibrating its local clock based on the timestamp data, and performing a bus contention detection operation according to the time slot strategy data include: The electronic speed governor extracts the time slot window from the time slot strategy data; The local clock is calibrated based on the timestamp data; When the local clock reaches the start time point of the time slot window, a random delay timer is started to perform a bus contention detection operation.

3. The data transmission method between the electronic speed controller and flight control system based on adaptive master-slave switching as described in claim 2, characterized in that, The bus contention detection operation includes: Generate a random delay seed value; The bus detection time interval is determined based on the random delay seed value; The bus level state is sampled according to the bus detection time interval to obtain the corresponding sampled value; When the sampled value is lower than the preset level for a consecutive preset number of times, it is determined that the bus competition detection is passed.

4. The data transmission method between the electronic speed controller and flight controller based on adaptive master-slave switching as described in claim 1, characterized in that, The steps of receiving the status report data and acquiring obstacle distance data collected by the obstacle avoidance sensor, and then performing correlation analysis between the obstacle distance data and the status report data to generate flight control command data include: Read the safe distance threshold from the preset aircraft safety parameter library; Compare and analyze the motor speed and obstacle distance data in the status report data; When the obstacle distance data is less than the safe distance threshold, the corresponding electronic speed controller is marked as high priority; Generate flight control command data containing high-priority tags.

5. The data transmission method between the electronic speed controller and flight control system based on adaptive master-slave switching as described in claim 4, characterized in that, The step of marking the corresponding electronic speed controller as high priority when the obstacle distance data is less than the safe distance threshold includes: Determine the physical address of the high-priority electronic speed controller; Update the priority identifier of the physical address in the time slot policy data; The first duration is preset for the start time of the time slot window corresponding to the high-priority physical address.

6. The data transmission method between the electronic speed controller and flight control system based on adaptive master-slave switching as described in claim 5, characterized in that, The step of generating optimized time slot strategy data for the next communication cycle based on the flight control command data and the retransmission command data includes: Extract the electronic speed controller physical address from the retransmission command data as the retransmission address; A new time slot window is generated based on the high-priority identifier and retransmission address in the flight control command data. The new time slot window is combined with the priority identifier to form the optimized time slot policy data.

7. The data transmission method between the electronic speed controller and flight control system based on adaptive master-slave switching as described in claim 1, characterized in that, The step of generating a new time slot window based on the high-priority identifier and retransmission address in the flight control command data includes: A dedicated transmission channel identifier is set for the retransmission address, a time slot window with a preset second duration is allocated to the physical address corresponding to the high priority identifier, and a parallel transmission path is created when the retransmission address conflicts with the high priority address.

8. A data transmission system between an electronic speed governor and a flight controller based on adaptive master-slave switching, characterized in that, The adaptive master-slave switching-based electronic speed controller and flight controller data transmission system includes: a memory, a processor, and an adaptive master-slave switching-based electronic speed controller and flight controller data transmission program stored in the memory and executable on the processor. The adaptive master-slave switching-based electronic speed controller and flight controller data transmission program is configured to implement the steps of the adaptive master-slave switching-based electronic speed controller and flight controller data transmission method as described in any one of claims 1 to 7.

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