Wafer-level packaging structure and manufacturing method

Abstract

The invention discloses a wafer-level packaging structure and a manufacturing method thereof. The manufacturing method comprises the following steps: step 1, wafer feeding: preparing a wafer to be processed; 2, a single-side coating process: coating a photoresist layer above the wafer to form a photoresist layer I; 3, performing a halftone mask photoetching process: exposing the photoresist layer I by using a photomask, wherein the photomask comprises a region A, a region B and a region C; the photomask in the B area is designed to be semi-transparent; step 4, developing and forming: removing part of the light resistance layer I which is not exposed and cured through a developing solution; and 5, single-layer curing: curing the developed and molded photoresist layer 1. The invention belongs to the field of semiconductor packaging, and particularly relates to a wafer-level packaging structure and a manufacturing method. According to the invention, the halftone mask is utilized, so that the photoresist layer can generate a step shape, a step type RDL wiring structure can be formed in a subsequent RDL process, a step-shaped intermetallic compound is formed after ball mounting, and the temperature cycle / drop reliability test strength is enhanced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a wafer-level packaging structure and a manufacturing method. BACKGROUND

[0002] In the current situation of rapid miniaturization and high integration of the semiconductor industry, wafer-level packaging technology has become the mainstream packaging solution in the fields of consumer electronics and the Internet of Things due to its size advantage and cost efficiency. However, in traditional packaging processes, the limitations of conventional mask technology are increasingly becoming a key bottleneck restricting the improvement of packaging performance, especially when dealing with reliability challenges under complex working conditions, the problem is increasingly prominent. Traditional mask technology can only form a planar structure when processing the photoresist layer (PI layer) due to the limitation of its binary exposure characteristics of "full light transmission / full non-transmission". This planar PI layer inevitably forms a flat wiring structure in the subsequent redistribution layer (RDL) process. After the ball planting process is completed, the intermetallic compound (IMC) also presents a flat shape. In actual application scenarios, especially in the board-level temperature cycle (TC) and drop reliability test, this flat structure exposes significant defects. Due to the lack of stress dispersion design, under the condition of temperature changes or mechanical impact, the flat IMC and RDL structure will produce serious stress concentration phenomenon, causing frequent failure problems such as solder ball cracking and line breakage, which is difficult to meet the stringent requirements of automotive electronics, industrial control and other high-reliability fields. At the same time, the demand for chip performance in the semiconductor industry continues to upgrade, and emerging technologies such as 5G communication and artificial intelligence have higher standards for the signal transmission efficiency, heat dissipation capacity and mechanical reliability of packaging. The traditional flat packaging structure not only cannot effectively disperse thermal stress and mechanical stress, but also limits the improvement of packaging density due to its single planar wiring method, making it difficult to adapt to the development trend of chip function integration. Under this background, it is an urgent need to develop a new wafer-level packaging structure and manufacturing method to break through the limitations of traditional mask technology, realize the non-planar design of PI layer, RDL layer and IMC, and improve the reliability and performance of packaging. This technology focuses on solving the pain points of traditional packaging processes, and aims to realize the preparation of stepped PI layer through innovative mask technology and process optimization, and then build stepped RDL wiring and IMC structure with stress dispersion function. The proposal of this scheme not only can effectively improve the reliability performance of packaging in the board-level TC and drop test, but also provides a new technical idea and practical path for the development of semiconductor packaging technology to higher performance and more complex structure. SUMMARY

[0003] In view of the above, in order to overcome the defects of the prior art, the application provides a wafer-level packaging structure and a manufacturing method, which effectively solve the problem that the mask cannot make the photoresist layer have a stepped shape and the intermetallic compound cannot form a stepped shape after ball planting in the current market.

[0004] The technical solutions adopted by the application are as follows: the application provides a wafer-level packaging structure and a manufacturing method, which comprise the following steps:

[0005] Further, step one: wafer incoming: preparing a wafer to be processed;

[0006] Step two: single-side coating process: coating a photoresist layer on the wafer to form a photoresist layer one;

[0007] Step three: half-tone mask photoetching process: using a mask to expose the photoresist layer one, wherein the mask comprises an A area, a B area and a C area; the mask in the B area is designed to be semi-transparent;

[0008] Step four: developing and forming: removing the unexposed and solidified part of the photoresist layer one by a developing solution;

[0009] Step five: single-layer solidification: solidifying the photoresist layer one after developing and forming;

[0010] Step six: redistribution layer process: setting an RDL layer on the photoresist layer one, setting a photoresist layer two on the RDL layer, and after exposure and development, part of the RDL layer is exposed to form a circuit;

[0011] Step seven: ball planting: setting a solder ball on the exposed RDL layer.

[0012] Further, the photoresist layer one comprises a positive photoresist and a negative photoresist.

[0013] Further, when the photoresist layer one is a negative photoresist, the A area is an opaque area, the B area is a semi-transparent area, and the C area is a transparent area.

[0014] Further, when the photoresist layer one is a positive photoresist, the A area is a transparent area, the B area is a semi-transparent area, and the C area is an opaque area.

[0015] Further, in step four, the unexposed and solidified part of the photoresist layer one is removed by a developing solution, including that a position one on the photoresist layer one corresponding to the opaque area is not exposed and solidified, is removed after development, a position two on the photoresist layer one corresponding to the transparent area is exposed and solidified, is retained after development, and a position three on the photoresist layer one corresponding to the semi-transparent area is exposed and solidified and is in a semi-setting state, the upper part of the position three is removed after development, the lower part of the position three is retained, and the position three forms a stepped structure.

[0016] Further, the step six of exposing the RDL layer partially includes exposing the RDL layer above the B area by exposure and development.

[0017] Further, the step seven of setting the solder ball on the exposed RDL layer includes forming the electrical connection by reflow soldering.

[0018] Further, the method comprises a wafer, a photoresist layer one is arranged above the wafer, an RDL layer is arranged above the photoresist layer one, a photoresist layer two is arranged above the RDL layer, the photoresist layer two exposes the RDL layer partially, and a solder ball is arranged above the partially exposed RDL layer.

[0019] Further, the method is prepared according to any one of claims 1-6.

[0020] The beneficial effects of the present application with the above structure are as follows: the present application provides a wafer level packaging structure and manufacturing method, which uses a half-tone mask to make the photoresist layer have a ladder shape, without increasing the process cycle and steps, and greatly increasing the temperature cycle / drop reliability test strength. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A general flow chart of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0022] Figure 2 A step one schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0023] Figure 3 A step two schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0024] Figure 4 A step three schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0025] Figure 5 A step four schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0026] Figure 6 A step five schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0027] Figure 7 A step six schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure;

[0028] Figure 8 A step seven schematic diagram of the wafer level packaging structure and manufacturing method provided by the present application is shown in the figure.

[0029] Wherein, 1, wafer; 2, photoresist layer one; 3, photomask; 4, RDL layer; 5, photoresist layer two; 6, solder ball; 7, A area; 8, B area; 9, C area; 10, position one; 11, position two; 13, position three.

[0030] The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the specification, and are used to explain the present application together with the embodiments of the present application, and do not constitute a limitation on the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0032] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0033] As shown in the drawings, Figures 1-8 The present application proposes a wafer-level packaging structure and manufacturing method, including the following steps: step one: wafer incoming: preparing a wafer 1 to be processed;

[0034] Step two: single-sided coating process: coating a photoresist layer on the wafer 1 to form a photoresist layer one 2;

[0035] Step three: half-tone mask photolithography process: using a photomask 3 to expose the photoresist layer one 2, the photomask 3 including an A area 7, a B area 8 and a C area 9; the photomask of the B area is designed to be semi-transparent;

[0036] Step four: developing and forming: removing the unexposed and solidified part of the photoresist layer one 2 by developing solution;

[0037] Step five: single-layer solidification: solidifying the photoresist layer one 2 after developing and forming;

[0038] Step six: redistribution layer process: setting an RDL layer 4 on the photoresist layer one 2, and setting a photoresist layer two 5 on the RDL layer 4, after exposure and development, part of the RDL layer 4 is exposed to form a circuit;

[0039] Step seven: ball planting: setting a solder ball 6 on the exposed RDL layer 4.

[0040] Specifically, the wafer 1 is prepared, a photoresist layer 1 is formed above the wafer by spin coating; the photoresist layer 1 is exposed by using the light-transmitting, non-light-transmitting and semi-light-transmitting regions of the mask for a single time, so that part of the photoresist layer is bonded and shaped; the unshaped part is removed by a developing solution, and the remaining photoresist layer is cured at high temperature to enhance the performance; after the RDL layer 4 is made, the photoresist layer 2 is coated and exposed and developed to expose the circuit; finally, the ball 6 is planted on the exposed RDL layer 4 and reflow soldering is performed to form electrical connection. The single-side coating process is combined with the half-tone mask photoetching process to reduce the process, the electrical performance is improved after the photoresist layer is cured, and the ball is planted on the exposed RDL layer 4 to realize high-density electrical interconnection.

[0041] The photoresist layer 1 2 includes a positive photoresist and a negative photoresist.

[0042] Specifically, the positive photoresist will change chemically after exposure and become easy to be dissolved by the developing solution; the negative photoresist is opposite, which will be cross-linked and cured after exposure and is difficult to be dissolved by the developing solution. The photoresist layer 1 2 provides two kinds of photoresist selection, which can be flexibly selected according to the specific process requirements, pattern complexity and other factors, thereby enhancing the adaptability of the process.

[0043] When the photoresist layer 1 2 is a negative photoresist, the A area 7 is a non-light-transmitting area, the B area 8 is a semi-light-transmitting area, and the C area 9 is a light-transmitting area. The position 1 0 of the photoresist layer 1 2 corresponding to the non-light-transmitting area 7 is not exposed and cured, and is removed after development; the position 1 1 of the photoresist layer 1 2 corresponding to the light-transmitting area 9 is exposed and cured, and is retained after development; the position 1 2 of the photoresist layer 1 2 corresponding to the semi-light-transmitting area 8 is exposed and cured and is in a semi-shaped state after development, the upper part of the position 1 2 is removed, and the lower part of the position 1 2 is retained, so as to form a stepped structure at the position 1 2.

[0044] Specifically, when the photoresist layer 1 2 is a negative photoresist, the A area 7 is non-light-transmitting, the photoresist of the corresponding area is not exposed and remains in an uncured state and is easy to be removed by the developing solution; the B area 8 is semi-light-transmitting, the corresponding photoresist receives part of light and is in a semi-cured state; the C area 9 is light-transmitting, the corresponding photoresist is fully exposed and cured and is difficult to be removed by the developing solution. By reasonably designing the light-transmitting property of each area of the mask, the exposure degree of the negative photoresist can be accurately controlled, so as to obtain a photoresist structure meeting the design requirements and lay a good foundation for subsequent processes. When the photoresist layer 1 2 is a positive photoresist, the A area 7 is a light-transmitting area, the B area 8 is a semi-light-transmitting area, and the C area 9 is a non-light-transmitting area.

[0045] Specifically, for the photoresist layer 1 2 of the positive photoresist, the A area 7 is light-transmitting, so that the corresponding photoresist is easy to be removed by the developing solution after exposure; the B area 8 is semi-light-transmitting, so that the corresponding photoresist is partially exposed; and the C area 9 is non-light-transmitting, so that the corresponding photoresist is not exposed and remains. In this way, the removal and retention areas of the photoresist can be effectively controlled, the accuracy of the photoetching process is ensured, and it is beneficial to form a complex circuit layout.

[0046] The above-mentioned stepped structure can be used in subsequent RDL layer wiring and other processes to realize electrical connections of different heights. The formation of the stepped structure increases the three-dimensional space utilization of the packaging structure, which is beneficial to realize more complex electrical connections and improve the packaging density.

[0047] In step six, part of the RDL layer 4 is exposed, including exposing the RDL layer 4 above the B area 8 by exposure and development.

[0048] Specifically, in step six, the RDL layer 4 above the B area 8 is exposed by exposure and development of the photoresist layer 2, and the exposed RDL layer serves as a node connected to the solder ball to ensure the reliability of the electrical connection.

[0049] In step seven, the solder ball 6 is arranged on the exposed RDL layer 4, including forming an electrical connection by reflow soldering.

[0050] Specifically, in step seven, when the solder ball 6 is arranged on the exposed RDL layer 4, the reflow soldering melts the solder ball by heating, and then cools and solidifies to form a firm electrical connection and mechanical combination between the solder ball and the RDL layer, ensuring effective communication between the packaging structure and the external circuit.

[0051] The wafer-level packaging structure of the application comprises a wafer 1, a photoresist layer 1 2 arranged above the wafer 1, an RDL layer 4 arranged above the photoresist layer 1 2, a photoresist layer 2 5 arranged above the RDL layer 4, part of the RDL layer 4 exposed by the photoresist layer 2 5, and a solder ball 6 arranged above the partially exposed RDL layer 4.

[0052] Specifically, the wafer 1 is the base of the entire structure, the photoresist layer 1 2 is arranged above the wafer to serve as insulation and support. The RDL layer 4 is arranged above the photoresist layer 1 to realize redistribution of the internal circuit of the wafer. The photoresist layer 2 5 is arranged above the RDL layer to protect part of the RDL layer while exposing part of the RDL layer area for arranging the solder ball 6, and the solder ball 6 realizes electrical connection with the outside.

[0053] The product is prepared according to the preparation method of any one of claims 1-6.

[0054] Compared with the traditional packaging, the present application uses a half-tone mask to make the photoresist layer have a stepped shape. After ball placement, the stepped metal interconnect compound (IMC) can be formed, which can greatly increase the product temperature cycle / drop reliability test strength, thereby increasing the reliability of the product. At the same time, the present application does not need to increase the product process cycle and steps, and the process level is relatively high.

[0055] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other present or future technologies can provide. Specifically, it is contemplated that some embodiments of the present application can be practiced without the specific details set forth in the preceding description.

[0056] While the embodiments of the application have been illustrated and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the application, which is defined by the appended claims and their equivalents.

[0057] The above description of the application and its embodiments is not restrictive, and the embodiments shown in the drawings are only one of the embodiments of the application, and the actual structure is not limited thereto. In general, if a person skilled in the art is inspired by it, without departing from the purpose of the application, without creative design, similar structure and embodiments of the technical solution should belong to the protection scope of the application.

Claims

1. A method for manufacturing a wafer level package structure, comprising the steps of: providing a wafer (1); applying a photoresist layer on the wafer (1) to form a photoresist layer (2); using a mask (3) to expose the photoresist layer (2), wherein the mask (3) comprises an A area (7), a B area (8) and a C area (9), and the B area is semi-transparent; removing the unexposed part of the photoresist layer (2) by developing; curing the developed photoresist layer (2); forming a RDL layer (4) on the photoresist layer (2), and forming a photoresist layer (5) on the RDL layer (4), wherein the RDL layer (4) is partially exposed after exposure and development, and a circuit is formed; and setting solder balls (6) on the exposed RDL layer (4).

2. The method according to claim 1, wherein the photoresist layer (2) is a positive photoresist or a negative photoresist.

3. The method according to claim 2, wherein when the photoresist layer (2) is a negative photoresist, the A area (7) is opaque, the B area (8) is semi-transparent, and the C area (9) is transparent.

4. The method according to claim 2, wherein when the photoresist layer (2) is a positive photoresist, the A area (7) is transparent, the B area (8) is semi-transparent, and the C area (9) is opaque.

5. The method according to claim 3, wherein in the step of removing the unexposed part of the photoresist layer (2) by developing, the position one (10) on the photoresist layer (2) corresponding to the opaque area (7) is not exposed and cured, and is removed after development; the position two (11) on the photoresist layer (2) corresponding to the transparent area (9) is exposed and cured, and is retained after development; and the position three (12) on the photoresist layer (2) corresponding to the semi-transparent area (8) is exposed and cured, and is in a semi-solidified state after development, wherein the upper part of the position three (12) is removed, and the lower part of the position three (12) is retained, and a stepped structure is formed at the position three (12).

6. The method according to claim 1, wherein in the step of partially exposing the RDL layer (4), the RDL layer (4) above the B area (8) is exposed and developed.

7. The method according to claim 1, wherein in the step of setting solder balls (6) on the exposed RDL layer (4), reflow soldering is used to form an electrical connection.

8. A wafer level package structure manufactured by the method according to claim 1. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The application relates to a wafer (1) provided with a photoresist layer (2) on the top, an RDL layer (4) on the top of the photoresist layer (2), a photoresist layer (5) on the top of the RDL layer (4), the photoresist layer (5) partially exposing the RDL layer (4), and a solder ball (6) on the top of the partially exposed RDL layer (4).

9. A wafer level package structure, characterized by, The application relates to a wafer (1) provided with a photoresist layer (2) on the top, an RDL layer (4) on the top of the photoresist layer (2), a photoresist layer (5) on the top of the RDL layer (4), the photoresist layer (5) partially exposing the RDL layer (4), and a solder ball (6) on the top of the partially exposed RDL layer (4). The application relates to a wafer (1) provided with a photoresist layer (2) on the top, an RDL layer (4) on the top of the photoresist layer (2), a photoresist layer (5) on the top of the

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