Narrow pulse generation system and method of FPGA (Field Programmable Gate Array) integrated fiber laser

Abstract

The invention discloses a narrow pulse generation system and method of an FPGA integrated fiber laser, and belongs to the field of all-digital fiber laser control. The narrow pulse generation system comprises a multi-phase clock generation module, a dynamic delay chain module, a pulse width search module, a signal selection module, a logic operation module, a frequency control module, a self-calibration module and an LVDS driving module which are in synergistic effect. The multi-phase clock generation module is used for realizing rough delay adjustment of nanosecond stepping; the dynamic delay chain module is used for realizing fine delay adjustment of picosecond stepping; therefore, based on the FPGA integrated design, an external delay chip and a high-frequency peripheral circuit are not needed, the hardware complexity and cost are reduced, and the anti-interference capability is high; picosecond-level stepping pulse width adjustment is realized through a two-level structure of nanosecond-level coarse adjustment and picosecond-level fine adjustment, and the limitation of a traditional FPGA (Field Programmable Gate Array) integration scheme is broken through; time delay deviation caused by environment change and hardware drift is considered, temperature compensation and TDC calibration are carried out, and the stability of pulse width is ensured.

Description

Technical Field

[0001] This invention relates to the field of all-digital fiber laser control technology, and in particular to a narrow pulse generation system and method for an FPGA-integrated fiber laser. Background Technology

[0002] In fiber lasers, narrow pulse signals are one of the core technologies for improving peak power and reducing thermal diffusion damage. Existing narrow pulse generation schemes have the following problems and corresponding defects: (1) Reliance on external delay chips (such as patents CN111404515A and CN112636167A): High-frequency peripheral circuits are required, which are easily affected by signal reflection and crosstalk. Strict impedance matching and shielding design are required, resulting in high hardware complexity. The maximum delay of a single chip is limited, and long delay requirements require cascading, which further increases the design difficulty; (2) Using only FPGA without peripheral circuits (such as patents CN109828632A and CN109981084B) (3) Based on DAC timing control (such as patent CN116318060A): Due to the limitation of DAC operating frequency, it is difficult to generate extremely narrow pulses <5ns, and the cost of high-frequency DAC is high; (4) Analog circuit scheme: Due to the influence of component parameter differences, the consistency and stability are poor, and the design is complicated.

[0003] Therefore, there is an urgent need for a narrow pulse generation scheme that is highly integrated, highly accurate, stable, and cost-controllable. Summary of the Invention

[0004] This invention aims to overcome the shortcomings of existing technologies, such as reliance on external circuits, insufficient accuracy, poor stability, and high cost. It provides a narrow pulse generation system and method for FPGA-integrated fiber lasers, which achieves high-precision narrow pulse output without the need for external delay chips through multi-phase clock synthesis and dynamic delay chain network closed-loop self-calibration technology.

[0005] In a first aspect, embodiments of this application provide a narrow pulse generation system for an FPGA-integrated fiber laser, comprising: The multi-phase clock generation module is configured to generate multiple high-frequency clock signals with fixed phase differences based on the system clock, which are used to achieve coarse delay adjustment in nanosecond-level steps. The dynamic delay chain module is a multi-level dynamic delay network built on dedicated logic units inside the FPGA, used to achieve fine delay adjustment in picosecond steps; The pulse width lookup module pre-stores the correspondence between pulse width and signal selection, and is used to select the instruction by outputting a signal based on the target pulse width. The signal selection module selects a target signal from the outputs of the multi-phase clock generation module and the dynamic delay chain module according to the signal selection instruction. The logic operation module performs logic operations on the target signal to generate an initial narrow pulse signal; The frequency control module is configured to generate a frequency control signal and perform logical operations with the initial narrow pulse signal to output a narrow pulse signal at the target frequency. The self-calibration module includes a temperature measurement self-calibration unit and a TDC measurement self-calibration unit, which are used to dynamically compensate for the delay deviation of narrow pulse signals caused by environmental changes and hardware drift. The LVDS driver module is configured to convert the compensated narrow pulse signal of the target frequency into a high-speed differential signal output.

[0006] Preferably, the phase difference between two adjacent high-frequency clock signals is the same. Preferably, the dynamic delay chain module uses the CARRY4 unit of the FPGA to construct a multi-level dynamic delay network.

[0007] Preferably, the single-level latency of the multi-level dynamic delay network is 60ps ± 5ps.

[0008] Preferably, the temperature measurement self-calibration unit is the on-chip XADC temperature sensor of the FPGA.

[0009] Preferably, the XADC temperature sensor acquires the temperature of the FPGA in real time and performs delay compensation on the dynamic delay chain module based on a pre-stored temperature-delay relationship table.

[0010] Preferably, the TDC measurement self-calibration unit is the OSERDES module of the FPGA.

[0011] Preferably, the TDC measurement self-calibration unit reads back the output narrow pulse signal and measures the actual pulse width, and dynamically adjusts the delay parameters of the dynamic delay chain module based on the deviation between the actual pulse width and the target pulse width.

[0012] Preferably, the frequency control module generates an enable signal, performs logical operations on the enable signal and the initial narrow pulse signal to adjust the target frequency and output the narrow pulse signal of the target frequency.

[0013] Preferably, the minimum output pulse width of the LVDS driver module is 0.5ns, and it supports multi-channel synchronous output.

[0014] Secondly, embodiments of this application provide a narrow pulse generation method for an FPGA-integrated fiber laser, comprising the following steps: S1: Generate multiple clock signals with a phase difference of 45° based on the system clock signal to form a coarse-adjustment delay network with nanosecond-level steps; S2: A multi-level dynamic delay network is constructed based on the dedicated logic unit inside the FPGA to form a fine-tuned delay network with picosecond-level steps; S3: Based on the target pulse width, call the pre-stored pulse width and signal selection relationship table, and select the corresponding target signal from the coarse-tuning delay network and the fine-tuning delay network; S4: Perform logical operations on the selected target signal to generate an initial narrow pulse signal; S5: Generates a frequency control signal and performs logical operations with the initial narrow pulse signal to output a narrow pulse signal at the target frequency; S6: Real-time monitoring of temperature changes and actual pulse width, performing temperature compensation and TDC calibration to dynamically compensate for delay deviations in narrow pulse signals caused by environmental changes and hardware drift; S7: Convert the compensated narrow pulse signal of the target frequency into a high-speed differential signal output.

[0015] Preferably, in step S5, when the target pulse width is ≤8ns, a single-cycle enable signal is generated and a logical AND operation is performed with the initial narrow pulse signal; when the target pulse width is >8ns, a base signal with multiple reference signal cycles is generated, and the single-cycle enable signal is shifted back by the number of cycles of the base signal and then a logical OR operation is performed with the initial narrow pulse signal.

[0016] Preferably, in step S6, the specific process of temperature compensation is as follows: the junction temperature of the FPGA is collected in real time, and when the temperature fluctuation exceeds the threshold, the delay parameters of the multi-level dynamic delay network are adjusted according to the pre-stored temperature-delay relationship table.

[0017] Preferably, in step S6, the specific process of TDC calibration is as follows: read back the output signal and measure the actual pulse width, calculate the deviation between the actual pulse width and the target pulse width, and dynamically correct the control word of the multi-level dynamic delay network through a PID algorithm.

[0018] Compared with existing technologies, this invention has the following advantages: a multi-phase clock generation module is used to achieve coarse delay adjustment in nanosecond-level steps; a dynamic delay chain module is used to achieve fine delay adjustment in picosecond-level steps; thus, based on FPGA integrated design, external delay chips and high-frequency peripheral circuits are not required, reducing hardware complexity and cost, and providing high anti-interference capability; simultaneously, through a two-stage structure of nanosecond-level coarse adjustment + picosecond-level fine adjustment, picosecond-level pulse width adjustment is achieved, breaking through the limitations of traditional FPGA integrated solutions; considering delay deviations caused by environmental changes and hardware drift, temperature compensation and TDC calibration are performed to ensure pulse width stability. Attached Figure Description

[0019] Exemplary embodiments of the present invention can be more fully understood by referring to the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the present invention and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0020] Figure 1 A schematic diagram of a narrow pulse generation system for an FPGA-integrated fiber laser, provided as an exemplary embodiment of this application; Figure 2 A multi-phase clock synthesis timing diagram provided for an exemplary embodiment of this application; Figure 3 A structural diagram of a dynamic delay chain module provided in an exemplary embodiment of this application; Figure 4 A timing diagram of a dynamic delay chain module provided for an exemplary embodiment of this application; Figure 5 A frequency control timing diagram provided for an exemplary embodiment of this application; Figure 6 A flowchart illustrating a narrow pulse generation method for an FPGA-integrated fiber laser, provided as an exemplary embodiment of this application. Detailed Implementation

[0021] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0022] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] Example 1 Reference Figure 1This embodiment discloses a narrow pulse generation system for an FPGA-integrated fiber laser, including: a multi-phase clock generation module, a dynamic delay chain module, a pulse width lookup module, a signal selection module, a logic operation module, a frequency control module, a self-calibration module (including a temperature measurement self-calibration unit and a TDC measurement self-calibration unit), and an LVDS driver module. The following will provide a detailed explanation of the working process of each module and the implementation effect of the scheme, combined with a practical solution.

[0025] In this embodiment, the narrow pulse signal generation of the fiber laser is based on a high-frequency clock signal. The high-frequency clock signal is a high-frequency periodic electrical signal used in electronic systems for synchronizing timing and quantizing time. It is the "time reference" of the system. Its core characteristics are high frequency (usually ≥10MHz, and up to GHz / THz in high-end scenarios) and short period (corresponding to the reciprocal of the frequency, such as a 1GHz clock period of only 1ns). Its main function is to provide a unified time scale for circuit modules and ensure that each component works together in a precise timing sequence.

[0026] Specifically, the multi-phase clock generation module can operate using the FPGA's system clock. To ensure that the phase difference between two adjacent high-frequency clock signals is the same, and that each high-frequency clock signal is effectively and strictly equidistantly distributed along the time axis, thereby achieving coarse delay adjustment in nanosecond-level steps, an MMCM (Mixed-Mode Clock Manager) and a PLL (Phase-Locked Loop) can be configured in the multi-phase clock generation module. MMCM and PLL are two core circuit modules commonly used in clock signal processing in electronic systems, both with the core functions of "stabilizing clock frequency, synchronizing phase, and realizing frequency conversion."

[0027] In some embodiments, the multi-phase clock generation module can generate eight 125MHz signals with a phase difference of 45 degrees and a period of 8ns, so that these eight signals achieve 360° phase coverage. The delay between each pair of adjacent signals is 1ns. If two of these signals are selected and processed by the logic operation module, narrow pulse signals with pulse widths of 1ns, 2ns, ..., 7ns can be obtained, thus achieving a reference pulse width with an equivalent pulse width resolution of 1ns. The clock synthesis timing diagram is shown below. Figure 2As shown in the figure, ch1 is a 125MHz signal with a phase of 0°, ch2 is a 125MHz signal with a phase of 45°, ch3 is a 125MHz signal with a phase of 90°, ..., ch8 is a 125MHz signal with a phase of 315°. Performing a logical AND operation between ch1 and ch6 yields a narrow pulse signal with a frequency of 125MHz and a pulse width of 1ns. Performing a logical AND operation between ch1 and ch7 yields a narrow pulse signal with a frequency of 125MHz and a pulse width of 2ns, ..., and so on. Therefore, the multi-phase clock generation module can realize a reference narrow pulse generation system with a resolution of 1ns. Thus, the multi-phase clock generation module in this embodiment implements a coarse delay adjustment process with nanosecond-level steps.

[0028] The dynamic delay chain module in this embodiment is implemented by building a 16-level dynamic delay network (also known as a dynamic delay chain) based on the dedicated CARRY4 unit within the FPGA. The module structure of this dynamic delay network is as follows: Figure 3 As shown. Specifically, CARRY4 is a dedicated carry logic unit in the FPGA. It achieves carry propagation through hardware-level optimization and dedicated routing resources, ensuring high-speed signal transmission. Therefore, the delay of each carry stage is relatively stable, approximately tens of ps, making it suitable as a high-precision delay reference unit. Combining layout constraints and dynamic calibration can fully leverage its performance. For example, by adding physical location constraints (LOC attributes) using FPGA tools, cascading ensures that CARRY4 units are arranged continuously and adjacently within the FPGA, avoiding additional delay deviations introduced by inconsistent routing; a multi-channel symmetrical layout is adopted to match trace lengths and suppress inter-channel delay differences; adding set_max_delay constraints limits the overall delay range of the carry chain, preventing automatic optimization by the tool from disrupting the chain structure. Through constraint-controlled CARRY4 unit delay networks, the delay of a single CARRY4 stage is approximately 60 ps, ​​with delay fluctuations controlled within ±5 ps (based on actual measurements on a 7-series FPGA). For example, the single-stage delay of a dynamic delay network can be 55 ps, 57 ps, 59 ps, 60 ps, ​​62 ps, 65 ps, etc. Therefore, the 16-level dynamic delay network constructed with CARRY4 units achieved 60ps step adjustment within 1ns, which means that fine delay adjustment with picosecond-level steps was achieved.

[0029] The timing of the dynamic delay chain is as follows: Figure 4As shown, each stage has a delay of 60 ps. Therefore, ch1-dly1 is delayed by 60 ps relative to ch1, ch1-dly2 by 120 ps, ​​ch1-dly3 by 180 ps, ​​..., ch1-dly16 by 960 ps. The delays for ch2-ch7 are similar. However, ch2 is delayed by 1 ns (1000 ps) relative to ch1, ch3 by 1 ns (1000 ps), ..., and so on. Therefore, the cascaded structure of the multi-phase clock generation module and the dynamic delay network constructs a delay system with a resolution of approximately 60 ps. Based on the same principle described in the multi-phase clock generation module above, according to the design pulse width requirements, the pulse width lookup module selects the corresponding two signals according to the pulse width lookup table and performs the corresponding logical operations to realize a narrow pulse generation system with a resolution of 60 ps.

[0030] The narrow pulse generation system constructed by the dual cascade structure of the multi-phase clock generation module and the dynamic delay network in this application can generate narrow pulses with a resolution as low as 60ps, but its frequency is fixed at 125MHz, and the narrow pulse width range is 60ps~8ns.

[0031] In practical applications of fiber lasers, variable frequency and pulse widths greater than 8ns are required. To address this, the frequency control module generates a corresponding control signal, which, when combined with a 125MHz narrow pulse signal in the logic operation module, yields a narrow pulse signal with controllable frequency and pulse width. The timing and principle are illustrated below. Figure 5 As shown, the frequency control module uses a 125MHz clock signal to generate a single-cycle or multi-cycle enable signal of the required frequency. By performing a logical AND operation between the single-cycle or multi-cycle enable signal and the 125MHz narrow pulse signal, the narrow pulse signal of the required frequency can be obtained.

[0032] For the frequency control module, when the designed pulse width is less than 8ns, the module uses a 125MHz clock signal with zero phase to generate a single-cycle (corresponding to 125MHz) enable signal `freq_select_en` for the required design frequency. The frequency of `freq_select_en` is the required design frequency, with a pulse width of 8ns and phase alignment. Performing a logical AND operation between `freq_select_en` and the 125MHz narrow pulse signal yields the required narrow pulse signal. When the designed pulse width is greater than 8ns, assuming the required pulse width is between 16ns and 24ns, a two-cycle base signal with the required design frequency is generated first. Simultaneously, the `freq_select_en` signal is shifted two cycles backward. The `freq_select_en` signal is first logically ANDed with the 125MHz narrow pulse signal, and then logically ORed with the base signal to obtain the required narrow pulse signal for the desired frequency and pulse width. The principle is similar for other pulse width requirements.

[0033] Specifically, the self-calibration module includes a temperature measurement self-calibration unit and a TDC measurement self-calibration unit; their working modes and principles differ, as follows: (1) Since the CARRY4 unit is a dedicated logic unit within the FPGA, its delay characteristics are affected by temperature changes. In this embodiment, the temperature measurement self-calibration unit uses the XADC (An analog-to-digital converter module integrated in Xilinx FPGA, mainly used to acquire external analog signals and convert them into digital signals for use within the FPGA) temperature sensor integrated on the FPGA chip to monitor the FPGA junction temperature in real time. By injecting standard pulses under various ambient temperatures, the actual delay value is measured to calibrate the actual delay value of the delay chain unit (CARRY4) at different temperatures, establish a temperature-delay relationship table, and pre-store this relationship table in the LUT unit of the FPGA. Then, the chip temperature is acquired in real time using the temperature sensor integrated on the FPGA chip to detect temperature changes. When the temperature fluctuation exceeds the set threshold, the temperature compensation logic is triggered. According to the temperature-delay relationship table, the delay change caused by the temperature change is compensated, thereby continuously correcting and calibrating the delay chain to ensure the high stability of the delay chain delay time. In practical applications, the delay units can also be distributed in the relative edge areas of the FPGA chip by position constraints, and the local temperature rise gradient can be reduced by utilizing the heat dissipation characteristics of the package, thereby ensuring the stability of the delay chain.

[0034] (2) The TDC measurement self-calibration unit captures the leading edge / trailing edge timestamp of the output narrow pulse through the OSERDES (Output Serializer-Deserializer, a dedicated primitive in FPGA for parallel-to-serial conversion, mainly used in high-speed data transmission scenarios, such as HDMI, LVDS and other signal processing) module of the FPGA, reads back the narrow pulse output signal, and then uses TDC (Time to Digital Converter) technology to measure the actual pulse width of the output narrow pulse signal, compares it with the design requirement pulse width, and dynamically adjusts the control word of the dynamic delay network according to the deviation to dynamically adjust the pulse width, thereby realizing the online self-calibration function of the narrow pulse width, minimizing the deviation between the output narrow pulse width and the design requirement pulse width, so as to form a closed-loop control.

[0035] In this embodiment, the narrow pulse electrical signal output uses the FPGA's LVDS (Low-Voltage Differential Signaling) interface, which is configured to drive the external circuitry. The LVDS interface supports high-speed signal transmission, thus enabling narrow pulse signal output. In actual testing, a minimum pulse width of 0.5ns can be achieved. Furthermore, the LVDS interface pin drive current is ≥16mA, supporting multi-channel synchronous triggering.

[0036] The narrow pulse generation system of this embodiment can theoretically generate narrow pulses as narrow as 60ps. However, due to the speed of FPGA devices and the hardware characteristics of the narrow pulse driving circuit, the actual measured narrow pulse electrical signal can reach about 0.5ns. This invention eliminates the need for external delay chips, uses an FPGA-integrated narrow pulse generation scheme, and employs multi-phase clock synthesis technology, dynamic delay network technology, and a closed-loop self-calibration mechanism to achieve a fiber laser narrow pulse generation system and method with a minimum pulse width of 0.5ns and an adjustable step size of up to 60ps.

[0037] Compared with the prior art, the present invention has the following beneficial effects: (1) No external circuit required: The entire system is designed based on FPGA, eliminating the need for external delay chips and high-frequency peripheral circuits, reducing hardware complexity and cost, and improving anti-interference capability; (2) High-precision adjustment: Through a two-level structure of nanosecond-level coarse adjustment (multi-phase clock synthesis technology) + picosecond-level fine adjustment (dynamic delay network technology), picosecond-level step pulse width adjustment is achieved, and the minimum output pulse width can reach 0.5ns, breaking through the precision limitation of traditional FPGA integration solutions; (3) High stability: The delay deviation caused by environmental changes and hardware drift is taken into account, and temperature dynamic compensation and TDC closed-loop calibration are performed to ensure the long-term stability of the pulse width. (4) Flexible and controllable: A frequency control module is introduced to support a wide range of arbitrary frequency adjustment, with a pulse width range of 60ps to any width, which can be adapted to the needs of different fiber lasers. (5) Ease of implementation: Designed based on general FPGA resources, no additional special devices are required, it is compatible with mainstream FPGA platforms, lowers the application threshold, and has good compatibility.

[0038] Example 2 Based on the same inventive concept, this application also provides a method for generating narrow pulses in an FPGA-integrated fiber laser, wherein the above embodiments execute the method described in this embodiment. The solution provided by this method is similar to the implementation scheme described in the above system. Therefore, the specific limitations in the following embodiment of the method for generating narrow pulses in an FPGA-integrated fiber laser can be found in the limitations of the narrow pulse generation system for an FPGA-integrated fiber laser described above, and will not be repeated here.

[0039] Reference Figure 6 This application discloses a method for generating narrow pulses using an FPGA-integrated fiber laser, comprising the following steps: S1: Based on the system clock signal generation module, multiple clock signals with a phase difference of 45° are generated to form a coarse adjustment delay network with nanosecond-level steps; S2: A multi-level dynamic delay network is constructed based on the dedicated logic unit inside the FPGA to form a fine-tuned delay network with picosecond-level steps; S3: Based on the target pulse width, call the pre-stored pulse width and signal selection relationship table, and select the corresponding target signal from the coarse-tuning delay network and the fine-tuning delay network; S4: Perform logical operations on the selected target signal to generate an initial narrow pulse signal; S5: Generates a frequency control signal and performs logical operations with the initial narrow pulse signal to output a narrow pulse signal at the target frequency; S6: Real-time monitoring of temperature changes and actual pulse width, performing temperature compensation and TDC calibration to dynamically compensate for delay deviations in narrow pulse signals caused by environmental changes and hardware drift; S7: Converts the compensated narrow pulse signal of the target frequency into a high-speed differential signal output.

[0040] Specifically, in step S5, when the target pulse width is ≤8ns, the frequency control module generates a single-cycle enable signal and performs a logical AND operation with the initial narrow pulse signal; when the target pulse width is >8ns, it generates a base signal with multiple reference signal cycles, shifts the single-cycle enable signal by the number of cycles of the base signal, and then performs a logical OR operation with the initial narrow pulse signal. Specifically, when the target pulse width is >8ns, multiple 8ns reference signal cycles of the base signal are first generated, the number of cycles depending on an integer multiple of the target pulse width relative to the 8ns reference signal, and then the single-cycle enable signal is shifted by the corresponding number of cycles and then performed a logical OR operation with the initial narrow pulse signal.

[0041] Specifically, in step S6, the temperature compensation process is as follows: the junction temperature of the FPGA is acquired in real time, and when the temperature fluctuation exceeds the threshold, the delay parameters of the dynamic delay chain are adjusted according to the pre-stored temperature-delay relationship table; the TDC calibration process is as follows: the output signal is read back and the actual pulse width is measured, the deviation between the actual pulse width and the target pulse width is calculated, and the control word of the dynamic delay chain is dynamically corrected through the PID algorithm.

[0042] Specifically, the control word that dynamically adjusts the dynamic delay network based on the deviation is used to dynamically adjust the pulse width, realize the online self-calibration function of narrow pulse width, thereby minimizing the deviation between the output narrow pulse width and the design requirement pulse width, and finally forming closed-loop control.

[0043] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0044] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0045] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interface; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0046] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0047] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application.

Claims

1. A narrow pulse generation system of an FPGA integrated fiber laser, characterized in that, The application relates to a high-speed narrow pulse signal generation method and device. The application comprises the following steps: A multi-phase clock generation module is configured to generate multiple high-frequency clock signals with fixed phase differences based on a system clock, which is used to realize coarse delay adjustment with nanosecond-level steps; A dynamic delay chain module is a multi-stage dynamic delay network based on a special logic unit in an FPGA, which is used to realize fine delay adjustment with picosecond-level steps; A pulse width lookup module pre-stores the corresponding relationship between pulse widths and signal selection, and is used to output signal selection instructions according to a target pulse width; A signal selection module selects a target signal from the outputs of the multi-phase clock generation module and the dynamic delay chain module according to the signal selection instructions; A logic operation module performs logic operation on the target signal to generate an initial narrow pulse signal; A frequency control module is configured to generate a frequency control signal and perform logic operation on the initial narrow pulse signal to output a narrow pulse signal with a target frequency; A self-calibration module comprises a temperature measurement self-calibration unit and a TDC measurement self-calibration unit, which are used to dynamically compensate for the delay deviation of the narrow pulse signal caused by environmental changes and hardware drift; 2. The system of claim 1, wherein, An LVDS driving module is configured to convert the compensated narrow pulse signal with the target frequency into a high-speed differential signal for output.

3. The system of claim 1, wherein, The phase difference of two adjacent high-frequency clock signals is the same.

4. The system of claim 3, wherein, The dynamic delay chain module adopts a CARRY4 unit of the FPGA to build a multi-stage dynamic delay network.

5. The system of claim 1, wherein, The single-stage delay of the multi-stage dynamic delay network is 60ps+ / -5ps.

6. The system of claim 5, wherein, The temperature measurement self-calibration unit is an on-chip XADC temperature sensor of the FPGA.

7. The system of claim 1, wherein, The XADC temperature sensor collects the temperature of the FPGA in real time, and compensates for the delay of the dynamic delay chain module based on a pre-stored temperature-delay relationship table.

8. The system of claim 7, wherein, The TDC measurement self-calibration unit is an OSERDES module of the FPGA.

9. The system of claim 1, wherein, The TDC measurement self-calibration unit reads back the output narrow pulse signal and measures the actual pulse width, and dynamically adjusts the delay parameters of the dynamic delay chain module based on the deviation between the actual pulse width and the target pulse width.

10. The system of claim 1, wherein, The frequency control module generates an enable signal, and performs logic operation on the enable signal and the initial narrow pulse signal to adjust the target frequency and output the narrow pulse signal with the target frequency.

11. A method for generating a narrow pulse of an FPGA integrated fiber laser, characterized in that, The minimum width of the output pulse of the LVDS driving module is 0.5ns, and the LVDS driving module supports multi-channel synchronous output. The application comprises the following steps: S1: multiple clock signals with a phase difference of 45 degrees are generated based on a system clock signal to form a coarse delay network with nanosecond-level steps; S2: a multi-stage dynamic delay network is built based on a special logic unit in an FPGA to form a fine delay network with picosecond-level steps; S3: a target signal is selected from the coarse delay network and the fine delay network according to a target pulse width by calling a pre-stored relationship table of pulse width and signal selection; S4: logic operation is performed on the selected target signal to generate an initial narrow pulse signal; S5: a frequency control signal is generated and logic operation is performed on the initial narrow pulse signal to output a narrow pulse signal with a target frequency. S6: Real-time monitoring of temperature change and actual pulse width, temperature compensation and TDC calibration are performed to dynamically compensate the delay deviation of narrow pulse signal caused by environmental change and hardware drift; S7: The compensated narrow pulse signal of the target frequency is converted into a high-speed differential signal output.

12. The method of claim 11, wherein, In step S5, when the target pulse width is ≤8ns, a single-cycle enable signal is generated and logically ANDed with the initial narrow pulse signal; when the target pulse width is >8ns, a plurality of base signals of the reference signal period are generated, the single-cycle enable signal is shifted by the number of periods of the base signal, and then logically ORed with the initial narrow pulse signal.

13. The method of claim 11, wherein, In step S6, the specific process of temperature compensation is: the junction temperature of the FPGA is collected in real time, and when the temperature fluctuation exceeds the threshold, the delay parameter of the multi-stage dynamic delay network is adjusted according to the pre-stored temperature-delay relationship table.

14. The method of claim 11, wherein, In step S6, the specific process of TDC calibration is: the output signal is read back and the actual pulse width is measured, the deviation of the actual pulse width from the target pulse width is calculated, and the control word of the multi-stage dynamic delay network is dynamically corrected through the PID algorithm.

Images