Multi-mode ideal diode controller

Abstract

The invention discloses a multi-mode ideal diode controller, and belongs to the field of analog circuits. The circuit comprises an internal control circuit and an external circuit. The internal control circuit monitors the voltage at the two ends of the anode and the cathode in real time and adjusts a driving signal to control the voltage from the GATE end of the NMOS tube in the external circuit to the anode so as to control the corresponding working mode of the diode, and therefore multi-mode ideal diode control of a full-conduction mode, a forward adjustment mode and a reverse protection mode is achieved. According to the invention, millivolt-level diode voltage drop can be realized, reverse current can be effectively prevented, multiple modes can be rapidly switched, and compared with a traditional diode, the diode is more controllable and reliable and is not influenced by temperature.

Description

Technical Field

[0001] This invention relates to the field of analog circuit technology, and in particular to a multi-mode ideal diode controller. Background Technology

[0002] With the development of low-power applications such as the Internet of Things and portable medical devices, there is an urgent need for a multi-mode ideal diode controller.

[0003] Multi-mode ideal diode controller and such Figure 1 Traditional diodes (such as silicon PN junction diodes and Schottky diodes) are similar in function, but they differ significantly in performance, operating principle, and application scenarios. For example, traditional diodes have a fixed forward voltage drop, typically ranging from 0.3V to 0.7V depending on the material. Traditional diodes are limited in function and cannot adapt to dynamic loads or complex power supply topologies. In contrast, an ideal diode controller can reduce the forward voltage drop of a diode to 20 millivolts using an external N-type MOSFET and can dynamically switch operating modes. This provides backup and protection for the power system and is applicable to scenarios such as automotive infotainment systems, industrial automation, enterprise power supplies, and redundant power supplies. Summary of the Invention

[0004] The purpose of this invention is to provide a multi-mode ideal diode controller to solve the problems in the prior art.

[0005] To solve the above-mentioned technical problems, the present invention provides a multi-mode ideal diode controller, comprising: an internal control circuit and an external circuit;

[0006] The internal control circuit includes a differential pressure detection module, a first comparator, an operational amplifier, a second comparator, a level conversion module, a latch, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first resistor;

[0007] The voltages at the anode and cathode ports are transmitted through the differential voltage detection module to the first comparator, operational amplifier, and second comparator. The outputs of the first and second comparators control the latch. The latch generates a signal that controls the operational amplifier through the level conversion module. The output of the operational amplifier is connected to the gate and drain of the first PMOS transistor, respectively. The source of the first PMOS transistor is connected to the second terminal of the first resistor, and the first terminal of the first resistor is connected to the VCAP charge pump voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the drain of the second NMOS transistor.

[0008] The output of the latch is connected to the gate of the first NMOS transistor, the drain of the first NMOS transistor and the drain of the second NMOS transistor are both connected to the GATE terminal in the external circuit, and the source of the first NMOS transistor and the source of the second NMOS transistor are both connected to the anode terminal; the gate of the second NMOS transistor is connected to the Vcap_uv signal, and the Vcap_uv signal is a charge pump undervoltage lock threshold;

[0009] The external circuit includes a third NMOS transistor, a diode, a charge pump capacitor, and a load; the gate of the third NMOS transistor is the GATE terminal, and is connected to the drain of the first PMOS transistor, the drain of the first NMOS transistor, the drain of the second NMOS transistor, and the output of the operational amplifier, respectively; the substrate and the source of the third NMOS transistor and the positive electrode of the diode are both connected to the anode terminal, and the anode terminal is connected to the VCAP charge pump voltage through the charge pump capacitor; the drain of the third NMOS transistor and the negative electrode of the diode are both connected to ground through the load; and the cathode terminal is connected between the drain of the third NMOS transistor and the load.

[0010] In an embodiment, in the internal control circuit, the anode terminal and the cathode terminal generate corresponding voltage division through the differential pressure detection module, when the VCAP charge pump voltage exceeds 6.6V, the Vcap_uv signal is low, the second NMOS transistor is closed, and the GATE terminal is released;

[0011] When the anode voltage-cathode voltage is <-11mV, at this time the first comparator and the operational amplifier are closed, the GATE pin is pulled low to the anode terminal, the third NMOS transistor is closed, and the diode is reverse cut-off, at this time it is in reverse protection mode;

[0012] When the cathode voltage-anode voltage is as low as 20mV, the first comparator is reversed, the operational amplifier is opened through the latch and the level conversion module, at this time the anode terminal voltage and the cathode terminal voltage in the range of -11mV to 50mV are linearly adjusted by the operational amplifier, at this time it is in forward adjustment mode;

[0013] When the anode voltage-cathode voltage is ≥50mV, the operational amplifier adjusts the GATE terminal to generate a strong pull-up current, and the GATE terminal is pulled high to the VCAP charge pump voltage, at this time it is in full conduction mode.

[0014] In an embodiment, in the external circuit, the voltage of the GATE terminal to the anode terminal is adjusted by adjusting the size of the load.

[0015] The application provides a multi-mode ideal diode controller, which comprises an internal control circuit and an external circuit. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic diagram of a traditional diode structure.

[0017] Figure 2 is a schematic diagram of a multi-mode ideal diode controller provided by the application.

[0018] Figure 3 is an output waveform diagram of the multi-mode ideal diode controller provided by the application. DETAILED DESCRIPTION

[0019] The application provides a multi-mode ideal diode controller, which comprises an internal control circuit and an external circuit.

[0020] The application provides a multi-mode ideal diode controller, which comprises an internal control circuit and an external circuit. Figure 2 The internal control circuit comprises a differential pressure detection module, a comparator COMP1, an operational amplifier GM_AMP, a comparator COMP2, a level conversion module, a latch, a PMOS tube MP0, an NMOS tube MN0, an NMOS tube MN1 and a resistor R1.

[0021] The internal control circuit comprises a differential pressure detection module, a comparator COMP1, an operational amplifier GM_AMP, a comparator COMP2, a level conversion module, a latch, a PMOS tube MP0, an NMOS tube MN0, an NMOS tube MN1 and a resistor R1.

[0022] The voltage of the anode port and the cathode port is transmitted to the comparator COMP1, the operational amplifier GM AMP and the comparator COMP2 through the differential pressure detection module. The outputs of the comparator COMP1 and the comparator COMP2 control the latch. The signal generated by the latch controls the operational amplifier GM AMP through the level conversion module. The output of the operational amplifier GM AMP is connected to the gate and the drain of the PMOS transistor MP0. The source of the PMOS transistor MP0 is connected to the second end of the resistor R1. The first end of the resistor R1 is connected to the VCAP charge pump voltage. The drain of the PMOS transistor MP0 is connected to the drain of the NMOS transistor MN0 and the drain of the NMOS transistor MN1.

[0023] The output of the latch is connected to the gate of the NMOS transistor MN0. The drain of the NMOS transistor MN0 and the drain of the NMOS transistor MN1 are connected to the GATE end in the external circuit. The source of the NMOS transistor MN0 and the source of the NMOS transistor MN1 are connected to the anode port. The gate of the NMOS transistor MN1 is connected to the Vcap_uv signal. The Vcap_uv signal is the under-voltage lock threshold of the charge pump.

[0024] The external circuit includes the NMOS transistor MN2, the diode D1, the charge pump capacitor C1 and the load. The gate of the NMOS transistor MN2 is the GATE end and is connected to the drain of the PMOS transistor MP0, the drain of the NMOS transistor MN0, the drain of the NMOS transistor MN1 and the output of the operational amplifier GM AMP. The substrate and the source of the NMOS transistor MN2 and the positive electrode of the diode D1 are connected to the anode port. The anode port is connected to the VCAP charge pump voltage through the charge pump capacitor C1. The drain of the NMOS transistor MN2 and the negative electrode of the diode D1 are connected to the ground through the load. The cathode port is connected between the drain of the NMOS transistor MN2 and the load.

[0025] Please continue to refer to Figure 2 The working mode of the ideal diode controller is determined by detecting the pressure difference between the ANODE port and the CATHODE port. The control signal generated by the internal control circuit 100 is used to control the gate GATE of the NMOS transistor MN2 in the external circuit 101, so as to control the diode D1. When VCAP>6.6V, the Vcap_uv signal is pulled down, the enable switch tube MN1 is turned off, the GATE end is released, and the GATE end can work freely and the working mode is determined by other places.

[0026] When VANODE-VCATHODE is greater than -11mV, the non-inverting terminal of the comparator COMP2 is equal to the inverting terminal; when the voltage of the ANODE port decreases further, the comparator COMP2 completes a flip, outputs a high level through the latch, and the GATE pin is pulled low to the ANODE, the GATE of the NMOS tube MN2 is connected to the ANODE, the NMOS tube MN2 is closed, the diode D1 is reversely cut off to block the current, and this mode is a reverse protection mode, that is, VANODE-VCATHODE<-11mV;

[0027] When the ANODE is higher than the CATHODE by more than 20mV, the comparator COMP1 flips, opens the operational amplifier GM_AMP through the latch and the level conversion module, at this time, VANODE and VCATHODE are linearly regulated by the GM_AMP in the range of -11mV to 50mV, that is, the forward voltage drop of the diode D1 from the anode to the cathode is 11mV to 50mV. By continuously monitoring the voltage between VANODE and VCATHODE and adjusting the voltage of the GATE to the anode of the external NMOS tube MN2, the voltage of the diode D1 can be regulated to 20mV, at this time, it is a forward regulation mode;

[0028] When VANODE-VCATHODE further increases and is greater than 50mV, under heavy load, the GM_AMP adjusts the GATE port to generate a strong pull-up current, the GATE is pulled high to the VCAP charge pump voltage, the voltage of the VCAP is higher than that of the ANODE, at this time, the channel of the external NMOS tube MN2 is opened, so that the on-resistance of the NMOS tube MN2 is minimized, thereby greatly reducing the power loss when the forward current is large, at this time, it is a full conduction mode, that is, VANODE-VCATHODE≥50mV.

[0029] In summary, in combination with the drawings and specific embodiments, the double-power supply channel time sequence controller circuit structure of the application is extremely simple, has the characteristics of strong practicability and simple structure.

[0030] In the application, the words such as "connection", "connection", "connection", "connection" represent electrical connection, and if no special description is given, it represents direct or indirect electrical connection. The upper end and the lower end of all the resistors described above are defined according to the direction of the current flowing through the resistor, and the current first passes through one end of the resistor as the upper end and the other end as the lower end.

[0031] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way, and any modification or modification of the application by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A multi-mode ideal diode controller characterized by, The application relates to a voltage regulator circuit. The internal control circuit comprises a differential pressure detection module, a first comparator, an operational amplifier, a second comparator, a level conversion module, a latch, a first PMOS tube, a first NMOS tube, a second NMOS tube and a first resistor. The voltage of the anode port and the cathode port is transmitted to the first comparator, the operational amplifier and the second comparator through the differential pressure detection module, the output of the first comparator and the second comparator controls the latch, the latch generates a signal which controls the operational amplifier through the level conversion module, the output of the operational amplifier is connected to the gate end and the drain end of the first PMOS tube, the source end of the first PMOS tube is connected to the second end of the first resistor, and the first end of the first resistor is connected to the VCAP charge pump voltage; the drain end of the first PMOS tube is connected to the drain end of the first NMOS tube and the drain end of the second NMOS tube. The output of the latch is connected to the gate end of the first NMOS tube, the drain end of the first NMOS tube and the drain end of the second NMOS tube are connected to the GATE end in the external circuit, and the source end of the first NMOS tube and the source end of the second NMOS tube are connected to the anode port; the gate end of the second NMOS tube is connected to the Vcap_uv signal, and the Vcap_uv signal is the under-voltage lockout threshold value of the charge pump. The external circuit comprises a third NMOS tube, a diode, a charge pump capacitor and a load; the gate end of the third NMOS tube is the GATE end and is connected to the drain end of the first PMOS tube, the drain end of the first NMOS tube, the drain end of the second NMOS tube and the output end of the operational amplifier; the substrate and the source end of the third NMOS tube and the positive pole of the diode are connected to the anode port, the anode port is connected to the VCAP charge pump voltage through the charge pump capacitor; the drain end of the third NMOS tube and the negative pole of the diode are connected to the ground through the load; and the cathode port is connected between the drain end of the third NMOS tube and the load. In the internal control circuit, the anode port and the cathode port generate corresponding partial pressure through the differential pressure detection module, the Vcap_uv signal is low when the VCAP charge pump voltage exceeds 6.6V, the second NMOS tube is closed, and the GATE end is released; 2. The multi-mode ideal diode controller of claim 1, wherein, When the anode voltage-cathode voltage is <-11mV, the first comparator and the operational amplifier are closed, the GATE pin is pulled low to the anode port, the third NMOS tube is closed, and the diode is reverse cut-off, so that the reverse protection mode is realized; When the cathode voltage-anode voltage is as low as 20mV, the first comparator is reversed, the operational amplifier is opened through the latch and the level conversion module, the anode port voltage and the cathode port voltage are linearly adjusted by the operational amplifier in the range of -11mV to 50mV, and the forward adjustment mode is realized; When the anode voltage-cathode voltage is >=50mV, the operational amplifier adjusts the GATE end to generate a strong pull-up current, the GATE end is pulled high to the VCAP charge pump voltage, and the full conduction mode is realized. In the external circuit, the voltage of the GATE end to the anode port is adjusted by adjusting the size of the load.

3. The multi-mode ideal diode controller of claim 2, wherein, ​

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