Burning voltage generating circuit, OTP type MCU and burning method

Abstract

The invention relates to the technical field of self-burning, and discloses a burning voltage generation circuit, an OTP type MCU and a burning method.The burning voltage generation circuit comprises a substrate voltage selection unit, a driving voltage generation unit, a driving unit, an MOS tube M1, an MOS tube M2 and an MOS tube M3; during use, the drive voltage generation unit generates a burning voltage or an LCD drive voltage based on a first enable signal EN1, and the drive unit controls the on-off of an MOS tube M1, an MOS tube M2 and an MOS tube M3 based on the first enable signal EN1 and a second enable signal EN2, so that the output of the burning voltage or the LCD drive voltage is realized; high voltage for self-burning and LCD driving voltage for LCD display can be generated only by using one circuit; in addition, the highest voltage is selected through the substrate voltage selection unit to be input to the substrates of the MOS transistor M1, the MOS transistor M2 and the MOS transistor M3, so that voltage backward flowing can be avoided, safe isolation of the MOS transistors can be achieved, the reliability of the circuit can be effectively guaranteed, and the burning success rate can be improved.

Description

Technical Field

[0001] This invention relates to the field of self-programming technology, specifically to a programming voltage generation circuit, an OTP-type MCU, and a programming method. Background Technology

[0002] OTP (One-Time Programmable Microcontroller) is an important branch of microcontrollers (MCUs). Its core feature is that the program memory can only be programmed once; once the program is written, it cannot be modified or erased. This characteristic makes it widely used in scenarios with specific requirements for cost, security, and stability.

[0003] For more flexible OTP-type MCUs, in addition to supporting programming mode, self-programming is also supported; the self-programming technology means that the MCU can complete the internal ROM programming by itself in a specific way, thereby effectively eliminating the need for external EEPROM.

[0004] For self-programming technology, a stable high voltage is required for programming, so a power supply circuit is needed to generate the high voltage. In addition, for OTP MCUs with LCD display function, an LCD driving voltage is also required. If the high voltage for programming and the LCD driving voltage are generated separately by two power supply circuits, the circuit structure will be complex and the cost will be high. Summary of the Invention In view of the shortcomings of the prior art, the present invention provides a programming voltage generation circuit, an OTP type MCU, and a programming method, which can generate a high voltage for self-programming and an LCD driving voltage for LCD display through a programming voltage generation circuit.

[0005] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a programming voltage generation circuit, comprising a substrate voltage selection unit, a driving voltage generation unit, a driving unit, a MOS transistor M1, a MOS transistor M2, and a MOS transistor M3; The source of MOSFET M1 is used to input a high-voltage programming signal; the source of MOSFET M2 is electrically connected to the output terminal of the drive voltage generation unit; and the source of MOSFET M3 is used to input a power supply voltage. The drains of MOSFET M1, MOSFET M2, and MOSFET M3 are electrically connected. The drive unit controls the on / off state of MOSFETs M1, M2, and M3 based on the input first enable signal EN1 and second enable signal EN2. The first enable signal EN1 is input to the driving voltage generating unit. The driving voltage generating unit generates a programming voltage when the first enable signal is high and generates an LCD driving voltage when the first enable signal is low. The substrate voltage selection unit is electrically connected to the source of MOS transistor M1, the source of MOS transistor M2, and the source of MOS transistor M3, respectively, and is used to select the highest voltage among the sources of MOS transistor M1, MOS transistor M2, and MOS transistor M3 for output. The voltage output terminal of the substrate voltage selection unit is electrically connected to the substrate of MOS transistor M1, the substrate of MOS transistor M2, and the substrate of MOS transistor M3, respectively.

[0006] In one embodiment of the first aspect, the substrate voltage selection unit includes MOSFET M21, MOSFET M22, MOSFET M23 and MOSFET M24; The source of MOS transistor M21 is electrically connected to the source of MOS transistor M1 and the gate of MOS transistor M22, respectively; the source of MOS transistor M22 is electrically connected to the source of MOS transistor M2 and the gate of MOS transistor M21, respectively. The drain of MOS transistor M21 is electrically connected to the source of MOS transistor M23, the drain of MOS transistor M22, and the gate of MOS transistor M24, respectively. The source of the MOS transistor M24 is electrically connected to the source of the MOS transistor M3 and the gate of the MOS transistor M23, respectively. The drain of MOS transistor M23 is electrically connected to the drain of MOS transistor M24, which is the voltage output terminal of the substrate voltage selection unit.

[0007] In one embodiment of the first aspect, the driving unit drives the MOS transistor M2 to conduct when both the first enable signal EN1 and the second enable signal EN2 are at a high level. The driving unit drives the MOS transistor M1 to conduct when the first enable signal EN1 is low and the second enable signal EN2 is high. The driving unit drives the MOS transistor M3 to conduct when the second enable signal EN2 is low.

[0008] In one embodiment of the first aspect, the driving voltage generating unit includes a control signal generating unit, a voltage divider branch, a first voltage divider switch, a second voltage divider switch, a comparator CMP1, a D flip-flop Q1, a four-phase non-overlapping clock generating unit, and a voltage multiplier unit. The control signal generation unit generates control signals CN1 and CN2 based on clock signal OSC1. The clock signal OSC1, control signal CN1, and control signal CN2 have the same frequency. The rising edge of control signal CN1 is later than the rising edge of clock signal OSC1, and the rising edge of control signal CN2 is later than the rising edge of control signal CN1. The falling edge of clock signal OSC1, the falling edge of control signal CN1, and the falling edge of control signal CN2 are the same. The input terminal of the voltage divider branch is electrically connected to the source of the MOSFET M2. The output terminal of the voltage divider branch is grounded through the first voltage divider switch. The second voltage divider switch is connected in parallel to the two intermediate nodes of the voltage divider branch. The control terminal of the first voltage divider switch is used to input the control signal CN1, and the control terminal of the second voltage divider switch is used to input the first enable signal EN1. The negative input terminal of the comparator CMP1 is electrically connected to the voltage divider node of the voltage divider branch. The positive input terminal of the comparator CMP1 is used for the reference voltage VBGR. The output terminal of the comparator CMP1 is electrically connected to the D input terminal of the D flip-flop Q1. The clock terminal of the D flip-flop Q1 is used to input the control signal CN2. The output terminal of the D flip-flop Q1 is electrically connected to the four-phase non-overlapping clock generation unit. When the output terminal of the D flip-flop Q1 is high, the four-phase non-overlapping clock generation unit generates four-phase non-overlapping clock signals clk1, clk2, clk3 and clk4. The voltage multiplier unit is electrically connected to the four-phase non-overlapping clock generation unit. It outputs voltages based on the clock signals clk1, clk2, clk3, and clk4 output by the four-phase non-overlapping clock generation unit. The voltage output terminal of the voltage multiplier unit is electrically connected to the input terminal of the MOS transistor M2.

[0009] In one embodiment of the first aspect, the control signal generation unit includes an OR gate OR1, an AND gate AND1, a first delay unit de1, an AND gate AND2, a second delay unit de2, and an AND gate AND3; The two inputs of OR1 are used to input the first enable signal EN1 and the LCD enable signal LCDEN, respectively. The output of OR1 is electrically connected to one input of AND1, and the other input of AND1 is used to input the clock signal OSC1. The output of AND1 is electrically connected to the input of the first delay unit de1 and one input of AND2, respectively. The output of the first delay unit de1 is electrically connected to the other input of AND2, respectively. The output of AND2 is electrically connected to the input of the second delay unit de2 and one input of AND3, respectively, for inputting the control signal CN1. The output of the second delay unit de2 is electrically connected to the other input of AND3, and the output of AND3 is used to output the control signal CN2.

[0010] In one embodiment of the first aspect, the first voltage divider switch is turned on when the control signal CN1 is high and turned off when the control signal CN1 is low; The second voltage divider switch is turned on when the first enable signal EN1 is high and turned off when the first enable signal EN1 is low.

[0011] In one embodiment of the first aspect, the voltage multiplier unit includes switches S10, S11, S12, S13, S14, S15, S16, and S17, and capacitors C10, C11, and C12. The input terminal of switch S10 is electrically connected to the input terminal of switch S14 and the output terminal of MOSFET M3, respectively. The output terminal of switch S10 is electrically connected to one end of capacitor C10 and the input terminal of switch S11, respectively. The output terminal of switch S14 is electrically connected to the other end of capacitor C10 and is grounded through switch S15. The output terminal of switch S11 is electrically connected to the input terminals of switch S12 and switch S16 respectively, and is grounded through capacitor C11. The output terminal of switch S12 is electrically connected to one end of capacitor C12 and the input terminal of switch S13 respectively. The output terminal of switch S16 is electrically connected to the other end of capacitor C12 and is grounded through switch S17. The output terminal of switch S13 is the voltage output terminal of the voltage multiplier unit. The control terminals of switch S10 and switch S15 are used to input clock signal clk1. The control terminals of switch S11 and switch S14 are used to input clock signal clk2; The control terminals of switch S13 and switch S16 are used to input clock signal clk3; The control terminals of switch S12 and switch S17 are used to input the clock signal clk4.

[0012] In one embodiment of the first aspect, the control terminals of the switches S10-S17 are turned on when the input clock signal is high and turned off when the input clock signal is low.

[0013] Secondly, the present invention also provides an OPT-type MCU, including the above-mentioned programming voltage generation circuit, and further including a first voltage detection unit, a second voltage detection unit, a ROM, and a logic control unit; the logic control unit is used to generate a first enable signal EN1 and a second enable signal EN2, the first voltage detection unit is used to detect the source voltage of MOSFET M2 and input a first detection signal to the logic control unit, the second voltage detection unit is used to detect the source voltage of MOSFET M3 and input a second detection signal to the logic control unit; the logic control unit is electrically connected to the ROM and is used to input a mode configuration signal, an enable signal WEN1, and perform data writing to the ROM.

[0014] Thirdly, the present invention also provides a programming method, implemented using the aforementioned OPT-type MCU, comprising the following steps: S1: Configure the magnitude of the clock signal OCS1, and make the first enable signal EN1 high through the logic control unit, so that the drive voltage generation unit starts to generate voltage; S2: The logic control unit detects whether the source voltage of the MOSFET M3 has reached the minimum power supply voltage through the second voltage detection unit. If it has not reached the minimum power supply voltage, step S2 ends and the programming process is exited; otherwise, step S3 is executed. S3: The logic control unit detects whether the voltage generated by the drive voltage generation unit has reached the minimum programming voltage through the first voltage detection unit. If it has not reached the minimum programming voltage, step S3 ends and programming is exited; otherwise, step S4 is executed. S4: Load the programming address and programming data into the ROM; S5: The logic control unit sets the configuration mode configuration signal to a high level to enable the ROM to enter write mode, and at the same time sets the second enable signal EN2 to a high level, thereby turning on the MOS transistor M2 and driving the programming voltage generated by the voltage generation unit to be input into the ROM. S6: The logic control unit enables the ROM to enter the enabled state by configuring the enable signal WEN1 to be high, and then performs programming, programming data into the ROM according to the loaded programming address; S7: After the data is burned, the logic control unit configuration mode configuration signal is low, the configuration enable signal WEN1 is low, and the second enable signal EN2 is low.

[0015] The beneficial effects of this invention compared with the prior art are as follows: This invention generates a programming voltage or an LCD driving voltage by having the driving voltage generation unit generate the programming voltage or LCD driving voltage based on the first enable signal EN1, and controls the on / off state of MOSFETs M1, M2 and M3 by having the driving unit control the on / off state of MOSFETs M1, M2 and M3 based on the first enable signal EN1 and the second enable signal EN2, thereby realizing the output of programming voltage or LCD driving voltage. Thus, only one circuit is needed to generate the high voltage for self-programming and the LCD driving voltage for LCD display. In addition, by using a substrate voltage selection unit to select the substrate with the highest voltage input to MOSFETs M1, M2, and M3, voltage backflow can be avoided, safe isolation of MOSFETs can be achieved, and the reliability of the circuit can be effectively guaranteed and the programming success rate can be improved. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of the programming voltage generation circuit in Example 1; Figure 2 This is a circuit diagram of the substrate voltage selection unit in Embodiment 1; Figure 3 This is a circuit diagram of the driving unit in Embodiment 1; Figure 4 This is a circuit diagram of the driving voltage generation unit in Embodiment 1; Figure 5 This is a circuit diagram of the control signal generation unit in Embodiment 1; Figure 6 The waveforms of clock signal OSC1, control signal CN1, and control signal CN2 in Example 1 are shown. Figure 7 The waveforms of clock signals clk1, clk2, clk3, and clk4 generated by the four-phase non-overlapping clock generation unit in Embodiment 1 based on clock signal OSC2 are shown. Figure 8 The circuit diagram is shown for the voltage multiplier unit in Example 1. Figure 9 This is a schematic diagram of the MCU structure in Example 2. Detailed Implementation

[0017] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0018] Example 1 like Figure 1As shown, this embodiment provides a programming voltage generation circuit, including a substrate voltage selection unit 2, a driving voltage generation unit 3, a driving unit 1, a MOS transistor M1, a MOS transistor M2, and a MOS transistor M3; The source of MOSFET M1 is used to input the programming high voltage signal. The source of MOSFET M2 is electrically connected to the output terminal of the drive voltage generation unit 3 and grounded through capacitor C0. Capacitor C0 is used to store charge and regulate voltage. The source of MOSFET M3 is used to input the power supply voltage. The drains of MOSFET M1, MOSFET M2 and MOSFET M3 are electrically connected. The drive unit 1 controls the on / off state of MOSFETs M1, M2, and M3 based on the input first enable signal EN1 and second enable signal EN2. The first enable signal EN1 is input to the drive voltage generation unit 3. The drive voltage generation unit 3 generates a programming voltage when the first enable signal is high and generates an LCD drive voltage when the first enable signal is low. The substrate voltage selection unit 2 is electrically connected to the source of MOSFET M1, the source of MOSFET M2 and the source of MOSFET M3 respectively, and is used to select the highest voltage among the sources of MOSFET M1, MOSFET M2 and MOSFET M3 for output. The voltage output terminal of the substrate voltage selection unit 2 is electrically connected to the substrate of MOSFET M1, the substrate of MOSFET M2 and the substrate of MOSFET M3 respectively.

[0019] In practical use, the present invention generates a programming voltage or an LCD driving voltage by having the driving voltage generation unit 3 generate the programming voltage or LCD driving voltage based on the first enable signal EN1, and controls the on / off state of MOSFETs M1, M2 and M3 by having the driving unit 1 control the on / off state of MOSFETs M1, M2 and M3 based on the first enable signal EN1 and the second enable signal EN2, thereby realizing the output of programming voltage or LCD driving voltage. Thus, only one circuit is needed to generate the high voltage for self-programming and the LCD driving voltage for LCD display, simplifying the circuit structure and reducing the circuit cost. In addition, by using substrate voltage selection unit 2, the highest voltage can be selected to be input to the substrates of MOSFETs M1, M2 and M3, thereby avoiding voltage backflow, achieving safe isolation of MOSFETs, and thus effectively ensuring circuit reliability and improving programming success rate.

[0020] exist Figure 1 In practice, the source of MOSFET M1 can be connected to the EXVPP pin to input a high-voltage programming signal. The source of MOSFET M2 can be electrically connected to the OP1 pin, and the source of MOSFET M3 can be electrically connected to the VDD pin to input the power supply voltage.

[0021] exist Figure 1 In the diagram, MOS transistors M1, M2, and M3 are all PMOS transistors.

[0022] In this embodiment, the circuit of the substrate voltage selection unit is as follows: Figure 2 As shown, it includes MOSFETs M21, M22, M23, and M24; wherein MOSFETs M21, M22, M23, and M24 are all PMOS transistors; The connection relationships of MOSFETs M21, M22, M23, and M24 are as follows: The source of MOSFET M21 is electrically connected to the source of MOSFET M1 and the gate of MOSFET M22, respectively. The source of MOSFET M22 is electrically connected to the source of MOSFET M2 and the gate of MOSFET M21, respectively. The drain of MOSFET M21 is electrically connected to the source of MOSFET M23, the drain of MOSFET M22, and the gate of MOSFET M24, respectively. The source of MOSFET M24 is electrically connected to the source of MOSFET M3 and the gate of MOSFET M23, respectively. The drain of MOSFET M23 is electrically connected to the drain of MOSFET M24, which is the voltage output terminal of substrate voltage selection unit 2.

[0023] for Figure 2 In the circuit shown, the cross-coupled structure composed of MOSFETs M21 and M22 can compare the source voltages of MOSFETs M21 and M22, and the comparison output signal VA is the larger of the two. Then, the cross-coupled structure composed of MOSFETs M23 and M24 compares the comparison output signal VA with the source voltage of MOSFET M24, and outputs the larger of the two voltage values, and finally outputs voltage VBULK. Voltage VBULK is input to the substrates of MOSFETs M1, M2 and M3.

[0024] Specifically, in this embodiment, the driving unit 1 controls the on / off process of MOS transistors M1, M2, and M3 based on the first enable signal EN1 and the second enable signal EN2 as follows: When both the first enable signal EN1 and the second enable signal EN2 are high, the drive unit 1 drives the MOS transistor M2 to turn on; the programming voltage generated by the drive voltage generation unit 2 is input to the ROM through the MOS transistor M2, and the circuit mode at this time is the self-programming mode. When the first enable signal EN1 is low and the second enable signal EN2 is high, the driving unit drives the MOS transistor M1 to conduct; at this time, the programming high voltage signal is input to the ROM through the MOS transistor M1, and the corresponding mode of the circuit is the burning mode. When the second enable signal EN2 is low, the driving unit drives the MOSFET M3 to turn on; at this time, the circuit corresponds to the other operating modes.

[0025] Another implementation circuit of the driving unit 1 is as follows: Figure 3 As shown, it includes an inverter INV10, a NAND gate NAND10, a NAND gate NAND11, and a buffer BUF10.

[0026] In this embodiment, the circuit of the driving voltage generating unit 3 is as follows: Figure 4 As shown, it includes a control signal generation unit 30, a voltage divider branch 31, a first voltage divider switch K10, a second voltage divider switch K11, a comparator CMP1, a D flip-flop Q1, a four-phase non-overlapping clock generation unit 32, and a voltage multiplier unit 33. The control signal generation unit 30 generates control signals CN1 and CN2 based on the clock signal OSC1. The waveforms of the control signals CN1 and CN2 generated by the clock signal OSC1 are as follows: Figure 6 As shown, from Figure 6 From this, we can obtain: The clock signal OSC1, control signal CN1, and control signal CN2 have the same frequency. The rising edge of control signal CN1 is later than the rising edge of clock signal OSC1, and the rising edge of control signal CN2 is later than the rising edge of control signal CN1. The falling edges of clock signal OSC1, control signal CN1, and control signal CN2 are the same. exist Figure 4 In the voltage divider branch 31, the input terminal is electrically connected to the source of the MOSFET M2, the output terminal of the voltage divider branch 31 is grounded through the first voltage divider switch K101, and the second voltage divider switch K11 is connected in parallel to the two intermediate nodes of the voltage divider branch 31. The control terminal of the first voltage divider switch K10 is used to input the control signal CN1, and the control terminal of the second voltage divider switch K11 is used to input the first enable signal EN1. The negative input of comparator CMP1 is electrically connected to the voltage divider node of voltage divider branch 31. The positive input of comparator CMP1 is used for the reference voltage VBGR. The output of comparator CMP1 is electrically connected to the D input of D flip-flop Q1. The clock terminal of D flip-flop Q1 is used to input the control signal CN2. The output of D flip-flop Q1 is electrically connected to the four-phase non-overlapping clock generation unit 32. When the output of D flip-flop Q1 is high, the four-phase non-overlapping clock generation unit 32 generates four-phase non-overlapping clock signals clk1, clk2, clk3, and clk4 based on the clock signal OSC2. The timing waveforms of clock signals clk1, clk2, clk3, and clk4 are as follows: Figure 7As shown, the other four-phase non-overlapping clock generation unit 32 is an existing circuit, and its structure will not be described further. The voltage multiplier unit 33 is electrically connected to the four-phase non-overlapping clock generation unit 32. The voltage output is based on the clock signals clk1, clk2, clk3 and clk4 output by the four-phase non-overlapping clock generation unit 32. The voltage output terminal of the voltage multiplier unit 33 is electrically connected to the source of the MOSFET M2.

[0027] for Figure 4 In the circuit shown, comparator CMP1 operates when control signal CN1 is high, and stops operating when comparator CN1 is low. In addition, the first voltage divider switch K10 is turned on when the control signal CN1 is high and turned off when the control signal CN1 is low; The second voltage divider switch K11 is turned on when the first enable signal EN1 is high and turned off when the first enable signal EN1 is low.

[0028] For voltage divider branch 31, when only the first voltage divider switch K10 is turned on, the voltage division ratio of the voltage divider node of voltage divider branch 31 is the first ratio, and the voltage output by the drive voltage generating unit 3 is the LCD drive voltage; when both the first voltage divider switch K10 and the second voltage divider switch K11 are turned on, the voltage division ratio of the voltage divider node of voltage divider branch 31 is the second ratio, and the voltage output by the drive voltage generating unit 3 is the programming voltage; in addition, the first ratio is greater than the second ratio.

[0029] The timing settings for control signals CN1 and CN2 in this embodiment serve the following purposes: First, the control signal CN1 can make the voltage divider branch 31 and comparator CMP1 work intermittently to reduce power consumption. The rising edge of the control signal CN2 is later than the rising edge of the control signal CN1, which can reserve enough time for the output of comparator CMP1 to stabilize. After the output of comparator CMP1 stabilizes, the current state value is latched by the D flip-flop Q1 when the rising edge of the control signal CN2 occurs, thereby controlling the working state of the four-phase non-overlapping clock generation unit 32. When both control signals CN1 and CN2 go low, the voltage divider branch 31 and comparator CMP1 stop working, but this does not affect the working state of the four-phase non-overlapping clock generation unit 32 until the next working cycle arrives. This timing design can save power consumption and improve the lifespan of the battery that powers the system without affecting the operation of the voltage multiplier unit 33 or the quality of the voltage multiplier output signal.

[0030] In this embodiment, the circuit of the control signal generation unit 30 is as follows: Figure 5As shown, it includes OR gate OR1, AND gate AND1, first delay unit de1, AND gate AND2, second delay unit de2, and AND gate AND3; The two inputs of OR gate OR1 are used to input the first enable signal EN1 and the LCD enable signal LCDEN, respectively. The output of OR gate OR1 is electrically connected to one input of AND gate AND1. The other input of AND gate AND1 is used to input the clock signal OSC1. The output of AND gate AND1 is electrically connected to the input of the first delay unit de1 and one input of AND gate AND2, respectively. The output of the first delay unit de1 is electrically connected to the other input of AND gate AND2, respectively. The output of AND gate AND2 is electrically connected to the input of the second delay unit de2 and one input of AND gate AND3, respectively, for inputting the control signal CN1. The output of the second delay unit de2 is electrically connected to the other input of AND gate AND3, and the output of AND gate AND3 is used to output the control signal CN2.

[0031] In this embodiment, the circuit of the voltage multiplier unit 33 is as follows: Figure 8 As shown, it includes switches S10, S11, S12, S13, S14, S15, S16, and S17, as well as capacitors C10, C11, and C12. The input terminal of switch S10 is electrically connected to the input terminal of switch S14 and the output terminal of MOSFET M3, respectively. The output terminal of switch S10 is electrically connected to one end of capacitor C10 and the input terminal of switch S11, respectively. The output terminal of switch S14 is electrically connected to the other end of capacitor C10 and is grounded through switch S15. The output terminal of switch S11 is electrically connected to the input terminals of switch S12 and switch S16 respectively, and is grounded through capacitor C11. The output terminal of switch S12 is electrically connected to one end of capacitor C12 and the input terminal of switch S13 respectively. The output terminal of switch S16 is electrically connected to the other end of capacitor C12 and is grounded through switch S17. The output terminal of switch S13 is the voltage output terminal of the voltage multiplier unit. The control terminals of switch S10 and switch S15 are used to input the clock signal clk1. The control terminals of switch S11 and switch S14 are used to input the clock signal clk2. The control terminals of switch S13 and switch S16 are used to input the clock signal clk3. The control terminals of switch S12 and switch S17 are used to input the clock signal clk4.

[0032] Specifically, the control terminals of switches S10-S17 are turned on when the input clock signal is high and turned off when the input clock signal is low. Furthermore, in this embodiment, controlling the voltage multiplier unit 33 with a high-speed four-phase non-overlapping clock signal effectively reduces charge leakage, resulting in extremely high efficiency for the drive voltage generation unit 3. This allows it to output a voltage multiplier of up to three times VDD while maintaining driving capability.

[0033] Example 2 like Figure 9 As shown, this embodiment also provides an OPT-type MCU, including a programming voltage generation circuit as described in Embodiment 1, and further including a first voltage detection unit 4, a second voltage detection unit 5, a ROM, and a logic control unit; the logic control unit is used to generate a first enable signal EN1 and a second enable signal EN2, the first voltage detection unit 4 is used to detect the source voltage of MOSFET M2 and input a first detection signal VD1 to the logic control unit, the second voltage detection unit 5 is used to detect the source voltage of MOSFET M3 and input a second detection signal VD2 to the logic control unit; the logic control unit is electrically connected to the ROM and is used to input a mode configuration signal MODE, an enable signal WEN1 to the ROM, and to write data.

[0034] The mode configuration signal MODE controls whether the ROM is in write mode or standby mode. Specifically, when the mode configuration signal MODE is high, the ROM is in write mode, and when the mode configuration signal MODE is low, the ROM is in standby mode. The enable signal WEN1 controls the ROM programming enable. The logic control unit writes data through the data port DATA and the address port ADDR.

[0035] In practical use, the logic control unit can start self-programming by generating the first enable signal EN1 and the second enable signal EN2 in sequence. At the same time, it can control whether to continue programming based on the detection results of the first voltage detection unit 4 and the second voltage detection unit 5. The specific programming process is described in Example 3.

[0036] Example 3 This embodiment provides a programming method, implemented using the OPT-type MCU in Embodiment 2, including the following steps: S1: Configure the magnitude of the clock signal OCS1, and make the first enable signal EN1 high through the logic control unit, so that the drive voltage generation unit 3 starts to generate voltage; S2: The logic control unit detects whether the source voltage of the MOSFET M3 has reached the minimum power supply voltage through the second voltage detection unit 5. If it has not reached the minimum power supply voltage, step S2 ends and the programming process is exited; otherwise, step S3 is executed. S3: The logic control unit detects whether the voltage generated by the drive voltage generation unit 3 has reached the minimum programming voltage through the first voltage detection unit 4. If it has not reached the minimum programming voltage, step S3 ends and programming is exited; otherwise, step S4 is executed. S4: Load the programming address and programming data into the ROM; S5: The logic control unit sets the configuration mode signal MODE to a high level to enable the ROM to enter write mode, and at the same time sets the second enable signal EN2 to a high level, thereby turning on the MOS transistor M2 and driving the programming voltage generated by the voltage generation unit 3 to be input into the ROM. S6: The logic control unit enables the ROM to enter the enabled state by configuring the enable signal WEN1 to be high, and then performs programming, programming data into the ROM according to the loaded programming address; S7: After the data is burned, the logic control unit configuration mode signal MODE is low, the configuration enable signal WEN1 is low, and the second enable signal EN2 is low.

[0037] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A write voltage generating circuit characterized by comprising: The substrate voltage selection unit, the driving voltage generation unit, the driving unit, MOS tube M1, MOS tube M2 and MOS tube M3 are included. The source of the MOS tube M1 is used for inputting a programming high voltage signal, the source of the MOS tube M2 is electrically connected with the output end of the driving voltage generation unit and grounded through the capacitor C0, and the source of the MOS tube M3 is used for inputting a power supply voltage; the drain of the MOS tube M1, the drain of the MOS tube M2 and the drain of the MOS tube M3 are electrically connected. The driving unit controls the on-off of the MOS tube M1, the MOS tube M2 and the MOS tube M3 based on the input first enable signal EN1 and second enable signal EN2. The first enable signal EN1 is input to the driving voltage generation unit, the driving voltage generation unit generates a burning voltage when the first enable signal is high, and generates an LCD driving voltage when the first enable signal is low. The substrate voltage selection unit is electrically connected with the source of the MOS tube M1, the source of the MOS tube M2 and the source of the MOS tube M3 respectively, and is used for selecting the highest voltage among the source of the MOS tube M1, the source of the MOS tube M2 and the source of the MOS tube M3 for output, and the voltage output end of the substrate voltage selection unit is electrically connected with the substrate of the MOS tube M1, the substrate of the MOS tube M2 and the substrate of the MOS tube M3 respectively.

2. A write voltage generating circuit according to claim 1, characterized in that The substrate voltage selection unit includes MOS tube M21, MOS tube M22, MOS tube M23 and MOS tube M24. The source of the MOS tube M21 is electrically connected with the source of the MOS tube M1 and the gate of the MOS tube M22 respectively, and the source of the MOS tube M22 is electrically connected with the source of the MOS tube M2 and the gate of the MOS tube M21 respectively. The drain of the MOS tube M21 is electrically connected with the source of the MOS tube M23, the drain of the MOS tube M22 and the gate of the MOS tube M24 respectively. The source of the MOS tube M24 is electrically connected with the source of the MOS tube M3 and the gate of the MOS tube M23 respectively. The drain of the MOS tube M23 is electrically connected with the drain of the MOS tube M24, and is the voltage output end of the substrate voltage selection unit.

3. A write voltage generating circuit according to claim 1 or 2, characterized in that The driving unit drives the MOS tube M2 to be turned on when the first enable signal EN1 and the second enable signal EN2 are both high. The driving unit drives the MOS tube M1 to be turned on when the first enable signal EN1 is low and the second enable signal EN2 is high. The driving unit drives the MOS tube M3 to be turned on when the second enable signal EN2 is low.

4. A write voltage generating circuit according to claim 3, wherein The driving voltage generation unit includes a control signal generation unit, a voltage division branch, a first voltage division switch, a second voltage division switch, a comparator CMP1, a D flip-flop Q1, a four-phase non-overlapping clock generation unit and a voltage doubling unit. The control signal generating unit generates control signals CN1 and CN2 based on a clock signal OSC1, the frequencies of the clock signal OSC1, the control signal CN1 and the control signal CN2 are the same, the rising edge of the control signal CN1 is later than the rising edge of the clock signal OSC1, the rising edge of the control signal CN2 is later than the rising edge of the control signal CN1, and the falling edge of the clock signal OSC1, the falling edge of the control signal CN1 and the falling edge of the control signal CN2 are the same; The input end of the voltage division branch is electrically connected to the source electrode of the MOS transistor M2, the output end of the voltage division branch is grounded through the first voltage division switch, the second voltage division switch is connected in parallel to the two intermediate nodes of the voltage division branch, the control end of the first voltage division switch is used for inputting the control signal CN1, and the control end of the second voltage division switch is used for inputting the first enable signal EN1; The negative input end of the comparator CMP1 is electrically connected to the voltage division node of the voltage division branch, the positive input end of the comparator CMP1 is used for the reference voltage VBGR, the output end of the comparator CMP1 is electrically connected to the D input end of the D flip-flop Q1, the clock end of the D flip-flop Q1 is used for inputting the control signal CN2, and the output end of the D flip-flop Q1 is electrically connected to the four-phase non-overlapping clock generating unit, which generates four-phase non-overlapping clock signals clk1, clk2, clk3 and clk4 when the output end of the D flip-flop Q1 is at a high level. The voltage doubling unit is electrically connected to the four-phase non-overlapping clock generating unit, outputs a voltage based on the clock signals clk1, clk2, clk3 and clk4 output by the four-phase non-overlapping clock generating unit, and the voltage output end of the voltage doubling unit is electrically connected to the input end of the MOS transistor M2.

5. A write voltage generating circuit according to claim 4, wherein The control signal generating unit includes an OR gate OR1, an AND gate AND1, a first delay unit de1, an AND gate AND2, a second delay unit de2 and an AND gate AND3; The two input ends of the OR gate OR1 are respectively used for inputting the first enable signal EN1 and the LCD enable signal LCDEN, the output end of the OR gate OR1 is electrically connected to one input end of the AND gate AND1, the other input end of the AND gate AND1 is used for inputting the clock signal OSC1, the output end of the AND gate AND1 is electrically connected to the input end of the first delay unit de1 and one input end of the AND gate AND2, the output end of the first delay unit de1 is electrically connected to the other input end of the AND gate AND2, the output end of the AND gate AND2 is electrically connected to the input end of the second delay unit de2 and one input end of the AND gate AND3, which is used for inputting the control signal CN1, the output end of the second delay unit de2 is electrically connected to the other input end of the AND gate AND3, and the output end of the AND gate AND3 is used for outputting the control signal CN2.

6. A write voltage generating circuit according to claim 5, wherein The first voltage division switch is turned on when the control signal CN1 is at a high level and is turned off when the control signal CN1 is at a low level. The second voltage dividing switch is turned on when the first enable signal EN1 is high, and is turned off when the first enable signal EN1 is low.

7. A write voltage generating circuit according to claim 6, wherein The voltage doubling unit comprises switches S10, S11, S12, S13, S14, S15, S16, S17, capacitors C10, C11 and C12. The input end of the switch S10 is electrically connected with the input end of the switch S14 and the source electrode of the MOS transistor M3, the output end of the switch S10 is electrically connected with one end of the capacitor C10 and the input end of the switch S11, the output end of the switch S14 is electrically connected with the other end of the capacitor C10 and grounded through the switch S15. The output end of the switch S11 is electrically connected with the input end of the switch S12 and the input end of the switch S16 and grounded through the capacitor C11, the output end of the switch S12 is electrically connected with one end of the capacitor C12 and the input end of the switch S13, the output end of the switch S16 is electrically connected with the other end of the capacitor C12 and grounded through the switch S17, and the output end of the switch S13 is the voltage output end of the voltage doubling unit. The control end of the switch S10 and the control end of the switch S15 are used for inputting a clock signal clk1. The control end of the switch S11 and the control end of the switch S14 are used for inputting a clock signal clk2. The control end of the switch S13 and the control end of the switch S16 are used for inputting a clock signal clk3. The control end of the switch S12 and the control end of the switch S17 are used for inputting a clock signal clk4.

8. A write voltage generating circuit according to claim 7, wherein The control end of the switch S10-S17 is turned on when the input clock signal is high, and is turned off when the input clock signal is low.

9. An OPT type MCU, characterized by The burning voltage generating circuit comprises the first voltage detecting unit, the second voltage detecting unit, the ROM and the logic control unit; the logic control unit is used for generating the first enable signal EN1 and the second enable signal EN2, the first voltage detecting unit is used for detecting the source voltage of the MOS transistor M2 and inputting a first detection signal to the logic control unit, and the second voltage detecting unit is used for detecting the source voltage of the MOS transistor M3 and inputting a second detection signal to the logic control unit; the logic control unit is electrically connected with the ROM and is used for inputting a mode configuration signal, an enable signal WEN1 and data writing to the ROM.

10. A method of burning, characterized by, The OPT type MCU is realized by the method of claim 9, comprising the following steps: S1: configuring the size of the clock signal OCS1, making the first enable signal EN1 high through the logic control unit, so that the driving voltage generating unit starts to generate voltage; S2: the logic control unit detects whether the voltage of the source electrode of the MOS transistor M3 reaches the minimum power supply voltage through the second voltage detecting unit, if not, the step S2 is ended and the burning is exited; otherwise, the step S3 is executed. S3: The logic control unit detects whether the voltage generated by the driving voltage generating unit reaches the minimum programming voltage through the first voltage detecting unit. If not, the step S3 is ended and the programming is exited. Otherwise, the step S4 is executed; S4: The programming address and data are loaded into the ROM; S5: The logic control unit makes the ROM enter the writing mode by making the configuration mode configuration signal high, and makes the MOS transistor M2 conduct by making the second enable signal EN2 high, so that the programming voltage generated by the driving voltage generating unit is input to the ROM; S6: The logic control unit makes the ROM enter the enable state by making the configuration enable signal WEN1 high, and then performs the programming, and burns the programming data into the ROM according to the loaded programming address; S7: After the programming data is burned, the logic control unit makes the configuration mode configuration signal low, the configuration enable signal WEN1 low, and the second enable signal EN2 low.

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