Current estimation or sensing method

Abstract

The invention relates to a current estimation or sensing method. The high-side switch has a current flow path between a high-side reference and the switching node, and the low-side switch has a current flow path between the switching node and a low-side reference. The high-side switch is turned on during a first time interval, and the low-side switch is turned on during a second time interval. An inductive element is coupled between the switch node and the output node. The switching voltage is sensed and filtered to provide a filtered voltage indicative of the output voltage at the output node. Based on a difference between the filtered voltage and the sensed switching voltage, an output current signal indicative of an intensity of a current flowing through the inductive load during an estimated time equal to or greater than the first time interval is generated.

Description

[0001] Priority Statement

[0002] This application claims priority to Italian Patent Application No. 102024000012970, filed on June 6, 2024, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This manual relates to current estimation and sensing methods.

[0004] For example, one or more embodiments can be applied to sensing current flowing through an inductive load in an electronic device, such as, for example, a switched (or switching) converter.

[0005] One or more embodiments can be used in applications such as those in the automotive field, where maintaining operational accuracy throughout the lifespan of an electronic device is a desirable feature. Background Technology

[0006] The power switch pairs in a so-called half-bridge arrangement can be configured to drive electromechanical loads in either of two configurations: a high-side driver (HSD) configuration, in which the load is connected between the output node of the half-bridge and ground; and a low-side driver (LSD) configuration, in which the load is connected between the voltage supply line and the output node of the half-bridge.

[0007] Power supply circuits such as AC / DC or DC / DC switch-mode power supplies are well known in the art. Many types of electronic converters exist, primarily categorized as isolated and non-isolated converters. For example, non-isolated electronic converters include "buck," "boost," and "buck-boost" converters. Converters of the "SEPIC" and "ZETA" types. Isolated converters are, for example, "flyback," "forward," "half-bridge," and "full-bridge" types. These types of converters are well known to those skilled in the art.

[0008] Figure 1This is a schematic diagram of a DC / DC electronic converter 20. Specifically, the conventional electronic converter 20 includes two input terminals 200a and 200b for receiving a DC voltage Vin, and two output terminals 202a and 202b for supplying a DC voltage Vout. For example, the input voltage Vin can be supplied by a DC voltage source 10 (such as a battery), or it can be obtained from an AC voltage by means of a rectifier circuit (such as a bridge rectifier) ​​and possibly by means of a filter circuit. The output voltage Vout can be used to power a load 30.

[0009] Non-isolated step-down voltage converters are widely used, for example, to power microcontrollers. Their ease of use, simplicity, and excellent versatility across a wide range of input and output voltage conditions make buck converters one of the most widely used topologies for this type of conversion.

[0010] Figure 2 A circuit diagram of a typical buck converter 20 is shown. Specifically, the buck converter 20 includes two input terminals 200a and 200b for receiving a DC input voltage Vin, and two output terminals 202a and 202b for supplying a regulated voltage Vout, wherein the output voltage is equal to or lower than the input voltage Vin.

[0011] Specifically, the buck converter 20 typically includes two electronic switches Q1 and Q2 (with their current paths) connected in series (e.g., directly) between input terminals 200a and 200b, wherein the intermediate node between electronic switches Q1 and Q2 represents a switching node SW. Specifically, electronic switch Q1 is a high-side switch (e.g., directly) connected between the (positive) terminal 200a and the switching node SW, and electronic switch Q2 is a low-side switch (e.g., directly) connected between the switching node SW and the (negative) terminal 200b, which typically represents ground (GND). Therefore, the (high-side) switch Q1 and the (low-side) switch Q2 represent a half-bridge configured to connect the switching node SW to either terminal 200a (voltage Vin) or terminal 200b (ground GND).

[0012] For example, switches Q1 and / or Q2 are typically transistors, such as field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), such as n-channel FETs, such as NMOS. Often, the second electronic switch Q2 is also implemented simply as a diode, with the anode connected to terminal 200b and the cathode connected to the switching node SW.

[0013] In the example under consideration, an inductor L, such as an inductor, is connected (e.g., directly) between the switching node SW and the (positive) output terminal 202a. The (negative) output terminal 202b is connected (e.g., directly) to the (negative) input terminal 200b.

[0014] In the example under consideration, in order to stabilize the output voltage Vout, converter 20 typically includes a capacitor Cout, which is connected (e.g., directly) between output terminals 202a and 202b.

[0015] like Figure 2 As shown, the operation of circuit 20 is driven by controller circuit block 22, which may include an input node for receiving common pulse width modulation (PWM) signals and an amplifier circuit system for providing corresponding control signals DRV1 and DRV2 to the first switch and the second switch Q1 and Q2.

[0016] In this context, Figure 3 Some signal waveforms of this electronic converter are shown, where: waveform a) shows the signal DRV1 used to switch electronic switch Q1; waveform b) shows the signal DRV2 used to switch the second electronic switch Q2; waveform c) shows the current IQ1 passing through electronic switch Q1; and waveform d) shows the voltage signal V at the switching node SW. SW (That is, the voltage at the second switch Q2); and waveform e) shows the current I passing through the inductor L. L .

[0017] Specifically, when electronic switch Q1 is closed (ON state) at time t1, the current I in inductor L is... L (Basically) linearly increasing. Electronic switch Q2 is simultaneously open (off state). While electronic switch Q1 is at interval HS... ON Then, at time t2, when the circuit is turned off (OFF state), electronic switch Q2 closes (ON), and current I... L (Essentially) linearly decreasing. Finally, switch Q1 at interval LS ON Then it closes again. In the example considered, therefore when switch Q1 is open, switch Q2 (or a similar diode) is closed, and vice versa.

[0018] Therefore, the current I in the inductor L This can be used to charge capacitor Cout, which supplies voltage Vout at terminals 202a and 202b. In the example considered, to stabilize the output voltage Vout, converter 20 typically includes capacitor Cout, which is connected (e.g., directly) between output terminals 202a and 202b.

[0019] like Figure 3 As shown in waveform e), the current I flowing in inductor L L The evolution over time is equal to the first time interval HS ON The current flowing in the first switch Q1 during the period is equal to the current flowing in the second time interval LS. ON The current flowing in the second switch Q2 during this period.

[0020] like Figure 1 The DC / DC buck converter illustrated includes half-bridge (HB) power stages Q1 and Q2, which transfer electrical energy between the input voltage level Vin and the output voltage level Vout. For example, the input voltage level Vin can be approximately 12 volts, while the output voltage level Vout can be approximately 1.2 volts. For example, the load current intensity I... L It can reach a value of approximately 50 amperes.

[0021] Effective power management is valuable for modern microprocessors because faster processors use lower supply voltages (e.g., as low as 1.2V) due to thinner gate oxides and higher currents (e.g., even up to 200 amps).

[0022] One of the most important parameters in a buck converter is load regulation, which is the circuit's ability to maintain a stable output voltage Vout in response to changing load conditions. This also means that the output current I varies. out When the output current I out As time changes, with the ratio ±ΔI out The change in / ΔT can be observed in the output voltage Vout as overshoot and undershoot, where ΔI out This represents the current I during a given time interval ΔT. out The change. In fact, when the output current I... out When the current I supplied by inductor L changes, L It may be too high or too low, resulting in a change in the voltage Vout at capacitor Cout.

[0023] In a way that is already known, Figure 1 and Figure 2 The buck converter illustrated can be used to power a microcontroller, which can also be configured to drive other loads. These microprocessors can be mounted in vehicles. Therefore, current sensing for monitoring the state of the power stage can be valuable for safety standards.

[0024] Used to sense the current I flowing in the inductive load L LExisting solutions involve using a shunt resistor in series with the inductor L. In the context of the applications under consideration, this option contrasts with reduced power consumption.

[0025] Other known solutions are based on measuring the current flowing in the inductive load L as the sum of the currents flowing in the HS and LS transistors during their respective on-times (i.e., when they are closed). In this case, any known method can be used to provide two separate measurements. However, the reliability of this current sensing method varies with the duty cycle, becoming less reliable for short duty cycle values ​​(e.g., for a typical 1MHz switching frequency, a duty cycle of about 0.1 results in an HS on-time as short as 100ns, where 1ns = 1 nanosecond = 10^646 seconds). -9 (seconds). Therefore, even if the LS on-time (e.g., 0.9 microseconds) remains long enough to allow for accurate current measurement of the low-side current component, measuring the current flowing in the HS becomes challenging.

[0026] Other existing solutions involve: providing a pin (called the VOS pin) to perform the measurement of the output voltage Vout, thereby providing the possibility of performing an indirect measurement of the high-side current; and providing a pin (called the LSET pin) to set the inductor load value, thereby providing a way to obtain an indirect measurement of the high-side current by relying on the accurate inductor value.

[0027] Referring to U.S. Patent Application Publication No. 2010 / 0060257A1, which is incorporated herein by reference, a technique for determining the output current of a power converter circuit is discussed. This technique samples the voltage of a switching node voltage signal at the midpoint of its low phase and generates a sensed current signal based at least in part on the sampled switching node voltage and a calibration voltage. In at least one embodiment of this solution, the device includes a current sensing circuit configured to generate a sensed current signal indicating the average output current of the power converter circuit. This sensed current signal is based at least in part on a sample of the voltage signal at a first node of the power converter circuit. The first node is used to supply current to an inductor of the power converter circuit.

[0028] Referring to U.S. Patent Application Publication No. 20210159788A1, which is incorporated herein by reference, a current estimation circuit is discussed that is configured to estimate the current within a power switch (e.g., within a switching voltage converter) using a voltage measured across its load terminals and its on-state resistance. Ringing and other transient anomalies associated with the power switch are ignored by neglecting the voltage measured across the power switch during the blanking interval following the power switch's turn-on transition. During the remainder of the power switch's on-interval, the measured voltage is sampled to provide a first sample and a second sample. Furthermore, during this interval, the slope of the measured voltage is estimated and tracked. The estimated slope, along with the first and second samples, is combined to produce an estimate of the current for the entire on-interval of the power switch, including the blanking interval. The estimated slope is used to correct for inaccuracies introduced by not using the voltage measured during the blanking interval.

[0029] There is a need in this field to properly address the problems discussed above. Summary of the Invention

[0030] One or more embodiments may relate to a method.

[0031] One or more embodiments may involve corresponding circuits.

[0032] One or more embodiments may relate to corresponding electronic converter devices.

[0033] One or more embodiments may involve corresponding processing or control units.

[0034] One or more embodiments can be equipped on a vehicle.

[0035] One or more embodiments may relate to corresponding current measurement methods.

[0036] One or more embodiments help to provide an estimate of the current flow in the high-side transistor of a half-bridge arrangement based on the current flow sensed in the low-side transistor during the time the low-side transistor is on.

[0037] One or more embodiments help to provide accurate readings without introducing any shunt resistors, thereby improving the energy efficiency of the power stage.

[0038] One or more embodiments use relatively simple components (means) compared to known solutions involving discrete power MOS transistors for current sensing. Attached Figure Description

[0039] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0040] Figure 1 Typical applications of electronic converters are shown;

[0041] Figure 2 An example of a buck converter is shown;

[0042] Figure 3 It shows Figure 2 Exemplary waveforms of the converter a) to e);

[0043] Figure 4 This is an exemplary schematic diagram of an electronic converter circuit and a current sensing circuit;

[0044] Figure 5 This is an exemplary schematic diagram illustrating the evolution of a signal over time in one or more embodiments;

[0045] Figure 6 This is an exemplary schematic diagram using waveforms a) and b) on the principles upon which one or more embodiments are based;

[0046] Figure 7 This is an exemplary schematic diagram using waveforms a) and b) on the principles upon which one or more embodiments are based;

[0047] Figure 8 This is an exemplary schematic diagram illustrating the principles upon which one or more embodiments are based;

[0048] Figure 9 yes Figure 4 Exemplary schematic diagrams detailing embodiments of the electronic converter circuit and current sensing circuit;

[0049] Figure 10 This is an exemplary schematic diagram illustrating the evolution of a signal over time in one or more embodiments;

[0050] Figure 11 This is an exemplary schematic diagram illustrating the principles upon which one or more embodiments are based;

[0051] Figure 12 yes Figure 4 Exemplary schematic diagrams detailing embodiments of the electronic converter circuit and current sensing circuit;

[0052] Figure 13 This is an exemplary schematic diagram illustrating the evolution of a signal over time in one or more embodiments;

[0053] Figure 14 This is a schematic diagram of an extrapolated signal in one or more embodiments;

[0054] Figure 15 This is a schematic diagram illustrating the evolution of a signal over time in one or more embodiments;

[0055] Figure 16 This is an exemplary schematic diagram of a sensing circuit according to one or more embodiments;

[0056] Figure 17 yes Figure 16 An exemplary schematic diagram of a portion of the circuit illustrated herein;

[0057] Figure 18 This is an exemplary schematic diagram of an electronic device equipped with the circuit;

[0058] Figure 19 This is an exemplary schematic diagram of an electronic system equipped with this circuit;

[0059] Figure 20 This is an exemplary schematic diagram of a vehicle equipped with this circuit; and

[0060] Figure 21 and Figure 22 This is an exemplary schematic diagram illustrating the working principle upon which one or more embodiments are based. Detailed Implementation

[0061] The corresponding numbers and symbols in different figures usually refer to the corresponding parts, unless otherwise stated.

[0062] The accompanying drawings are intended to clearly illustrate relevant aspects of the embodiments, and the drawings are not necessarily drawn to scale.

[0063] The edges of features drawn in the attached figures do not necessarily indicate the end of the feature's range.

[0064] In the following description, one or more specific details are illustrated to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details or using other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been illustrated or described in detail so as not to obscure certain aspects of the embodiments.

[0065] References to “embodiment” or “one embodiment” within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described in connection with an embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear at one or more points in this specification do not necessarily refer to the same embodiment.

[0066] Furthermore, in one or more embodiments, specific constructions, structures, or characteristics can be combined in any suitable manner.

[0067] The references used in this document are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0068] For simplicity, in the following detailed description, the same reference numerals may be used to designate both nodes / lines in a circuit and signals that may appear at that node or line.

[0069] like Figure 4 As illustrated, the electronic converter circuit 20 includes: a control node PWM configured to receive a pulse width modulation signal to drive a first switch Q1 and a second switch Q2 in a half-bridge arrangement; a first amplifier circuit 220 coupled to the control node PWM and configured to provide a first drive signal DRV1 to the first switch Q1 to control its operation in a manner known per se; and a second amplifier circuit 222 coupled to the control node PWM via an inverter circuit 221 and configured to provide a second drive signal DRV2 to the second switch Q2 to control its operation in a manner known per se.

[0070] like Figure 4 As illustrated, the electronic converter circuit 20 is coupled to the current sensing circuit 40.

[0071] According to this disclosure, the current sensing circuit 40 includes: a first current amplifier circuit 41, located between the switching node SW and the second switch Q2 of the converter 20, and configured to operate when the second switch Q2 is turned on or off (i.e., during the second time interval LS). ON (At least a portion of the period) senses the low-side current I flowing in the current path through the second switch Q2. LS The current estimation cascades of the circuit blocks 42, 44, and 46 are coupled to the switching node SW of the converter 20 and include an estimation circuit system and a selector element K1 (such as a switch) configured to estimate the value of the high-side current flowing in the first switch Q1. The selector element K1 is configured to turn on or off based on a timing signal K1. The selector element K1 is coupled to a current sensing amplifier 48 configured to provide the value of the current flowing in the inductor element L coupled to the converter circuit 20.

[0072] It should be noted that, in principle, the value of the inductor L is not necessarily known to the current sensing circuit 40.

[0073] In one or more embodiments, the current sensing amplifier 41 may be known per se. In a manner known per se, the sensing signal provided by amplifier 41 may be related to the low-side current I... LS A voltage sensing signal that has a certain relationship. For example, this relationship can be expressed as 5mV / A·I. LS .

[0074] like Figure 4As illustrated, the current estimation cascades 42, 44, and 46 include: an output voltage estimator (OVE) circuit block 42 configured to provide an estimated voltage Vo_est of the output voltage Vout at the output of the converter 20; and a superposition circuit 43 coupled to the switching node SW and the output voltage estimator circuit block 42 to provide the estimated voltage drop Vind across the inductor element L as the voltage V at the switching node SW. SW The difference between the estimated output voltage Vo_est and the inductance estimator (IE) circuit block 44, coupled to the superposition circuit 43, and configured to provide an estimate of the inverse 1 / L of the inductance of the inductor element L; the integrator (INT) circuit block 46, coupled to the inductance estimator circuit block 44, and configured to calculate the ratio of the estimated voltage drop Vind to the inverse inductance 1 / L, thereby providing the estimated inductance current intensity IHS_est as a result.

[0075] like Figure 5 As illustrated, the selector circuit K1 is configured to sense time interval ΔT MEAS During this period, the sensed current I through the second switch Q2 is provided for measurement. LS And in the estimated time interval ΔT EST The estimated inductor current intensity IHS_est is provided during this period.

[0076] like Figure 5 As illustrated in the figure, in the second time interval LS ON At the beginning, the current sensing amplifier switches from off to on, so it may not yet be ready to provide current measurement. Therefore, the estimated time interval K1 can be greater than the on-time HS of the first switch Q1. ON For example, the estimated time interval K1 can be equal to the first conduction time interval HS. ON This is the sum of the settling time interval used by the current sensing amplifier to generate the measurement result. For example, the settling time can be approximately 200 ns (1 ns = 1 nanosecond = 10^645 seconds). -9 Second).

[0077] As illustrated herein, the output voltage estimator circuit block 42 includes a cutoff angular frequency ω. C The cutoff angular frequency indicates the actual cutoff frequency of the LC circuit coupled to the switching node SW. For example, in one or more embodiments, a second-order low-pass filter, known per se, can be used for the output voltage estimator circuit block 42. For example, the cutoff frequency f of the output voltage estimator circuit block 42... c It can be set in the range of 15kHz to 17kHz, preferably 16.0kHz (1kHz = 1 kilohertz = 10 kHz). 3(Hertz), which takes into account that the typical value of inductance L is about 0.15 microhenries and the typical value of capacitance C is about 660 microfarads.

[0078] like Figure 6 As illustrated in the example, even if there is a small difference between the estimated output voltage Vo_est and the actual output voltage Vout, such as Figure 6 As shown in waveform b), the estimated current ISENSE(Vo_est) also has a value close to the actual current ISENSE(Vout), as... Figure 6 The waveform is shown in a).

[0079] Figure 7 yes Figure 6 An enlarged view of a portion of the schematic diagram illustrated herein. (See also:) Figure 7 As illustrated in the figure, waveform b) presents a comparison between the estimated output voltage signal Vo_est and the actual output voltage signal Vout, and waveform a) presents a comparison between the output voltage ISENSE of buffer 48 based on the estimated ISENSE (Vo_est) or the actual ISENSE (Vout), which in both cases achieves an output current value of approximately 20 amps and a constant on-time during a time interval of 4 microseconds.

[0080] like Figure 4 As illustrated, the output signal ISENSE can indicate the current flowing in the inductive load L, because it can be expressed as ISENSE = 5mV / A·I. L The (known) relationship.

[0081] As illustrated herein, the inductance estimator circuit block 44 includes an automatic gain control (AGC) loop whose gain indicates the inductance value 1 / L and whose value is continuously refreshed at each PWM cycle.

[0082] Figure 8 An example of the principle upon which the operation of circuit block 44 is based.

[0083] like Figure 8 As illustrated, the AGC starts with an initial approximate gain value (e.g., after power-on) and can remain stable for several PWM cycles (e.g., 100 cycles) before stabilizing to a steady-state gain value. For example, the AGC is partially digital and is able to retain the gain value in digital volatile memory as long as power is supplied.

[0084] like Figure 8As illustrated, the AGC loop samples the value of the output current sensing signal ISENSE during the time interval between the selector circuit K1 closing and the first switch Q1 opening (specifically, very close to the switching time of selector K1) to obtain an initial estimate L0. If the initial estimate L0 is too low relative to the actual inductance value L, the output ISENSE of buffer 48 exhibits a vertical decrease in current value Phigh; therefore, the AGC loop reduces its gain. If the initial estimate L0 is too high relative to the actual inductance value L, the output ISENSE of buffer 48 exhibits a vertical increase in current value Plow; therefore, the AGC loop increases its gain. This process is iterated until the comparison between the output sensing signal ISENSE before and after the sampling time Tsample of the AGC loop can be considered negligible.

[0085] Figure 9 Is using Figure 8 The diagram illustrates how the gain update of circuit block 44 is implemented according to the principle.

[0086] In such Figure 9 In the circuit 40' illustrated herein: the first sense amplifier 41 includes a programmable gain amplifier (PGA) configured to output an indication at a second time interval LS. ON The voltage PGAout of the current flowing in the second switch Q2 during this period; and the output voltage estimator (OVE) circuit block 42 is coupled to (e.g., transconductance) amplifier 43, which provides the current output signal OTAout.

[0087] For example, inductance estimator (IE) circuit block 44 includes: a comparator circuit 440 coupled to circuit block 43 and a first sensing circuit 41, the comparator being configured to respond to a measured current I received from the first sensing circuit 41. LS The system outputs a first (e.g., "1" or "true") logic value and a second (e.g., "0" or "false") logic value, respectively; and a digital counter 444, coupled to comparator 440, and configured to count incremented or decremented at clock signal edge GAIN_CK based on the logic value U received from comparator 440.

[0088] For example, the digital counter 444 outputs a signal gm_control, which, for example, comprises 9 bits and its value can be in a certain range (e.g., from 0 to 511), and is configured to cause the gain of OTA 43 to vary in a certain range, for example, from 0 to 1.31 μA / V.

[0089] like Figure 9As illustrated, circuit 40' further includes: a first selector switch K10, interposed between the output of circuit block 43 and the input of buffer 48, and configured to be selectively turned on in response to a first switch signal K10 having a first logic value (e.g., "1" or "true"); a second selector switch K11, interposed between the output of current sensing amplifier circuit 41 and the input of buffer 48, and configured to be selectively turned on in response to a second switch signal K11 having a first logic value (e.g., "1" or "true"); and a third selector switch K12, interposed between the output of circuit block 43 and the output of current sensing amplifier circuit 41, and configured to be selectively turned on in response to a third switch signal K12 having a first logic value (e.g., "1" or "true").

[0090] exist Figure 9 The example shown can be used as described below (primarily referenced). Figure 16 and Figure 17 The calibrated current sensing amplifier 41 discussed. Second switching current I LS The improved accuracy in the measurement can advantageously provide improved accuracy in current estimation cascades 42, 43, 44, 46, and 48, as discussed below.

[0091] Figure 10 It is possible to be with Figure 9 The circuit illustrated here is an exemplary timing diagram of the signals used in combination.

[0092] like Figure 10 As illustrated: at the first (e.g., rising) edge of the drive signal PWM, the second selector switch K11 is turned off, and the third selector switch K12 is also turned off, thereby coupling amplifier 41 to comparator 440 and decoupling it from output buffer 48. Once the value of the current sensing curve PGAout is made available from the current sensing amplifier circuit 41, the value of the current sensing curve PGAout is sampled at the edge of the clock signal GAIN_CK. Subsequently, the AGC loop is driven by digital counter 444 to increase or decrease the gain of OTA 43 based on the result of the comparison 440 between the sampled sensed current value PGAout and the output OTA signal OTAout.

[0093] For example, after 100 iterations, the values ​​of signals PGAout and OTAout are approximately the same at the sampling time GAIN_CK.

[0094] Figure 11 It is considered Figure 9 The diagram illustrates the principle upon which one or more embodiments of the nonlinearity in the circuits illustrated are based.

[0095] like Figure 9 As illustrated, in the presence of negative or positive (unknown and undesirable) offset currents, even with a very good match of the value L0 at the sampling clock edge, the estimated current evolves significantly differently over time from the actual measured current I. MEAS .

[0096] like Figure 12 The circuit 40” illustrating the current offset compensation circuit block 43 includes an additional digital counter 442 coupled to comparator circuit 440 and a programmable current generator 443 coupled to the output of OTA amplifier 43. The programmable current generator 443 is configured to generate current based on a digital count indicated by the additional digital counter 442. For example, the additional digital counter 442 is configured to generate a multi-bit additional digital counter signal, such as a 10-bit signal whose value can vary within a range (e.g., from -512 to 511), to drive the current generator 443 to generate a current intensity within a range (e.g., from -2.5 μA to +2.5 μA).

[0097] like Figure 13 exemplified in Figure 12 The operation of circuit 40" shown is similar to Figure 10 The operation is the same as that already illustrated, but an additional clock signal OFFSET_CK is added. This additional clock signal OFFSET_CK drives an additional digital counter 442 to sample the value of the measured current signal PGAout and the estimated output value OTAout to perform a comparison between them, and outputs a logic value that determines whether the digital counter increments or decrements the count, thereby increasing or decreasing the amplitude of the programmable current generator 443 accordingly.

[0098] In one or more embodiments, comparator 440 may include autocalibrating comparator circuitry or selfcalibrating comparator circuitry (known per se) to account for the introduction of additional non-ideals. For example, circuit architectures 40, 40', 40" are configured to provide space to perform autocalibration of comparator circuitry 440 in a manner known per se.

[0099] like Figure 13 As illustrated, relative to the first counter 444, the additional counter 442 can be activated a reduced number of times (e.g., once every four PWM signal cycles) because the change in offset that must be compensated over time can be considered slower than the gain change tracked by the AGC loop.

[0100] like Figure 13As illustrated, the third switch K12 can be asserted as the first logic value once every four cycles (e.g., once every period of time) to perform offset compensation and trigger another counter 442 accordingly.

[0101] like Figure 14 As illustrated in the example, in the second time interval LS ON The settling time of amplifier circuit 41 lasts longer than a fixed delay time (e.g., 200 ns, where 1 ns = 1 nanosecond = 10). -9 In the case of short intervals (seconds), the outputs of circuits 40, 40', and 40" provide an estimate of the current flowing through the inductor L up to a given number (e.g., ten) of PWM cycles; therefore, in situations where the system responds to fast load / line transients and the time interval LS... ON The estimated current ISENSE can also remain valid for a finite number (e.g., ten) of PWM cycles under relatively short transient conditions.

[0102] As illustrated herein, one advantage of the circuits 40, 40', 40" according to this disclosure is that they help to reconstruct the evolution of the current flowing in the inductor L of the converter 20 over time, even when both switches Q1 and Q2 of the half-bridge arrangement are turned off for time intervals much longer than the dead time.

[0103] like Figure 9 and Figure 12 As illustrated, the current sensing amplifier circuit block 41 is coupled to a reference voltage line VREF, which is also connected via a capacitor element Cc (e.g., having a capacitance of approximately 10 pF (1 pF = 1 picofarad = 10 picofarads)). -12 The capacitor (Faraday) is coupled to the output of the OTA 43.

[0104] like Figure 15 The sensing method illustrated in the example includes: in response to both HS and LS being turned off, a (digital) counter is triggered to begin counting; during the active counting period of the counter, the loop maintains a tracking load current value via an active OTA (transconductance) amplifier; once the counter reaches a preset value (e.g., 12 μs, where 1 μs = 1 microsecond = 10), the loop continues to track the load current value. -6 (seconds), the comparator detects whether the voltage at the switching node SW has changed sign (e.g., from negative to positive); as a result of the comparator detecting a change in the sign of the voltage at the switching node, the voltage output of amplifier 41 is forced to VREF (corresponding to the zero current signal at the ISENSE pin).

[0105] like Figure 15As illustrated, this circuit helps ensure the accuracy of the reconfigured current even in the presence of the following non-ideal conditions: 1) the voltage slope and delay at the switching node SW; 2) the dead time DT of the half-bridge switches Q1 and Q2; 3) the voltage drop across the half-bridge switches Q1 and Q2; and 4) any voltage waveform at the switching node SW during the high-impedance state of the half-bridge switches Q1 and Q2, particularly: 4a) the recirculation on the body diodes of switches Q1 and Q2; and 4b) the switching node voltage signal V during current turn-off. SW The dumped oscillation.

[0106] like Figures 1 to 15 The method illustrated in the example includes: at the high-side reference node V IN The high-side switch Q1 is coupled between the switch node SW and the low-side reference node PGND; and the low-side switch Q2 is coupled between the switch node SW and the low-side reference node PGND.

[0107] For example, the high-side switch includes a high-side control terminal configured to receive a high-side control signal PWM, DRV1, and a current flow path through the high-side switch between the high-side reference node and the switching node. The high-side switch is configured to respond to the high-side control signal in a first time interval HS. ON It is turned on when it has the first logic value during the period.

[0108] For example, the current flow path of the high-side switch provides a high-side current flow path I between the high-side reference node and the switching node. HS .

[0109] For example, the low-side switch includes a low-side control terminal configured to receive low-side control signals PWM and DRV2, and a current flow path through the low-side switch between the switching node and the low-side reference node. The low-side switch is configured to respond to the low-side control signal in a second time interval LS. ON During this period, the first logic value is used to enable conduction.

[0110] For example, the current flow path I between the switching node and the low-side reference node is provided through the current flow path of the low-side switch. LS .

[0111] like Figures 1 to 15 As illustrated, the method further includes: coupling an inductor L to a switching node and configuring it to be coupled to an output node Vout of a load 30; sensing a switching voltage V at the switching node. SWThe sensed switching voltage is provided to a filter circuit 42, which is configured to provide a filtered voltage Vo_est based on the sensed switching voltage, the filtered voltage indicating the output voltage at the output node; and based on the difference V between the filtered voltage and the sensed switching voltage. IND The user circuit system 48 is provided with 43, 44, and 46 indicating an estimated time ΔT equal to or greater than the first time interval. EST The output current signals IHS_est and ISENSE represent the intensity of the current flowing through the inductive load during this period.

[0112] like Figures 1 to 15 The illustrated filter circuit includes a filter circuit having a cutoff frequency (e.g., about 16.0 kHz) based on the expected inductance value of the inductor element.

[0113] like Figures 1 to 15 as well as Figure 16 As illustrated, the method further includes: receiving, via measurement circuit 41, a low-side current I indicating the current flow path through the low-side switch. LS The current measurement signal PGAout is obtained by applying transconductance amplification to the difference between the filtered voltage and the sensed switching voltage via a transconductance amplifier with variable gain and an OTA circuit 43, thereby obtaining an amplified and filtered current signal OTAout as a result.

[0114] For example, the variable gain of the transconductance amplifier and OTA circuit is based on a stored digital code set via the digital counter circuit 444.

[0115] like Figures 9 to 13 As illustrated, setting the digital code via the digital counter circuit includes: initiating the digital code of the digital counter as an initial digital code value; when the estimated time expires (GAIN_ck, K12), performing a comparison 440 between the amplified and filtered current signal and the current measurement signal; incrementing and decrementing U / D and the digital code respectively, as results of the current measurement signal exceeding and not exceeding the amplified and filtered current signal; and changing the variable gain of the transconductance amplifier and the OTA circuit based on the digital code incremented or decremented via the digital counter.

[0116] like Figures 12 to 15 As illustrated, for example, the transconductance amplifier and OTA circuit have an offset current, and the method further includes: generating an offset compensation current with a programmable current intensity via a programmable current generator circuit 443; and superimposing the offset compensation current onto the amplified and filtered current signal.

[0117] For example, the programmable current intensity of the offset programmable current generator circuit is based on a stored digital code set via a separate digital counter circuit 442, such as... Figure 12 exemplified.

[0118] like Figures 12 to 15 As illustrated, setting the additional digital code via the additional digital counter circuit includes: initiating the digital code of the additional digital counter to an initial digital code value equal to zero; immediately following this, at an estimated time interval ΔT... EST Before starting OFFSET_CK, the amplified and filtered current signal is compared with the current measurement signal; U / D and the additional digital code are decremented and incremented respectively, based on whether the current measurement signal exceeds or does not exceed the amplified and filtered current signal; and the programmable strength of the offset compensation current generator circuit is changed based on the additional digital code incremented or decremented via the additional digital counter.

[0119] like Figures 1 to 15 As illustrated, during the estimated time interval, the method includes coupling the outputs of the OTA circuits K1, K10, K11, and K12 to an output buffer 48 to supply power to user circuits (such as...). Figures 18 to 20 The method provides an output current signal to the measurement circuits 41 (such as those illustrated in the diagram), while during the remaining time (outside of the estimated time interval), the method includes coupling the measurement circuits 41 described in K1; K10, K11, K12 to the output buffer to supply a signal to the user circuit (such as...). Figures 18 to 20 Those shown in the example provide output current signals.

[0120] like Figures 1 to 15 as well as Figure 16 As illustrated, measuring the current measurement signals PGAout and Vsense includes: coupling one input node 410a of an additional programmable gain OTA amplifier circuit 410 to the switching node and coupling another input node 410b of the OTA circuit to the low-side reference node; measuring the voltage drop across the low-side switch; and applying the sensed voltage across a set of variable resistors R1 and R2 configured to change the gain of the additional OTA circuit, thereby providing the current measurement signal as a result.

[0121] For example, the resistance of at least one of the variable resistor elements in the set of variable resistor elements is set by an error compensation digital code Acode set via the error compensation circuit 411.

[0122] like Figure 16 and Figure 17The error compensation circuit illustrated herein includes: a non-volatile memory (NVM) circuit 414 storing parameter values ​​Gon11, Gon12, Gon21, Gon22 of the low-side switch collected during the manufacture of the low-side switch at multiple temperatures and operating / drive voltage values; operating voltage sensing circuits 412, 413 configured to sense the operating / drive voltage Vgs at the control terminal of the low-side switch during the measurement of the current measurement signal 41; temperature sensing circuits 415, 416 configured to sense the operating temperature Tj of the low-side switch during the measurement of the current measurement signal; and resistance calculation (ResCal) circuits 417, 418 configured to provide the error compensation digital code based on the stored low-side switch parameter values, the sensed operating / drive voltage, and the sensed operating temperature.

[0123] like Figure 16 and Figure 17 As shown, the process parameters stored in the non-volatile memory include the on-conductance values ​​of the low-side switches collected by changing the operating temperature for a given operating voltage and by changing the operating / drive voltage at a given operating temperature.

[0124] like Figure 16 and Figure 17 As illustrated, the resistance calculation circuit 417 includes: a first linear interpolation circuit 4172 configured to perform linear interpolation on a set of conductance values ​​collected and stored in non-volatile memory at a given operating voltage, thereby providing a set of interpolation curves indicating the evolution of the conductance of the low-side switch with temperature as a result; the first linear interpolator circuit is further configured to extract a set of conductance values ​​Gon1T, Gon2T at the sensed temperature signal from the set of interpolation curves; and a second linear interpolation circuit 4176 coupled to the first linear interpolator circuit to receive the extracted set of conductance values ​​therefrom; the second linear interpolation circuit is configured to perform linear interpolation on the extracted conductance values, thereby providing an interpolation curve indicating the evolution of the conductance of the low-side switch with operating voltage as a result; the second linear interpolator circuit is further configured to extract the conductance value GonVT at the sensed operating voltage from the interpolation curves.

[0125] like Figures 1 to 15The circuit illustrated includes: a high-side switch coupled to a high-side reference node and a switching node, wherein the high-side switch includes a high-side control terminal configured to receive a high-side control signal and a current flow path through the high-side switch between the high-side reference node and the switching node, the high-side switch being configured to be turned on in response to the high-side control signal having a first logic value during a first time interval, wherein the current flow path through the high-side switch provides a high-side current flow path between the high-side reference node and the switching node; and a low-side switch coupled to the switching node and a low-side reference node, wherein the low-side switch includes a low-side control terminal configured to receive a low-side control signal and a current flow path through the low-side switch between the switching node and the low-side reference node, the low-side switch... A switch is configured to be turned on in response to a low-side control signal having the first logic value during a second time interval, wherein a current flow path through the low-side switch provides a current flow path between the switch node (SW) and the low-side reference node; an inductor element coupled to the switch node and configured to be coupled to an output node of a load; a filter circuit coupled to the switch node to sense a switch voltage from the switch node, the filter circuit being configured to provide a filtered voltage based on the sensed switch voltage, the filtered voltage indicating the output voltage at the output node; and a signal processing circuit system coupled to the filter circuit, the signal processing circuit system being configured to, based on the difference between the filtered voltage and the sensed switch voltage, according to... Figures 1 to 15 The method illustrated herein provides an indication to the user circuit system that the time interval is equal to or greater than the first time interval HS. ON Estimated time ΔT EST The output current signals IHS_est and ISENSE represent the intensity of the current passing through the inductive load during this period.

[0126] like Figure 18 or Figure 19 The switch converter device (SCD) 180 and controller unit 190 illustrated herein include, as follows: Figures 1 to 15 The illustrated circuits 40, 40', 40'', and the battery (B) 10 configured to supply a voltage level to the reference node VI (see [link]). Figure 20 Alternatively, it may be configured to provide a ground voltage level to the reference node, PGND. The switch converter device also includes a control circuitry configured to provide the control signals to the low-side and high-side switches of the circuit.

[0127] like Figure 19 As illustrated, the electronic control unit (ECU) includes: Figure 18 At least one switch-converter device 180 as illustrated or such Figures 1 to 15At least one circuit 40, 40', 40" is illustrated; a microcontroller 190 is coupled to the at least one switching converter device or the at least one circuit and is configured to provide the control signal thereto; and at least one load 30; 301, 302 (see also...) Figure 20 ), is configured to be coupled to the circuit to receive the regulated output voltage Vout from the circuit.

[0128] like Figure 20 As illustrated, the ECU is installed in the vehicle V (such as a battery-powered car).

[0129] As discussed above, the accuracy of estimating the cascades 42, 43, 44, 46, and 48 can be a function of the non-idealities of the components involved and the current sensing amplifier 41 providing the measured current I. LS The accuracy and timing of the signal.

[0130] Figure 16 This is an exemplary arrangement of the current sensing amplifier circuit block 41, which can be used in the circuits 40, 40', 40" according to this disclosure, or it can also be used in a conventional half-bridge circuit 20 to detect the current flowing through any of the switches Q1, Q2.

[0131] like Figure 16 As illustrated, the sensing circuit block 41 includes: a programmable gain amplifier (PGA) 410, including a first PGA input node 410a coupled to a switching node SW and a second PGA input node 410b coupled to terminals of switches Q1 and Q2 (whose on-resistance Ron is under monitoring), for example, a terminal coupled to a second switch Q2; the PGA also includes a first output node Vsense configured to provide a signal indicating the current flowing across switch Q2 and a reference signal V. REF The second output node V REF The compensation circuit block 411 is coupled to the monitored switch Q2 via a corresponding driver 222, and to the PGA 410 to provide it with compensation for non-idealities, as described below.

[0132] It will be understood by those skilled in the art that the gain value PGAgain of the PGA circuit 410 can be expressed as:

[0133]

[0134] like Figure 16 As illustrated, the sensed voltage signal Vsense is based on a reference voltage VREF and a known expression, such as:

[0135] V SENSE =VREF +5mV / A·I LS

[0136] Since the sensed signal is also a function of the on-resistance Ron of switch Q2 and the current flowing through switch Q2, the above expression can be rewritten as:

[0137]

[0138] This produces

[0139]

[0140] like Figure 16 As illustrated, the compensation circuit system 411 is configured to ensure that the entire power MOS R ON The variable resistances of resistor elements R1 and R2 are modified in accordance with the above equation during the PVT change.

[0141] Specifically, the direct gain can be changed by altering the first resistive element R1 of the PGA circuit 410, or the inverse gain can be changed by altering the second resistive element R2 of the PGA circuit 410.

[0142] like Figure 16 As illustrated, the PGA circuit 410 includes a differential amplifier 4100 having a set of variable resistors R1, R2 coupled to a first input node and an output node to control the direct gain of the PGA circuit 410, or a second set of variable resistors R1', R2' coupled to a second input node and an output node to control the inverse gain of the PGA circuit 410, as discussed below.

[0143] like Figure 16 The illustrated compensation circuit block 411 includes: a differential amplifier 412 including a first input node 412a and a second input node 412b, which are coupled across a driver 222 of the second switch Q2 to detect its drive (e.g., gate) signal DRV2; and a first analog-to-digital converter (ADC) circuit 413 coupled to the output node of the differential amplifier 412, the first ADC circuit 413 being configured to output an indication of the on-resistance R of the second switch Q2 at operating temperature and supply voltage VCC. ON The digital signal D of the "real-time" value VGSData storage circuitry 414 (such as non-volatile memory NVM) is configured to store calibration data Dcalibr for correcting Ron measurements, as described below. For example, data storage circuitry 414 stores data output from the production line after the switch Q2 is assembled with its driver (to store data related to non-idealities in the system-in-package, SiP). Programmable current generator 415 is coupled to diode Qa (reference ground), and a second ADC circuitry 416 is coupled to programmable current generator 415 and configured to apply analog-to-digital conversion thereto, thereby providing a second digital current signal Dtemp indicating the temperature of switch Q2. Linear interpolator 417 is coupled to first ADC circuitry 413 to receive a first digital signal Dvgs therefrom, coupled to data storage circuitry 414 to receive the calibration signal Dcalibr therefrom, and coupled to second ADC circuitry 416 to receive the second digital signal Dtemp therefrom. Linear interpolator 417 is configured to provide a gain code GONcode based on the received digital signals Dvgs, Dtemp, and Dcalibr, as described below. Figure 17 The digital controller circuit 418 is coupled to the linear interpolator 417 to receive the gain digital code GONcode from it, and is configured to provide changes in the values ​​of resistors R1 and R2 of the PGA amplifier 410 based on the received gain digital code GONcode.

[0144] like Figure 16 The method for compensating for non-idealities in the PGA circuit 410, as illustrated in the diagram, includes: receiving calibration data Dcalibr from a data storage circuit 414, the calibration data indicating the manufacturing process of the SiP including switch Q2; receiving a first digital signal Dvgs from a first ADC circuit 412, the first digital signal Dvgs indicating calibration data collected from the manufacturing process of switch Q2; receiving a second digital signal Dtemp from a second ADC circuit 416, the second digital signal Dtemp indicating the operating temperature of switch Q2; and performing adjustments to the received signals Dcalibr and Dtemp. Linear interpolation of mp and Dvgs provides a digital conductance value GONcode based on the on-conductance of switch Q2 at the "real-time" operating / drive voltage Vgs and temperature T (i.e., the reciprocal of the on-resistance Ron); and a digital control code Acode (e.g., a 10-bit digital code) is generated based on the digital conductance value GONcode, and the direct gain resistors R1, R2 or the inverse gain resistors R1', R2' are changed (in a manner known per se) to change the gain of the PGA circuit 410 until it reaches a target value, which can be represented as PGA GAIN =G ON *5mV / A.

[0145] For example, the control circuit block 418 may include a multiplier circuit, and the digital control code Acode may be the result of multiplying the digital conductance value GONcode with the first digital signal Dvgs provided by the first ADC circuit 413, thereby mapping the conductance value to the control values ​​of the resistive elements R1 and R2 of the PGA 410.

[0146] As will be understood by those skilled in the art, the conductance Gon of the on-resistance Ron of an inverted (e.g., MOSFET) switch Q2 can be expressed as:

[0147]

[0148] Where: VGS is the gate-source operating / driving voltage; VT is the MOSFET threshold voltage; W is the width of the MOSFET channel; L is the length of the MOSFET channel; Cox is the gate oxide capacitance per unit area; and μ is the carrier mobility parameter that forms the inversion channel of the MOSFET.

[0149] It is advantageous to utilize the linear relationship between conductivity Gon and temperature T, as well as the operating voltage Vgs.

[0150] Figure 17 This is an example diagram of a linear interpolator circuit 170, which can... Figure 16 It is used in block 4170 of the digital controller 417 illustrated therein.

[0151] For simplicity, one or more embodiments of the interpolator will be discussed primarily with reference to an example of a linear interpolator based on two temperature values. It should be understood that this number of temperature values ​​is merely exemplary and not limiting. One or more embodiments may employ an N-temperature interpolator, where N is potentially equal to any integer equal to or greater than two.

[0152] like Figure 17 As illustrated, the data storage circuit block 414 includes at least four data storage units, such as a first data storage unit 4140 configured to store a first manufacturing / assembly process value, such as a first conductance value Gon11 at a first temperature T1 and a first operating voltage V1, for example, G... ON11 =G ON @V1,T1; The second data storage unit 4141 is configured to store a second manufacturing process value, such as a second conductivity value Gon12 at the first operating voltage V1 and the second temperature T2, for example, G ON12 =G ON@V1,T2; The third data storage unit 4142 is configured to store a third manufacturing process value, such as a third conductivity value Gon21 at the second operating voltage V2 and the first temperature T1, for example, G ON21 =G ON @V2,T1; and the fourth data storage unit 4143, configured to store a fourth manufacturing process value, such as a fourth conductivity value Gon22 at the second operating voltage V2 and the second temperature T2, for example, G ON22 =G ON @V2,T2.

[0153] like Figure 17 As illustrated, the linear interpolator 417 includes: a first multiplexer circuit 4170A coupled to a first data storage unit 4140 and a third data storage unit 4142 of the NVM circuit 414, the first multiplexer circuit 4170A being configured to select a signal Gonx1 from either a first process parameter Gon11 or a third process parameter Gon21 stored in the respective data storage units 4140 and 4142 of the NVM circuit 414 based on a selection signal X; and a second multiplexer circuit 4170B coupled to a second data storage unit 4141 and a fourth data storage unit 4143 of the NVM circuit 414, the second multiplexer circuit 4170B being configured to select a signal Gonx2 from either a second process parameter Gon12 or a fourth process parameter Gon22 stored in the respective data storage units 4140 and 4142 of the NVM circuit 414 based on the selection signal X.

[0154] The first linear interpolator circuit 4172 is configured to interpolate a curve between signals Gonx1 and Gonx2 selected by multiplexers 4170A and 4170B, the interpolated curve indicating the evolution of the process parameter Gon of switch Q2 with temperature T1 and T2.

[0155] like Figure 17 As illustrated, the first linear interpolator circuit 4172 is also configured to receive a digital temperature code Dtemp from the second ADC circuit 416, thereby receiving data related to the real-time operating temperature Tj of switch Q2.

[0156] As illustrated, based on the received digital temperature code Dtemp and the interpolation of process parameters Gonx1, Gonx2 of the selected switch Q2 as the temperature evolves, the first linear interpolator 4172 is configured to provide a set of estimated Gon1T, Gon2T of process parameters at real-time temperature Tj, and store them in corresponding memory cells of temporary memory circuitry 4174 (e.g., RAM). For example, the set of estimated Gon1T, Gon2T can be sequentially stored in temporary memory 4174 via an additional multiplexer 4173 driven by selector signal X, wherein the additional multiplexer 4173 selects the corresponding cell of RAM 4174 as the linear interpolator provides the corresponding data value GonxT for each value of selector signal X.

[0157] like Figure 17 As illustrated, the linear interpolator 417 also includes a second linear interpolator 4176, which is coupled to a temporary memory 4174 to receive the values ​​of process parameters Gon1T and Gon2T at the real-time temperature Tj of switch Q2.

[0158] like Figure 17 As illustrated, the second linear interpolator 4176 is configured to: perform linear interpolation on data stored in temporary memory 4174 to obtain a curve indicating the evolution of process parameter values ​​with respect to the operating / drive voltage value Vgs as a result; and based on the obtained curve, provide a digital parameter code 4178 GONcode as the value GonVT of the process parameter Gon under the real-time temperature Tj and real-time operating / drive voltage Vgs of switch Q2 extracted from the obtained curve.

[0159] Figure 21 This is an example schematic diagram of the extrapolation curve of the evolution of the conductance Gon relative to temperature T, which can be provided by the first linear interpolator circuit block 4172.

[0160] Figure 22 This is an example schematic diagram of the extrapolation curve of the on-conductance Gon relative to the operating / drive voltage Vgs, which can be provided by the second linear interpolator circuit block 4176.

[0161] like Figure 16 and Figure 17As illustrated, one method includes measuring a current measurement signal PGAout 41 via a low-side switch Q2 coupled between a switching node SW and a low-side reference node PGND, wherein the low-side switch includes a low-side control terminal configured to receive a low-side control signal and a current flow path through the low-side switch between the switching node and the low-side reference node, the low-side switch being configured to be turned on in response to the low-side control signal having the first logic value during a second time interval, wherein the current flow path through the low-side switch provides a current flow path between the switching node and the low-side reference node.

[0162] like Figure 16 and Figure 17 As illustrated, the method includes: coupling one input node of an additional programmable gain OTA amplifier circuit to the switching node and coupling another input node of the OTA circuit to the low-side reference node, measuring the voltage drop across the low-side switch; and applying the sensed voltage across a set of variable resistors configured to change the gain of the additional OTA circuit, thereby providing the current measurement signal as a result.

[0163] For example, the resistance of at least one of the group of variable resistors can be set by means of an error compensation digital code provided by an error compensation circuit.

[0164] like Figure 16 and Figure 17 The error compensation circuit illustrated herein includes: a non-volatile memory (NVM) circuit storing parameter values ​​of a low-side switch collected at multiple temperature and operating voltage values ​​during its system-in-package assembly and / or manufacturing; an operating voltage sensing circuit configured to sense the operating voltage at a control terminal of the low-side switch during a current measurement signal; a temperature sensing circuit configured to sense the operating temperature of the low-side switch during a current measurement signal; and a resistance calculation circuit configured to provide the error compensation digital code based on the stored low-side switch parameter values, the sensed operating voltage, and the sensed operating temperature.

[0165] like Figure 16 and Figure 17 As illustrated, the process parameters stored in the non-volatile memory include a set of on-conductance values ​​of the low-side switches collected by changing the operating temperature for a given operating voltage and changing the operating voltage at a given operating temperature.

[0166] like Figure 16 and Figure 17The resistance calculation circuit illustrated herein includes: a first linear interpolation circuit 4172 configured to perform linear interpolation on a set of conductance values ​​collected and stored in non-volatile memory at a given operating voltage, thereby providing a set of interpolation curves indicating the evolution of the conductance of the low-side switch with temperature as a result, the first linear interpolator circuit being further configured to extract a set of conductance values ​​at a sensed temperature signal from the set of interpolation curves; and a second linear interpolation circuit coupled to the first linear interpolator circuit to receive the extracted set of conductance values ​​therefrom, the second linear interpolation circuit being configured to perform linear interpolation on the extracted conductance values, thereby providing an interpolation curve indicating the evolution of the conductance of the low-side switch with operating voltage as a result, the second linear interpolator circuit being further configured to extract the conductance value at a sensed operating voltage from the interpolation curves.

[0167] like Figure 18 As illustrated herein, the current sensing circuits 40, 40', 40" according to this disclosure may be part of an integrated circuit 180 including a half-bridge arrangement of switches Q1, Q2, their drivers 220, 221, 222 and other circuit systems (known per se), such as a boot circuit system 1802, a control logic and protection circuit system 1804 and a thermal sensing circuit system 1806.

[0168] like Figure 19 As illustrated, multiple integrated circuits 180 (such as...) Figure 18 (As illustrated in the figure) can be coupled to a signal processing core (such as a microcontroller unit 190) and multiple corresponding inductive loads L.

[0169] like Figure 20 As illustrated, multiple controller units (CUs) 190 may be coupled to multiple power stages (such as switching converter devices SCDs) 180 according to the present disclosure, and may be embedded on one or more printed circuit boards (PCBs) 2000, which are coupled to a battery (B) 10 and equipped on a vehicle V (such as an autonomous vehicle or an electric vehicle).

[0170] like Figure 20 As illustrated, power stage 180 can be used to power loads 301 and 302, such as general purpose processing units or data storage units known in themselves.

[0171] In addition, it will be understood that the various individual implementation options illustrated throughout the accompanying drawings are not necessarily intended to be employed in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise mandatory) options individually and / or in combinations different from those illustrated in the drawings.

[0172] The claims are an integral part of the technical teachings provided herein with reference to the embodiments.

[0173] Details and embodiments may vary, even significantly, relative to what has been described by way of example only, without departing from the scope of protection, provided that the fundamental principles are not altered. The scope of protection is defined by the appended claims.

Claims

1. A method for current sensing in a DC-DC converter, wherein the DC-DC converter comprises: A high-side switch, which is coupled between a high-side reference node and a switch node; A low-side switch, which is coupled between a switch node and a low-side reference node; Wherein: the high-side switch includes a high-side control terminal configured to receive a high-side control signal and a current flow path between a high-side reference node and a switching node, the high-side switch being configured to be turned on in response to the high-side control signal having a first logic value during a first time interval, wherein the current flow path of the high-side switch provides a high-side current flow path between the high-side reference node and the switching node; and the low-side switch includes a low-side control terminal configured to receive a low-side control signal and a current flow path between the switching node and the low-side reference node, the low-side switch being configured to be turned on in response to the low-side control signal having the first logic value during a second time interval, wherein the current flow path of the low-side switch provides a current flow path between the switching node and the low-side reference node; and An inductor element, the inductor element being coupled to a switching node and an output node configured to be coupled to a load; The method includes: Sensing the switching voltage at the switching node; The sensed switching voltage is filtered using a filter circuit to provide a filtered voltage indicating the output voltage at the output node; and An output current signal is generated based on the difference between the filtered voltage and the sensed switching voltage. The output current signal indicates the intensity of the current flowing through the inductive load during an estimated time period equal to or greater than the first time interval.

2. The method of claim 1, wherein the filter circuit comprises a filter circuit having a cutoff frequency based on the expected inductance value of the inductor element.

3. The method according to claim 1, further comprising: A current measurement signal is received via a measurement circuit, the current measurement signal indicating the low-side current flowing through the current flow path through the low-side switch; as well as The difference between the filtered voltage and the sensed switching voltage is amplified by a transconductance amplifier with variable gain to generate an amplified and filtered current signal. The variable gain is based on a digital code set via a digital counter circuit.

4. The method of claim 3, further comprising setting the digital code via the digital counter circuit through the following step: The digital code of the digital counter is initiated as the initial digital code value; When the estimated time expires, the amplified and filtered current signal and the current measurement signal are compared. The digital code is incremented or decremented based on the comparison between the amplified and filtered current signal and the current measurement signal. as well as The variable gain of the transconductance amplification is changed based on the digital code incremented or decremented by the digital counter.

5. The method of claim 3, wherein the transconductance amplification has an offset current, and the method further comprises: Offset compensation current is generated via a programmable current generator circuit with programmable current intensity. as well as The offset compensation current is superimposed on the amplified and filtered current signal; The programmable current intensity of the offset programmable current generator circuit is based on a stored digital code set via a separate digital counter circuit.

6. The method of claim 5, wherein setting the additional digital code via the additional digital counter circuit comprises: Set the digital code of the other digital counter to an initial digital code value equal to zero; Immediately before the start of the estimation time interval, the amplified and filtered current signal and the current measurement signal are compared; As a result of comparing the amplified and filtered current signal with the current measurement signal, the additional digital code is decremented or incremented. as well as The programmable strength of the offset compensation current generator circuit is changed based on the additional digital code incremented or decremented via the additional digital counter.

7. The method according to claim 3, comprising: During the estimated time interval, the output of the transconductance amplifier is buffered to provide the output current signal to the user circuit; as well as During the remaining time, the output of the measurement circuit is buffered to provide the output current signal to the user circuit.

8. The method according to claim 3, wherein the current measurement signal comprises: Perform a transconductance amplification with variable gain on the difference between the voltage at the switching node and the voltage at the low-side reference node to sense the voltage drop across the low-side switch; The sensed voltage drop is applied to a set of variable resistors configured to change the variable gain of transconductance amplification to generate the current measurement signal; The resistance of at least one of the group of variable resistor elements is set using an error compensation digital code provided via an error compensation process; The error compensation process includes: The parameter values ​​of the low-side switch, collected at multiple temperature and operating voltage values ​​during the manufacturing process of the low-side switch, are stored in the non-volatile memory circuit. The operating voltage at the control terminal of the low-side switch is sensed during the measurement of the current measurement signal; The operating temperature of the low-side switch is sensed during the measurement of the current measurement signal; and The error compensation digital code is calculated based on the stored low-side switch parameter values, the sensed operating voltage, and the sensed operating temperature.

9. The method according to claim 8, wherein: The parameter values ​​stored in the non-volatile memory include the on-conductance values ​​of the low-side switch collected by changing the operating temperature for a given operating voltage and by changing the operating voltage at a given operating temperature. Calculating the error compensation digital code includes: Perform a first linear interpolation on the set of on-conductance values ​​collected and stored in the non-volatile memory at a given operating voltage to generate a set of interpolation curves indicating the evolution of the on-conductance of the low-side switch as a function of temperature. Extract a set of conductance values ​​at the sensed temperature signal from the set of interpolation curves; A second linear interpolation is performed on the extracted set of conductance values ​​to generate an interpolation curve indicating the evolution of the conductance of the low-side switch as a function of the operating voltage. The conductance at the sensed operating voltage is extracted from the interpolation curve.

10. A circuit comprising: A high-side switch, the high-side switch including a high-side control terminal configured to receive a high-side control signal and a current flow path between a high-side reference node and a switch node, the high-side switch being configured to be turned on in response to the high-side control signal having a first logic value during a first time interval, wherein a high-side current flow path between the high-side reference node and the switch node is provided through the current flow path of the high-side switch. A low-side switch, the low-side switch including a low-side control terminal configured to receive a low-side control signal and a current flow path between a switch node and a low-side reference node, the low-side switch being configured to be turned on in response to the low-side control signal having a first logic value during a second time interval, wherein the current flow path through the low-side switch provides a current flow path between the switch node and the low-side reference node. An inductor element, the inductor element being coupled to a switching node and an output node configured to be coupled to a load; A filter circuit coupled to the switching node to sense a switching voltage from the switching node, the filter circuit being configured to provide a filtered voltage based on the sensed switching voltage, the filtered voltage indicating the output voltage at the output node; as well as A signal processing circuit system coupled to a filter circuit is configured to provide an output current signal to a user circuit system based on the difference between the filtered voltage and the sensed switching voltage, indicating the strength of the current passing through the inductive load during an estimated time period equal to or greater than the first time interval.

11. A switching converter device, comprising: The circuit according to claim 10; A battery configured to provide a voltage supply level to the reference node, or a ground node configured to provide a ground voltage level to the reference node; as well as A control circuit system configured to provide the control signal.

12. An electronic control unit, comprising: At least one switching converter device according to claim 11; A microcontroller coupled to the at least one switching converter device or the at least one circuit, and configured to provide the control signal to the at least one switching converter device or the at least one circuit; as well as At least one load, the at least one load being configured to be coupled to the circuit to receive a regulated output voltage from the circuit.

13. The electronic control unit of claim 12, wherein the electronic control unit is mounted on a vehicle.

14. A method for measuring current through a low-side switch coupled between a switching node and a low-side reference node, wherein the low-side switch includes a low-side control terminal configured to receive a low-side control signal and a current flow path between the switching node and the low-side reference node, the low-side switch being configured to be turned on in response to the low-side control signal having a first logic value during a second time interval, wherein a current flow path between the switching node and the low-side reference node is provided through the current flow path of the low-side switch, the method comprising: The voltage drop across the low-side switch is measured by coupling one input node of the programmable gain amplifier circuit to the switching node and the other input node of the programmable gain amplifier circuit to the low-side reference node. A current measurement signal is generated by applying a set of variable resistive elements configured to change the gain of a programmable gain amplifier circuit, across which the measured voltage drop is applied. The resistance of at least one of the group of variable resistor elements is set via an error compensation digital code generated by the error compensation process; The error compensation process includes: The parameter values ​​of the low-side switch, collected at multiple temperatures and operating voltage values ​​during the manufacturing process, are stored in a non-volatile memory circuit. The operating voltage at the control terminal of the low-side switch is sensed during the measurement of the current measurement signal; The operating temperature of the low-side switch is sensed during the measurement of the current measurement signal, and The resistance is calculated based on the stored low-side switch parameter values, the sensed operating voltage, and the sensed operating temperature to provide the error compensation digital code.

15. The method of claim 14, wherein: The conductance of the low-side switch is collected as parameter values ​​stored in the non-volatile memory by changing the operating temperature for a given operating voltage and by changing the operating voltage at a given operating temperature. as well as Calculating resistance includes: A first linear interpolation is performed on the set of on-conductance values ​​collected and stored in non-volatile memory at a given operating voltage to generate a set of interpolation curves indicating the evolution of the on-conductance of the low-side switch as a function of temperature. Extract a set of conductance values ​​at the sensed temperature signal from the set of interpolation curves; A second linear interpolation is performed on the extracted on-conductance value to generate an interpolation curve indicating the evolution of the on-conductance of the low-side switch as a function of the operating voltage; and The conductance at the sensed operating voltage is extracted from the interpolation curve.

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