Adjustable gate voltage drive circuit and device

Abstract

This application provides a drive circuit and device for adjustable gate voltage, relating to the field of semiconductor testing technology. The circuit includes: a driver chip, a constant voltage power supply, a subsequent drive circuit, a positive voltage adjustable power supply, and a negative voltage adjustable power supply. The subsequent drive circuit receives the drive signal output from the driver chip through its control terminal and outputs an adjustable gate voltage to the device under test (DUT) under the influence of the drive signal. The subsequent drive circuit is powered by both the independently adjustable positive voltage power supply and the negative voltage adjustable power supply. This application utilizes three voltage sources to supply power to the driver chip and the subsequent drive circuit respectively. Under the influence of the drive signal, the subsequent drive circuit outputs an adjustable gate voltage to the DUT, achieving independent positive and negative gate voltage adjustment for the DUT. This solves the problem of limited gate voltage provided to the DUT in existing drive schemes, making it difficult to meet the requirements of high-pressure stress testing.

Description

Technical Field

[0001] This application relates to the field of power device testing technology, and more specifically, to a drive circuit and device with adjustable gate voltage. Background Technology

[0002] In reliability testing of semiconductor devices such as silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) and gallium nitride metal-oxide-semiconductor field-effect transistors (GaN MOSFETs), dynamic high-voltage stress is often applied to the device under test (DUT) to evaluate its long-term stability under extreme conditions such as high temperature, high voltage, and high frequency. Among these parameters, the gate voltage (VGS) is one of the key parameters affecting the stability and lifespan of the DUT, and it is generally provided by the gate drive circuit.

[0003] Currently, driver chips are commonly used as gate drive circuits. Driver chips as gate drive circuits have the following characteristics: the operating voltage of the driver chip is the upper limit of the gate voltage, and the positive and negative voltage adjustment ranges are limited and cannot be adjusted independently. This characteristic means that the gate voltage output by the driver chip cannot meet the requirements of high-pressure stress testing. Summary of the Invention

[0004] The purpose of this application is to provide an adjustable gate voltage drive circuit and device to address the shortcomings of the prior art, thereby solving the technical problems existing in the prior art.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide a driving circuit with an adjustable gate voltage, the driving circuit with an adjustable gate voltage including: a driving chip, a constant voltage power supply, a subsequent driving circuit, a positive voltage adjustable power supply and a negative voltage adjustable power supply;

[0007] The power supply terminal of the driver chip is connected to the constant voltage power supply, which is used to provide constant voltage to the driver chip.

[0008] The output terminal of the driver chip is connected to the control terminal of the subsequent driver circuit. The positive terminal of the driver power supply of the subsequent driver circuit is connected to the positive terminal of the positive voltage adjustable power supply. The negative terminal of the driver power supply of the subsequent driver circuit is connected to the negative terminal of the negative voltage adjustable power supply. The output terminal of the subsequent driver circuit is connected to the first terminal of the device under test. The second terminal of the device under test, the negative terminal of the positive voltage adjustable power supply, and the positive terminal of the negative voltage adjustable power supply are sequentially connected to the midpoint of the driver power supply.

[0009] The subsequent driving circuit is used to receive the driving signal output by the driving chip through the control terminal of the subsequent driving circuit, and output an adjustable gate voltage to the device under test under the action of the driving signal. The power supply of the subsequent driving circuit is the positive voltage adjustable power supply and the negative voltage adjustable power supply. The positive voltage adjustable power supply provides an adjustable positive voltage, and the negative voltage adjustable power supply provides an adjustable negative voltage.

[0010] Optionally, the third terminal of the device under test is connected to the detection terminal of the driver chip, and the third terminal of the device under test is also connected to an external test interface.

[0011] The driving chip detects the current signal flowing through the third terminal of the device under test through the detection terminal, and outputs the driving signal according to the detection result.

[0012] Optionally, the subsequent drive circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0013] The first terminal of the first transistor is used to receive the drive signal, and the second terminal of the first transistor, the second terminal of the second transistor, and the third terminal of the fourth transistor are connected to the negative terminal of the drive power supply in sequence.

[0014] The third terminal of the first transistor, the first terminal of the second transistor, the third terminal of the second transistor, the first terminal of the third transistor, the second terminal of the third transistor, the third terminal of the third transistor, the first terminal of the fourth transistor, the second terminal of the fourth transistor, and the first terminal of the device under test are sequentially connected to the positive terminal of the driving power supply.

[0015] Optionally, the subsequent driving circuit further includes: a first resistor, a second resistor, and a third resistor;

[0016] One end of the first resistor is connected to the third end of the first transistor and the first end of the second transistor, respectively;

[0017] The other end of the first resistor and one end of the second resistor are connected in sequence to the positive terminal of the driving power supply. The other end of the second resistor is connected to the third terminal of the second transistor, one end of the third resistor, the first terminal of the third transistor, and the first terminal of the fourth transistor, respectively.

[0018] The other end of the third resistor is connected to the second end of the third transistor, the second end of the fourth transistor, and the first end of the device under test.

[0019] Optionally, the step of outputting an adjustable gate voltage to the device under test under the action of the driving signal includes:

[0020] If the driving signal is a constant voltage signal, then under the action of the constant voltage signal, the first transistor and the third transistor are both in the conducting state, and the second transistor and the fourth transistor are both in the cut-off state, so that the positive voltage adjustable power supply is connected to the device under test, so that the positive voltage adjustable power supply provides an adjustable positive voltage to the device under test, and the adjustable positive voltage provided by the positive voltage adjustable power supply is output to the third terminal of the device under test through the third terminal and the second terminal of the third transistor, so that the device under test outputs a first adjustable gate voltage.

[0021] Optionally, the step of outputting an adjustable gate voltage to the device under test under the action of the driving signal includes:

[0022] If the driving signal is a zero-voltage signal, then under the action of the zero-voltage signal, the first transistor and the third transistor are both in the off state, and the second transistor and the fourth transistor are both in the on state, so that the negative voltage adjustable power supply is connected to the device under test, so that the negative voltage adjustable power supply provides an adjustable negative voltage to the device under test, and the adjustable negative voltage provided by the negative voltage adjustable power supply is output to the second terminal of the device under test through the third terminal and the second terminal of the fourth transistor, so that the device under test outputs a second adjustable gate voltage.

[0023] Optionally, the adjustable range of the positive voltage adjustable power supply is [0, 60V], and the adjustable range of the negative voltage adjustable power supply is [-60V, 0V].

[0024] Optionally, the driving circuit for the adjustable gate voltage further includes a fourth resistor and a fifth resistor;

[0025] One end of the fourth resistor is connected to the first output terminal of the driver chip, the other end of the fourth resistor is connected to the other end of the fifth resistor and the first terminal of the first transistor, and one end of the fifth resistor is connected to the second output terminal of the driver chip.

[0026] Optionally, the driving circuit for the adjustable gate voltage further includes: a high-voltage diode, a sampling resistor, and a filter capacitor;

[0027] The reverse terminal of the high-voltage diode is connected to the third terminal of the device under test, and the forward terminal of the high-voltage diode is connected to one end of the sampling resistor.

[0028] The other end of the sampling resistor is connected to the detection terminal of the driver chip and one end of the filter capacitor, respectively.

[0029] The other end of the filter capacitor is connected to the negative terminal of the drive power supply.

[0030] Secondly, embodiments of this application also provide a driving device for adjustable gate voltage, including the driving circuit for adjustable gate voltage described in the first aspect.

[0031] The beneficial effects of this application are:

[0032] This application provides a drive circuit and device for adjustable gate voltage. The circuit includes: a driver chip, a constant voltage power supply, a subsequent drive circuit, a positive voltage adjustable power supply, and a negative voltage adjustable power supply. Specifically, it utilizes three voltage sources to supply power to the driver chip and the subsequent drive circuit. The driver chip is powered by the constant voltage power supply, while the subsequent drive circuit is powered by two sets of positive and negative voltage adjustable power supplies. Under the action of a drive signal, the subsequent drive circuit outputs an adjustable gate voltage to the device under test (DUT), thus realizing the gate voltage (V) of the DUT. GS The function of independent positive and negative adjustment means that the gate positive and negative voltage of the device under test can be adjusted independently over a wide range, thereby observing the permanent drift of the gate and drain parameters of the device under test under different extreme stress conditions. This meets the reliability testing requirements of the device under test, improves the accuracy of the test results, and solves the problem that the existing driving scheme has limited gate voltage provided to the device under test and cannot independently adjust the positive and negative voltage, making it difficult to meet the high-pressure stress testing requirements. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A schematic diagram of a drive circuit with adjustable gate voltage provided in an embodiment of this application;

[0035] Figure 2A schematic diagram of another adjustable gate voltage driving circuit provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram of the structure of the subsequent driving circuit in an adjustable gate voltage driving circuit provided in an embodiment of this application;

[0037] Figure 4 A schematic diagram of the peripheral circuit of the driver chip in a driver circuit with adjustable gate voltage provided in an embodiment of this application;

[0038] Figure 5 This is a schematic diagram of a drive device with adjustable gate voltage provided in an embodiment of this application.

[0039] Icons: 100 - Driving circuit with adjustable gate voltage; 1 - Driver chip; 2 - Constant voltage power supply; 3 - Subsequent driving circuit; 4 - Positive voltage adjustable power supply; 5 - Negative voltage adjustable power supply; 200 - Driving device with adjustable gate voltage. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0041] First, the technical terms used in this application will be explained.

[0042] 1. Gate voltage: In a field-effect transistor (FET) or insulated-gate bipolar transistor (IGBT), the voltage applied between the gate and the source (or emitter) is the core control signal for controlling the device to turn on and off.

[0043] Secondly, a brief explanation of the technical problem to be solved in this application will be given.

[0044] Typically, an integrated driver chip is used as the gate drive circuit for the device under test. For example, the maximum operating voltage of an existing driver chip is 42V, with a positive voltage range of 20V~32V and a negative voltage range of 5V~10V. That is, the maximum operating voltage of the driver chip is the upper limit of the gate voltage of the device under test, and the adjustment range of the positive and negative voltages is limited.

[0045] However, it is usually necessary to apply greater voltage stress to the gate of the device under test, and the positive and negative voltages must be independently adjustable. For example, in the Dynamic High Temperature Reverse Bias (DHTRB) test requirements, many users require that the gate positive and negative voltages of the device under test be independently adjustable within a range of ±60V. This voltage range makes it impossible to use almost all driver chips. Circuits designed with discrete components have problems such as complex structure, numerous components, and low reliability.

[0046] To address the aforementioned problems, this application proposes a drive circuit with adjustable gate voltage. This circuit includes a driver chip, a constant voltage power supply, a subsequent drive circuit, a positive voltage adjustable power supply, and a negative voltage adjustable power supply. Specifically, it utilizes three voltage sources to supply power to the driver chip and the subsequent drive circuit. The driver chip is powered by a constant voltage power supply, while the subsequent drive circuit is powered by two sets of positive and negative voltage adjustable power supplies. This achieves the goal of independently adjusting the positive and negative gate drive voltage of the device under test (DUT), ensuring that the gate voltage of the DUT is not limited by the operating voltage of the driver chip and can be freely adjusted according to the user's testing needs, thus meeting the testing requirements of semiconductors.

[0047] The following will describe the specific implementation steps and beneficial effects of the adjustable gate voltage driving circuit provided in this application through several specific embodiments.

[0048] Optionally, refer to Figure 1 As shown, the adjustable gate voltage drive circuit 100 includes: a drive chip 1, a constant voltage power supply 2, a subsequent drive circuit 3, a positive voltage adjustable power supply 4, and a negative voltage adjustable power supply 5.

[0049] Among them, the driver chip 1 can be any existing chip, such as NSI66x1A series Gate Driver, Gate Driver SQ55837 or Gate Driver 1EBN1001AE, and the constant voltage power supply 2 can provide a constant operating voltage, such as 20V, to the driver chip.

[0050] The positive voltage signal provided by the positive adjustable power supply 4 can be adjusted independently. For example, the adjustment range of the positive adjustable power supply is 0V to 50V, meaning that the voltage signal currently provided by the positive adjustable power supply can be adjusted to any voltage value between 0V and 50V. Similarly, the adjustment range of the negative voltage signal provided by the negative adjustable power supply 5 is -50V to 0V, meaning that the negative voltage signal currently provided by the negative adjustable power supply 5 can be adjusted to any voltage value between -50V and 0V.

[0051] Continue to refer to Figure 1As shown, the power supply terminal of the driver chip 1 is connected to the constant voltage power supply 2. The constant voltage power supply 2 is used to provide constant voltage to the driver chip 1, that is, the driver chip 1 can be powered by the constant voltage power supply 2 alone.

[0052] The output terminal of the driver chip 1 is connected to the control terminal of the subsequent driver circuit 3. The positive terminal of the driver power supply of the subsequent driver circuit 3 is connected to the positive terminal of the positive voltage adjustable power supply 4. The negative terminal of the driver power supply of the subsequent driver circuit 3 is connected to the negative terminal of the negative voltage adjustable power supply 5. The output terminal of the subsequent driver circuit 3 is connected to the first terminal of the device under test. The second terminal of the device under test, the negative terminal of the positive voltage adjustable power supply 4, and the positive terminal of the negative voltage adjustable power supply 5 are connected to the midpoint of the driver power supply in sequence.

[0053] For example, the device under test can be a field-effect transistor (FET), with the first terminal of the FET being the gate, the second terminal being the source, and the third terminal being the drain.

[0054] The post-stage drive circuit 3 is used to receive the drive signal output by the drive chip 1 through the control terminal of the post-stage drive circuit 3, and output an adjustable gate voltage to the device under test under the action of the drive signal. The power supply of the post-stage drive circuit 3 is a positive voltage adjustable power supply 4 and a negative voltage adjustable power supply 5. That is, the positive voltage adjustable power supply 4 and the negative voltage adjustable power supply 5, which are independently adjustable, are jointly powered by the post-stage drive circuit 3. The positive voltage adjustable power supply 4 provides an adjustable positive voltage, and the negative voltage adjustable power supply 5 provides an adjustable negative voltage.

[0055] The drive signal is generated by the drive chip and output to the subsequent drive circuit via the output terminal of the drive chip. The drive signal can be the working voltage of the drive chip, 20V, or 0V.

[0056] It should be noted that, for example, the adjustable positive voltage provided by the positive voltage adjustable power supply 4 is currently 45V, and the adjustable negative voltage provided by the negative voltage adjustable power supply 5 is currently -45V. The power supply for the subsequent drive circuit is the positive voltage adjustable power supply 4 and the negative voltage adjustable power supply 5. When the control terminal of the subsequent drive circuit 3 receives a drive signal of 20V from the drive chip 1, the positive voltage adjustable power supply 4 is turned on with the device under test, and the adjustable gate voltage output to the device under test is the adjustable positive voltage of 45V provided by the positive voltage adjustable power supply 4. When the control terminal of the subsequent drive circuit 3 receives a drive signal of 0V from the drive chip 1, the negative voltage adjustable power supply 5 is turned on with the device under test, and the adjustable gate voltage output to the device under test is the adjustable positive voltage of -45V provided by the negative voltage adjustable power supply 5. In this way, the gate voltage of the device under test is adjustable.

[0057] In this embodiment, a fixed input signal PWM_IN is connected to the signal input terminal of the driver chip. The input signal PWM_IN is processed to generate a drive signal PWM_OUT, such as 20V or 0V. The drive signal PWM_OUT is then output to the control terminal of the subsequent drive circuit. The gate of the device under test (DUT) is connected to the output terminal of the subsequent drive circuit, and the source of the DUT is connected to the midpoint of the drive power supply. In this way, under the action of the drive signal PWM_OUT, the subsequent drive circuit outputs an adjustable voltage signal between the gate (G) and source (S) of the DUT, thereby achieving the gate voltage (V) of the DUT. GS The function of independent positive and negative adjustment means that the positive and negative gate voltage of the device under test can be adjusted independently over a wide range, thereby observing the permanent drift of the gate and drain parameters of the device under test under different extreme stress conditions, which meets the reliability testing requirements of the device under test and improves the accuracy of the test results.

[0058] In summary, this application provides a driving circuit for an adjustable gate voltage. The circuit includes a driver chip, a constant voltage power supply, a subsequent driving circuit, a positive adjustable power supply, and a negative adjustable power supply. Specifically, it utilizes three voltage sources to supply power to the driver chip and the subsequent driving circuit. The driver chip is powered by a constant voltage power supply, while the subsequent driving circuit is powered by two sets of positive and negative adjustable power supplies. Under the influence of a driving signal, the subsequent driving circuit outputs an adjustable gate voltage to the device under test (DUT), thus realizing the gate voltage (Vg) of the DUT. GS The function of independent positive and negative adjustment means that the gate positive and negative voltage of the device under test can be adjusted independently over a wide range, thereby observing the permanent drift of the gate and drain parameters of the device under test under different extreme stress conditions. This meets the reliability testing requirements of the device under test, improves the accuracy of the test results, and solves the problem that the existing driving scheme has limited gate voltage provided to the device under test and cannot independently adjust the positive and negative voltage, making it difficult to meet the high-pressure stress testing requirements.

[0059] Optionally, refer to Figure 2 As shown, the third terminal of the device under test is connected to the detection terminal of the driver chip, and the third terminal of the device under test is also connected to an external test interface.

[0060] The driver chip detects the current signal flowing through the third terminal of the device under test through the detection terminal, and outputs a drive signal based on the detection result.

[0061] For example, the external test interface can be an interface of a reliability testing device. The reliability testing device can output a high voltage stress signal (High Voltage Input, or HV_IN) through its own external test interface and apply the high voltage stress signal HV_IN between the drain and source of the device under test (such as a SiC MOSFET). This can test the long-term stability and parameter drift characteristics of the device under test under various extreme conditions (such as high temperature, high voltage, and high frequency switching).

[0062] In one feasible approach, to achieve overcurrent protection for the device under test (DUT) during testing, the third terminal of the DUT can be connected to the detection terminal of the driver chip, and the third terminal of the DUT is also connected to a high-voltage stress signal HV_IN. During the testing of the DUT, the detection terminal of the driver chip detects the current signal flowing through the DUT in real time and outputs a drive signal based on the current detection result. If the current detection result indicates that the DUT has experienced an overcurrent or short-circuit fault during operation (such as a short circuit in the load inductance), the subsequent drive circuit immediately shuts off the gate voltage (i.e., V) of the DUT under the action of the drive signal. GS = 0 or negative pressure), which triggers the protection mechanism to prevent the device under test from being damaged due to abnormal operating conditions during high voltage and high current stress testing.

[0063] Optionally, refer to Figure 3 As shown, the subsequent drive circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.

[0064] in, Figure 3 The positive voltage adjustable power supply is P2, the negative voltage adjustable power supply is P3, and the device under test is Q5.

[0065] The first terminal of the first transistor Q1 is used to receive the drive signal, and the second terminal of the first transistor Q1, the second terminal of the second transistor Q2, and the third terminal of the fourth transistor Q4 are connected to the negative terminal of the drive power supply in sequence.

[0066] The third terminal of the first transistor Q1, the first terminal of the second transistor Q2, the third terminal of the second transistor Q2, the first terminal of the third transistor Q3, the second terminal of the third transistor Q3, the third terminal of the third transistor Q3, the first terminal of the fourth transistor Q4, the second terminal of the fourth transistor Q4, and the first terminal of the device under test are sequentially connected to the positive terminal of the drive power supply.

[0067] In this embodiment, four transistors in the subsequent drive circuit can be used to form a non-inverting amplifier structure. This ensures that the gate voltage output to the device under test is in phase with the drive signal PWM_OUT provided by the drive chip, thereby ensuring that the waveform of the gate voltage applied to the device under test is consistent with the timing of the drive signal PWM_OUT output by the drive chip. This achieves precise control, avoids malfunctions, and improves system stability and safety.

[0068] Optionally, continue to refer to Figure 3 As shown, the subsequent drive circuit also includes: a first resistor R4, a second resistor R5, and a third resistor R6.

[0069] One end of the first resistor R4 is connected to the third end of the first transistor Q1 and the first end of the second transistor Q2, respectively;

[0070] The other end of the first resistor R4 and one end of the second resistor R5 are connected to the positive terminal of the drive power supply in sequence. The other end of the second resistor R5 is connected to the third terminal of the second transistor Q2, one end of the third resistor R6, the first terminal of the third transistor Q3, and the first terminal of the fourth transistor Q4, respectively.

[0071] The other end of the third resistor R6 is connected to the second end of the third transistor Q3, the second end of the fourth transistor Q4, and the first end of the device under test.

[0072] In this embodiment, after receiving the drive signal, the first transistor Q1 in the subsequent drive circuit drives the on / off states of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 under the action of the drive signal, so that the positive voltage adjustable power supply (or the negative voltage adjustable power supply) is turned on with the device under test, so that the adjustable gate voltage can be output to the device under test to meet the requirements of high-voltage stress testing of the device under test.

[0073] Optionally, continue to refer to Figure 3 As shown, an adjustable gate voltage is output to the device under test under the action of a drive signal, including:

[0074] If the driving signal is a constant voltage signal, then under the action of the constant voltage signal, the first and third transistors are both in the conducting state, while the second and fourth transistors are both in the cut-off state, so that the positive voltage adjustable power supply and the device under test are connected, so that the positive voltage adjustable power supply provides an adjustable positive voltage to the device under test, and the adjustable positive voltage provided by the positive voltage adjustable power supply is output to the third terminal of the device under test through the third terminal and the second terminal of the third transistor, so that the device under test outputs the first adjustable gate voltage.

[0075] In one feasible approach, during operation, the voltage value currently provided by the positive voltage adjustable power supply +VG_ADJ is first adjusted to the target positive voltage value required for the test, according to the high-pressure stress test requirements. When the drive signal PWM_OUT output by the driver chip is a constant voltage signal of 20V, the constant voltage signal of 20V is transmitted to the gate G of the first transistor Q1, that is, the voltage between the gate and source of the first transistor Q1 is 20V, driving the first transistor Q1 to turn on, the second transistor Q2 to turn off, the third transistor Q3 to turn on, and the fourth transistor Q4 to turn off. The first adjustable gate voltage, V, is then output to the device under test through the third terminal and the second terminal of the third transistor Q3. GS It equals the adjustable positive voltage provided by the positive voltage adjustable power supply + VG_ADJ.

[0076] Optionally, an adjustable gate voltage is output to the device under test under the action of a drive signal, including:

[0077] If the drive signal is a zero-voltage signal, then under the action of the zero-voltage signal, the first and third transistors are both in the off state, and the second and fourth transistors are both in the on state, so that the negative voltage adjustable power supply and the device under test are connected, so that the negative voltage adjustable power supply provides an adjustable negative voltage to the device under test, and the adjustable negative voltage provided by the negative voltage adjustable power supply is output to the second terminal of the device under test through the third terminal and the second terminal of the fourth transistor, so that the device under test outputs the second adjustable gate voltage.

[0078] In another feasible approach, during operation, the voltage value currently provided by the negative voltage adjustable power supply -VG_ADJ is first adjusted to the target negative voltage value required for the test, according to the high-pressure stress test requirements. When the drive signal PWM_OUT output by the driver chip is a zero voltage signal 0V, the zero voltage signal 0V is transmitted to the gate G of the first transistor Q1, that is, the voltage between the gate and source of the first transistor Q1 is 0V. This drives the first transistor Q1 to turn off, the second transistor Q2 to turn on, the third transistor Q3 to turn off, and the fourth transistor Q4 to turn on. The second adjustable gate voltage, V, is then output to the device under test through the third terminal and the second terminal of the fourth transistor Q4. GS This is equivalent to the adjustable negative voltage provided by the adjustable negative voltage power supply -VG_ADJ.

[0079] Optionally, the adjustable range of the positive voltage adjustable power supply is [0, 60V], and the adjustable range of the negative voltage adjustable power supply is [-60V, 0V].

[0080] In this embodiment, in order to meet the goal of independently adjusting the positive and negative gate voltages of the device under test within a range of ±60V, it is proposed that the adjustable range of the positive voltage adjustable power supply be set to [0, 60V] and the adjustable range of the negative voltage adjustable power supply be set to [-60V, 0V], thus solving the problem of not being able to independently adjust the positive and negative gate voltages of the device under test over a large range.

[0081] Optionally, refer to Figure 4 As shown, the adjustable gate voltage drive circuit also includes: a high-voltage diode D1, a sampling resistor R3, and a filter capacitor C1.

[0082] The reverse terminal of the high-voltage diode D1 is connected to the third terminal of the device under test, and the forward terminal of the high-voltage diode D1 is connected to one end of the sampling resistor R3.

[0083] The other end of the sampling resistor R3 is connected to the detection terminal (i.e., VCE pin) of the driver chip U1 and one end of the filter capacitor C1, respectively.

[0084] The other end of the filter capacitor C1 is connected to the negative terminal of the drive power supply.

[0085] It should be noted that during the conduction period of the device under test, the drain voltage V of the device under test... DS When the voltage is low (e.g., below a few volts), if an overcurrent or short circuit occurs, the drain voltage V DS It will increase significantly (e.g., exceeding 10V), at which point it enters the "desaturation" state (DESAT).

[0086] In this embodiment, to achieve overcurrent protection for the device under test (DUT), a method is proposed to detect the current signal flowing through the DUT in real time using a high-voltage diode D1 and transmit the current signal to a sampling resistor R3. An RC filter network composed of the sampling resistor R3 and the filter capacitor C1 filters the detected current signal to prevent false triggering by transient interference. The filtered current signal is then transmitted to the detection terminal (VCE pin) of the driver chip U1. The driver chip U1 compares the filtered current signal with a preset current threshold. If the filtered current signal exceeds the current threshold, it is determined that the DUT has an overcurrent or short circuit. At this time, the driver chip U1 outputs a drive signal of 0V. Under the action of the 0V drive signal, the subsequent drive circuit immediately shuts off the gate voltage (Vgate) of the DUT. GS (The voltage is 0 or negative) to achieve overcurrent protection for the device under test.

[0087] Optionally, continue to refer to Figure 4 As shown, the drive circuit for the adjustable gate voltage also includes: a fourth resistor R1 and a fifth resistor R2;

[0088] One end of the fourth resistor R1 is connected to the first output terminal (i.e., CHP1 pin and CHP2 pin) of the driver chip U1. The other end of the fourth resistor R1 is connected to the other end of the fifth resistor R2 and the first terminal of the first transistor Q1. One end of the fifth resistor R2 is connected to the second output terminal (i.e., GLP1 pin and GLP2 pin) of the driver chip U1.

[0089] In this embodiment, the stability, anti-interference capability, and safety of the drive signal output by the drive chip can be ensured by using two resistors set around the drive chip U1.

[0090] Optionally, refer to Figure 5 As shown, this application also provides a drive device with adjustable gate voltage. The drive device 200 with adjustable gate voltage includes the drive circuit 100 with adjustable gate voltage provided in the above embodiments.

[0091] In this embodiment, the adjustable gate voltage driving circuit provided in the above embodiment can be integrated into the adjustable gate voltage driving device 200. The adjustable gate voltage driving device 200 outputs an adjustable gate voltage to the device under test, so that the gate voltage of the device under test is not limited by the driving chip and can be adjusted at will according to the test requirements, thus meeting the testing requirements of semiconductors.

[0092] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A gate voltage adjustable driving circuit, characterized by, The drive circuit of the adjustable gate voltage comprises a drive chip, a constant voltage power supply, a post-stage drive circuit, a positive voltage adjustable power supply and a negative voltage adjustable power supply; The power supply end of the drive chip is connected with the constant voltage power supply, and the constant voltage power supply is used for providing constant voltage to the drive chip; The output end of the drive chip is connected with the control end of the post-stage drive circuit, the positive electrode end of the drive power supply of the post-stage drive circuit is connected with the positive electrode end of the positive voltage adjustable power supply, the negative electrode end of the drive power supply of the post-stage drive circuit is connected with the negative electrode end of the negative voltage adjustable power supply, and the output end of the post-stage drive circuit is connected with the first end of the measured device; the second end of the measured device, the negative electrode end of the positive voltage adjustable power supply and the positive electrode end of the negative voltage adjustable power supply are sequentially connected with the midpoint of the drive power supply; The post-stage drive circuit is used for receiving the drive signal output by the drive chip through the control end of the post-stage drive circuit, and outputting the adjustable gate voltage to the measured device under the action of the drive signal, wherein the power supply of the post-stage drive circuit is the positive voltage adjustable power supply and the negative voltage adjustable power supply, the positive voltage adjustable power supply provides adjustable positive voltage, and the negative voltage adjustable power supply provides adjustable negative voltage; The post-stage drive circuit comprises a first triode, a second triode, a third triode and a fourth triode; The first end of the first triode is used for inputting the drive signal, the second end of the first triode, the second end of the second triode and the third end of the fourth triode are sequentially connected with the negative electrode end of the drive power supply; The third end of the first triode, the first end of the second triode, the third end of the second triode, the first end of the third triode, the second end of the third triode, the third end of the third triode, the first end of the fourth triode, the second end of the fourth triode and the first end of the measured device are sequentially connected with the positive electrode end of the drive power supply.

2. The adjustable gate voltage drive circuit of claim 1, wherein, The third end of the measured device is connected with the detection end of the drive chip, and the third end of the measured device is also connected to an external test interface; The drive chip detects the current signal flowing through the third end of the measured device through the detection end, and outputs the drive signal according to the detection result.

3. The adjustable gate voltage drive circuit of claim 1, wherein, The post-stage drive circuit further comprises a first resistor, a second resistor and a third resistor; One end of the first resistor is connected with the third end of the first triode and the first end of the second triode respectively; The other end of the first resistor and one end of the second resistor are sequentially connected with the positive electrode end of the drive power supply, and the other end of the second resistor is connected with the third end of the second triode, one end of the third resistor, the first end of the third triode and the first end of the fourth triode respectively; The other end of the third resistor is connected with the second end of the third triode, the second end of the fourth triode and the first end of the measured device respectively.

4. The adjustable gate voltage drive circuit of claim 3, wherein, The outputting of the adjustable gate voltage to the measured device under the action of the drive signal comprises: If the driving signal is a constant voltage signal, under the action of the constant voltage signal, the first transistor and the third transistor are both in a conducting state, and the second transistor and the fourth transistor are both in a cut-off state, so that the positive voltage adjustable power supply is connected with the measured device, the adjustable positive voltage provided by the positive voltage adjustable power supply is output to the third end of the measured device through the third end of the third transistor and the second end of the third transistor, and the measured device outputs a first adjustable gate voltage.

5. The adjustable gate voltage drive circuit of claim 3, wherein, The adjustable gate voltage output to the measured device under the action of the driving signal comprises: If the driving signal is a zero voltage signal, under the action of the zero voltage signal, the first transistor and the third transistor are both in a cut-off state, and the second transistor and the fourth transistor are both in a conducting state, so that the negative voltage adjustable power supply is connected with the measured device, the adjustable negative voltage provided by the negative voltage adjustable power supply is output to the second end of the measured device through the third end of the fourth transistor and the second end of the fourth transistor, and the measured device outputs a second adjustable gate voltage.

6. The adjustable gate voltage drive circuit of claim 1, wherein, The adjustable range of the positive voltage adjustable power supply is [0, 60V], and the adjustable range of the negative voltage adjustable power supply is [-60V, 0V].

7. The adjustable gate voltage drive circuit of claim 1, wherein, The adjustable gate voltage driving circuit further comprises a fourth resistor and a fifth resistor. One end of the fourth resistor is connected with the first output end of the driving chip, and the other end of the fourth resistor is respectively connected with the other end of the fifth resistor and the first end of the first transistor.

8. The adjustable gate voltage drive circuit of claim 2, wherein, The adjustable gate voltage driving circuit further comprises a high-voltage diode, a sampling resistor and a filter capacitor. The reverse end of the high-voltage diode is connected with the third end of the measured device, and the forward end of the high-voltage diode is connected with one end of the sampling resistor. The other end of the sampling resistor is respectively connected with the detection end of the driving chip and one end of the filter capacitor. The other end of the filter capacitor is connected with the negative electrode end of the driving power supply.

9. A driving apparatus of an adjustable gate voltage, characterized by comprising: The adjustable gate voltage driving circuit comprises any one of claims 1-8. The adjustable gate voltage driving circuit comprises any one of claims 1-8.

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