Inter-chip communication circuit and electronic device

Abstract

The application provides an inter-chip communication circuit and an electronic device. The inter-chip communication circuit comprises a first serial communication circuit and a second serial communication circuit arranged between a first chip and a second chip. An output end of a first comparator is connected to a first receiving end, and an inverting input end of the first comparator is connected between a first resistor and a second resistor. An output end of a second comparator is connected to a second receiving end, and an inverting input end of the second comparator is connected between a fifth resistor and a sixth resistor. A non-inverting input end of the first comparator is directly connected to a non-inverting input end of the second comparator, so that only one signal line for receiving and transmitting data is formed between the first chip and the second chip. The application avoids the problems of self-receiving and data transmission errors when multiplexing TX and RX through one signal line, and can adapt to a larger range of baud rates.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to an inter-chip communication circuit and an electronic device comprising the same. BACKGROUND

[0002] In serial communication, data is transmitted in sequence according to bits. Serial communication includes TX (transmit) and RX (receive) two signal ports, which can simultaneously realize full-duplex data transmission and data reception. Serial communication can transmit data between different devices (or chips). Full-duplex serial communication requires the use of two signal lines. In order to save the number of signal lines, single-wire half-duplex serial communication is used, and at this time the transmission and reception operations of TX data and RX data need to be multiplexed on one signal line.

[0003] CN216527161U discloses a single-wire serial communication circuit and a power-using device having the same, which discloses the use of a single signal transmission line between the first serial port module and the second serial port module. However, when the RXD ends of the first serial port module and the second serial port module are both high, the RXD ends of the first serial port module and the second serial port module are also high. When the TXD end of the second serial port module sends data and is low, the RXD ends of the first serial port module and the second serial port module will both receive the data sent by the TXD end of the second serial port module. Therefore, when the single signal line is multiplexed with TX and RX, the self-receiving problem still exists, and signal isolation cannot be performed on TX and RX. In addition, when the Baud Rate is high, the communication between the first serial port module and the second serial port module is abnormal, which cannot meet the minimum requirement of high level, resulting in data transmission errors. For surgical microscopes or other electronic devices, the data transmission distance formed by the serial communication between the sending end and the receiving end is not fixed, and the clock accuracy may not be uniform, and there are many technical problems such as poor compatibility and data bandwidth waste. At the same time, when multiplexing TX and RX with a single signal line, software filtering is required at the sending end or the receiving end, which causes additional resource consumption of the chip at the sending end or the receiving end, and makes the chip and its peripheral circuit design more complex, and increases the manufacturing cost.

[0004] Therefore, it is necessary to improve the serial communication in the prior art to solve the above problems. It should be noted that the above introduction to the background art is only for the convenience of clearly and completely describing the technical solutions of the present application, and for the convenience of understanding by those skilled in the art. The above technical solutions cannot be considered as known by those skilled in the art only because they are described in the background art part of the present application. SUMMARY

[0005] The chip-to-chip communication circuit and the electronic device are used to overcome and solve the above technical problems, avoid self-receiving and data transmission errors when multiplexing TX and RX through a signal line in serial communication, reduce the number of cables used between two devices based on serial communication, and adapt to different transmission speeds corresponding to a larger range of baud rates.

[0006] To achieve one of the above purposes, the chip-to-chip communication circuit is provided between a first chip and a second chip, the first chip is provided with a first sending end and a first receiving end, and the second chip is provided with a second sending end and a first receiving end.

[0007] Further comprising: a first serial communication circuit connected to the first chip and a second serial communication circuit connected to the second chip;

[0008] The first serial communication circuit comprises: a first voltage dropping device, a first comparator, the first sending end is connected in series with a first resistor and a second resistor and grounded, the inverting input end of the first comparator is connected between the first resistor and the second resistor, the output end of the first comparator is connected to the first receiving end, the non-inverting input end of the first comparator is connected to a first pull-up resistor connected to a power supply, and the first sending end and the non-inverting input end of the first comparator are connected in parallel with the first voltage dropping device.

[0009] The second serial communication circuit comprises: a second voltage dropping device, a second comparator, the second sending end is connected in series with a fifth resistor and a sixth resistor and grounded, the inverting input end of the second comparator is connected between the fifth resistor and the sixth resistor, the output end of the second comparator is connected to the second receiving end, the non-inverting input end of the second comparator is connected to a second pull-up resistor connected to a power supply, and the second sending end and the non-inverting input end of the second comparator are connected in parallel with the second voltage dropping device.

[0010] The non-inverting input end of the first comparator is directly connected to the non-inverting input end of the second comparator, so as to form only one signal line for receiving data and sending data between the first chip and the second chip.

[0011] As a further improvement of the present application, the first comparator and the second comparator are push-pull output type comparators, and the slew rate of the first comparator and the second comparator is 500-1000V / μs.

[0012] As a further improvement of the present application, the first voltage dropping device and the second voltage dropping device are both diodes, and the anode of the diode in the first serial communication circuit is connected to the anode of the diode in the second serial communication circuit.

[0013] As a further improvement of the application, the first voltage dropping device comprises a first NPN triode and a seventh resistor, and the second voltage dropping device comprises a second NPN triode and an eighth resistor.

[0014] In the first serial communication circuit, the base of the first NPN triode is connected between the seventh resistor and a power supply, the emitter of the first NPN triode is connected to the first sending end, and the collector of the first NPN triode is connected between the first pull-up resistor and the non-inverting input terminal of the first comparator.

[0015] In the second serial communication circuit, the base of the second NPN triode is connected between the eighth resistor and a power supply, the emitter of the second NPN triode is connected to the second sending end, and the collector of the second NPN triode is connected between the second pull-up resistor and the non-inverting input terminal of the second comparator.

[0016] The collector of the first NPN triode is directly connected to the collector of the second NPN triode.

[0017] As a further improvement of the application, the first voltage dropping device is a ninth resistor, and the second voltage dropping device is a tenth resistor; the resistance value of the ninth resistor is 1 / 20-1 / 3 of the resistance value of the first pull-up resistor, and the resistance value of the tenth resistor is 1 / 20-1 / 3 of the resistance value of the second pull-up resistor.

[0018] As a further improvement of the application, the ratio of the resistance values of the first pull-up resistor and the second pull-up resistor is 1:2-2:1.

[0019] As a further improvement of the application, the ratio of the resistance values of the first resistor and the second resistor is 1:4-4:1, and the ratio of the resistance values of the fifth resistor and the sixth resistor is 1:4-4:1.

[0020] As a further improvement of the application, the first chip and the second chip are both chips for transmitting data based on a serial communication protocol, and the first chip and the second chip are respectively arranged in two logically independent devices to establish serial communication between the first chip and the second chip by the inter-chip communication circuit; neither the first serial communication circuit nor the second serial communication circuit comprises a capacitor connected in parallel with the signal line and grounded.

[0021] Based on the same inventive concept, the application further provides an electronic device comprising:

[0022] At least two devices, any two devices establish serial communication through the inter-chip communication circuit as described in any one of the preceding embodiments; any device receives data sent by another device to drive the execution terminal connected with the device to perform an execution action matching the received data sent by another device.

[0023] As a further improvement of the present application, a surgical microscope is included;

[0024] The surgical microscope includes:

[0025] An operating handle forms a joint partially embedded in the movable arm; the operating handle is internally provided with the first chip, and the joint and the interior of the movable arm form a continuous and deformable accommodation channel, and the signal line penetrates through the accommodation channel to perform receiving and sending data between the first chip and the second chip.

[0026] Compared with the prior art, the present application has the following beneficial effects:

[0027] Firstly, the output end of the first comparator is connected with the first receiving end, the inverting input end of the first comparator is connected between the first resistor and the second resistor, the output end of the second comparator is connected with the second receiving end, the inverting input end of the second comparator is connected between the fifth resistor and the sixth resistor, and the non-inverting input end of the first comparator is directly connected with the non-inverting input end of the second comparator, so as to form only one signal line for receiving and sending data between the first chip and the second chip. When the first chip sends data to the second chip based on the serial communication protocol, the second voltage dropping device is cut off and the second comparator outputs low level. At this time, the first receiving end remains high level and the second receiving end is at low level, so that data can only be sent from the first sending end to the second receiving end, and finally to the second chip and received by the second chip. The process of sending data from the second chip to the first chip and receiving is also the same. Therefore, the present application can effectively isolate the RX level signal of the chip on the data sending side in the serial communication established based on the serial communication protocol, so that the data cannot be forwarded to the RXD port (i.e. the second receiving end) of the chip on the data sending side, thereby realizing the isolation of the TX and RX level signals of the chip on the data sending side, overcoming the self-sending and self-receiving defects when using one signal line to multiplex TX and RX in the prior art, avoiding data transmission errors and data conflicts, and especially reducing the number of cables used between devices based on serial communication;

[0028] Secondly, the first comparator and the second comparator with high rate of change of voltage swing are arranged in the first serial communication circuit and the second serial communication circuit respectively, so that the requirement of the first serial communication circuit and the second serial communication circuit on the change rate of the high and low level switching when receiving data and sending data is improved, so that there is no delay between the driving voltage and the signal output when the data is transmitted between devices, a larger range of baud rate is met, the requirement of different transmission speeds on the baud rate is met, higher data bandwidth is supported and formed. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A schematic diagram of establishing serial communication between a master device and a slave device in the prior art;

[0030] Figure 2 A schematic diagram of establishing serial communication between a master device and a slave device by using a chip-to-chip communication circuit of the application, the master device is provided with a first chip and the slave device is provided with a second chip;

[0031] Figure 3 A circuit diagram of a chip-to-chip communication circuit in one embodiment of the application;

[0032] Figure 4 A circuit diagram of the first serial communication unit in Figure 3 ;

[0033] Figure 5 A circuit diagram of a chip-to-chip communication circuit in another embodiment of the application;

[0034] Figure 6 A circuit diagram of the first serial communication unit in Figure 5 ;

[0035] Figure 7 A circuit diagram of a chip-to-chip communication circuit in another embodiment of the application;

[0036] Figure 8 A circuit diagram of the first serial communication unit in Figure 7 ;

[0037] Figure 9 A waveform diagram of the first chip sending data to the second chip at a baud rate of 1200bit / s;

[0038] Figure 10 A waveform diagram of the first chip sending data to the second chip at a baud rate of 9600bit / s;

[0039] Figure 11 A waveform diagram of the first chip sending data to the second chip at a baud rate of 115200bit / s;

[0040] Figure 12 The waveform diagram shows the first chip sending data to the second chip at a baud rate of 1,500,000 bits / s.

[0041] Figure 13 A waveform diagram of data transmission at a baud rate of 9600 bits / s in the prior art;

[0042] Figure 14 This is a topology diagram of an electronic device according to the present invention;

[0043] Figure 15 A three-dimensional view of the operating handle of a surgical microscope;

[0044] Figure 16 For along Figure 15 Sectional view along the middle AA direction;

[0045] Figure 17 for Figure 15 A schematic diagram showing the connection between a first PCB built into the control handle and a second PCB connected to a drive motor via an inter-chip communication circuit of the present invention, wherein the first PCB houses a first chip and the second PCB houses a second chip.

[0046] A brief explanation of the reference numerals in the attached figures is as follows:

[0047] First chip - 100; Second chip - 200; Electronic device - 1000; Inter-chip communication circuit - 300, 300a, 300b; Cable path - 400; Master device - 3; Slave device - 4; Devices - 6, 7, 8, 9; Signal line - 50; Power line - 30; Grounding wire - 40; First serial communication unit - 301; Second serial communication unit - 302; First voltage drop device - 33, 33a, 33b; Second voltage drop device - 34 34a, 34b; First transmitter-101; First receiver-102; Second transmitter-201; Second receiver-202; First connector-235; Second connector-245; First PCB-223; Second PCB-243; Joint-221; Joint socket-231; Operating handle-21; Reception channel-20; Channels-222, 232, 242; Press button-224; Toggle button-225; Mounting base-24. Detailed Implementation

[0048] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent transformations or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the protection scope of the present invention. Before describing the various embodiments of this application in detail, the technical terms contained in this application and their meanings are explained and defined as necessary.

[0049] The term "master device" is a superordinate concept for medical instruments such as surgical robots or surgical microscopes and other similar electronic devices. The master device may also include an electronic device with a specific purpose, and the master device can establish serial communication with a slave device based on the serial communication circuit referred to in the present invention, so as to communicate with each other between the master device and the slave device to perform data reception and transmission.

[0050] The term "slave device" is a relative concept to the "master device". Based on the data of serial communication, it can be sent from the master device to the slave device, or from the slave device to the master device, or can be sent to each other between the master device and the slave device. Both the master device and the slave device in this application can be the data sending end or the data receiving end, and are relative concepts to each other. In each embodiment of this application, the master device (or the sending end) and the slave device (or the receiving end) are parallel concepts to each other.

[0051] The term "each device" or "device" is a general term or a superordinate generalization of the master device (or the sending end) and the slave device (or the receiving end).

[0052] The term "connection" includes but is not limited to physical connection, and more covers electrical connection and connection established based on a specific communication protocol.

[0053] The term "electronic device" includes an electronic device or an electronic system that transceives at least including serial communication.

[0054] The term "data" includes serial data forwarded between two devices based on a serial protocol (for example, UART protocol).

[0055] The term "PCB" is an abbreviation for Printed Circuit Board, which is a support for electronic components (for example, resistors, chips, connectors), and constitutes a carrier for the electrical interconnection of the aforementioned electronic components.

[0056] The terms "first", "second", etc. are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so as to implement the embodiments of the present invention disclosed here.

[0057] See Figure 1 As shown, in the prior art such as CN216527161U, if the first serial port module (located in Figure 1 the master device 3a) and the second serial port module (located in Figure 1 the slave device 4a) use UART communication, establishing data transceiver operations with each other requires the use of a clock signal line (SCK), a bidirectional signal line (SDA), a level data loading line (SH), a power supply line (VCC) and a ground line (GND). Five lines are required for the first serial port module and the second serial port module to implement data communication.

[0058] Referring to Figure 2 The number of cables relied on by the communication path for data forwarding between the master device 3 and the slave device 4 and other devices in the application such as Figure 2 is one (i.e., the signal line 50), and three lines (i.e., the signal line 50 (TX / RX), the power line 30 (VCC), and the ground line 40 (GND)) are needed for data transceiving operation between each other. The TXD port and the RXD port configured for each device are time-division multiplexed to forward serial port data between devices, so as to ultimately realize communication between the master device 3 and the slave device 4 (i.e., between devices) through the inter-chip communication circuit 300 (or 300a or 300b) of the application.

[0059] Referring to Figures 2 to 4 , Figures 9 to 13 corresponds to a typical embodiment of the inter-chip communication circuit 300 of the application. The inter-chip communication circuit 300 in each embodiment of the application can be applied to half-duplex communication or full-duplex communication, and two signal lines 50 based on half-duplex communication are established in full-duplex communication.

[0060] An inter-chip communication circuit 300 is arranged between a first chip 100 and a second chip 200, the first chip 100 is provided with a first sending end 101 and a first receiving end 102, and the second chip 200 is provided with a second sending end 201 and a second receiving end 202. The inter-chip communication circuit 300 further comprises a first serial port communication circuit 301 connected to the first chip 100 and a second serial port communication circuit 302 connected to the second chip 200. The first chip 100 and the second chip 200 are chips for transmitting data based on a serial port communication protocol, and the aforementioned chips include electronic elements such as MCUs and FPGAs. The first chip 100 and the second chip 200 are respectively arranged in two logically independent devices (for example, the first chip 100 is arranged in the master device 3, and the second chip 200 is arranged in the slave device 4), so as to establish serial port communication between the first chip 100 and the second chip 200 by the inter-chip communication circuit 300.

[0061] In particular, in each embodiment of the application, neither the first serial port communication circuit 301 nor the second serial port communication circuit 302 contains a capacitor connected in parallel with the signal line 50 and grounded. The first serial port communication circuit 301 and the second serial port communication circuit 302 are symmetrical structures, and the resistance values of the electronic elements contained therein are usually equal. For example, the resistance values of the first resistor R1 and the fifth resistor R5 are equal, and the resistance values of the second resistor R2 and the sixth resistor R6 are equal. However, the resistance values of the resistors contained in the first serial port communication circuit 301 or the second serial port communication circuit 302 can not be equal. The TXD port includes the first sending end 101 and the second sending end 201, and the RXD port includes the first receiving end 102 and the second receiving end 202.

[0062] The baud rate represents the rate of the effective data signal modulating the carrier, i.e. the number of times the carrier modulating state changes per unit time. The baud rate determines the transmission speed of the data between the first chip 100 and the second chip 200. The formula for calculating the capacitive reactance Xc is Xc = 1 / (2pfC), wherein f is the signal frequency and C is the capacitance value. When the capacitance value C is constant, as the baud rate increases, the signal frequency f increases and the capacitive reactance Xc decreases. In the embodiments of the present application, since the first serial communication circuit 301 and the second serial communication circuit 302 do not contain a capacitor connected in parallel with the signal line 50 and grounded, the bypass of the signal line 50 connecting two devices (or two chips) is avoided, and further, the capacitive reactance Xc is less than the minimum requirement for the high level when the data is transmitted from the first chip 100 to the second chip 200, thereby solving the aforementioned defects of the prior art due to the need for a capacitor connected in parallel with the signal line 50 and grounded, avoiding data errors and data conflicts when transmitting data between chips (or devices). At the same time, it also avoids many problems such as enable exception of the chip (including the first chip 100 or the second chip 200), unstable level signal, frequent interruption, etc. that may be caused by insufficient high level when the data is transmitted from the first chip 100 to the second chip 200.

[0063] The first serial communication circuit 301 comprises a first voltage dropping device 33, a first comparator U1, a first sending end 101 connected in series with a first resistor R1 and a second resistor R2 and grounded, an inverting input end (i.e. pin 4) of the first comparator U1 connected between the first resistor R1 and the second resistor R2, an output end (i.e. pin 1) of the first comparator U1 connected to a first receiving end 102, a non-inverting input end (i.e. pin 3) of the first comparator U1 connected to a first pull-up resistor R3 connected to a power supply VCC, and the first sending end 101 and the non-inverting input end of the first comparator U1 connected in parallel with the first voltage dropping device 33. The first serial communication circuit 301 connects the first sending end 101 and the first receiving end 102 of the first chip 100.

[0064] The second serial port communication circuit 302 comprises: the second voltage drop device 34, the second comparator U2, the second sending end 201 connected with the fifth resistor R5 and the sixth resistor R6 in series and grounded, the inverting input end of the second comparator U2 (i.e. pin 4 of the second comparator U2) connected between the fifth resistor R5 and the sixth resistor R6, the output end of the second comparator U2 (i.e. pin 1 of the second comparator U2) connected with the second receiving end 202, the non-inverting input end of the second comparator U2 (i.e. pin 3 of the second comparator U2) connected with the second pull-up resistor R4 connected with the power supply VCC, and the second voltage drop device 34 connected in parallel with the non-inverting input end of the second comparator U2 and the second sending end 201. The non-inverting input end of the first comparator U1 is directly connected with the non-inverting input end of the second comparator U2, so as to form only one signal line 50 for executing the receiving data and the sending data between the first chip 100 and the second chip 200. The second serial port communication circuit 302 is connected with the second sending end 201 and the second receiving end 202 of the second chip 200.

[0065] For example, the resistance values of the first resistor R1, the second resistor R2, the first pull-up resistor R3, the second pull-up resistor R4, the fifth resistor R5 and the sixth resistor R6 are all 4.7KΩ. The first comparator U1 and the second comparator U2 have pin 5 and pin 2 respectively, pin 5 connected with the power supply (+5V) and pin 2 grounded.

[0066] In the embodiment, the ratio of the resistance values of the first pull-up resistor R3 and the second pull-up resistor R4 is 1:2~2:1, and preferably, the resistance values of the first pull-up resistor R3 and the second pull-up resistor R4 are equal. Alternatively, the resistance values of the first pull-up resistor R3 and the second pull-up resistor R4 can also be unequal. The ratio of the resistance values of the first resistor R1 and the second resistor R2 is 1:4~4:1, and can be 4:1, 3:1, 2:1, 1:2, 1:3, 1:4 or 1:1, etc. and the most preferred ratio is 1:1. The ratio of the resistance values of the fifth resistor R5 and the sixth resistor R6 is 1:4~4:1, and can be 4:1, 3:1, 2:1, 1:2, 1:3, 1:4 or 1:1, etc. and the most preferred ratio is 1:1. The port voltage change processes of the first sending end 101, the first receiving end 102, the second sending end 201 and the second receiving end 202 when different ratios of the resistance values between the first resistor R1 and the second resistor R2 and between the fifth resistor R5 and the sixth resistor R6 are formed will be shown below and embodied in the form of high and low levels.

[0067] The first comparator U1 and the second comparator U2 are push-pull output type comparators to realize fast alternate conduction of positive and negative half cycle signals and form full cycle output. The model of the first comparator U1 and the second comparator U2 can be TLV3201AIDBVR. The slew rate of the first comparator U1 and the second comparator U2 is 500-1000V / μs; specifically, the slew rate can be 500V / μs, 600V / μs, 700V / μs, 900V / μs or 1000V / μs, etc. The input common mode voltage range of the first comparator U1 and the second comparator U2 completely covers the voltage range of the power supply (VCC) and is preferably close to the voltage range of the power supply (VCC). For example, the voltage of the power supply (VCC) is +5V, and it can also be +3.3V and other specifications of voltage. The first comparator U1 and the second comparator U2 have characteristics such as rail-to-rail input, low offset voltage (1mV), high speed (40ns), low power consumption (40µA) and high output drive current, and the voltage range of the power supply (VCC) is +2.7V to +5.5V.

[0068] The first voltage dropping device 33 and the second voltage dropping device 34 are both diodes, and the model is B5819WS. The anode of the diode D1 in the first serial communication circuit 301 is connected to the anode of the diode D2 of the second serial communication circuit 302. The diode D1 and the diode D2 are Schottky diodes. In combination with Figure 4 As shown, the cathode of the diode D1 is connected to the connection point 31, and the anode of the diode D1 is connected to the connection point 32. The connection point 31 and the connection point 32 form a voltage drop. When the voltage of the non-inverting input of the first comparator U1 is greater than the voltage of the inverting input, the output voltage of the first comparator U1 is +5V to be high. When the voltage of the non-inverting input of the first comparator U1 is less than the voltage of the inverting input, the output voltage of the first comparator U1 is 0V to be low. The level change of the output end of the first comparator U1 is based on voltage comparison between the non-inverting input and the inverting input of the second comparator U2. The foregoing is described in the first comparator U1, and will not be repeated here.

[0069] The embodiment illustrates how to avoid the data being received by the data sending end and only received by the receiving end in the typical scenarios of no data transmission between the first chip 100 and the second chip 200 (i.e. scenario (1)), data transmission from the first chip 100 to the second chip 200 (i.e. scenario (2)), data transmission from the second chip 200 to the first chip 100 (i.e. scenario (3)), and the first resistor R1 (or the fifth resistor R5) and the second resistor R2 (or the sixth resistor R6) forming the same different resistance value ratio. When data is transmitted from the first chip 100 to the second chip 200, the first chip 100 (the master device 3) is regarded as the data sending end (i.e. the "sending end"), and the second chip 200 is regarded as the data receiving end (i.e. the "receiving end"). In the process of data transmission from the second chip 200 to the first chip 100, the second chip 200 is regarded as the sending end, and the first chip 100 is regarded as the receiving end.

[0070] The meanings of the voltages of the ports in the application are briefly described below.

[0071] V TX1 : the voltage of the data sending end of the first chip 100 (i.e. the voltage of the port of the first sending end 101 of the first chip 100);

[0072] V RX1 : the voltage of the data receiving end of the first chip 100 (i.e. the voltage of the port of the first receiving end 102 of the first chip 100);

[0073] V IN1+ : the voltage of the positive input pin of the first comparator U1 (i.e. the voltage of the port of pin 3 of the first comparator U1);

[0074] V IN1- : the voltage of the negative input pin of the first comparator U1 (i.e. the voltage of the port of pin 4 of the first comparator U1);

[0075] V TX2 : the voltage of the data sending end of the second chip 200 (i.e. the voltage of the port of the second sending end 201 of the second chip 200);

[0076] V RX2 : the voltage of the data receiving end of the second chip 200 (i.e. the voltage of the port of the second receiving end 202 of the second chip 200);

[0077] V IN2+ : the voltage of the positive input pin of the second comparator U2 (i.e. the voltage of the port of pin 3 of the second comparator U2);

[0078] V IN2- : the voltage of the negative input pin of the second comparator U2 (i.e. the voltage of the port of pin 4 of the second comparator U2);

[0079] V RX / TX : voltage of single-wire data transceiver point (i.e. voltage across signal line 50); V D1 : voltage drop between positive and negative electrodes when diode D1 is turned on by forward bias, about 0.3V when diode D1 is a Schottky diode. RX / TX about 0.3V;

[0080] V D2 : voltage drop between positive and negative electrodes when diode D2 is turned on by forward bias, about 0.3V when diode D2 is a Schottky diode.

[0081] This embodiment shows scenarios (1) to (3), and combines Figure 3 and Figure 4 to further illustrate the technical solutions and corresponding technical effects.

[0082] Scenario (1): No data transmission between first chip 100 and second chip 200.

[0083] First sending end 101 and second sending end 201 both output high level and port voltage is +5V, and resistance values of first resistor R1 and second resistor R2 and fifth resistor R5 and sixth resistor R6 are equal. Under the action of first pull-up resistor R3 and second pull-up resistor R4, diode D1 and diode D2 are turned on, and port voltages of V RX / TX , V IN1+ and V IN2+ are all +5V. Since the inverting input end of first comparator U1 is connected between first resistor R1 and second resistor R2 and second resistor R2 is grounded, the resistance values of first resistor R1 and second resistor R2 are equal, thus achieving voltage division through first resistor R1 and second resistor R2. The resistance value of second resistor R2 (or sixth resistor R6) relative to first resistor R1 (or fifth resistor R5) cannot be too small and is kept between 1:4 and 4:1, so as to avoid the port voltages of the non-inverting input end and the inverting input end of the same comparator being too close, thus causing the level output error of the output end of the comparator. Therefore, first resistor R1, second resistor R2, fifth resistor R5 and sixth resistor R6 in each embodiment of the application can be collectively referred to as "voltage division resistor".V IN1- = V TX1 ×R2 / (R1+R2), V IN2- = V TX1 ×R6 / (R5+R6). In the foregoing formula, the resistance values of first resistor R1 and second resistor R2, or the resistance values of fifth resistor R5 and sixth resistor R6 are substituted into the calculation to obtain V IN1- =+2.5V, V IN2- =+2.5V. At this time, V IN1+ and VIN2+ the port voltage of V IN1- or V IN2- , and thus are greater than the port voltage of the inverting input of the corresponding comparator. Thus, the output of the first comparator U1 and the output of the second comparator U2 are both at high level. At this time, V RX1 and V RX2 are both +5V and at high level.

[0084] For scenario (1), for example, the resistance values of the first resistor R1 and the second resistor R2, the fifth resistor R5 and the sixth resistor R6 can also be unequal. Specifically, the resistance value of the second resistor R2 is 1 / 4 of the resistance value of the first resistance value R1, and the resistance value of the sixth resistor R6 is 1 / 4 of the resistance value of the fifth resistance value R5. V RX / TX , V IN1+ and V IN2+ are all +5V. Substituting the resistance values of the first resistor R1 and the second resistor R2, the fifth resistor R5 and the sixth resistor R6 into the two calculation formulas in the foregoing scenario (1), it is obtained that V IN1- =+1V, V IN2- =+1V. At this time, the port voltages of V IN1+ and V IN2+ are kept at +5V (i.e., greater than V IN1- or V IN2- ), and thus are greater than the port voltage of the inverting input of the corresponding comparator. Thus, the output of the first comparator U1 and the output of the second comparator U2 are both at high level. At this time, V RX1 and V RX2 are both +5V and at high level.

[0085] For scenario (1), for example, the resistance values of the first resistor R1 and the second resistor R2, the fifth resistor R5 and the sixth resistor R6 can also be unequal. Specifically, the resistance value of the second resistor R2 is 1 / 4 of the resistance value of the first resistance value R1, and the resistance value of the sixth resistor R6 is 1 / 4 of the resistance value of the fifth resistance value R5. V RX / TX , V IN1+ and V IN2+ are all +5V. Based on the foregoing calculation formulas of scenario (1), it is obtained that V IN1- =+4V, V IN2- =+4V. At this time, the port voltages of V IN1+ and V IN2+ are kept at +5V (i.e., greater than V IN1- or V IN2- ), and thus are greater than the port voltage of the inverting input of the corresponding comparator. At this time, V RX1 and V RX2= +5V and at high level. It can be seen that the resistance value of the second resistor R2 cannot be too large than the resistance value of the first resistor R1, and the resistance value of the sixth resistor R6 cannot be too large than the resistance value of the fifth resistor R5, otherwise it will cause the port voltage of the non-inverting input terminal and the inverting input terminal of the same comparator to be too close, although it can form a port voltage difference between the non-inverting input terminal and the inverting input terminal of the same comparator. Therefore, configuring the resistance value of the second resistor R2 to be less than or equal to the resistance value of the first resistor R1, and configuring the resistance value of the sixth resistor R6 to be less than or equal to the resistance value of the fifth resistor R5 constitute a more preferred embodiment.

[0086] Scenario (2): The first chip 100 sends data to the second chip 200.

[0087] The resistance values of the first resistor R1 and the second resistor R2, and the fifth resistor R5 and the sixth resistor R6 are equal. When the first chip 100 sends data, the first sending end 101 outputs low level (i.e., V TX1 = 0V), and the second sending end 201 outputs high level (i.e., V TX2 = +5V). At this time, when the diode D1 is forward biased and turned on, the voltage drop between the positive and negative electrodes thereof is 0.3V (i.e., V D1 = 0V); and at this time, the diode D2 is in the reverse-biased off state, so that the voltage drop between the positive and negative electrodes of the diode D2 is negative (-4.7V). V RX / TX = V IN1+ = V IN2+ = V TX1 + V D1 = +0.3V. The first resistor R1 and the second resistor R2 realize voltage division, and the fifth resistor R5 and the sixth resistor R6 realize voltage division. V IN1- = V TX1 × R2 / (R1+R2), V IN2- = V TX1 × R6 / (R5+R6). In the foregoing formula, the resistance values of the first resistor R1 and the second resistor R2, or the resistance values of the fifth resistor R5 and the sixth resistor R6 are substituted into the calculation to obtain V IN1- = 0V and V IN2- = +2.5V. At this time, V IN1+ = 0.3V and is greater than V IN1- , and makes the non-inverting input terminal and the inverting input terminal of the first comparator U1 form a port voltage difference, so that the output terminal voltage of the first comparator U1 is +5V to be at high level (i.e., V RX1 = +5V). Since V IN2+ = +0.3V and is less than V IN2- , the port voltage of the output terminal of the second comparator U2 is 0V to be at low level, and at this time V RX1= +5V and is at high level. Therefore, the data sent by the first chip 100 through the first sending end 101 cannot be forwarded to the first receiving end 102, but can only be sent to the second receiving end 202, so that the data sent by the first chip 100 is received by the second chip 200, avoiding the problem of self-sending and self-receiving of the first chip 100.

[0088] For scenario (2), for example, the resistance value of the second resistor R2 is 1 / 4 of the resistance value of the first resistance value R1, and the resistance value of the sixth resistor R6 is 1 / 4 of the resistance value of the fifth resistance value R5. At this time, V TX1 = 0V, V TX2 = +5V. When the diode D1 is forward biased and turned on, the voltage drop between the positive and negative electrodes thereof is 0.3V (i.e., V D1 = 0V); and at this time, the diode D2 is in a reverse-biased and cut-off state, so that the voltage drop between the positive and negative electrodes of the diode D2 is negative (-4.7V). Therefore, V RX / TX = V IN1+ = V IN2+ = V TX1 + V D1 = +0.3V. The first resistor R1 and the second resistor R2 achieve voltage division, and the fifth resistor R5 and the sixth resistor R6 achieve voltage division. The resistance values of the first resistor R1 and the second resistor R2, and the fifth resistor R5 and the sixth resistor R6 are substituted into the two calculation formulas in scenario (2) above, and V IN1- = 0V, V IN2- = +1V. Since V IN1+ = 0.3V and is greater than V IN1- , the non-inverting input terminal and the inverting input terminal of the first comparator U1 form a port voltage difference, so that the output terminal voltage of the first comparator U1 is +5V to be at a high level (i.e., V RX1 = +5V). Since V IN2+ = 0.3V and is less than V IN2- , the non-inverting input terminal and the inverting input terminal of the second comparator U2 form a port voltage difference, so that the output terminal voltage of the second comparator U2 is 0V to be at a low level (i.e., V RX2 = 0V). As can be seen, the data sent by the first chip 100 through the first sending end 101 cannot be forwarded to the first receiving end 102, but can only be sent to the second receiving end 202, so that the data sent by the first chip 100 is received by the second chip 200, avoiding the problem of self-sending and self-receiving of the first chip 100.

[0089] For scenario (2), for example, the resistance value of the second resistor R2 is 1 / 4 of the resistance value of the first resistance value R1, and the resistance value of the sixth resistor R6 is 1 / 4 of the resistance value of the fifth resistance value R5. At this time, V RX / TX , V IN1+, V IN2+ , V TX1 With V D1 the sum of the port voltages are +0.3V. Based on the aforementioned calculation formula of scenario (2), V IN1- =0V, V IN2- =4V. Since V IN1+ is greater than V IN1- , the non-inverting input and the inverting input of the first comparator U1 form a port voltage difference to drive the output voltage of the first comparator U1 to +5V to be high (i.e., V RX1 =+5V). Since V IN2+ is less than V IN2- , the non-inverting input and the inverting input of the second comparator U2 form a port voltage difference to drive the output voltage of the second comparator U2 to 0V to be low (i.e., V RX2 =0V). Thus, the problem of spontaneous sending and receiving of the first chip 100 is also avoided.

[0090] Scenario (3): the second chip 200 sends data to the first chip 100.

[0091] Scenario (3) is similar to scenario (2), and the main difference is that the data sending direction is opposite to that of scenario (2). Therefore, scenario (3) is briefly described.

[0092] The resistance values of the first resistor R1 and the second resistor R2 and the fifth resistor R5 and the sixth resistor R6 are equal. When the second chip 200 sends data through the second sending end 201, the first sending end 101 outputs high (i.e., V TX1 =+5V), and the second sending end 201 outputs low (i.e., V TX2 =0V). At this time, the diode D1 is in a reverse-biased cutoff state, and the voltage drop between its positive and negative electrodes is negative (-4.7V); the diode D2 is forward-biased and turned on, and the voltage drop between its positive and negative electrodes is 0.3V (i.e., V D2 =+0.3V). V RX / TX , V IN1+ , V IN2+ , V TX1 With V D2 the sum of the port voltages are +0.3V. Substitute the resistance values of the first resistor R1 and the second resistor R2, the fifth resistor R5 and the sixth resistor R6 into the two calculation formulas in scenario (2) above, to obtain V IN1- =+5V, V IN2- =0V. Since V IN1+ is less than V IN1- , the non-inverting input and the inverting input of the first comparator U1 form a port voltage difference to drive the output voltage of the first comparator U1 to 0V to be low (i.e., VRX1 =0V). Since V IN2+ is greater than V IN2- , the non-inverting input and the inverting input of the second comparator U2 form a port voltage difference, so as to drive the output voltage of the second comparator U2 to be +5V to be a high level (i.e., V RX2 =+5V). Thus, the data sent by the second sending end 201 of the second chip 200 cannot be forwarded to the second receiving end 202, but can only be sent to the first receiving end 102, so that the data sent by the second chip 200 is received by the first chip 100, thereby avoiding the problem of self-sending and self-receiving of the second chip 200.

[0093] For scenario (3), for example, the resistance value of the second resistor R2 is 1 / 4 of the resistance value of the first resistance value R1, and the resistance value of the sixth resistor R6 is 1 / 4 of the resistance value of the fifth resistance value R5. V RX / TX =V IN1+ =V IN2+ =V TX1 +V D2 =+0.3V. The first resistor R1 and the second resistor R2 realize voltage division, and the fifth resistor R5 and the sixth resistor R6 realize voltage division. The resistance values of the first resistor R1 and the second resistor R2, and the fifth resistor R5 and the sixth resistor R6 are substituted into the two calculation formulas in the scenario (3) above, and V IN1- =1V, V IN2- =0V. Since V IN1+ =0.3V and is less than V IN1- , the non-inverting input and the inverting input of the first comparator U1 form a port voltage difference, so as to drive the output voltage of the first comparator U1 to be 0V to be a low level (i.e., V RX1 =0V). Since V IN2+ =0.3V and is greater than V IN2- , the non-inverting input and the inverting input of the second comparator U2 form a port voltage difference, so as to drive the output voltage of the second comparator U2 to be +5V to be a high level (i.e., V RX2 =+5V). Thus, the problem of self-sending and self-receiving of the second chip 200 is also avoided.

[0094] For scenario (3), for example, the resistance value of the second resistor R2 is 1 / 4 of the resistance value of the first resistance value R1, and the resistance value of the sixth resistor R6 is 1 / 4 of the resistance value of the fifth resistance value R5. V RX / TX =V IN1+ =V IN2+ =V TX2 +V D2=+0.3V. The first resistor R1 and the second resistor R2 implement voltage division, and the fifth resistor R5 and the sixth resistor R6 implement voltage division. The resistance values of the first resistor R1 and the second resistor R2, and the fifth resistor R5 and the sixth resistor R6 are substituted into the two calculation formulas in the above scenario (3), and V IN1- =+4V, V IN2- =0V. Since V IN1+ =0.3V and is less than V IN1- , the non-inverting input terminal and the inverting input terminal of the first comparator U1 form a port voltage difference, so that the output terminal voltage of the first comparator U1 is 0V to be low (i.e., V RX1 =0V); since V IN2+ =0.3V and is greater than V IN2- , the non-inverting input terminal and the inverting input terminal of the second comparator U2 form a port voltage difference, so that the output terminal voltage of the second comparator U2 is +5V to be high (i.e., V RX2 =+5V). Thus, the problem of spontaneous sending and receiving of the second chip 200 is also avoided.

[0095] Through the above scenarios (1)-(3) and the examples of different resistance value ratios of each voltage dividing resistor in each serial communication circuit (i.e., the first serial communication circuit 301 and the second serial communication circuit 302), the problem of spontaneous sending and receiving and data transmission error when multiplexing TX and RX through one signal line 50 is avoided.

[0096] This embodiment takes the first chip 100 sending hexadecimal data 0X55, 0X55, 0X55, 0X55 to the second chip 200 as an example, and respectively shows the waveform diagrams formed at different baud rates.

[0097] As Figures 9 to 13 The level waveform diagrams of each port in the process of forwarding the data from the first chip 100 to the second chip 200 are shown from top to bottom. The level of the second receiving end 202 is abbreviated as “V(rx2)”, the level of the signal line 50 is abbreviated as “V(rx / tx)”, the level of the first receiving end 102 is abbreviated as “V(rx1)”, and the level of the first sending end 101 is abbreviated as “V(tx1)”. Figures 9 to 13 The lower case subscript (such as rx2) has the same meaning as the aforementioned capital letter subscript (such as RX2).

[0098] In Figures 9 to 12In the first chip 100, the first sending end 101 sends data, V(rx2), V(rx / tx) and V(tx1) are periodic square waves, and are periodically switched between high level (+5V) and low level (0V). In the data sending process, V(rx1) is always at high level (+5V), which proves that the data sent from the first sending end 101 cannot be sent to the first receiving end 102, but can only be received by the second receiving end 202, thereby avoiding the problem of self-receiving caused by the first chip 100 receiving the data sent by the first chip 100 (or the second chip 200 receiving the data sent by the second chip 100).

[0099] As a comparison example, if the first sending end 101 of the first chip 100 sends data and is received by the first receiving end 102 of the first chip 100, and there is a self-receiving phenomenon, there are problems such as Figure 13 The waveform diagram is shown. Figure 13 V(rx1) in the first chip 100 is a periodic square wave, and V(rx2), V(rx / tx), V(rx1) and V(tx1) have consistency in the period of the rising and falling edges of the waveform diagram, thereby proving that the data sent from the first chip 100 can be received by itself and can be received by the second chip 200, and thus there is a defect of self-receiving.

[0100] Meanwhile, for other baud rates such as 2400bit / s and 4800bit / s, the aforementioned technical effects of the present application are still applicable, and will not be described here.

[0101] The chip-to-chip communication circuit 300 disclosed in the present application can receive and send data in a wide baud rate range of 1200-1500000bit / s, and can realize high-speed transmission and low-speed transmission of data in different application scenarios. For a surgical microscope, a lower baud rate (for example, a baud rate of 1200bit / s) is used for transmission of control instructions, and the required data bandwidth is usually small; and a higher baud rate (for example, a baud rate of 1500000bit / s) is used for firmware upgrade, and the required data bandwidth is usually large, thereby realizing adjustment of different data bandwidths. The present application can reasonably utilize data bandwidth resources, and improve the response sensitivity of the electronic device 1000 containing the chip-to-chip communication circuit 300 of the present application during operation, thereby avoiding the waste of data bandwidth resources caused by uniformly using a higher baud rate. The adjustment of the baud rate is adjusted by the register in the MCU (i.e., a lower concept of the first chip 100 or the second chip 200). Since the adjustment of the baud rate is a prior art, it is not the point of the present application. Therefore, it is not described in detail in the embodiments of the present application.

[0102] Referring toFigure 5 With reference to Fig. 3b, another typical embodiment of the inter-chip communication circuit 300b is shown. The main difference between this embodiment and the aforementioned embodiments is that the first voltage dropping device and the second voltage dropping device show another alternative implementation. Figure 6

[0103] In the inter-chip communication circuit 300b, the first voltage dropping device 33b includes a first PNP transistor Q3 and a ninth resistor R9, and the second voltage dropping device 34b includes a second PNP transistor Q4 and a tenth resistor R10. In the first serial communication circuit 301, the base B of the first PNP transistor Q3 is connected between the ninth resistor R9 and the power supply (VCC), the emitter E of the first PNP transistor Q3 is connected to the first sending end 101, and the collector C of the first PNP transistor Q3 is connected between the first pull-up resistor R3 and the non-inverting input terminal of the first comparator U1. In the second serial communication circuit 302, the base B of the second PNP transistor Q4 is connected between the tenth resistor R10 and the power supply (VCC), the emitter E of the second PNP transistor Q4 is connected to the second sending end 201, and the collector C of the second PNP transistor Q4 is connected between the second pull-up resistor R4 and the non-inverting input terminal of the second comparator U2. The collector C of the first PNP transistor Q3 is directly connected to the collector C of the second PNP transistor Q4. The resistance values of the ninth resistor R9 and the tenth resistor R10 can both be 4.7KΩ. The first PNP transistor Q3 and the ninth resistor R9, and the second PNP transistor Q4 and the tenth resistor R10 are both connected to form a voltage drop between the connection point 31 and the connection point 32. Specifically, after the first PNP transistor Q3 and the second PNP transistor Q4 are saturated and turned on, the voltage drop formed between the connection point 31 and the connection point 32 is about 0.1-0.3V. The first voltage dropping device 33b and the second voltage dropping device 34b are symmetrical structures to each other, and the two connection points (not labeled) contained in the second voltage dropping device 34b are similar to the connection point 31 and the connection point 32 between the collector C and the emitter E of the first voltage dropping device 33b. Figure 5

[0104] The inter-chip communication circuit 300b in this embodiment has the same technical solutions as the inter-chip communication circuit 300 in the aforementioned embodiments. For details, refer to the previous description, which will not be repeated here.

[0105] Referring to Fig. 4a, another typical embodiment of the inter-chip communication circuit 400a is shown. The main difference between this embodiment and the aforementioned embodiments is that the first voltage dropping device and the second voltage dropping device show another alternative implementation. Figure 7 With reference to Fig. 4b, another typical embodiment of the inter-chip communication circuit 400b is shown. The main difference between this embodiment and the aforementioned embodiments is that the first voltage dropping device and the second voltage dropping device show another alternative implementation. Figure 8

[0106] ​​​In the inter-chip communication circuit 300b, the first voltage dropping device 33b is a ninth resistor R9, and the second voltage dropping device 34b is a tenth resistor R10. The resistance value of the ninth resistor R9 is 1 / 20~1 / 3 of the resistance value of the first pull-up resistor R3, and is further preferably 1 / 10; the resistance value of the tenth resistor R10 is 1 / 20~1 / 3 of the resistance value of the second pull-up resistor R4, and is further preferably 1 / 10; optionally, the resistance value of the ninth resistor R9 is equal to that of the tenth resistor R10, and can be 470Ω. The resistance values of the ninth resistor R9 and the tenth resistor R10 cannot be too small, and are preferably 1 / 10 of the resistance values of the pull-up resistors respectively arranged in the first serial communication circuit 301 or the second serial communication circuit 302. In this way, the ninth resistor R9 and the tenth resistor R10 can have sufficient voltage drop, and at the same time, the voltage divided by the first pull-up resistor R3 and the ninth resistor R9 (or the second pull-up resistor R4 and the tenth resistor R10) when transmitting data is a low level. The ninth resistor R9 and the tenth resistor R10 as voltage dropping devices make the voltage division effect close to 0V. When the first pull-up resistor R3 and the second pull-up resistor R4 are both 4.7 KΩ, the voltage drop formed by connecting the ninth resistor R9 between the connection point 31 and the connection point 32 is the voltage of the power supply (VCC)×R9 / (R3+R9), and the voltage drop is about 0.45V; the voltage drop formed by connecting the tenth resistor R10 between the connection point 31 and the connection point 32 is the voltage of the power supply (VCC)×R10 / (R4+R10), and the voltage drop is about 0.45V. The first voltage dropping device 33a and the second voltage dropping device 34b are symmetrical structures, Figure 7 The two connection points (not labeled) in the second voltage dropping device 34b in the middle are similar to the connection point 31 and the connection point 32 at both ends of the ninth resistor R9.

[0107] The inter-chip communication circuit 300b in this embodiment has the same technical solutions as the inter-chip communication circuit 300 (or 300a) in the foregoing embodiments, and details are described above and will not be repeated here.

[0108] As shown in the specific embodiments of the electronic device 1000 in Figure 2 and Figure 14 .

[0109] An electronic device 1000 includes at least two devices (for example, the device 6, the device 7, the device 8, and the device 9), and any two devices (i.e., the device 6~the device 9) are connected through the inter-chip communication circuit 300 (or 300a or 300b) in any of the foregoing specific manners to establish serial communication; any device receives data transmitted by another device to drive an execution terminal connected to the device to perform an execution action matching the received data transmitted by another device. The foregoing device 6~the device 9 are Figure 2 master devices 3 and slave devices 4 in the upper concept, and can be arbitrarily interconnected.

[0110] Device 6 connects to execution terminal 61 and can connect to multiple execution terminals. Device 7 connects to execution terminal 71 and can connect to multiple execution terminals 71. Device 8 connects to execution terminal 81 and can connect to multiple execution terminals 81. Device 9 connects to execution terminal 91 and can connect to multiple execution terminals 91. An inter-chip communication circuit 300 (or 300a or 300b) is established between devices 6 and 9 to enable mutual access and control between devices 6 and 9. Execution terminals 61, 71, 81, and 91 execute actions adapted to the received data after receiving the data. Any one of devices 6 to 9 can be considered as master device 3, while the other devices are considered as slave devices 4. The devices perform (serial port) data transmission and reception based on the inter-chip communication circuit 300 (or 300a or 300b). It should be noted that the master device referred to in this application is not limited to the sender of (serial port) data, and can also be understood as the receiver of (serial port) data, while slave devices are considered as the senders of (serial port) data.

[0111] like Figure 2 and Figure 17 As shown, the two wire harnesses are the power supply line (VCC) 30 and the ground line (GND) 40, respectively, to provide power to the master device 3 and the slave device 4. The third wire harness is the signal line 50, which performs the reception and transmission of (serial port) data between the master device 3 (or the first chip 100) and the slave device (or the second chip 200). The power supply line 30, the ground line 40, and the signal line 50 together form the inter-chip communication circuit 300, which consists of three cables. One end of the inter-chip communication circuit 300 (or 300a or 300b) is connected to the first connector 235 via a terminal (not shown), and the other end is connected to the second connector 245 via a terminal (not shown).

[0112] For example, the electronic device 1000 may be a surgical microscope (not shown). (See reference...) Figures 15 to 17As shown, the surgical microscope includes: an operating handle 21 and a movable arm 23. The operating handle 21 forms a joint 221 that is partially embedded in the movable arm 23. A connecting rod 22 is formed between the operating handle 21 and the joint 221, and a communicating channel 222 is formed between the connecting rod 22 and the interior of the joint 221. The end of the movable arm 23 near the connecting rod 22 forms a socket 231 that movably accommodates the joint 221. Another channel 232 is formed inside the movable arm 23, and the channels 222 and 232 together form a continuous and deformable receiving channel 20, thereby forming a continuous and deformable receiving channel 20 inside the joint 221 and the movable arm 23. The connecting rod 22 is also movably connected to a mounting base 24, allowing the connecting rod 22 and the mounting base 24 to rotate relative to each other. A channel 242 is also formed inside the mounting base 24 and communicates with the receiving channel 20. A signal line 50 and two other cables including the signal line 50 (i.e., a power line 30 and a ground line 40) are connected along... Figure 16 The cable passing through path 400 passes through receiving channel 20, and after passing through channel 242, it connects to another PCB (i.e., second PCB 243) mounted on the optical zoom unit (not shown, but considered a subordinate concept of slave device 4). Thus, by triggering the press button 224 or the toggle button 225, the motor inside the optical zoom unit is driven to perform optical zoom, or the electric drive assembly is driven to perform an action that moves the optical zoom unit in space. Both the press button 224 and the toggle button 225 are considered as execution terminals connected to master device 3. Second chip 200 is located inside the optical zoom unit or the electric drive assembly. Thus, receiving and transmitting data is performed between first chip 100 and second chip 200. Devices such as the optical zoom unit may include a motor for optical zoom; the motor can be considered as an execution terminal connected to slave device 4, or as one or more execution terminals connected to devices 6 to 9.

[0113] Combination Figure 17 As shown, the first chip 100 located within the operating handle 21 is connected to the second chip 200 in the slave device located away from the operating handle 21 via a wiring harness consisting of three cables. The operating handle 21 houses the first chip 100, which is mounted on the first PCB 223. The received and transmitted data is serial port data based on a serial communication protocol; for example, based on I... 2 Data is forwarded between master device 3 and slave device 4 using C protocol, RS485 protocol or UART protocol; the forwarding of data is considered bidirectional, which can be data sent from master device 3 to slave device 3, or data sent from slave device 4 to master device 3.

[0114] As an optional embodiment, the master device is a chip (not shown, and regarded as a lower concept of the first chip 100) arranged on the first PCB 223 inside the operation handle 21. The slave device 4 can be an optical zoom body or an electric driving assembly of the surgical microscope. The aforementioned optical zoom body or electric driving assembly can be regarded as a slave device 4, which contains a control chip (not shown) for driving the slave device 4 to perform a specific physical action, and regarded as a lower concept of the second chip 200. The electronic device such as the surgical microscope usually contains one or more master devices 3 and one or more slave devices 4, so as to perform the sending of the control instructions embodied by the data by the master device 3, and control and drive the slave device to perform a specific execution action. The whole process can be regarded as the data transmission and signal control between the two devices. For example, the first PCB 223 is arranged with one or more push buttons 224 and one or more dial buttons 225. Pressing or dialing the push button 224 or the dial button 225 forms a driving signal, which is connected and controls one or more slave devices 4 as a data through the inter-chip communication circuit 300, and the second PCB 243 is arranged in the slave device 4.

[0115] The operation handle 21 must be convenient to hold, so its volume is usually small, and it puts high requirements on the volume of the first PCB 223 that can be installed inside the operation handle. The smaller first PCB 223 leads to the smaller size of the first PCB 223 that can weld the first connector 235. At the same time, since the electronic device 1000 or the surgical microscope is a precision electromechanical structure, the volume of the second PCB 243 at the slave device 4 and the second connector 245 welded by the second PCB 243 is also small. The present application can reduce the number of cables used between the two devices based on the serial communication, so that the number of Pin terminals of the connector based on the serial communication is reduced from five to three. Therefore, the present application can significantly reduce the volume of the first connector 235 and the second connector 245, and further reduce the area and size occupied by the first PCB 223 and the second PCB 243, avoid the waste of the PCB area and reduce the manufacturing cost; at the same time, the relatively small number of cables and the relatively small size of the connector are also conducive to threading in the narrow accommodation channel 20, and can more conveniently install and replace the wire harness. The specific implementation of the inter-chip communication circuit 300 (or 300a or 300b) contained in the embodiment is described above, and will not be repeated here.

[0116] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present application, and are not used to limit the protection scope of the present application. Any equivalent embodiments or changes made without departing from the concept of the present application should be included in the protection scope of the present application.

[0117] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An inter-chip communication circuit arranged between a first chip and a second chip, the first chip being provided with a first transmitting end and a first receiving end, and the second chip being provided with a second transmitting end and a second receiving end; characterized in that Further comprising: a first serial port communication circuit connected to the first chip and a second serial port communication circuit connected to the second chip; the first serial port communication circuit comprising: a first voltage dropping device, a first comparator, the first transmitting end being connected in series with a first resistor and a second resistor and grounded, the inverting input terminal of the first comparator being connected between the first resistor and the second resistor, the output terminal of the first comparator being connected to the first receiving end, the non-inverting input terminal of the first comparator being connected to a first pull-up resistor connected to a power supply, and the first transmitting end and the non-inverting input terminal of the first comparator being connected in parallel to the first voltage dropping device; the second serial port communication circuit comprising: a second voltage dropping device, a second comparator, the second transmitting end being connected in series with a fifth resistor and a sixth resistor and grounded, the inverting input terminal of the second comparator being connected between the fifth resistor and the sixth resistor, the output terminal of the second comparator being connected to the second receiving end, the non-inverting input terminal of the second comparator being connected to a second pull-up resistor connected to a power supply, and the second transmitting end and the non-inverting input terminal of the second comparator being connected in parallel to the second voltage dropping device; the non-inverting input terminal of the first comparator being directly connected to the non-inverting input terminal of the second comparator, so as to form only one signal line for transmitting and receiving data between the first chip and the second chip.

2. The inter-chip communication circuit according to claim 1, characterized by, the first comparator and the second comparator are push-pull output type comparators, and the slew rate of the first comparator and the second comparator is 500-1000 V / μs.

3. The inter-chip communication circuit according to claim 2, wherein the first voltage dropping device and the second voltage dropping device are diodes, and the anode of the forward bias type diode in the first serial port communication circuit is connected to the anode of the diode in the second serial port communication circuit.

4. The inter-chip communication circuit according to claim 2, wherein the first voltage dropping device comprises a first NPN type transistor and a seventh resistor, and the second voltage dropping device comprises a second NPN type transistor and an eighth resistor; in the first serial port communication circuit, the base of the first NPN type transistor is connected between the seventh resistor and a power supply, the emitter of the first NPN type transistor is connected to the first transmitting end, and the collector of the first NPN type transistor is connected between the first pull-up resistor and the non-inverting input terminal of the first comparator; in the second serial port communication circuit, the base of the second NPN type transistor is connected between the eighth resistor and a power supply, the emitter of the second NPN type transistor is connected to the second transmitting end, and the collector of the second NPN type transistor is connected between the second pull-up resistor and the non-inverting input terminal of the second comparator; the collector of the first NPN type transistor is directly connected to the collector of the second NPN type transistor.

5. The inter-chip communication circuit according to claim 2, wherein the first voltage dropping device is a ninth resistor, and the second voltage dropping device is a tenth resistor; the resistance value of the ninth resistor is 1 / 20-1 / 3 of the resistance value of the first pull-up resistor, and the resistance value of the tenth resistor is 1 / 20-1 / 3 of the resistance value of the second pull-up resistor.

6. The inter-chip communication circuit according to claim 5, wherein The ratio of resistance values of the first pull-up resistor and the second pull-up resistor is 1:2~2:

1.

7. The inter-chip communication circuit according to claim 1, wherein The ratio of resistance values of the first resistor and the second resistor is 1:4~4:1, and the ratio of resistance values of the fifth resistor and the sixth resistor is 1:4~4:

1.

8. The chip-to-chip communication circuit of claim 1, wherein, The first chip and the second chip are chips for transmitting data based on a serial communication protocol, and the first chip and the second chip are respectively deployed in two logically independent devices to establish serial communication between the first chip and the second chip by the inter-chip communication circuit. The first serial communication circuit and the second serial communication circuit do not include a capacitor connected in parallel with the signal line and grounded.

9. An electronic device, comprising: Comprise: At least two devices, any two devices establish serial communication through the inter-chip communication circuit of any one of claims 1 to 8; Any device receives data sent by another device to drive an execution terminal connected to the any device receiving the data sent by the another device to perform an execution action matching the received data.

10. The electronic device of claim 9, wherein, Comprise a surgical microscope; The surgical microscope comprises: An operating handle, a movable arm, the operating handle forms a part embedded in the joint of the movable arm; the operating handle is built-in the first chip, the joint and the inside of the movable arm form a continuous and deformable accommodation channel, the signal line penetrates through the accommodation channel to perform receiving data and sending data between the first chip and the second chip. The ratio of resistance values of the first pull-up resistor and the second pull-up resistor is 1:2~2:

1. The ratio of resistance values of the first resistor and the second resistor is 1:4~4:1, and the ratio of resistance values of the fifth resistor and the sixth resistor is 1:4~4:

1. The first chip and the second chip are chips for transmitting data based on a serial communication protocol, and the first chip and the second chip are respectively deployed in two logically independent devices to establish serial communication between the first chip and the second chip by the inter-chip communication circuit. The first serial communication circuit and the second serial communication circuit do not include a capacitor connected in parallel with the signal line and grounded. Comprise: At least two devices, any two devices establish serial communication through the inter-chip communication circuit of any one of claims 1 to 8; Any device receives data sent by another device to drive an execution terminal connected to the any device receiving the data sent by the another device to perform an execution action matching the received data. Comprise a surgical microscope; The surgical microscope comprises: An operating handle, a movable arm, the operating handle forms a part embedded in the joint of the movable arm; the operating handle is built-in the first chip, the joint and the inside of the movable arm form a continuous and deformable accommodation channel, the signal line penetrates through the accommodation channel to perform receiving data and sending data between the first chip and the second chip.

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