An Aging Test Method for Dynamic Random Access Memory

Abstract

This invention discloses an aging test method for dynamic random access memory (DRAM), relating to the field of memory testing technology. The method includes: S1: Model Establishment: Aging tests are performed on a reference chip sample, and the test results are monitored and acquired. Simultaneously, based on the test results and a statistical analysis model, a correlation model between real-time monitoring parameters and the long-term lifespan of the chip is constructed; S2: Closed-Loop Testing: Based on the correlation model, a damage control threshold is determined. Simultaneously, based on the damage control threshold, selected electrical parameters for the aging test of the DRAM chip under test are monitored, and the test parameters are adjusted; S3: Test Judgment: Functional tests are performed on each DRAM chip under test to determine the chip test results. This method avoids the problem of hidden damage to virgin chips caused by excessive stress in traditional aging tests, ensuring the long-term lifespan and stability of the chips in actual use.

Description

Technical Field

[0001] This invention relates to the field of memory testing technology, specifically to an aging test method for dynamic random access memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a core storage component in modern electronic devices, widely used in computers, mobile terminals, servers, and embedded systems. Because its storage cells rely on capacitors to store charge, it suffers from charge leakage, necessitating periodic refresh operations to maintain data integrity. This characteristic makes DRAM more challenging to maintain in terms of reliability compared to Static RAM (SRAM).

[0003] In the DRAM manufacturing process, burn-in testing is a crucial step in ensuring product reliability and screening for devices that are prone to early failure. Burn-in testing accelerates the exposure of potential defects by running the chip under extreme conditions such as high temperature, high pressure, and high frequency for extended periods. This process eliminates devices with an early failure risk, thereby improving the yield rate and long-term stability of the finished products.

[0004] Currently, common DRAM aging test methods mainly include two modes: static aging and dynamic aging. Static aging typically applies a constant voltage to the memory cells under high temperature conditions, mainly detecting static defects such as leakage and short circuits; dynamic aging, on the other hand, simulates actual working conditions by repeatedly reading and writing to the memory array under high temperature conditions, thereby inducing dynamic faults related to time and operating frequency, such as refresh failure, insufficient data retention time, and bit line interference.

[0005] Chinese invention patent CN116953472A discloses a method and testing apparatus for multi-stress aging testing of circuit boards. The method includes: determining environmental stress and its magnitude; determining electrical stress load; temperature control, adjusting the temperature of a temperature control chamber according to the stated temperature stress value; load control, sending a test excitation signal to the circuit board under test, which generates a control signal for controlling the electrical stress load; and test analysis, acquiring the output signals of each electrical stress load and analyzing the output signals to obtain the test conclusion. This invention's multi-stress aging testing method for circuit boards, by employing both environmental and electrical stresses simultaneously, induces early product failures and exposes potential early defects through screening tests, resulting in higher detection accuracy and improved product reliability.

[0006] While the aforementioned technical solutions can improve the efficiency of fault detection and make screening more accurate through the constructed testing environment, existing DRAM aging tests, in order to improve testing efficiency, apply excessively harsh stress (such as ultra-high voltage and extreme temperature) during the screening of defective products. This may cause hidden electrical damage or microstructure degradation to good chips. Furthermore, since this damage is difficult to detect during testing, it irreversibly depletes the chip's inherent reliability margin, resulting in the chip's lifespan and stability in actual use falling short of design expectations. Summary of the Invention

[0007] The purpose of this invention is to provide an aging test method for dynamic random access memory (DRAM) to solve the problems mentioned in the background art.

[0008] To achieve the above objectives, the present invention provides the following technical solution: an aging test method for dynamic random access memory, comprising:

[0009] S1: Model building: Aging tests are performed on the reference chip sample, and the test results are monitored and obtained. At the same time, based on the test results and statistical analysis model, a correlation model between real-time monitoring parameters and chip long-term lifespan is constructed.

[0010] S2: Closed-loop test: Based on the aforementioned correlation model, a damage control threshold is determined. Simultaneously, based on this damage control threshold, selected electrical parameters for the aging test of the DRAM chip under test are monitored and adjusted, including:

[0011] S2.1: Threshold setting: The lifespan of the DRAM chip under test is used as the input of the correlation model, and the output is to obtain the threshold of the selected electrical parameter to be monitored and set as the upper limit threshold of the damage control threshold range. At the same time, according to the adjustment ratio of the selected electrical parameter threshold, the lower limit threshold of the damage control threshold range is set.

[0012] S2.2: Test monitoring: The DRAM chip under test is subjected to aging test through the stress application module and the online monitoring module, and the selected electrical parameters of each DRAM chip under test are monitored and obtained in real time.

[0013] S2.3: Monitoring Feedback: The selected electrical parameters of the DRAM chip under test are compared with the damage control threshold range to determine the decision interval corresponding to each DRAM chip under test, specifically:

[0014] When the selected electrical parameter is less than the lower limit of the damage control threshold range, it is in the blue optimization zone, and the test stress is increased; when the selected electrical parameter is within the damage control threshold range, it is in the green safety zone, and the test parameter is maintained; when the selected electrical parameter is greater than the upper limit of the damage control threshold range, it is in the red alarm zone, and the test stress is reduced.

[0015] S3: Test Judgment: Perform functional tests on each of the DRAM chips under test to determine the chip test results, specifically:

[0016] If the DRAM chip under test fails to function, it is a defective chip; otherwise, it is a good chip.

[0017] Furthermore, a correlation model between real-time monitoring parameters and the long-term lifespan of the chip is constructed, including:

[0018] S1.1: Determine the sample chip: Based on the set confidence score and error range, determine the corresponding required number of samples, and randomly select reference chip samples from the current production line through multiple variation dimensions and the required number of samples;

[0019] S1.2: Sample testing: The reference chip sample is subjected to accelerated aging test under high voltage and high temperature, and the selected electrical parameters are monitored. At the same time, the tested reference chip sample is subjected to high temperature working life test to obtain the high temperature working life corresponding to each reference chip sample.

[0020] S1.3: Quantitative Correlation: Using the selected electrical parameters and high-temperature operating life as inputs to the statistical analysis model, the corresponding nonlinear regression model is obtained as the output, specifically:

[0021]

[0022] in: To monitor the high-temperature operating life corresponding to the selected electrical parameters, This is the scaling factor. is the base of the natural logarithm. The attenuation rate, Selected electrical parameters to be monitored, It is an asymptote.

[0023] Furthermore, based on the selected electrical parameters and high-temperature operating life corresponding to each of the reference chip samples, a modeling data pair for each of the reference chip samples is determined, and the modeling data pair is used as the input to a statistical analysis model. Through nonlinear regression analysis of the statistical analysis model, the corresponding scaling factor, attenuation rate, and asymptote are obtained as output.

[0024] Furthermore, the stress application module includes a high-temperature unit and a power supply unit, which are connected by a load board. The DRAM chip under test is fixed on the load board. The high-temperature unit provides the ambient temperature required for the aging test, and the power supply unit provides the operating voltage required for the aging test.

[0025] Furthermore, the online monitoring module includes a measurement unit and a multiplexer, which are connected to each other. The measurement unit is used to monitor and acquire the Iddq change rate of the DRAM chip under test, and the multiplexer is used for measurement switching between multiple DRAM chips under test during aging tests.

[0026] Furthermore, by adjusting the test parameters corresponding to each of the DRAM chips under test within the damage control threshold range, including:

[0027] S2.3.1: Determine the deviation: Based on the damage control threshold range, determine the center value of the damage control threshold range and use it as the center line of the green safety zone. At the same time, compare the selected electrical parameters of the DRAM chip under test located in the blue optimization zone / red alarm zone with the center line of the green safety zone to obtain the real-time deviation of each DRAM chip under test.

[0028] S2.3.2: Determine the scaling factor: Perform closed-loop testing on the reference chip sample. At the same time, according to the size of the preset scaling factor value sequence, the reference chip sample of the closed-loop test is divided equally. The divided reference chip sample to be tested is then tested with the corresponding preset scaling factor value to obtain the corresponding reference chip sample curve. Based on the reference chip sample curve, the final scaling factor value is determined.

[0029] S2.3.3: Determine the adjustment voltage: Combine the real-time deviation of the DRAM chip under test with the final proportional coefficient value to determine the corresponding voltage adjustment amount, specifically:

[0030]

[0031] in: This is the voltage adjustment amount. This is the proportionality coefficient value. This represents the real-time deviation.

[0032] Furthermore, based on the sample curves of all reference chips under test corresponding to the same scaling factor value, the average value of all sample curves of the reference chips under test is determined and used as the system response curve corresponding to the scaling factor value. At the same time, based on the system response curve, the stable overshoot data corresponding to each scaling factor value is determined, and all stable overshoot data are compared to determine the minimum stable overshoot data. The scaling factor value corresponding to the minimum stable overshoot data is the final scaling factor value.

[0033] Furthermore, based on the system response curve corresponding to the proportional coefficient value, the settling time required from the start of the test to the green safe zone is taken as the settling time corresponding to the proportional coefficient value. The difference between the peak value of the system response curve and the center line of the green safe zone is taken as the overshoot corresponding to the proportional coefficient value. Based on the settling time and overshoot corresponding to the proportional coefficient value, the stable overshoot data corresponding to the proportional coefficient value is obtained, specifically:

[0034]

[0035] in: To stabilize overshoot data, To stabilize the time, This is the overshoot.

[0036] Compared with the prior art, the beneficial effects of the present invention are:

[0037] Firstly, this invention determines the corresponding damage control threshold range by selecting a nonlinear regression model between electrical parameters and chip lifespan, and performs real-time monitoring and dynamic stress adjustment. This ensures that good chips are always tested within a safe threshold range, thereby avoiding the problem of hidden damage to good chips caused by excessive stress in traditional aging tests, and ensuring the long-term lifespan and stability of the chips in actual use.

[0038] Secondly, this invention constructs a nonlinear regression model between selected electrical parameters and chip lifespan by extracting reference chip samples, and sets a damage control threshold based on the nonlinear regression model. At the same time, it adaptively adjusts the stress according to the individual differences of each chip through the damage control threshold, thereby realizing precise testing tailored to each chip.

[0039] Thirdly, for chips with a large performance margin, i.e., those in the blue optimization zone, this invention increases stress to accelerate their aging process, thereby shortening the test time. For chips in the red alarm zone, stress is reduced to protect their aging process, thus helping to optimize the efficiency of the overall test process while ensuring reliability. Attached Figure Description

[0040] Figure 1This is a schematic diagram of the aging test method in this invention;

[0041] Figure 2 A graph is created to establish the correlation model between the selected electrical parameters and high-temperature operating life in this invention.

[0042] Figure 3 This is a diagram showing the test pressure adjustment for closed-loop testing in this invention;

[0043] Figure 4 This is a comparison diagram of the effects in this invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Existing DRAM aging tests, in order to improve testing efficiency, apply excessively harsh stress (such as ultra-high voltage or extreme temperature) during the defect screening process, which may cause hidden electrical damage or microstructure degradation to good chips. Furthermore, since this damage is difficult to detect during testing, it irreversibly depletes the chip's inherent reliability margin, resulting in a lower-than-expected lifespan and stability in actual use. The technical solution of this application, however, establishes a nonlinear regression model between selected electrical parameters and chip lifespan by performing accelerated aging tests and lifespan analysis on reference chip samples. During the aging test of the DRAM chip under test, the electrical parameters are monitored in real time within the damage control threshold range set by the nonlinear regression model. Based on the monitoring results, the test stress is dynamically adjusted, and the chip's yield is determined through functional testing. This effectively solves the problem of hidden damage to good chips caused by excessive stress in traditional aging tests, ensuring the long-term reliability of good chips while screening for defective ones.

[0046] Example 1

[0047] refer to Figures 1-4 This embodiment provides an aging test method for dynamic random access memory, which specifically includes the following steps:

[0048] Step S1: Model Building. This involves testing a reference chip sample and monitoring the results in real time. Based on these results and statistical methods, a correlation model between the real-time monitoring parameters and the long-term lifespan of the chip is constructed. Details are as follows:

[0049] Step S1.1: Determine the sample chips. This involves randomly selecting a predetermined number of chips from the current production line to serve as reference chip samples. It is important to note that during the chip selection process, it is necessary to ensure that the selected reference chip samples can fully represent all normal and acceptable fluctuations on the production line. This means selecting chips through multiple dimensions of variation, including but not limited to wafer batch number, production time point, production line or equipment, and location on the wafer.

[0050] Furthermore, during the chip extraction process, based on the selected confidence level and confidence interval, the corresponding confidence score and error range are determined, and these are combined with the population standard deviation to determine the required sample size. Specifically:

[0051]

[0052] in: The required number of samples, The confidence score corresponds to the confidence level. The population standard deviation is 1. This represents the error range corresponding to the confidence interval.

[0053] In this embodiment, the corresponding confidence scores are determined by setting a standard normal distribution table and selecting a confidence level. Specifically, according to the set standard normal distribution table, the confidence score corresponding to a 90% confidence level is 1.645, the confidence score corresponding to a 95% confidence level is 1.96, and the confidence score corresponding to a 99% confidence level is 2.576. Simultaneously, the error range corresponding to the confidence interval is determined based on the difference between the set sample estimate and the true population mean. Furthermore, based on historical production data or test data of similar products and products with the same process corresponding to the currently extracted chip, the standard deviation of the historical production data or test data is used as the population standard deviation corresponding to the currently extracted chip.

[0054] In the specific implementation process, the difference between the current sample estimate, i.e., the average rate of change of Iddq, and the true population mean is ±0.015 mA / h. Therefore, the error range corresponding to the confidence interval is 0.015. Meanwhile, the standard deviation of the rate of change of Iddq in the historical production data is 0.04 mA / h, so the population standard deviation is 0.04. At the same time, a 95% confidence level is selected. According to the standard normal distribution table, the confidence score is 1.96. That is to say, the required sample size is approximately 27.32. Therefore, the number of reference chip samples extracted in this embodiment is 28.

[0055] Step S1.2: Sample Testing. The reference chip samples extracted in Step S1.1 undergo accelerated aging testing. Specifically, high voltage and high temperature are used as accelerating stresses, and the selected electrical parameters are monitored frequently and continuously during the accelerated aging test. After the accelerated aging test, the tested reference chip samples undergo high-temperature operating life testing, i.e., all are subjected to 125℃ and 1V operating conditions for 1000 hours of HTOL testing. After the high-temperature operating life test, the corresponding test results are determined, i.e., the number of good and defective products, and the pass time and failure time of the good / defective reference chip samples are statistically analyzed.

[0056] Step S1.3: Quantitative Correlation. This involves using the selected electrical parameters monitored in Step S1.2, the pass time of the good reference chip sample, and the failure time of the defective reference chip sample as inputs to a statistical analysis model (e.g., an exponential decay model). The output is the corresponding nonlinear regression model, specifically:

[0057]

[0058] in: To monitor the high-temperature operating life corresponding to the selected electrical parameters, This is the scaling factor. is the base of the natural logarithm. The attenuation rate, Selected electrical parameters to be monitored, It is an asymptote.

[0059] In this embodiment, the selected electrical parameters monitored in step S1.2, the pass time of the good reference chip sample, and the failure time of the defective reference chip sample are matched together. That is, the selected electrical parameters monitored during the sample testing of each reference chip sample are matched with the corresponding high-temperature operating life, which serves as the modeling data pair for each reference chip sample. Simultaneously, the modeling data pair for each reference chip sample is used as input to the statistical analysis model. Through nonlinear regression analysis of the statistical analysis model, the specific magnitudes of the corresponding scaling factor, attenuation rate, and asymptote can be determined, thereby determining the corresponding nonlinear regression model.

[0060] In the specific implementation process, nonlinear regression analysis was performed on the modeling data of each reference chip sample to obtain the corresponding scaling factor, attenuation rate, and asymptote as 12350.5, 5.82, and 60985.3, respectively. Figure 2 .

[0061] Step S2: Closed-loop testing. Based on the nonlinear regression model obtained in step S1.3, the corresponding damage control threshold is determined. Simultaneously, the DRAM chip under test is subjected to aging testing. During the aging test, selected electrical parameters are monitored in real time according to the determined damage control threshold, and the test parameters are adjusted in real time based on the monitoring results. Figure 3 The details are as follows:

[0062] Step S2.1: Threshold setting. Based on the nonlinear regression model determined in step S1.3, the set high-temperature operating life, i.e., the lifespan of the DRAM chip under test, is used as its output to determine the corresponding input size, that is, the threshold value of the corresponding monitored electrical parameter.

[0063] Furthermore, based on the determined threshold values ​​of the selected electrical parameters, this is used as the upper limit of the damage control threshold range. Simultaneously, based on the upper limit of the damage control threshold range and the set adjustment ratio (which can be specifically set according to actual needs, such as 20%-50%), the lower limit of the corresponding damage control threshold range is determined.

[0064] In the specific implementation process, when the set high-temperature working life is 7 years, or 61,400 hours, this 61,400 hours is used as the output of the nonlinear regression model in step S1.3. Since the corresponding scaling factor, attenuation rate and asymptote are 12350.5, 5.82 and 60985.3 respectively, the corresponding selected electrical parameter for monitoring is 0.583mA / h. At the same time, the adjustment ratio is set to 30%, which means that the corresponding damage control threshold range is 0.1749mA / h-0.583mA / h.

[0065] Step S2.2: Test Monitoring. This involves using the set stress application module and online monitoring module to perform aging tests on the DRAM chips under test, and monitoring and acquiring selected electrical parameters for each DRAM chip during the aging test.

[0066] In this embodiment, the stress application module includes a high-temperature unit and a power supply unit. The high-temperature unit provides the corresponding ambient temperature for the aging test of the DRAM chip under test, and a fan is installed inside the high-temperature unit to ensure uniform temperature within the unit. The power supply unit provides the corresponding operating voltage for the aging test of the DRAM chip under test. Specifically, the high-temperature unit and the power supply unit are connected through a load board, and the DRAM chip under test is fixed on the load board.

[0067] Furthermore, the DRAM chip under test is fixed on a load board, and high temperature and high voltage are provided through a high-temperature unit and a power supply unit to allow the DRAM chip under test to undergo aging tests under the corresponding high temperature and high voltage environment. Simultaneously, during the aging test, an online monitoring module monitors the selected electrical parameter, Iddq, of each DRAM chip under test in real time at fixed time intervals.

[0068] Specifically, the online monitoring module in this embodiment includes a measurement unit and a multiplexer. The measurement unit is used to monitor and acquire the Iddq change rate of the DRAM chip under test using a high-precision digital multimeter. The multiplexer is connected to the measurement unit and is used to switch between monitoring each DRAM chip under test during the simultaneous testing of multiple DRAM chips under test.

[0069] Step S2.3: Monitoring Feedback. This involves comparing the selected electrical parameters obtained from monitoring each DRAM chip under test in Step S2.2 with the damage control threshold range determined in Step S2.1, and based on the comparison results, determining the decision interval for each DRAM chip under test. Specifically:

[0070] When the selected electrical parameter obtained from monitoring is less than the lower limit of the damage control threshold range (0.1749 mA / h), the corresponding DRAM chip under test is in the blue optimization zone, and the stress during the test needs to be increased. When the selected electrical parameter obtained from monitoring is within the damage control threshold range (0.1749 mA / h - 0.583 mA / h), the corresponding DRAM chip under test is in the green safe zone, and the test parameters remain unchanged. When the selected electrical parameter obtained from monitoring is greater than the upper limit of the damage control threshold range (0.583 mA / h), the corresponding DRAM chip under test is in the red alarm zone, and the stress during the test needs to be reduced.

[0071] Step S3: Test Judgment. Based on the decision range determined in Step S2.3, the test parameters for each DRAM chip under test are adjusted in real time during the aging test to ensure that each chip remains within the safe green range during testing. It is worth noting that functional testing can be performed on the DRAM chips under test during the aging test. In other words, by performing functional tests, read and write tests are conducted on the DRAM chips under test during the aging test to verify their basic functionality.

[0072] Furthermore, during the aging test, the end of the aging test is determined by the total test time and the functional tests performed on the DRAM chip under test. In other words, the aging test of the DRAM chip under test ends when the total test time is reached or when the functional tests determine that the DRAM chip under test has a functional failure.

[0073] Furthermore, during the aging test, if the functional test determines that the DRAM chip under test has a functional failure, then the corresponding DRAM chip under test is a defective chip. Conversely, if the functional test does not determine that the DRAM chip under test has a functional failure, then the corresponding DRAM chip under test is a good chip.

[0074] refer to Figure 4 It can be seen that the median lifetime of the traditional fixed high stress method is 40286 hours and the number of outliers is 0, while the median lifetime of the technical solution of the present invention is 57629 hours and the number of outliers is 1, which means that the median lifetime is improved by 43.1%.

[0075] Example 2

[0076] This embodiment provides an aging test method for dynamic random access memory (DRAM), which is implemented in the same way as in Embodiment 1. The difference is that in step S2.3, the test parameters for each DRAM chip under test are adjusted according to the decision interval and the set damage control threshold range. The invention will now be illustrated with specific examples from this embodiment.

[0077] In this embodiment, the test parameters for each DRAM chip under test are adjusted according to the set damage control threshold range, as follows:

[0078] Step S2.3.1: Determine the deviation. Based on the damage control threshold range determined in Step S2.1, determine the center value of this range, which is the corresponding center line of the green safety zone. Simultaneously, compare the selected electrical parameters of the DRAM chip under test located in the blue optimization zone / red alarm zone with the center line of the green safety zone. The real-time deviation for each DRAM chip under test is obtained by comparing the numerical difference between the selected electrical parameters and the center line of the green safety zone.

[0079] In the specific implementation process, the damage control threshold range in this embodiment is set to 0.1749 mA / h-0.583 mA / h, and the center value of the corresponding damage control threshold range is 0.37895 mA / h, which is the center line of the green safe zone. Meanwhile, in this embodiment, the selected electrical parameter for the DRAM chip under test located in the blue optimization zone is 0.07 mA / h, and the corresponding real-time deviation is 0.30895 mA / h. Conversely, in this embodiment, the selected electrical parameter for the DRAM chip under test located in the red alarm zone is 0.62 mA / h, and the corresponding real-time deviation is 0.24105 mA / h.

[0080] Step S2.3.2: Determine the scaling factor. That is, based on the reference chip sample obtained in step S1.1, perform the closed-loop test in step S2. That is, through the set stress application module and online monitoring module, perform aging test on the reference chip sample under test, and monitor and acquire the selected electrical parameters of each reference chip sample under test during the aging test.

[0081] Furthermore, based on the preset proportional coefficient value sequence, the reference chip samples under test during the aging test are equally divided, and each of the divided reference chip samples is tested against its corresponding preset proportional coefficient value, i.e., the test parameters are adjusted during the aging test. Simultaneously, during the corresponding tests, the corresponding Iddq value, Iddq change rate, proportional coefficient adjustment amount, and adjustment voltage are monitored in real time to obtain the corresponding damage rate-time curve and operating voltage-time curve.

[0082] Furthermore, based on the obtained damage rate-time curves and operating voltage-time curves, all sample curves of the reference chips under test corresponding to the same scaling factor value are determined. The average value of all sample curves of the reference chips under test is then used as the system response curve corresponding to that scaling factor value. It is worth noting that, based on the system response curve corresponding to each scaling factor value, the settling time required from the start of the test to the green safe zone and the difference between the peak value of the system response curve and the center line of the green safe zone are determined for each system response curve; these represent the settling time and overshoot for each scaling factor value.

[0083] Furthermore, based on the settling time and overshoot corresponding to each proportional coefficient value, the settling time and overshoot corresponding to each proportional coefficient value are combined to obtain the stable overshoot data corresponding to each proportional coefficient value, specifically:

[0084]

[0085] in: To stabilize overshoot data, To stabilize the time, This is the overshoot.

[0086] Furthermore, the stable overshoot data corresponding to each proportional coefficient value are compared to determine the minimum stable overshoot data. The proportional coefficient value corresponding to the minimum stable overshoot data is the final proportional coefficient value.

[0087] Step S2.3.3: Determine the adjustment voltage. This involves combining the real-time deviation of the DRAM chip under test obtained in step S2.3.1 and the final proportional coefficient value determined in step S2.3.2 to determine the corresponding voltage adjustment amount. Specifically:

[0088]

[0089] in: This is the voltage adjustment amount. This is the proportionality coefficient value. This represents the real-time deviation.

[0090] In the specific implementation process, the final proportional coefficient value was set to 0.002V (mA / h). Meanwhile, the real-time deviation of the DRAM chip under test in the blue optimization zone was 0.30895mA / h, corresponding to a voltage adjustment of 0.0006179V. The real-time deviation of the DRAM chip under test in the red alarm zone was 0.24105mA / h, corresponding to a voltage adjustment of 0.0004821V.

[0091] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended embodiments and their equivalents.

Claims

1. A method of aging test for a dynamic random access memory, characterized by, The method comprises the following steps: S1: model establishment: performing aging test on reference chip samples and monitoring test results, and constructing a correlation model between real-time monitoring parameters and long-term life of chips according to test results and statistical analysis model; S2: closed-loop test: determining a damage control threshold according to the correlation model, and monitoring selected electrical parameters of the aging test of the to-be-tested DRAM chip according to the damage control threshold, and adjusting the test parameters, comprising: S2.1: threshold setting: taking the service life of the to-be-tested DRAM chip as the input of the correlation model, and outputting the monitoring selected electrical parameter threshold, which is set as the upper threshold of the damage control threshold range, and setting the lower threshold of the damage control threshold range according to the adjustment ratio of the monitoring selected electrical parameter threshold; S2.2: test monitoring: performing aging test on the to-be-tested DRAM chip through the stress applying module and the online monitoring module, and monitoring the selected electrical parameters of each to-be-tested DRAM chip in real time; S2.3: monitoring feedback: comparing the selected electrical parameters of the to-be-tested DRAM chip with the damage control threshold range to determine the decision interval corresponding to each to-be-tested DRAM chip, specifically: when the selected electrical parameters are less than the lower threshold of the damage control threshold range, the to-be-tested DRAM chip is in the blue optimization zone, at which time the test stress is increased; when the selected electrical parameters are within the damage control threshold range, the to-be-tested DRAM chip is in the green safety zone, at which time the test parameters are maintained; when the selected electrical parameters are greater than the upper threshold of the damage control threshold range, the to-be-tested DRAM chip is in the red alarm zone, at which time the test stress is reduced; S3: test determination: performing functional test on each to-be-tested DRAM chip to determine the chip test result, specifically: when the to-be-tested DRAM chip fails in function, it is a defective chip, otherwise, it is a good chip.

2. The method of claim 1, wherein the method further comprises: The correlation model between real-time monitoring parameters and long-term life of chips is constructed, comprising: S1.1: determining sample chips: determining the required sample number corresponding to the set confidence score and error range, and randomly extracting reference chip samples from the current production line through multiple variation dimensions and the required sample number; S1.2: sample test: performing accelerated aging test on the reference chip samples under high voltage and high temperature, and monitoring the selected electrical parameters, and performing high-temperature working life test on the tested reference chip samples to obtain the high-temperature working life corresponding to each reference chip sample; S1.3: quantitative correlation: taking the selected electrical parameters and high-temperature working life as the input of the statistical analysis model, and outputting the corresponding nonlinear regression model, specifically: ， wherein: is the high temperature operational lifetime of the selected electrical parameter being monitored, is a scaling factor, is the base of the natural logarithm, is the decay rate, is the selected electrical parameter being monitored, is the asymptote.

3. The aging test method for a dynamic random access memory according to claim 2, characterized in that, determining the modeling data pair of each reference chip sample according to the selected electrical parameters and high-temperature working life corresponding to each reference chip sample, taking the modeling data pair as the input of the statistical analysis model, and outputting the corresponding scaling coefficient, decay rate and asymptote through nonlinear regression analysis of the statistical analysis model.

4. The aging test method for a dynamic random access memory according to claim 1, characterized in that, The stress applying module comprises a high-temperature unit and a power supply unit, the high-temperature unit and the power supply unit are connected through a load board, and the to-be-tested DRAM chip is fixed on the load board, the high-temperature unit is used for providing the environmental temperature required by the aging test, and the power supply unit is used for providing the working voltage required by the aging test.

5. The method of claim 1, wherein the method further comprises: determining a number of refreshes of the memory cell; and determining a number of refreshes of the memory cell that are required to reach a predetermined threshold of the memory cell. 5 The online monitoring module comprises a measurement unit and a multi-way switch, the measurement unit and the multi-way switch are connected, the measurement unit is used for monitoring the Iddq change rate of the to-be-tested DRAM chip, and the multi-way switch is used for measurement switching between multiple to-be-tested DRAM chips in the aging test.

6. The method of claim 1, wherein the method further comprises: The test parameters corresponding to each to-be-tested DRAM chip are adjusted through the damage control threshold range, comprising: S2.3.1: determining the deviation: according to the damage control threshold range, the center value of the damage control threshold range is determined as the center line of the green safety zone, and the selected electrical parameters of the to-be-tested DRAM chip in the blue optimization zone / red alert zone are compared with the center line of the green safety zone to obtain the real-time deviation of each to-be-tested DRAM chip; S2.3.2: determining the proportion coefficient: the reference chip sample is closed-loop tested, the reference chip sample is equally divided according to the size of the preset proportion coefficient value sequence, and the divided to-be-tested reference chip sample is tested with the corresponding preset proportion coefficient value to obtain the corresponding to-be-tested reference chip sample curve, and the final proportion coefficient value is determined according to the to-be-tested reference chip sample curve; S2.3.3: determining the adjustment voltage: the real-time deviation of the to-be-tested DRAM chip and the final proportion coefficient value are combined to determine the corresponding voltage adjustment amount, specifically: ， wherein: is a voltage adjustment amount, is a proportional coefficient value, is a real-time deviation.

7. The aging test method for a dynamic random access memory according to claim 6, characterized in that, According to all to-be-tested reference chip sample curves corresponding to the same proportion coefficient value, the average value of all to-be-tested reference chip sample curves is determined as the system response curve corresponding to the proportion coefficient value, and the stable overshoot data corresponding to each proportion coefficient value is determined according to the system response curve, and all stable overshoot data are compared to determine the minimum stable overshoot data, and the proportion coefficient value corresponding to the minimum stable overshoot data is the final proportion coefficient value.

8. The aging test method for a dynamic random access memory according to claim 7, characterized in that, According to the system response curve corresponding to the proportion coefficient value, the stable time required from the start of the test to the green safety zone is taken as the stable time corresponding to the proportion coefficient value, the difference between the peak value of the system response curve and the center line of the green safety zone is taken as the overshoot amount corresponding to the proportion coefficient value, and the stable overshoot data corresponding to the proportion coefficient value is obtained according to the stable time and the overshoot amount corresponding to the proportion coefficient value, specifically: ， wherein: is the stable overshoot data, is the stable time, is the overshoot amount.

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