Double-PFC input power supply circuit and high-frequency interleaving control method thereof

Abstract

The invention discloses a double-PFC input power supply circuit and a high-frequency interleaving control method thereof, the double-PFC input power supply circuit comprises two PFC circuits which are connected in parallel, two micro-control units MCU are used for controlling the two PFC circuits to work respectively, a synchronous circuit is arranged between the two micro-control units, the synchronous circuit is used for sending a synchronous signal between the two micro-control units MCU, and the two PFC circuits are connected in parallel. Therefore, the same-frequency interleaving control of the driving signals of the two PFC circuits is realized. Independent working modes of the two PFC circuits are reserved, fault isolation is achieved, the reliability of system operation is improved, a high-frequency interleaving control mode is implemented on the two PFC circuits through the two micro-control units, parallel interleaving driving of the two PFC circuits is achieved, input current ripples are reduced, the power density is improved, the load efficiency is improved, and the system reliability is improved. And the system reliability is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of double-input AC-DC converter, and particularly relates to a double-PFC input power supply circuit and a high-frequency stagger control method thereof. BACKGROUND

[0002] With the rapid development of science and technology, electronic products gradually play an important role in various aspects of people's life and work. As the heart of electronic products, power supply plays an irreplaceable role. The development of double-input power supply is the result of the interweaving of reliability demand, energy transformation and technological progress. With the increasing penetration of renewable energy and the maturity of digital control technology, its application scenarios will further expand to smart home, edge computing and other emerging fields, becoming one of the key technologies for building flexible energy systems.

[0003] At present, the double-PFC control is mostly in the mode of controlling the stagger of 180° by the same MCU or in the mode of sharing the same bus capacitor by the parallel connection of the outputs of two PFCs. The former two PFC circuits are in a non-independent working mode and are not suitable for redundancy or shunt power supply scenarios. The latter has large ripple and low efficiency, and needs more capacitors to cope with the ripple current. SUMMARY

[0004] Therefore, it is necessary to provide a double-PFC input power supply circuit and a high-frequency stagger control method thereof, which can meet the independent working mode, have small current ripple and high efficiency.

[0005] A double-PFC input power supply circuit includes two parallel connected PFC circuits, each of which has a micro control unit MCU, and two micro control units MCU are used to control the working of two PFC circuits respectively, and a synchronization circuit is arranged between the two micro control units. The two micro control units MCU include a master control unit MCU1 and a slave control unit MCU2, and the synchronization circuit is used for the master control unit MCU1 to send a high-frequency synchronization signal SYN to the slave control unit MCU2 to realize the same-frequency stagger control of the driving signals of two PFC circuits.

[0006] Preferably, the two PFC circuits include a first PFC circuit and a second PFC circuit, the input ends of the first PFC circuit and the second PFC circuit are connected to the same AC power supply end or different AC power supply ends, the output ends of the first PFC circuit and the second PFC circuit are connected in parallel to the load end, the first PFC circuit includes a first switch tube S1, and the second PFC circuit includes a second switch tube S2.

[0007] Preferably, the input end of the main control unit MCU1 is connected to the input end of the first PFC circuit, the output end of the main control unit MCU1 is connected to the gate of the first switch tube S1, and the main control unit MCU1 is used to send a driving signal to the first switch tube S1. The input end of the slave control unit MCU2 is connected to the input end of the second PFC circuit, the output end of the slave control unit MCU2 is connected to the gate of the second switch tube S2, and the slave control unit MCU2 is used to send a driving signal to the second switch tube S2.

[0008] Preferably, the main control unit MCU1 comprises a first timer, and the first timer is used for period timing of the main control unit MCU1. The slave control unit MCU2 comprises a second timer, and the second timer is used for period timing of the slave control unit MCU2. The timing duration of the first timer and the second timer is the same.

[0009] And a high-frequency interleaving control method of a double-PFC input power supply circuit, used to realize high-frequency interleaving control of the switch tubes of the two PFC circuits in the double-PFC input power supply circuit, the specific steps of the method comprising: Step one, circuit configuration; the two PFC circuits are arranged in parallel, the output ends of the two micro control units MCU are respectively connected to the first switch tube S1 of the first PFC circuit and the second switch tube S2 of the second PFC circuit, and a synchronization circuit is arranged between the main control unit MCU1 and the slave control unit MCU2; Step two, the main control unit MCU1 generates a first period signal; the device is powered on to start, and the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2 start; Step three, a high-frequency synchronization signal SYN is generated, and the high-frequency synchronization signal SYN is transmitted from the main control unit MCU1 to the slave control unit MCU2; Step four, the slave control unit MCU2 generates a synchronized second period signal; after the second timer is controlled to clear by the high-frequency synchronization signal SYN, the second timer restarts timing; Step five, the main control unit MCU1 and the slave control unit MCU2 generate interleaving wave; Step six, the main control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit to work respectively according to the interleaving wave.

[0010] Preferably, the step two, the specific steps of the main control unit MCU1 generating a first period signal comprising: Step 2.1: Power on the device and start it up; Step 2.2: The main control unit MCU1 and the slave control unit MCU2 synchronize their clocks via a phase-locked loop (PLL). Step 2.3: Start the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2; Step 2.4: The main control unit MCU1 generates a first cycle signal according to the timing duration of the first timer; Step 2.5: The control unit MCU2 generates a second cycle signal based on the timing duration of the second timer.

[0011] Preferably, step three, generating the high-frequency synchronization signal SYN, includes the following specific steps: Step 3.1: The first timer starts counting from 0. After the time count value increases from 0 to a predetermined value for a predetermined duration, the first timer is reset to zero and restarts counting. Step 3.2: In the main control unit MCU1, when the time count value of the first timer is 0, the high-frequency synchronization signal SYN flips from low level to high level; when the time count value of the first timer is half of the predetermined duration, the high-frequency synchronization signal SYN flips from high level to low level. Step 3.3: The high-frequency synchronization signal SYN is transmitted from the main control unit MCU1 to the slave control unit MCU2 via the synchronization circuit.

[0012] Preferably, step four, which involves generating a synchronized second-cycle signal from the control unit MCU2, includes the following steps: Step 4.1: Receive the high-frequency synchronization signal SYN from the control unit MCU2; Step 4.2: The rising edge of the high-frequency synchronization signal SYN triggers the second timer to be cleared; Step 4.3: The second timer restarts from 0, and the time count value increases from 0 to a predetermined value for a predetermined duration; Step 4.4: The control unit MCU2 generates a second cycle signal based on the timing duration of the second timer.

[0013] Preferably, step five, the specific steps for the main control unit MCU1 and the slave control unit MCU2 to generate interleaved waveforms, include: Step 5.1, the main control unit MCU1 generates a first high-frequency drive signal, which spreads out to both sides from halfway point of the first cycle signal; Step 5.2: Generate a second high-frequency drive signal from the control unit MCU2. The second high-frequency drive signal expands to both sides from the starting point of the second periodic signal.

[0014] Preferably, step six, in which the main control unit MCU1 and the slave control unit MCU2 control the operation of the first PFC circuit and the second PFC circuit respectively according to interleaved waveforms, includes the following specific steps: Step 6.1: The main control unit MCU1 samples the input voltage Vin1, input current Iin1 and output voltage Vout of the first PFC circuit, runs the PFC control algorithm, the voltage loop generates a current command based on the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the first high-frequency drive signal based on the current command and the sampled input current Iin1. Step 6.2: The input voltage Vin2, input current Iin2 and output voltage Vout of the second PFC circuit are sampled from the control unit MCU2. The PFC control algorithm is run. The voltage loop generates a current command based on the error of the output voltage Vout. The current loop calculates the PWM duty cycle of the second high-frequency drive signal based on the current command and the sampled input current Iin2. Step 6.3: Send the first high-frequency drive signal and the second high-frequency drive signal to the gate of the first switch S1 of the first PFC circuit and the gate of the second switch S2 of the second PFC circuit, respectively.

[0015] In the aforementioned dual PFC input power supply circuit and its high-frequency interleaved control method, the main control unit MCU1 and the slave control unit MCU2 respectively control the first PFC circuit and the second PFC circuit, which are connected in parallel. This allows the first PFC circuit and the second PFC circuit to maintain independent operating modes, achieving fault isolation and improving the reliability of system operation. Simultaneously, the main control unit MCU1 and the slave control unit MCU2 implement high-frequency interleaved control on the first PFC circuit and the second PFC circuit, realizing parallel interleaved drive of the two PFC circuits, reducing input current ripple, increasing power density, improving load efficiency, and enhancing system reliability. This invention has a simple structure, is easy to implement, has low cost, and is easy to promote. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the dual PFC input power supply circuit according to an embodiment of the present invention.

[0017] Figure 2 This is a flowchart of a high-frequency interleaving control method for a dual PFC input power supply circuit according to an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the high-frequency interleaving control method for the dual PFC input power supply circuit according to an embodiment of the present invention. Detailed Implementation

[0019] This embodiment takes a dual PFC input power supply circuit and its high-frequency interleaving control method as an example. The present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0020] Please see Figure 1 This invention illustrates a dual PFC input power supply circuit provided by an embodiment of the present invention, comprising two parallel PFC circuits, each of which has a microcontroller unit (MCU), the two MCUs being used to control the operation of the two PFC circuits respectively, and a synchronization circuit being provided between the two MCUs. The two microcontroller units (MCUs) include a master control unit (MCU1) and a slave control unit (MCU2). The synchronization circuit is used for the master control unit (MCU1) to send a high-frequency synchronization signal SYN to the slave control unit (MCU2) to achieve synchronous interleaving control of the drive signals of the two PFC circuits.

[0021] Specifically, power factor correction (PFC) circuits are mainly used to improve the power factor of AC-DC conversion systems and reduce harmonic pollution. PFC circuits improve energy utilization efficiency by adjusting the input current waveform to be in phase with the input voltage waveform.

[0022] By connecting two PFC circuits in parallel, high-power loads can be shared, making it suitable for high-power applications. The two PFC circuits with interleaved control can cancel out some of the ripple, making the input current smoother. This improves system efficiency, enhances housing reliability, and makes the two PFC circuits in parallel more suitable for high-power applications.

[0023] Preferably, the two PFC circuits include a first PFC circuit and a second PFC circuit. The input terminals of the first PFC circuit and the second PFC circuit are connected to the same AC power supply or different AC power supply terminals. The output terminals of the first PFC circuit and the second PFC circuit are connected in parallel to the load terminal. The first PFC circuit includes a first switching transistor S1, and the second PFC circuit includes a second switching transistor S2.

[0024] Preferably, the input terminal of the main control unit MCU1 is connected to the input terminal of the first PFC circuit, and the output terminal of the main control unit MCU1 is connected to the gate of the first switching transistor S1. The main control unit MCU1 is used to send a drive signal to the first switching transistor S1. The input terminal of the slave control unit MCU2 is connected to the input terminal of the second PFC circuit, and the output terminal of the slave control unit MCU2 is connected to the gate of the second switching transistor S2. The slave control unit MCU2 is used to send a drive signal to the second switching transistor S2.

[0025] Specifically, the main control unit MCU1 and the slave control unit MCU2 use communication protocols such as SPI, I2C, UART or USART to realize the transmission of high-frequency synchronization signal SYN.

[0026] The synchronization circuit achieves impedance matching by using shielding wires and terminating resistors, thereby avoiding electromagnetic interference and ensuring signal integrity.

[0027] Preferably, the main control unit MCU1 includes a first timer, which is used for timing the period of the main control unit MCU1; The slave control unit MCU2 includes a second timer, which is used for timing the period of the slave control unit MCU2; The first timer and the second timer have the same timing duration.

[0028] Specifically, the first timer and the second timer have a predetermined timing duration. After the predetermined timing duration has elapsed, the first timer and the second timer are reset to zero and the timing restarts.

[0029] Specifically, the predetermined timing duration of the first timer and the second timer depends on the frequency and period of the drive signal of the switching transistor in the PFC circuit. The higher the frequency of the switching transistor and the shorter the period, the shorter the timing duration of the first timer and the second timer; conversely, the lower the frequency of the switching transistor and the longer the period, the longer the timing duration of the first timer and the second timer.

[0030] And, please see Figure 2 This paper presents a high-frequency interleaved control method for a dual PFC input power supply circuit, used to achieve high-frequency interleaved control of the switching transistors of the two PFC circuits in the dual PFC input power supply circuit described above. The specific steps of the method include: Step S10, circuit configuration: Two PFC circuits are set in parallel, and the output terminals of the two microcontrollers (MCUs) are respectively connected to the first switch S1 of the first PFC circuit and the second switch S2 of the second PFC circuit; a synchronization circuit is set between the master control unit MCU1 and the slave control unit MCU2.

[0031] Specifically, the operating frequency of the PFC is set in the main control unit MCU1, and the corresponding switching cycle is calculated.

[0032] Step S20: The main control unit MCU1 generates a first cycle signal; the device is powered on and started, and the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2 are started.

[0033] The specific steps include: Step S21: Power on the device and start it up; Step S22: The main control unit MCU1 and the slave control unit MCU2 synchronize their clocks through a phase-locked loop (PLL). Step S23: The first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2 are started; Step S24: The main control unit MCU1 generates a first cycle signal according to the timing duration of the first timer; Step S25: The control unit MCU2 generates a second cycle signal based on the timing duration of the second timer.

[0034] Step S30: Generate a high-frequency synchronization signal SYN and transmit the high-frequency synchronization signal SYN from the main control unit MCU1 to the slave control unit MCU2.

[0035] The specific steps include: Step S31: The first timer starts counting from 0. After the time count value increases from 0 to a predetermined value for a predetermined duration, the first timer is reset to zero and starts counting again. Step S32: In the main control unit MCU1, when the time count value of the first timer is 0, the high-frequency synchronization signal SYN flips from low level to high level; when the time count value of the first timer is half of the predetermined duration, the high-frequency synchronization signal SYN flips from high level to low level. Step S33: The high-frequency synchronization signal SYN is transmitted from the main control unit MCU1 to the slave control unit MCU2 through the synchronization circuit.

[0036] Step S40: A second cycle signal for synchronization is generated from the control unit MCU2; after the second timer is cleared by the high-frequency synchronization signal SYN, the second timer restarts its timing.

[0037] The specific steps include: Step S41: Receive high-frequency synchronization signal SYN from control unit MCU2; Step S42: The rising edge of the high-frequency synchronization signal SYN triggers the second timer to be cleared; Step S43: The second timer restarts from 0, and the time count value increases from 0 to a predetermined value for a predetermined duration; Step S44: The control unit MCU2 generates a second cycle signal based on the timing duration of the second timer.

[0038] Specifically, under the action of the high-frequency synchronization signal SYN, the first timer in the main control unit MCU1 is synchronized with the second timer in the slave control unit MCU2. Therefore, the first periodic signal generated by the main control unit MCU1 is synchronized with the second periodic signal generated by the slave control unit MCU2.

[0039] In step S50, the main control unit MCU1 and the slave control unit MCU2 generate interleaved waveforms.

[0040] The specific steps include: Step S51: The main control unit MCU1 generates a first high-frequency drive signal, which spreads out to both sides from halfway point of the first cycle signal. Step S52: A second high-frequency drive signal is generated from the control unit MCU2. The second high-frequency drive signal expands to both sides from the starting point of the second periodic signal.

[0041] Specifically, the first high-frequency drive signal and the second high-frequency drive signal are out of phase by 180°. In order to provide power density for the circuit, the duty cycle of the first high-frequency drive signal and the second high-frequency drive signal is less than 50%. By reducing ripple current and optimizing the operating point, the system efficiency is improved.

[0042] In step S60, the main control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit to work respectively according to the interleaved waveform.

[0043] The specific steps include: In step S61, the main control unit MCU1 samples the input voltage Vin1, input current Iin1 and output voltage Vout of the first PFC circuit, runs the PFC control algorithm, the voltage loop generates a current command based on the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the first high-frequency drive signal based on the current command and the sampled input current Iin1. Step S62: The input voltage Vin2, input current Iin2 and output voltage Vout of the second PFC circuit are sampled from the control unit MCU2. The PFC control algorithm is run. The voltage loop generates a current command based on the error of the output voltage Vout. The current loop calculates the PWM duty cycle of the second high-frequency drive signal based on the current command and the sampled input current Iin2. Step S63: The first high-frequency drive signal and the second high-frequency drive signal are respectively sent to the gate of the first switch S1 of the first PFC circuit and the gate of the second switch S2 of the second PFC circuit.

[0044] Specifically, the operation of dual PFC is controlled by two MCUs. Although the two channels will be controlled to the same operating frequency in software control, the unavoidable differences between the two MCUs make it impossible to guarantee that the frequencies of the two PFC channels are completely consistent. This will lead to input current beat frequency effect, which may affect the normal operation of the load. Therefore, it is necessary to ensure that the operating frequencies of the two PFC channels are completely consistent.

[0045] In this embodiment, the dual PFC circuits are each independently controlled by a microcontroller unit (MCU). Under these conditions, such as Figure 3 As shown, the MCU determines the timer period value based on the timer's period value. Figure 3 The P value indicates the operating frequency. The timer counts from 0 to P and then resets to 0, performing periodic counting. Figure 3 It can be seen that when MCU1's cycle count reaches P, MCU2's count value has not yet reached P. Assuming the operating frequency error time between MCU1 and MCU2 is t0, it can be seen that when MCU1's cycle count reaches P, MCU2's count value is at (P-t0). However, at this time, MCU2 has not reached the counting cycle value P and therefore does not reset, while MCU1 has reached the cycle value P and has already reset. Only by ensuring that the counts of MCU1 and MCU2 are completely synchronized can they guarantee complete frequency synchronization and interleaving. Therefore, before the two PFC circuits are working normally and emitting PWM, a high-frequency synchronization signal SYN is needed to immediately synchronize them before power-on. This signal is transmitted from MCU1 to MCU2. When MCU1's timer count is 0 (P), the high-frequency synchronization signal flips from low to high. At P / 2, it flips from high to low. When MCU2's timer count reaches (P-t0), it receives the high-frequency synchronization signal SYN from MCU1. MCU2 uses the rising edge of the high-frequency synchronization signal SYN as a trigger condition to reset the timer counter, completing the timer synchronization of MCU1 and MCU2. After the PFC circuit starts sending PWM, the timer counting period of MCU2 is finely adjusted to ensure real-time dynamic synchronization. This fine adjustment is strictly limited to ensure it does not affect current harmonics, power factor, or other operating states, causing P-t0 to approach 0(P). Based on this, we can achieve... Figure 3 The staggered waveforms shown are as follows: SYN_MCU1_PWM waveforms spread outwards from P / 2, while SYN_MCU2_PWM waveforms spread outwards from P, ensuring a 180° stagger.

[0046] Figure 3 The annotations for each signal in the code are as follows: MCU1-MasterTimer — The timer counter for MCU1; MCU2-MasterTimer — The timer counter for MCU2; SYN—A high-frequency synchronization signal from MCU1 to MCU2; SYN_MCU2-MaterTimer — The timer counter of MCU2 after synchronization; SYN_MCU1_PWM — The PWM waveform of MCU1 after the counter is synchronized; SYN_MCU2_PWM — PWM waveform generation of MCU2 after counter synchronization.

[0047] In the aforementioned dual PFC input power supply circuit and its high-frequency interleaved control method, the main control unit MCU1 and the slave control unit MCU2 respectively control the first PFC circuit and the second PFC circuit, which are connected in parallel. This allows the first PFC circuit and the second PFC circuit to maintain independent operating modes, achieving fault isolation and improving the reliability of system operation. Simultaneously, the main control unit MCU1 and the slave control unit MCU2 implement high-frequency interleaved control on the first PFC circuit and the second PFC circuit, realizing parallel interleaved drive of the two PFC circuits, reducing input current ripple, increasing power density, improving load efficiency, and enhancing system reliability. This invention has a simple structure, is easy to implement, has low cost, and is easy to promote.

[0048] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dual PFC input power supply circuit, comprising two parallel-connected PFC circuits, characterized in that, Each of the PFC circuits has a microcontroller unit (MCU), and the two MCUs are used to control the operation of the two PFC circuits respectively. A synchronization circuit is provided between the two MCUs. The two microcontroller units (MCUs) include a master control unit (MCU1) and a slave control unit (MCU2). The synchronization circuit is used for the master control unit (MCU1) to send a high-frequency synchronization signal SYN to the slave control unit (MCU2) to achieve synchronous interleaving control of the drive signals of the two PFC circuits.

2. The dual PFC input power supply circuit as described in claim 1, characterized in that, The two PFC circuits include a first PFC circuit and a second PFC circuit. The input terminals of the first PFC circuit and the second PFC circuit are connected to the same AC power supply terminal or different AC power supply terminals. The output terminals of the first PFC circuit and the second PFC circuit are connected in parallel to the load terminal. The first PFC circuit includes a first switching transistor S1, and the second PFC circuit includes a second switching transistor S2.

3. The dual PFC input power supply circuit as described in claim 2, characterized in that, The input terminal of the main control unit MCU1 is connected to the input terminal of the first PFC circuit, and the output terminal of the main control unit MCU1 is connected to the gate of the first switching transistor S1. The main control unit MCU1 is used to send a drive signal to the first switching transistor S1. The input terminal of the slave control unit MCU2 is connected to the input terminal of the second PFC circuit, and the output terminal of the slave control unit MCU2 is connected to the gate of the second switching transistor S2. The slave control unit MCU2 is used to send a drive signal to the second switching transistor S2.

4. The dual PFC input power supply circuit as described in claim 1, characterized in that, The main control unit MCU1 includes a first timer, which is used for timing the period of the main control unit MCU1; The slave control unit MCU2 includes a second timer, which is used for timing the period of the slave control unit MCU2; The first timer and the second timer have the same timing duration.

5. A high-frequency interleaved control method for a dual PFC input power supply circuit, used to achieve high-frequency interleaved control of the switching transistors of the two PFC circuits in the dual PFC input power supply circuit as described in any one of claims 1-4, characterized in that, The specific steps of the method include: Step 1, Circuit Configuration: Two PFC circuits are connected in parallel, and the outputs of the two microcontrollers (MCUs) are respectively connected to the first switch S1 of the first PFC circuit and the second switch S2 of the second PFC circuit; a synchronization circuit is set between the master control unit MCU1 and the slave control unit MCU2. Step 2: The main control unit MCU1 generates the first cycle signal; the device is powered on and started, and the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2 are started. Step 3: Generate a high-frequency synchronization signal SYN and transmit the high-frequency synchronization signal SYN from the main control unit MCU1 to the slave control unit MCU2; Step 4: Generate a second cycle signal for synchronization from the control unit MCU2; after the second timer is cleared by the high-frequency synchronization signal SYN, the second timer restarts its timing. Step 5: The main control unit MCU1 and the slave control unit MCU2 generate interleaved waveforms; Step six: The main control unit MCU1 and the slave control unit MCU2 control the first PFC circuit and the second PFC circuit respectively according to the interleaved waveform.

6. The high-frequency interleaving control method for the dual PFC input power supply circuit as described in claim 5, characterized in that, Step two, the specific steps for the main control unit MCU1 to generate the first cycle signal, include: Step 2.1: Power on the device and start it up; Step 2.2: The main control unit MCU1 and the slave control unit MCU2 synchronize their clocks via a phase-locked loop (PLL). Step 2.3: Start the first timer in the main control unit MCU1 and the second timer in the slave control unit MCU2; Step 2.4: The main control unit MCU1 generates a first cycle signal according to the timing duration of the first timer; Step 2.5: The control unit MCU2 generates a second cycle signal based on the timing duration of the second timer.

7. The high-frequency interleaving control method for the dual PFC input power supply circuit as described in claim 5, characterized in that, Step three, the specific steps for generating the high-frequency synchronization signal SYN, include: Step 3.1: The first timer starts counting from 0. After the time count value increases from 0 to a predetermined value for a predetermined duration, the first timer is reset to zero and restarts counting. Step 3.2: In the main control unit MCU1, when the time count value of the first timer is 0, the high-frequency synchronization signal SYN flips from low level to high level; when the time count value of the first timer is half of the predetermined duration, the high-frequency synchronization signal SYN flips from high level to low level. Step 3.3: The high-frequency synchronization signal SYN is transmitted from the main control unit MCU1 to the slave control unit MCU2 via the synchronization circuit.

8. The high-frequency interleaving control method for the dual PFC input power supply circuit as described in claim 5, characterized in that, Step four, which involves generating a synchronized second-cycle signal from the control unit MCU2, includes the following steps: Step 4.1: Receive the high-frequency synchronization signal SYN from the control unit MCU2; Step 4.2: The rising edge of the high-frequency synchronization signal SYN triggers the second timer to be cleared; Step 4.3: The second timer restarts from 0, and the time count value increases from 0 to a predetermined value for a predetermined duration; Step 4.4: The control unit MCU2 generates a second cycle signal based on the timing duration of the second timer.

9. The high-frequency interleaving control method for the dual PFC input power supply circuit as described in claim 5, characterized in that, Step five, the specific steps for the main control unit MCU1 and the slave control unit MCU2 to generate interleaved waveforms, include: Step 5.1, the main control unit MCU1 generates a first high-frequency drive signal, which spreads out to both sides from halfway point of the first cycle signal; Step 5.2: Generate a second high-frequency drive signal from the control unit MCU2. The second high-frequency drive signal expands to both sides from the starting point of the second periodic signal.

10. The high-frequency interleaving control method for the dual PFC input power supply circuit as described in claim 5, characterized in that, Step six, in which the main control unit MCU1 and the slave control unit MCU2 control the operation of the first PFC circuit and the second PFC circuit respectively based on interleaved waveforms, includes the following specific steps: Step 6.1: The main control unit MCU1 samples the input voltage Vin1, input current Iin1 and output voltage Vout of the first PFC circuit, runs the PFC control algorithm, the voltage loop generates a current command based on the error of the output voltage Vout, and the current loop calculates the PWM duty cycle of the first high-frequency drive signal based on the current command and the sampled input current Iin1. Step 6.2: The input voltage Vin2, input current Iin2 and output voltage Vout of the second PFC circuit are sampled from the control unit MCU2. The PFC control algorithm is run. The voltage loop generates a current command based on the error of the output voltage Vout. The current loop calculates the PWM duty cycle of the second high-frequency drive signal based on the current command and the sampled input current Iin2. Step 6.3: Send the first high-frequency drive signal and the second high-frequency drive signal to the gate of the first switch S1 of the first PFC circuit and the gate of the second switch S2 of the second PFC circuit, respectively.

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