Isolation type MOSFET device structure capable of reducing device electric leakage and preparation method of isolation type MOSFET device structure

Abstract

The invention relates to an isolation type MOSFET device structure capable of reducing device electric leakage and a preparation method. The device structure comprises a substrate, an epitaxial region, a deep isolation well, an ion implantation well, a source region, a drain region, an isolation region, a body region, a region, source electrode metal, drain electrode metal, isolation region electrode metal, body electrode metal, region electrode metal, a gate oxide layer and a gate electrode. The epitaxial region is located on the substrate; the deep isolation well extends into the epitaxial region from the surface of the epitaxial region; the ion implantation well extends into the deep isolation well from the surface of the deep isolation well; the source region, the drain region and the body region extend from the surface of the ion implantation well to the interior of the ion implantation well; the isolation region extends into the deep isolation well from the surface of the deep isolation well; the region extends from the surface of the epitaxial region to the interior of the epitaxial region; the gate oxide layer is located on the ion implantation well; the gate electrode is located on the gate oxide layer. According to the structure, the leakage current of the device is reduced, and the breakdown resistance and crosstalk resistance of the device are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an isolated MOSFET device structure and fabrication method for reducing device leakage current. Background Technology

[0002] Silicon carbide (SiC), as a wide-bandgap semiconductor, is receiving increasing attention and research in integrated circuit device design. Power integrated circuits made from SiC have advantages such as high input impedance, good temperature characteristics, strong voltage withstand capability, excellent frequency characteristics, and fast switching speed, and are widely used in various fields.

[0003] Existing silicon carbide power integrated circuits mostly use power circuit modules fabricated with vertical power devices and low-voltage circuit modules fabricated with horizontal devices for integration. During fabrication, it is necessary to first fabricate the devices separately, integrate the devices, and then perform circuit-level packaging integration. This process is complicated and time-consuming. Therefore, designing a BCD integration process with all horizontal devices is an important requirement.

[0004] However, when all devices are integrated on the same wafer, low-voltage MOSFETs are affected by high-voltage regions, which can cause problems such as leakage and threshold drift. Summary of the Invention To address the aforementioned problems in the prior art, this invention provides an isolated MOSFET device structure and fabrication method for reducing device leakage current. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides an isolated MOSFET device structure for reducing leakage current, comprising: a substrate, an epitaxial region, a deep isolation trap, an ion implantation trap, a source region, a drain region, an isolation region, a body region, a ground region, a source metal, a drain metal, an isolation region electrode metal, a body metal, a ground region electrode metal, a gate oxide layer, and a gate electrode. The epitaxial region is located on the substrate; the deep isolation trap extends from the surface of the epitaxial region to the interior of the epitaxial region, and its width is smaller than the width of the epitaxial region; the ion implantation trap extends from the surface of the deep isolation trap to the interior of the deep isolation trap, and its width is smaller than the width of the deep isolation trap. The source region, the drain region, and the body region all extend from the surface of the ion implantation trap to the interior of the ion implantation trap and are spaced apart; the isolation region extends from the surface of the deep isolation trap to the interior of the deep isolation trap and is spaced apart from the ion implantation trap; the region extends from the surface of the epitaxial region to the interior of the epitaxial region and is spaced apart from the deep isolation trap. The source metal, the drain metal, the body metal, the isolation region electrode metal, and the region electrode metal are respectively located on the source region, the drain region, the body region, the isolation region, and the region. The gate oxide layer is located on the ion implantation trap, and its ends partially overlap with the source and drain regions; the gate electrode is located on the gate oxide layer; The substrate, the deep isolation trap, the source region, the drain region, and the isolation region have a first conductivity type, and the epitaxial region, the ion implantation trap, the body region, and the region have a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

[0005] In one embodiment of the present invention, the body region includes a first sub-body region and a second sub-body region, wherein, The source region, the drain region, the first sub-region, and the second sub-region are distributed at intervals, and the source region and the drain region are located between the first sub-region and the second sub-region.

[0006] In one embodiment of the present invention, the isolation region includes a first sub-isolation region and a second sub-isolation region, wherein, The first sub-isolation region is located in the deep isolation trap between the first end of the deep isolation trap and the first end of the ion implantation trap; The second sub-isolation region is located in the deep isolation trap between the second end of the deep isolation trap and the second end of the ion implantation trap.

[0007] In one embodiment of the present invention, the region includes a first sub-region and a second sub-region, wherein, The first sub-region is located in the epitaxial region between the first end of the epitaxial region and the first end of the deep isolation trap; The second sub-region is located in the epitaxial region between the second end of the epitaxial region and the second end of the deep isolation trap.

[0008] In one embodiment of the present invention, the substrate material comprises 4H-SiC with a doping concentration of 5e18cm. -3 ; The material of the epitaxial region includes 4H-SiC with a thickness of 6~10μm.

[0009] In one embodiment of the present invention, the doping concentration of the deep isolation well is less than or equal to 5e16cm. -3 The depth is 1.5~2μm; The doping concentration of the ion implantation trap is greater than or equal to 5e17cm. -3 The depth is 0.6~1.0μm.

[0010] In one embodiment of the present invention, the doping concentration of the body region and the region is greater than or equal to 1e19cm. -3 ; The doping concentration of the source region, the drain region, and the isolation region is greater than or equal to 1e19cm.-3 .

[0011] In one embodiment of the present invention, the width of the overlap between the end of the gate oxide layer and the source region and the drain region is 0.5~1μm.

[0012] In one embodiment of the present invention, the first conductivity type is N-type, the second conductivity type is P-type, and the isolated MOSFET device structure is nMOSFET; Alternatively, the first conductivity type is P-type, the second conductivity type is N-type, and the isolated MOSFET device structure is pMOSFET.

[0013] Another embodiment of the present invention provides a method for fabricating an isolated MOSFET device structure to reduce device leakage current, comprising the steps of: Provide substrate; An epitaxial region is formed on the substrate; A deep isolation trap is formed in the epitaxial region, extending from the surface of the epitaxial region to the interior of the epitaxial region, and having a width smaller than the width of the epitaxial region; An ion implantation trap is formed in the deep isolation trap, extending from the surface of the deep isolation trap into the interior of the deep isolation trap, and having a width smaller than the width of the deep isolation trap; A body region and a region are simultaneously formed on the sample surface, wherein the body region extends from the surface of the ion implantation trap to the interior of the ion implantation trap, and the region extends from the surface of the epitaxial region to the interior of the epitaxial region; The sample surface simultaneously contains a source region, a drain region, and an isolation region, wherein the source region and the drain region extend from the surface of the ion implantation trap to the interior of the ion implantation trap, and the isolation region extends from the surface of the deep isolation trap to the interior of the deep isolation trap; A gate oxide layer is formed on the ion implantation trap, the ends of which overlap with the source region and the drain region, and a gate electrode is formed on the gate oxide layer; Metals are deposited and annealed on the source region, the drain region, the isolation region, the body region, and the area region to form source metal, drain metal, isolation region electrode metal, body metal, and area electrode metal. The substrate, the deep isolation trap, the source region, the drain region, and the isolation region have a first conductivity type, and the epitaxial region, the ion implantation trap, the bulk region, and the region have a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: The isolated MOSFET device structure of the present invention introduces a deep isolation well and an isolation region between the device channel and the epitaxial region, forming a local isolation region in the epitaxial region. When the MOSFET device structure is working normally, it can significantly enhance the internal charge storage capacity of the device, act as a high-voltage buffer layer to improve the breakdown voltage of the device, isolate high-voltage and low-voltage circuits, and reduce the leakage current of the device by optimizing the internal electric field distribution of the device, preventing leakage current from crosstalking through the substrate, thereby improving the device's resistance to breakdown and crosstalk, thereby reducing the influence of the epitaxial region potential on the current magnitude of the device in the linear region and saturation region, and optimizing the electrical characteristics of the device under high voltage. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an isolated MOSFET device structure for reducing device leakage current, provided by an embodiment of the present invention. Figures 2a-2i A schematic diagram illustrating the process of fabricating an isolated MOSFET device structure to reduce leakage current, as provided by the present invention. Figure 3 This is a schematic diagram comparing the leakage current of a traditional 4H-SiC low-voltage nMOSFET device structure and a 4H-SiC isolated nMOSFET device structure with reduced leakage current in this embodiment, with respect to the epitaxial layer. Figure 4 A schematic diagram comparing the threshold voltage of a traditional 4H-SiC low-voltage nMOSFET device structure and a proposed 4H-SiC isolated nMOSFET device structure to reduce device leakage current. Figure 5 A schematic diagram comparing the internal leakage current of a traditional 4H-SiC low-voltage nMOSFET device structure and a proposed 4H-SiC isolated nMOSFET device structure that reduces device leakage current. Figure 6 This diagram shows a comparison of the operating current stability between the traditional 4H-SiC low-voltage nMOSFET device structure and the proposed 4H-SiC isolated nMOSFET device structure with reduced leakage current. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0017] Example 1 Please see Figure 1 , Figure 1This is a schematic diagram of an isolated MOSFET device structure for reducing device leakage current, provided by an embodiment of the present invention. The isolated metal-oxide-semiconductor field-effect transistor (MOSFET) device structure includes: a substrate 1, an epitaxial region 2, a deep isolation well 3, an ion implantation well 4, a source region 5, a drain region 6, an isolation region 7, a body region 8, a ground region 9, a source metal 10, a drain metal 11, an isolation region electrode metal 12, a body metal 13, a ground region electrode metal 14, a gate oxide layer 15, and a gate electrode 16.

[0018] Epitaxial region 2 is located on substrate 1; deep isolation well 3 extends from the surface of epitaxial region 2 to the interior of epitaxial region 2, and its width is less than the width of epitaxial region 2; ion implantation well 4 extends from the surface of deep isolation well 3 to the interior of deep isolation well 3, and its width is less than the width of deep isolation well 3; source region 5, drain region 6, and body region 8 all extend from the surface of ion implantation well 4 to the interior of ion implantation well 4 and are spaced apart; isolation region 7 extends from the surface of deep isolation well 3 to the interior of deep isolation well 3 and is spaced apart from ion implantation well 4; region 9 extends from the surface of epitaxial region 2 to the interior of epitaxial region 2 and is spaced apart from deep isolation well 3. The electrode is spaced apart; source metal 10, drain metal 11, body metal 13, isolation region electrode metal 12, and region electrode metal 14 are located on source region 5, drain region 6, body region 8, isolation region 7, and region 9 respectively; gate oxide layer 15 is located on ion implantation trap 4, and its ends partially overlap with source region 5 and drain region 6; gate electrode 16 is located on gate oxide layer 15; substrate 1, deep isolation trap 3, source region 5, drain region 6, and isolation region 7 have a first conductivity type, and epitaxial region 2, ion implantation trap 4, body region 8, and region 9 have a second conductivity type, with the first conductivity type being the opposite of the second conductivity type.

[0019] Specifically, horizontally, the deep isolation trap 3 is located in the middle of the epitaxial region 2, with its two ends spaced a certain distance from the two ends of the epitaxial region 2. Region 9 is located in the area between the end of the deep isolation trap 3 and the end of the epitaxial region 2. Horizontally, the ion implantation trap 4 is located in the middle of the deep isolation trap 3, with its two ends spaced a certain distance from the two ends of the deep isolation trap 3. Isolation region 7 is located in the area between the end of the ion implantation trap 4 and the end of the deep isolation trap 3. Source region 5 and drain region 6 are adjacent, and body region 8 is located outside source region 5 and drain region 6. The first end of the gate oxide layer 15 contacts and at least partially overlaps with source region 5, and the second end contacts and at least partially overlaps with drain region 6. Further, a device channel is formed below the gate electrode 16, i.e., between source region 5 and drain region 6.

[0020] Source metal 10 is located on source region 5. Drain metal 11 is located on drain region 6. Body metal 13 is located on body region 8. Isolation electrode metal 12 is located on isolation region 7 and does not coincide with ion implantation trap 4. Ground electrode metal 14 is located on region 9. Isolation electrode metal 12 is connected to a high potential, i.e., the highest potential of the circuit it is connected to. Body metal 13 is the base (B) of the MOSFET device, providing a base voltage to the MOSFET device, generally the same as the source potential, to prevent base potential fluctuations, ensuring stable device operation and preventing parasitic effects. Ground electrode metal 14 mainly functions as a test electrode, measuring the leakage current of the external epitaxial layer. When necessary, 0V can be applied to further stabilize the device operation.

[0021] Substrate 1, deep isolation well 3, source region 5, drain region 6, and isolation region 7 have the same first conductivity type, while epitaxial region 2, ion implantation well 4, body region 8, and isolation region 9 have the same second conductivity type. If the first conductivity type is N-type and the second conductivity type is P-type, then the isolated MOSFET device structure is an nMOSFET; or, if the first conductivity type is P-type and the second conductivity type is N-type, then the isolated MOSFET device structure is a pMOSFET.

[0022] The isolated MOSFET device structure of this embodiment introduces a deep isolation well and isolation region between the device channel and the epitaxial region, forming a local isolation region in the epitaxial region. When the MOSFET device structure is working normally, it can significantly enhance the internal charge storage capacity of the device, act as a high-voltage buffer layer to improve the breakdown voltage of the device, isolate high-voltage and low-voltage circuits, and reduce the leakage current of the device by optimizing the internal electric field distribution of the device, preventing leakage current from crosstalking through the substrate, thereby improving the device's resistance to breakdown and crosstalk. This reduces the influence of the epitaxial region potential on the current magnitude of the device in the linear and saturation regions, optimizes the electrical characteristics of the device under high voltage, and improves the problem of leakage current being greatly affected by external potential in existing low-voltage MOSFET structures, which is beneficial to the design and research of high and low voltage integrated circuits.

[0023] In one specific embodiment, there are two body areas 8, two isolation areas 7, and two areas 9.

[0024] Specifically, the body region 8 includes a first sub-body region 81 and a second sub-body region 82, wherein the source region 5, the drain region 6, the first sub-body region 81, and the second sub-body region 82 are distributed at intervals, and the source region 5 and the drain region 6 are located between the first sub-body region 81 and the second sub-body region 82.

[0025] The isolation region 7 includes a first sub-isolation region 71 and a second sub-isolation region 72, wherein the first sub-isolation region 71 is located in the deep isolation trap 3 between the first end of the deep isolation trap 3 and the first end of the ion implantation trap 4; and the second sub-isolation region 72 is located in the deep isolation trap 3 between the second end of the deep isolation trap 3 and the second end of the ion implantation trap 4.

[0026] Region 9 includes a first sub-region 91 and a second sub-region 92, wherein the first sub-region 91 is located in the extension region 2 between the first end of the extension region 2 and the first end of the deep isolation trap 3; and the second sub-region 92 is located in the extension region 2 between the second end of the extension region 2 and the second end of the deep isolation trap 3.

[0027] It can be understood that, along the horizontal direction, the source region 5, the leak region 6, the body region 8, the isolation region 7, and the region 9 are distributed in the following order: first sub-region 91, first sub-isolation region 71, first sub-body region 81, source region 5, leak region 6, second sub-body region 82, second sub-isolation region 72, and second sub-region 92.

[0028] In one specific embodiment, the substrate 1 is made of 4H-SiC with a doping concentration of 5e18cm. -3 The epitaxial region 2 is made of 4H-SiC with a thickness of 6~10 μm. The doping concentration of the deep isolation well 3 is less than or equal to 5e16cm. -3 The depth is 1.5~2μm. The doping concentration of ion implantation trap 4 is greater than or equal to 5e17cm. -3 The depth is 0.6~1.0 μm. The doping concentration of bulk region 8 and region 9 is greater than or equal to 1e19 cm⁻¹. -3 The doping concentration of source region 5, drain region 6, and isolation region 7 is greater than or equal to 1e19cm. -3 The overlap width between the end of the gate oxide layer 15 and the source region 5 and the drain region 6 is 0.5~1μm.

[0029] This embodiment enhances the device's internal charge storage capacity by setting up deep isolation traps and isolation regions. By combining the parameters of each layer and adjusting the doping concentration and depth of the deep isolation traps and the doping concentration of the isolation regions, the electric field can be optimized, resulting in a significant reduction in device leakage current.

[0030] Please see Figures 2a-2i , Figures 2a-2i This is a schematic diagram illustrating the process of fabricating an isolated MOSFET device structure to reduce leakage current, as provided by the present invention.

[0031] The fabrication method of the isolated MOSFET device structure for reducing device leakage current in this embodiment includes the following steps: S1, Provide substrate 1, such as Figure 2a As shown.

[0032] Specifically, substrate 1 includes, but is not limited to, purchased wafers or self-made wafers. The material of substrate 1 includes 4H-SiC with a doping concentration of 5e18cm⁻¹. -3 .

[0033] S2. An epitaxial region 2 is formed on substrate 1, such as... Figure 2b As shown.

[0034] Specifically, an epitaxial layer is grown on substrate 1 to form epitaxial region 2. The material of epitaxial region 2 includes 4H-SiC, and the thickness is 6~10μm. The thickness of epitaxial region 2 can be set according to actual needs. For example, the thickness of epitaxial region 2 is 6μm, 7μm, 8μm, 9μm or 10μm.

[0035] S3. A deep isolation trap 3 is formed in the epitaxial region 2, extending from the surface of the epitaxial region 2 to the interior of the epitaxial region 2, and having a width smaller than the width of the epitaxial region 2. Figure 2c As shown.

[0036] Specifically, a mask is deposited above the epitaxial region 2. The mask is then etched to create vias by etching ion implantation windows of the second conductivity type. Ion implantation is performed through these vias on the epitaxial region to form a deep isolation trap 3 of the first conductivity type. The mask is then removed. Furthermore, the deep isolation trap 3 is formed using high-energy ion implantation technology for silicon carbide, i.e., ballistic implantation technology.

[0037] The deep isolation well 3 can be a lightly doped region with a doping concentration less than or equal to 5e16cm. -3 The depth is 1.5~2μm. For example, the depth of the deep isolation trap 3 is 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, and 2.0μm.

[0038] S4. An ion implantation trap 4 is formed in the deep isolation trap 3, extending from the surface of the deep isolation trap 3 into the interior of the deep isolation trap 3, and having a width smaller than the width of the deep isolation trap 3. Figure 2d As shown.

[0039] Specifically, a mask is deposited above the deep isolation trap 3, and the mask is etched with ion implantation windows of the first conductivity type to form vias. Ions are then implanted into the deep isolation trap through the vias to form an ion implantation trap 4 with the second conductivity type, and the mask is then removed.

[0040] Specifically, ion implantation trap 4 can be a heavily doped region with a doping concentration greater than or equal to 5e17cm. -3 The depth is 0.6~1.0μm. For example, the depth of ion implantation trap 4 is 0.6μm, 0.7μm, 0.8μm, 0.9μm, and 1.0μm.

[0041] S5. Simultaneously form a body region 8 and a region 9 on the sample surface, wherein the body region 8 extends from the surface of the ion implantation trap 4 to the interior of the ion implantation trap 4, and the region 9 extends from the surface of the epitaxial region 2 to the interior of the epitaxial region 2, as shown below. Figure 2e As shown.

[0042] Specifically, a mask is deposited on top of the sample, and the mask is etched with ion implantation windows of the first conductivity type to form vias. Ions are then implanted into the structure through the vias to form heavily doped regions of the second conductivity type, including body region 8 and region 9. The mask is then removed.

[0043] Specifically, the heavily doped region of the second conductivity type can be a highly doped region, typically with a doping concentration greater than or equal to 1e19 cm⁻¹. -3 That is, the doping concentration of region 8 and region 9 is greater than or equal to 1e19cm. -3 .

[0044] S6. Simultaneously, source region 5, drain region 6, and isolation region 7 are formed on the sample surface. Source region 5 and drain region 6 extend from the surface of ion implantation trap 4 to the interior of ion implantation trap 4, and isolation region 7 extends from the surface of deep isolation trap 3 to the interior of deep isolation trap 3. Figure 2f As shown.

[0045] Specifically, a mask is deposited on the sample surface, and the mask is etched to form vias with ion implantation windows. Ions are then implanted into the structure through the vias to form heavily doped regions of the first conductivity type, including source region 5, drain region 6, and isolation region 7. The mask is then removed.

[0046] Specifically, the heavily doped region of the first conductivity type can be a highly doped region, typically with a doping concentration greater than or equal to 1e19 cm⁻¹. -3 That is, the doping concentration of source region 5, drain region 6, and isolation region 7 is greater than or equal to 1e19cm. -3 .

[0047] S7. A gate oxide layer 15 is formed on the ion implantation trap 4, with its ends overlapping the source region 5 and the drain region 6, and a gate electrode 16 is formed on the gate oxide layer 15, as shown. Figure 2g and 2h As shown.

[0048] Specifically, an oxide layer can be deposited on the upper surface of the ion implantation trap 4 as a gate dielectric material layer to form a gate oxide layer 15; for example, the oxide is SiO2. A polysilicon layer can be deposited on the upper surface of the gate oxide layer 15 as a gate conductive material layer to form a gate electrode 16.

[0049] S8. Deposit metals on source region 5, drain region 6, isolation region 7, body region 8, and area region 9, and anneal them to form source electrode metal 10, drain electrode metal 11, isolation region electrode metal 12, body electrode metal 13, and area electrode metal 14, as shown. Figure 2i As shown.

[0050] Specifically, copper can be electroplated as the metal electrode using processes such as electroplating, but not limited to electroplating.

[0051] Furthermore, this embodiment simulates the structure of a 4H-SiC isolated nMOSFET device. The simulation results can be found in [link to simulation results]. Figure 3 , Figure 4 , Figure 5 and Figure 6 , Figure 3 This diagram illustrates a comparison of the leakage current of a traditional 4H-SiC low-voltage nMOSFET device structure and the 4H-SiC isolated nMOSFET device structure with reduced leakage current in this embodiment, based on their relative epitaxial dimensions. Figure 4 This diagram illustrates a comparison of the threshold voltages of a traditional 4H-SiC low-voltage nMOSFET device structure and a proposed 4H-SiC isolated nMOSFET device structure that reduces device leakage current. Figure 5 This diagram illustrates a comparison of internal leakage current between a traditional 4H-SiC low-voltage nMOSFET device structure and a proposed 4H-SiC isolated nMOSFET device structure designed to reduce leakage current. Figure 6 This diagram shows a comparison of the operating current stability of a traditional 4H-SiC low-voltage nMOSFET device structure and a proposed 4H-SiC isolated nMOSFET device structure that reduces device leakage current. In the diagram, Vgs is the gate-source voltage, Iepi is the epitaxial region leakage current, Ids is the drain-source current, Vds is the drain-source voltage, and Ibase is the base region leakage current.

[0052] like Figure 3 and Figure 5 As shown, in the 4H-SiC isolated nMOSFET device structure for reducing device leakage current in this embodiment, the substrate leakage current and body leakage current are reduced by 99.99%.

[0053] like Figure 4 and Figure 6 As shown, in the transfer and output characteristic curves of the 4H-SiC isolated nMOSFET device with reduced leakage current and the ordinary low-voltage nMOSFET in this embodiment, the device output characteristics are significantly optimized and the saturation current is stabilized at 11.3% while the threshold voltage remains basically unchanged.

[0054] In the 4H-SiC isolated MOSFET device structure and its fabrication method for reducing device leakage current in this embodiment, by adding the deep isolation well and isolation region, the internal charge storage capacity of the device can be greatly enhanced when the MOSFET device structure is working normally, the substrate leakage current can be reduced, the device breakdown voltage can be increased, thereby improving the device's resistance to breakdown and crosstalk.

[0055] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An isolated MOSFET device structure for reducing leakage current, characterized in that, include: Substrate (1), epitaxial region (2), deep isolation trap (3), ion implantation trap (4), source region (5), drain region (6), isolation region (7), body region (8), regional region (9), source metal (10), drain metal (11), isolation region electrode metal (12), body metal (13), regional region electrode metal (14), gate oxide layer (15), and gate electrode (16), wherein, The epitaxial region (2) is located on the substrate (1); the deep isolation trap (3) extends from the surface of the epitaxial region (2) to the interior of the epitaxial region (2) and has a width smaller than the width of the epitaxial region (2); the ion implantation trap (4) extends from the surface of the deep isolation trap (3) to the interior of the deep isolation trap (3) and has a width smaller than the width of the deep isolation trap (3); The source region (5), the drain region (6), and the body region (8) all extend from the surface of the ion implantation trap (4) to the interior of the ion implantation trap (4) and are spaced apart; the isolation region (7) extends from the surface of the deep isolation trap (3) to the interior of the deep isolation trap (3) and is spaced apart from the ion implantation trap (4); the region (9) extends from the surface of the epitaxial region (2) to the interior of the epitaxial region (2) and is spaced apart from the deep isolation trap (3); The source metal (10), the drain metal (11), the body metal (13), the isolation region electrode metal (12), and the region electrode metal (14) are respectively located on the source region (5), the drain region (6), the body region (8), the isolation region (7), and the region (9); The gate oxide layer (15) is located on the ion implantation trap (4), and its ends partially overlap with the source region (5) and the drain region (6); the gate electrode (16) is located on the gate oxide layer (15); The substrate (1), the deep isolation trap (3), the source region (5), the drain region (6), and the isolation region (7) have a first conductivity type, and the epitaxial region (2), the ion implantation trap (4), the body region (8), and the region (9) have a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

2. The isolated MOSFET device structure for reducing leakage current according to claim 1, characterized in that, The body region (8) includes a first sub-body region (81) and a second sub-body region (82), wherein, The source region (5), the drain region (6), the first sub-region (81), and the second sub-region (82) are distributed at intervals, and the source region (5) and the drain region (6) are located between the first sub-region (81) and the second sub-region (82).

3. The isolated MOSFET device structure for reducing leakage current according to claim 1, characterized in that, The isolation zone (7) includes a first sub-isolation zone (71) and a second sub-isolation zone (72), wherein, The first sub-isolation region (71) is located in the deep isolation trap (3) between the first end of the deep isolation trap (3) and the first end of the ion implantation trap (4); The second sub-isolation region (72) is located in the deep isolation trap (3) between the second end of the deep isolation trap (3) and the second end of the ion implantation trap (4).

4. The isolated MOSFET device structure for reducing device leakage current according to claim 1, characterized in that, The region (9) includes a first sub-region (91) and a second sub-region (92), wherein, The first sub-region (91) is located in the extension region (2) between the first end of the extension region (2) and the first end of the deep isolation trap (3); The second sub-region (92) is located in the extension region (2) between the second end of the extension region (2) and the second end of the deep isolation trap (3).

5. The isolated MOSFET device structure for reducing leakage current according to claim 1, characterized in that, The substrate (1) is made of 4H-SiC with a doping concentration of 5e18cm. -3 ; The material of the epitaxial region (2) includes 4H-SiC with a thickness of 6~10μm.

6. The isolated MOSFET device structure for reducing device leakage current according to claim 1, characterized in that, The doping concentration of the deep isolation trap (3) is less than or equal to 5e16cm. -3 The depth is 1.5~2μm; The doping concentration of the ion implantation trap (4) is greater than or equal to 5e17cm. -3 The depth is 0.6~1.0μm.

7. The isolated MOSFET device structure for reducing leakage current according to claim 1, characterized in that, The doping concentration of the body region (8) and the region (9) is greater than or equal to 1e19cm. -3 ; The doping concentration of the source region (5), the drain region (6), and the isolation region (7) is greater than or equal to 1e19cm. -3 .

8. The isolated MOSFET device structure for reducing device leakage current according to claim 1, characterized in that, The width of the overlap between the end of the gate oxide layer (15) and the source region (5) and the drain region (6) is 0.5~1μm.

9. The isolated MOSFET device structure for reducing leakage current according to claim 1, characterized in that, The first conductivity type is N-type, the second conductivity type is P-type, and the isolated MOSFET device structure is nMOSFET; Alternatively, the first conductivity type is P-type, the second conductivity type is N-type, and the isolated MOSFET device structure is pMOSFET.

10. A method for fabricating an isolated MOSFET device structure to reduce leakage current, characterized in that, Including the following steps: Provide substrate (1); An epitaxial region (2) is formed on the substrate (1); A deep isolation trap (3) is formed in the epitaxial region (2) extending from the surface of the epitaxial region (2) into the interior of the epitaxial region (2) and having a width smaller than the width of the epitaxial region (2); An ion implantation trap (4) is formed in the deep isolation trap (3) extending from the surface of the deep isolation trap (3) into the interior of the deep isolation trap (3) and having a width smaller than the width of the deep isolation trap (3); A body region (8) and a region (9) are simultaneously formed on the sample surface, wherein the body region (8) extends from the surface of the ion implantation trap (4) to the interior of the ion implantation trap (4), and the region (9) extends from the surface of the epitaxial region (2) to the interior of the epitaxial region (2); The sample surface simultaneously contains a source region (5), a drain region (6), and an isolation region (7), wherein the source region (5) and the drain region (6) extend from the surface of the ion implantation trap (4) to the interior of the ion implantation trap (4), and the isolation region (7) extends from the surface of the deep isolation trap (3) to the interior of the deep isolation trap (3); A gate oxide layer (15) is formed on the ion implantation trap (4) with its ends overlapping the source region (5) and the drain region (6), and a gate electrode (16) is formed on the gate oxide layer (15); Metals are deposited and annealed on the source region (5), the drain region (6), the isolation region (7), the body region (8), and the region (9) to form source metal (10), drain metal (11), isolation region electrode metal (12), body metal (13), and region electrode metal (14); The substrate (1), the deep isolation trap (3), the source region (5), the drain region (6), and the isolation region (7) have a first conductivity type, and the epitaxial region (2), the ion implantation trap (4), the body region (8), and the region (9) have a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type.

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