Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate and a thin film transistor arranged on the substrate. The thin film transistor comprises a grid electrode, a first metal oxide active layer, a source electrode and a drain electrode. The first metal oxide active layer is located on one side of the grid electrode and comprises an indium element, a lanthanide element and a copper element. The source electrode and the drain electrode are connected with the first metal oxide active layer. Therefore, the copper element can improve the shallow energy level defect caused by the lanthanide doped metal oxide, and the positive bias stability of the thin film transistor is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] As demands for higher resolution, higher definition, faster response, and lower power consumption in display devices increase, metal-oxide transistors (MOS) are increasingly being used in high-end display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays due to their lower leakage current. However, the relatively low mobility of current mainstream MOS transistors still makes them difficult to apply in high-end smart terminal products that require even higher resolution and definition.

[0003] In recent years, breakthroughs in lanthanide-doped high-mobility oxide target formulations have improved the performance of metal-oxide transistors (MOS transistors). These breakthroughs have resulted in increased mobility while maintaining low leakage current, along with excellent light stability, thus broadening the application prospects of MOS transistors. However, lanthanide-doped MOS transistors exhibit poor stability under voltage, making them unsuitable for display devices.

[0004] Therefore, it is necessary to propose a technical solution to improve the stability of lanthanide-doped metal oxide transistors under voltage. Summary of the Invention

[0005] This application provides an array substrate and a display panel to improve the forward bias stability of thin-film transistors and enhance the display effect of the display panel.

[0006] In a first aspect, some embodiments of this application provide an array substrate. The array substrate includes a substrate and thin-film transistors disposed on the substrate. The thin-film transistors include a gate, a first metal oxide active layer, and source and drain electrodes. The first metal oxide active layer is located on one side of the gate and includes indium, lanthanides, and copper. The source and drain electrodes are connected to the first metal oxide active layer.

[0007] Secondly, some embodiments of this application also provide a display panel, which includes the array substrate of any of the above embodiments.

[0008] In some embodiments of the array substrate and display panel of this application, copper is further doped into the first metal oxide active layer doped with lanthanide elements to improve the shallow energy level defects caused by lanthanide doping of metal oxide, improve the stability of thin transistors under forward bias, that is, improve the forward bias stability of thin film transistors, and thus improve the display effect of display panel. Attached Figure Description

[0009] Figure 1Cross-sectional structural schematic diagrams of array substrates provided for some embodiments of this application;

[0010] Figure 2 A cross-sectional structural schematic diagram of the array substrate provided for some other embodiments of this application;

[0011] Figure 3 A cross-sectional structural schematic diagram of the array substrate provided in some other embodiments of this application;

[0012] Figure 4 A cross-sectional structural schematic diagram of the array substrate provided in some other embodiments of this application;

[0013] Figure 5 A schematic diagram of the planar structure of the display panel provided in some embodiments of this application;

[0014] Figure 6 A circuit diagram of the pixel driving circuit of the display panel provided in some embodiments of this application;

[0015] Figure 7 Circuit diagrams of pixel driving circuits for display panels in other embodiments provided in this application;

[0016] Figure 8 A circuit diagram of the gate driving circuit of the display panel in some embodiments provided in this application;

[0017] Figure 9 The transfer characteristic curve of the thin-film transistor in Embodiment 4 provided in this application;

[0018] Figure 10 The transfer characteristic curves of the thin-film transistor are shown as a comparative example.

[0019] The attached figures are labeled as follows:

[0020] 100, Display panel;

[0021] 10. Thin-film transistor;

[0022] 101, gate;

[0023] 1021, First metal oxide active layer; 1022, Second metal oxide active layer;

[0024] 103, source; 104, drain;

[0025] 105, Gate insulating layer; 106, Interlayer insulating layer;

[0026] 107, Light-shielding layer; 108, Etching barrier layer;

[0027] 20, pixel driving circuit; 201, switching transistor; 202, first driving transistor; 203, second driving transistor;

[0028] 21, gate drive circuit; 211, pull-up transistor; 212, pull-down transistor; 213, pull-up control transistor;

[0029] 22, pixel; 23, scan line; 24, data line;

[0030] VDD, first power supply voltage; VSS1, second power supply voltage; VSS2, third power supply voltage;

[0031] 30. Substrate. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] Please refer to Figures 1 to 4 As shown, Figure 1 This application provides cross-sectional structural schematic diagrams of array substrates for some embodiments. Figure 2 A cross-sectional structural schematic diagram of the array substrate provided for some other embodiments of this application. Figure 3 A cross-sectional structural schematic diagram of the array substrate provided in some other embodiments of this application. Figure 4 This is a cross-sectional structural schematic diagram of the array substrate provided in some further embodiments of this application. Wherein, Figure 1 and Figure 2 The thin-film transistor shown is a back-channel etched transistor. Figure 3 The thin-film transistor shown is an etch-block transistor. Figure 4 The thin-film transistor shown is a top-gate thin-film transistor.

[0034] like Figures 1 to 4 As shown, a thin-film transistor 10 is disposed on a substrate 30. The thin-film transistor 10 includes a gate 101, a first metal oxide active layer 1021, a source 103, and a drain 104. The first metal oxide active layer 1021 is located on one side of the gate 101. The source 103 and the drain 104 are connected to the first metal oxide active layer 1021.

[0035] In some embodiments, the gate 101, source 103, and drain 104 may comprise metals. These metals may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum (Al) alloys, and aluminum nitride (AlN). x ), silver (Ag) alloy, tungsten (W), tungsten nitride (WN) x It includes at least one of copper (Cu) alloys and molybdenum (Mo) alloys.

[0036] The first metal oxide active layer 1021 includes indium (In), lanthanides, and copper (Cu). Indium contributes to the high mobility of the thin-film transistor 10. The lanthanide-doped metal oxide active layer further increases the mobility of the thin-film transistor 10, and the lanthanides also improve its photoluminescence stability. Further doping of copper into the lanthanide-doped metal oxide active layer improves the shallow level defects caused by the lanthanides, enhancing the stability of the thin-film transistor under forward bias, i.e., improving the forward bias stability of the thin-film transistor 10. Furthermore, further doping of copper into the lanthanide-doped metal oxide active layer also increases the process window of the thin-film transistor. Thus, the thin-film transistor 10 achieves a balance of high mobility, high photoluminescence stability, process window, and forward bias stability.

[0037] The lanthanide elements may include at least one selected from lanthanum (La), cerium (Ce), praseodymium (Pr), phthalic acid (Nd), pyroxene (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). Optionally, the lanthanide elements in the first metal oxide active layer 1021 may include praseodymium.

[0038] In some embodiments, copper may exist in the first metal oxide active layer 1021 in the form of copper oxide. This improves the stability of copper in the first metal oxide active layer 1021, thereby ensuring the stability of the thin-film transistor.

[0039] In some embodiments, the number of lanthanide atoms in the first metal oxide active layer 1021 is less than the number of copper atoms. Thus, in the first metal oxide active layer 1021, the number of copper atoms is greater than the number of lanthanide atoms, and copper atoms can better mitigate the problem of poor forward bias stability caused by lanthanide doping.

[0040] In some embodiments, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 1% and less than or equal to 10%. This effectively improves the shallow energy level defect state problem caused by lanthanides, thereby enhancing the forward bias stability of the thin film transistor 10.

[0041] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 3% and less than or equal to 8%. In this way, while improving the forward bias stability of the thin-film transistor, the saturation threshold voltage of the thin-film transistor 10 is raised to a suitable range, thereby reducing the power consumption required to turn on the thin-film transistor 10.

[0042] It should be noted that lanthanide-doped metal oxides result in a low threshold voltage for the thin-film transistor 10. If the threshold voltage is too low, the thin-film transistor 10 is prone to turning on. However, further doping the lanthanide-doped metal oxide with an appropriate amount of copper can effectively suppress the high carrier concentration caused by the lanthanide-doped metal oxide, thereby increasing the saturation threshold voltage of the thin-film transistor 10 to a suitable range and thus optimizing the saturation threshold voltage of the thin-film transistor 10.

[0043] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 4.5% and less than or equal to 8%. This improves the forward bias stability of the thin-film transistor 10, raises the saturation threshold voltage of the thin-film transistor 10 to a suitable range to reduce the power consumption required to turn on the thin-film transistor 10, and further improves the negative bias stability of the thin-film transistor 10.

[0044] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 1% and less than or equal to 5%. Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be greater than or equal to 5.5% and less than or equal to 10%.

[0045] For example, in the first metal oxide active layer 1021, the percentage ratio of the number of copper atoms to the number of indium atoms can be 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, or 10%.

[0046] In other embodiments, the percentage ratio of copper atoms to indium atoms in the first metal oxide active layer 1021 may also be greater than 10%. This significantly improves the shallow defect states caused by lanthanides. Optionally, the percentage ratio of copper atoms to indium atoms in the first metal oxide active layer 1021 may also be greater than 10% and less than or equal to 20%.

[0047] In other embodiments, the percentage ratio of the number of copper atoms to the number of indium atoms in the first metal oxide active layer 1021 may also be less than 1% and greater than or equal to 0.001%.

[0048] In some embodiments, in the first metal oxide active layer 1021, the percentage ratio of the number of lanthanide atoms to the number of indium atoms is greater than or equal to 0.1% and less than or equal to 5%. This ensures the switching characteristics of the thin-film transistor 10 and enables the thin-film transistor 10 to have high mobility and high light stability.

[0049] Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of lanthanide atoms to the number of indium atoms is greater than or equal to 0.2% and less than or equal to 4.5%. Optionally, in the first metal oxide active layer 1021, the percentage ratio of the number of lanthanide atoms to the number of indium atoms is greater than or equal to 0.5% and less than or equal to 3%.

[0050] For example, in the first metal oxide active layer 1021, the percentage ratio of the number of lanthanide atoms to the number of indium atoms can be 0.1%, 0.2%, 0.5%, 0.6%, 0.7%, 0.9%, 1.0%, 1.1%, 1.2%, 1.5%, 1.6%, 1.7%, 1.9%, 2.0%, 2.1%, 2.2%, 2.5%, 2.6%, 2.7%, 2.9%, 3.0%, 3.1%, 3.2%, 3.5%, 3.6%, 3.7%, 3.9%, 4.0%, 4.1%, 4.2%, 4.5%, 4.6%, 4.7%, or 4.9%.

[0051] In some embodiments, the first metal oxide active layer 1021 further includes at least one of gallium, zinc, and tin, wherein the ratio of the number of indium atoms to the number of atoms of any one of gallium, zinc, and tin is greater than or equal to 1.8 and less than or equal to 5. This ensures that the thin-film transistor 10 has high mobility and guarantees its switching characteristics.

[0052] Optionally, the first metal oxide active layer 1021 further includes at least one of gallium, zinc and tin, wherein the ratio of the number of indium atoms to the number of atoms of any one of gallium, zinc and tin is greater than or equal to 2 and less than or equal to 4.5.

[0053] Optionally, the first metal oxide active layer 1021 further includes zinc, wherein the ratio of the number of indium atoms to the number of zinc atoms is greater than or equal to 1.8 and less than or equal to 5. Thus, the inclusion of zinc in the first metal oxide active layer 1021 can further improve the mobility of the thin-film transistor 10.

[0054] Optionally, the first metal oxide active layer 1021 further includes tin, wherein the ratio of the number of indium atoms to the number of tin atoms is greater than or equal to 1.8 and less than or equal to 5. Thus, the inclusion of tin in the first metal oxide active layer 1021 can further improve the mobility of the thin-film transistor 10.

[0055] Optionally, the first metal oxide active layer 1021 further includes gallium, wherein the ratio of the number of indium atoms to the number of gallium atoms is greater than or equal to 1.8 and less than or equal to 5. Thus, the inclusion of gallium in the first metal oxide active layer 1021 can suppress high carrier concentration, reduce the off-state leakage current of the thin-film transistor 10, and improve the stability of the thin-film transistor 10.

[0056] Optionally, the first metal oxide active layer 1021 may also include two or three of gallium, zinc and tin.

[0057] In some embodiments, the metal oxide matrix in the first metal oxide active layer 1021 may include one or more mixtures of indium gallium zinc oxide, indium zinc oxide, indium gallium oxide, indium tin zinc oxide, and indium oxide.

[0058] In some embodiments, the metal oxide matrix in the first metal oxide active layer 1021 may be indium zinc oxide, and the lanthanide elements may include praseodymium. In the first metal oxide active layer 1021, the ratio of the number of copper atoms, praseodymium atoms, indium atoms, and zinc atoms is (0.02–0.15):(0.001–0.09):(1.8–2.0):(0.8–1.2). This achieves a balance between high mobility, forward bias stability, and high light-induced stability in the thin-film transistor 10.

[0059] Optionally, the metal oxide matrix in the first metal oxide active layer 1021 can be indium zinc oxide, and the lanthanide elements can include praseodymium. In the first metal oxide active layer 1021, the ratio of the number of copper atoms, praseodymium atoms, indium atoms, and zinc atoms is (0.05–0.15):(0.001–0.09):(1.8–2.0):(0.8–1.2). This achieves a balance between high mobility, forward bias stability, and high illumination stability of the thin-film transistor 10, while also optimizing the saturation threshold voltage of the thin-film transistor.

[0060] Optionally, in the first metal oxide active layer 1021, the ratio of the number of copper atoms, praseodymium atoms, indium atoms, and zinc atoms is (0.1–0.15):(0.001–0.09):(1.8–2.0):(0.8–1.2). This balances the high mobility, forward bias stability, high illumination stability, and saturation threshold voltage of the thin-film transistor, while also improving its negative bias stability.

[0061] like Figure 2 As shown, in some embodiments, the thin-film transistor 10 may further include a second metal oxide active layer 1022. The second metal oxide active layer 1022 is layered and contacted with the first metal oxide active layer 1021, and the source 103 and drain 104 are in contact with the second metal oxide active layer 1022. The proportion of indium atoms in the second metal oxide active layer 1022 is less than the proportion of indium atoms in the first metal oxide active layer 1021. Thus, the first metal oxide active layer 1021, as a front channel layer, has high mobility, resulting in a large on-current for the thin-film transistor 10, while the second metal oxide active layer 1022, as a back channel layer, has low mobility, resulting in a low leakage current for the thin-film transistor 10.

[0062] In some embodiments, the second metal oxide active layer 1022 may further include at least one of gallium and zinc. This reduces the leakage current of the thin-film transistor 10. In the second metal oxide active layer 1022, the ratio of the number of indium atoms to the number of gallium and zinc atoms is greater than or equal to 0.01 and less than or equal to 1. This makes the proportion of indium atoms in the second metal oxide active layer 1022 less than the proportion of indium atoms in the first metal oxide active layer 1021, thereby reducing the mobility of the second metal oxide active layer 1022.

[0063] In some embodiments, the second metal oxide active layer 1022 may not include lanthanide elements. This ensures that the mobility of the second metal oxide active layer 1022 is lower than that of the first metal oxide active layer 1021.

[0064] In some embodiments, the second metal oxide active layer 1022 may further include lanthanides. This improves the photostability of the second metal oxide active layer 1022. In other embodiments, the proportion of lanthanide atoms in the second metal oxide active layer 1022 is less than the proportion of lanthanide atoms in the first metal oxide active layer 1021.

[0065] In other embodiments, where the second metal oxide active layer 1022 comprises lanthanides, it may also comprise copper. This improves both the photostability of the second metal oxide active layer 1022 and the forward bias stability of the thin-film transistor 10. In other embodiments, the percentage of copper atoms in the second metal oxide active layer 1022 may be less than the percentage of copper atoms in the first metal oxide layer.

[0066] In other embodiments, the thin-film transistor 10 may further include a third metal oxide active layer. The third metal oxide active layer is located on the side of the second metal oxide active layer 1022 opposite to the first metal oxide active layer 1021. Thus, the thin-film transistor 10 may include three metal oxide active layers. It is understood that the thin-film transistor 10 may include three or more stacked metal oxide active layers.

[0067] like Figures 1 to 4 As shown, the thin-film transistor 10 is disposed on the substrate 30. The substrate 30 may include any one of a glass substrate, a flexible substrate, and a semiconductor substrate.

[0068] like Figures 1 to 4 As shown, in some embodiments, the first metal oxide active layer 1021 and the second metal oxide active layer 1022 are disposed parallel or substantially parallel to the substrate 30. In other embodiments, the thin-film transistor 10 can be a vertical transistor, in which case the first metal oxide active layer 1021 and the second metal oxide active layer 1022 can be disposed tilted or perpendicular to the substrate 30.

[0069] As 1 to Figure 3 As shown, the thin-film transistor 10 can be a bottom-gate thin-film transistor 10. In this case, the gate 101 is located between the substrate 30 and the first metal oxide active layer 1021. A gate insulating layer 105 is disposed between the gate 101 and the first metal oxide active layer 1021. Figure 1 and Figure 3 As shown, the source 103 and drain 104 are disposed on and in contact with the first metal oxide active layer 1021. Figure 2As shown, the source 103 and drain 104 are disposed on and in contact with the second metal oxide active layer 1022. The thin-film transistor 10 may further include an interlayer insulating layer 106, which covers the source 103 and drain 104, the first metal oxide active layer 1021, and the gate insulating layer 105.

[0070] In some embodiments, such as Figure 1 and Figure 3 As shown, when the thin-film transistor 10 is a bottom-gate thin-film transistor and the channel layer of the thin-film transistor 10 is a single layer, the orthogonal projection of the first metal oxide active layer 1021 on the substrate 30 can be located within the orthogonal projection of the gate 101 on the substrate 30. In this way, the gate 101 can act as a light shield, improving the problem that the first metal oxide active layer 1021 easily causes photo-generated leakage current in the thin-film transistor 10 under illumination. It also makes the first metal oxide active layer 1021 flatter, ensuring the performance of the first metal oxide active layer 1021.

[0071] In some embodiments, such as Figure 2 As shown, when the thin-film transistor 10 is a bottom-gate thin-film transistor, and the channel layer of the thin-film transistor 10 includes a first metal oxide active layer 1021 and a second metal oxide active layer 1022, the first metal oxide active layer 1021 is located on the side of the second metal oxide active layer 1022 closer to the gate 101. The orthogonal projection of the second metal oxide active layer 1022 on the substrate 30 lies within the orthogonal projection of the first metal oxide active layer 1021 on the substrate 30.

[0072] like Figure 4 As shown, the thin-film transistor 10 can be a top-gate thin-film transistor. A first metal-oxide active layer 1021 is located between the gate 101 and the substrate 30, with the gate 101 located on the side of the first metal-oxide active layer 1021 facing away from the substrate 30. A gate insulating layer 105 is located between the gate 101 and the first metal-oxide active layer 1021.

[0073] Please continue to refer to Figure 4 As shown, in some embodiments, when the thin-film transistor 10 is a top-gate thin-film transistor 10, a light-shielding layer 107 may be provided between the substrate 30 and the thin-film transistor 10. The orthographic projection of the first metal oxide active layer 1021 on the substrate 30 lies within the orthographic projection of the light-shielding layer 107 on the substrate 30. Thus, the light-shielding layer 107 blocks light incident on the first metal oxide active layer 1021.

[0074] like Figure 3As shown, in some embodiments, the thin-film transistor 10 may further include an etch barrier layer 108. The etch barrier layer 108 is located between the source 103 and the first metal oxide active layer 1021, and between the drain 104 and the first metal oxide active layer 1021. Thus, the etch barrier layer 108 protects the first metal oxide active layer 1021.

[0075] As can be seen from the above, for some embodiments of the thin-film transistor 10 of this application, further doping with copper in the lanthanide-doped metal oxide active layer can improve the shallow energy level defect states caused by lanthanide doping, improve the forward bias stability of the thin-film transistor 10, and reduce the difficulty of threshold voltage regulation.

[0076] Based on the same inventive concept, this application also provides a display panel. Please refer to... Figures 5 to 8 As shown, Figure 5 This application provides schematic diagrams of the planar structure of the display panel for some embodiments. Figure 6 The circuit diagrams provided in this application are for the pixel driving circuits of the display panel in some embodiments. Figure 7 Circuit diagrams of pixel driving circuits for display panels provided in other embodiments of this application. Figure 8 A circuit diagram of the gate driving circuit of a display panel provided in some embodiments of this application.

[0077] The display panel 100 can be any one of a liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, or a sub-millimeter light-emitting diode display panel.

[0078] like Figures 5 to 8 As shown, the display panel 100 includes multiple scan lines 23, multiple data lines 24, multiple pixel driving circuits 20, multiple pixels 22, and gate driving circuit 21.

[0079] Multiple scan lines 23 intersect multiple data lines 24 in an insulated manner. Multiple pixel driving circuits 20 are connected to the multiple scan lines 23 and the multiple data lines 24. Multiple pixel driving circuits 20 are connected to multiple pixels 22 to drive the multiple pixels 22 to emit light.

[0080] The gate driving circuit 21 is connected to multiple scan lines 23 to output scan signals to the multiple scan lines 23. The gate driving circuit 21 can be integrated into an integrated chip and the integrated chip can be bonded to the display panel 100, or the gate driving circuit 21 can be integrated into the display panel 100.

[0081] like Figure 6As shown, in some embodiments, when the display panel 100 is a liquid crystal display panel, the pixel driving circuit 20 may include a first driving transistor 202. The source of the first driving transistor 202 is connected to the data line 24, the drain of the first driving transistor 202 is connected to the pixel electrode (not shown), and the gate 101 of the first driving transistor 202 is connected to the scan line 23. The pixel electrode, the common electrode, and the liquid crystal located between them constitute a liquid crystal capacitor Clc. The pixel electrode, the common electrode line, and the insulating layer located between them constitute a storage capacitor Cst.

[0082] like Figure 7 As shown, in some other embodiments, when the display panel 100 is an organic light-emitting diode (OLED) display panel or a current-driven light-emitting panel, the pixel driving circuit 20 may include a second driving transistor 203 and a switching transistor 201. The source of the switching transistor 201 is connected to the data line 24, and the gate of the switching transistor 201 is connected to the scan line 23. The gate of the second driving transistor 203 is connected to the drain of the switching transistor 201, the source of the second driving transistor 203 is connected to a first power supply voltage VDD, the drain of the second driving transistor 203 is connected to a first terminal of the light-emitting device, and the second terminal of the light-emitting device is connected to a second power supply voltage VSS1. The second power supply voltage VSS1 is lower than the first power supply voltage VDD.

[0083] for Figure 6 and Figure 7 As shown in the pixel driving circuit 20, during the operation of the pixel driving circuit 20, the transistors in the pixel driving circuit 20 continuously receive positive bias voltage and / or negative bias voltage, which makes the transistors in the pixel driving circuit 20 more demanding in terms of bias voltage stability.

[0084] The gate drive circuit 21 may include multiple cascaded gate drive units. For example... Figure 8 As shown, each gate drive unit may include a pull-up transistor 211, a pull-down transistor 212, and a pull-up control transistor 213. The nth gate drive unit is used as an example, where n is an integer greater than or equal to 2.

[0085] Pull-up control transistor 213 is configured to output a pull-up drive signal. The gate and source of pull-up control transistor 213 can receive the previous stage scan signal G(ni) output by the previous stage gate drive unit, and the drain of pull-up control transistor 213 outputs the previous stage scan signal G(ni) as a pull-up drive signal, where i is an integer greater than or equal to 1.

[0086] Pull-up transistor 211 is connected to scan line 23 and configured to output a conduction scan signal to scan line 23, which turns on the transistor connected to scan line 23. The gate of pull-up transistor 211 is connected to the drain of pull-up control transistor 213. The source of pull-up transistor 211 can receive clock signal CK, but is not limited to this. The drain of pull-up transistor 211 can be connected to scan line 23. Pull-up transistor 211 is turned on by pull-up drive signal, outputting a high-level clock signal as the conduction scan signal to the gate of the transistor in pixel driving circuit 20 (e.g., switching transistor 201 and first driving transistor 202).

[0087] Pull-down transistor 212 is connected to scan line 23 and configured to output a scan-off signal to scan line 23, which turns off the transistor connected to scan line 23. The gate of pull-down transistor 212 can receive the previous stage scan signal G(nj), where j is an integer greater than or equal to 1 and can be different from i. The source of pull-down transistor 212 receives the third power supply voltage VSS2. The drain of pull-down transistor 212 is connected to scan line 23.

[0088] In some embodiments, the gate drive circuit 21 may also include other transistors such as a pull-down sustaining transistor.

[0089] During the operation of the gate drive circuit 21, compared with other transistors in the gate drive circuit 21, the pull-up transistor 211 and the pull-down transistor 212 are under forward bias for a longer time, which makes the requirements for forward bias stability of the pull-up transistor 211 and the pull-down transistor 212 higher.

[0090] In some embodiments, at least one of the gate driving circuit 21 and the pixel driving circuit 20 includes the aforementioned thin-film transistor 10 to improve the forward bias stability of the thin-film transistor in the gate driving circuit 21 and the pixel driving circuit 20, thereby improving the display effect of the display panel 100.

[0091] In some embodiments, the pixel driving circuit 20 may include the thin-film transistor 10 described above. In some embodiments, at least one of the first driving transistor 202 and the second driving transistor 203 may include the thin-film transistor 10 described above. In some embodiments, the switching transistor 201 may include the thin-film transistor 10 described above.

[0092] In some embodiments, at least one of the pull-up transistor 211 and the pull-down transistor 212 includes a thin-film transistor 10. Exemplarily, both the pull-up transistor 211 and the pull-down transistor 212 include the aforementioned thin-film transistor 10.

[0093] In some embodiments, other circuitry of the display panel 100 may also include the aforementioned thin-film transistor 10. Other circuitry may include, but is not limited to, multiplexing circuitry.

[0094] Therefore, in some embodiments of this application, at least one of the pixel driving circuit 20 and the gate driving circuit 21 of the display panel 100 includes the aforementioned thin-film transistor 10, which can improve the display effect of the display panel 100.

[0095] Based on the same inventive concept, this application also provides a display device. The display device can be applied to electronic devices such as mobile terminals, tablet computers, desktop computers, and smart bracelets. The display device may include the aforementioned display panel.

[0096] The performance of the thin-film transistor 10 described above is verified below with reference to specific embodiments and comparative examples. The structures of the thin-film transistors in Embodiments 1 to 4 and the comparative examples are as follows. Figure 2 As shown, the second metal oxide active layer is the same in Examples 1 to 4 and the comparative example, while the first metal oxide active layer is different. The composition of the first and second metal oxide active layers of the thin-film transistors in Examples 1 to 4 and the comparative example, as well as the performance test results of the thin-film transistors, are shown in Table 1. Figure 9 and Figure 10 As shown.

[0097] in, Figure 9 The transfer characteristic curve of the thin-film transistor in Embodiment 4 provided in this application. Figure 10 The transfer characteristic curves of the thin-film transistor are shown as a comparative example. Figure 9 and Figure 10 The test conditions corresponding to the transfer characteristic curves include: during testing, a gate voltage increasing from -15V to 25V is applied to the gate of the thin-film transistor (TFT), with the gate voltage increasing in increments of 0.5V. The source of the TFT is grounded, and the drain of the TFT is connected to voltages of 0.1V and 15V, respectively. With a 0.1V voltage connected to the drain of the TFT, the transfer characteristic curves of 12 TFT (samples) are measured, resulting in 12 transfer characteristic curves under the 0.1V condition, as shown below. Figure 9 The curve in the dashed box corresponds to 101A. Figure 10 The curve in the dashed box corresponds to 201A. With a 15V voltage applied to the drain of the thin-film transistor, the transfer characteristic curves of 12 thin-film transistors were measured, resulting in 12 transfer characteristic curves under the 15V condition, as shown below. Figure 9 The curve in the dashed box corresponds to 101B. Figure 10 The curve in the dashed box corresponds to 201B. The saturation threshold voltage, subthreshold swing, and saturation mobility in Table 1 are obtained based on the transfer characteristic curves.

[0098] Furthermore, the 1-hour positive bias voltage offset value is obtained based on a positive bias voltage stability test. The positive bias voltage stability test conditions are as follows: a +30V gate voltage is applied to the gate of the thin-film transistor at 60°C for 3600 seconds, and the transfer characteristic curve is tested at regular intervals. The 1-hour positive bias voltage offset value is the difference in threshold voltage between time 3600s and time 0s. The 1-hour negative bias voltage offset value is obtained based on a negative bias voltage stability test. The negative bias voltage stability test conditions are as follows: a -30V gate voltage is applied to the gate at 60°C and the transistor is exposed to 4500 nits of light for 3600 seconds, and the transfer characteristic curve is tested at regular intervals. The 1-hour negative bias voltage offset value is the difference in threshold voltage between time 3600s and time 0s.

[0099] Table 1 shows the composition and performance test results of the first and second metal oxide active layers of the thin-film transistors in Examples 1 to 4 and the comparative examples.

[0100]

[0101] As shown in Table 1, the 1-hour positive bias offset values ​​of Examples 1 to 4 are smaller than those of the comparative examples. Therefore, some embodiments of this application can improve the stability of thin-film transistors under positive bias by further doping copper into lanthanide-doped metal oxides.

[0102] Furthermore, the saturation threshold voltage of the thin-film transistors in Examples 2 to 4 is greater than that of the thin-film transistors in the comparative examples. Therefore, when the percentage ratio of copper atoms to indium atoms is within a certain range, as the doping amount of copper increases within a certain range, the saturation threshold voltage of the thin-film transistor increases, thereby effectively improving the problem of negative bias threshold voltage in lanthanide-doped high-migration oxide devices.

[0103] Furthermore, the 1-hour negative bias offset values ​​in Examples 3 and 4 are smaller than those in the comparative example. Therefore, when the percentage ratio of copper atoms to indium atoms is within a certain range, the negative bias stability of the thin-film transistor can be improved.

[0104] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: substrate; A thin-film transistor, disposed on the substrate, and comprising: Gate; A first metal oxide active layer, located on one side of the gate, includes indium, lanthanides, and copper; and The source and drain are connected to the first metal oxide active layer.

2. The array substrate according to claim 1, characterized in that, In the first metal oxide active layer, the percentage ratio of the number of copper atoms to the number of indium atoms is greater than or equal to 1% and less than or equal to 10%.

3. The array substrate according to claim 1 or 2, characterized in that, In the first metal oxide active layer, the percentage ratio of the number of copper atoms to the number of indium atoms is greater than or equal to 3% and less than or equal to 8%.

4. The array substrate according to claim 1, characterized in that, In the first metal oxide active layer, the percentage ratio of the number of lanthanide atoms to the number of indium atoms is greater than or equal to 0.1% and less than or equal to 5%.

5. The array substrate according to claim 1, characterized in that, The first metal oxide active layer further includes at least one of gallium, zinc and tin, wherein the ratio of the number of indium atoms to the number of atoms of any one of gallium, zinc and tin is greater than or equal to 1.8 and less than or equal to 5.

6. The array substrate according to claim 1, characterized in that, In the first metal oxide active layer, the number of lanthanide atoms is less than the number of copper atoms.

7. The array substrate according to claim 1, characterized in that, The first metal oxide active layer also includes zinc, and the lanthanide elements include praseodymium. In the first metal oxide active layer, the ratio of the number of copper atoms, the number of praseodymium atoms, the number of indium atoms, and the number of zinc atoms is (0.02~0.15):(0.001~0.09):(1.8~2.0):(0.8~1.2).

8. The array substrate according to claim 1, characterized in that, The thin-film transistor further includes: The second metal oxide active layer is stacked on top of the first metal oxide active layer and is in contact with the source and the drain, and includes indium. The proportion of indium atoms in the second metal oxide active layer is less than the proportion of indium atoms in the first metal oxide active layer.

9. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1 to 8.

10. The display panel according to claim 9, characterized in that, Also includes: Multiple scan lines; Multiple pixel driving circuits are respectively connected to multiple scan lines; Multiple pixels are respectively connected to multiple pixel driving circuits; as well as A gate driving circuit is connected to multiple scan lines; Wherein, at least one of the gate driving circuit and the pixel driving circuit includes the thin-film transistor.

11. The display panel according to claim 10, characterized in that, The gate driving circuit includes: A pull-up transistor, the pull-up transistor being connected to one of the scan lines and configured to output a conduction scan signal to one of the scan lines; and A pull-down transistor, the pull-down transistor being connected to one of the scan lines and configured to output a turn-off scan signal to one of the scan lines that is different from the turn-on scan signal; Wherein, at least one of the pull-up transistor and the pull-down transistor includes the thin-film transistor.

Images