3D stacked silicon-based germanium detector

Abstract

The invention discloses a 3D stacked silicon-based germanium detector, relates to the field of short-wave infrared light detection and imaging, and solves the technical problem that an existing silicon-based germanium photoelectric detector is low in spectral responsivity. The detector is formed by a first wafer and a second wafer in an inverted bonding mode, an MOSFET structure is arranged in the first wafer, a Ge-on-Si photodiode structure is arranged in the second wafer and used for receiving external light and generating electrons and holes, and the electrons and the holes are accumulated in a substrate of the MOSFET structure to change the potential of the substrate so as to increase output current. The gain, the responsivity and the spectral range of the device are improved by adopting the light-induced substrate bias effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of short-wave infrared light detection and imaging, and more particularly, to a 3D stacked silicon-based germanium detector. BACKGROUND

[0002] At present, the most widely used in the field of short-wave infrared light detection and imaging is InGaAs detector, but its performance tends to saturation, and the sensitivity in the visible light band is low, and there are also disadvantages such as high manufacturing cost and not fully compatible with CMOS process. Silicon-based germanium detector has good absorption in short-wave infrared band, and its preparation process is compatible with CMOS, which is a good choice to replace InGaAs detector. However, the current silicon-based germanium photodetector has low responsivity, low quantum efficiency, and limited spectral range, which limits its further application and development.

[0003] Specifically, the short-wave infrared wavelength corresponds to 1-3um, which is one of the "atmospheric transmission windows", and has strong penetration in the atmosphere, so the detector working in this band can obtain more radiation energy of the target. In addition, short-wave infrared detection imaging is similar to visible light reflection imaging, rather than thermal imaging, which not only has detail resolution capability, but also can penetrate obstacles such as dust and smoke for imaging, so it is widely used in low-light night vision, space remote sensing, spectral analysis, biological medicine and other aspects. The traditional silicon-based CMOS image sensor is difficult to break through the detection of longer wavelengths beyond 1.1um due to the limitation of silicon material, so more new material photodetectors are developed and prepared, such as InGaAs, quantum dots, germanium, etc. Among them, InGaAs material has high manufacturing cost, and its preparation process is not fully compatible with CMOS, and there are still challenges in the problem of pixel size reduction. Quantum dot material has the advantages of low cost, flexible response spectrum, and high compatibility with CMOS process, but its dark current is high, quantum efficiency is low, and material stability is questionable, which limits its further application.

[0004] Germanium material preparation process is fully compatible with CMOS, has high absorption rate in short-wave infrared, and has the characteristics of low cost, which is an important candidate material for promoting the commercialization of high-performance, large-scale short-wave infrared focal plane array. Benefiting from the development of silicon epitaxial germanium technology, the comprehensive performance of silicon-based germanium photodetector is continuously improved. The commonly used silicon-based germanium photodetector mainly includes PIN type photodiode (PD) and avalanche diode (Avalanche Photodiode, APD). The structure of the commonly used PIN type silicon-based germanium PD is as follows Figure 1As shown, that is, the structure of the intrinsic region sandwiched between P and N doped regions. Under the applied reverse bias, the intrinsic region is depleted and the voltage drop mainly falls in this region, so that the high electric field can effectively separate the photo-generated electron-hole pairs, improve the collection ability of photo-generated carriers, and reduce the influence of diffusion time on device bandwidth. Therefore, the PIN type photodetector generally has large bandwidth, but it mainly works at low bias voltage, has no internal gain and therefore has low responsivity, which is difficult to meet the demand of long-distance light detection. The simplest APD has a similar device structure to PIN, but its working voltage is usually added to the vicinity of the breakdown voltage, so that the internal electric field is high enough to trigger the avalanche effect, thereby achieving carrier multiplication. In order to achieve high performance, the current silicon-based germanium APD usually adopts the structure of absorption-charge and multiplication separation (SACM), as shown. Figure 2 The intrinsic Ge layer is used to absorb incident light and generate electron-hole pairs, and under the action of reverse bias voltage, electrons drift to the Ge-Si interface and enter the Si multiplication layer, which maintains a high enough electric field to cause electron collision ionization and achieve avalanche multiplication. Compared with PIN photodiode, APD has higher detection sensitivity, but its structure is relatively complex, the working voltage is high, and due to the avalanche effect, its dark noise is large, and the device performance is greatly affected by temperature, thereby limiting its application range.

[0005] The current silicon-based germanium photodetector is mainly divided into two types, PIN type and APD. Among them, the PIN type device has low responsivity and cannot meet the demand of long-distance detection and low-light detection. APD has the disadvantages of high power consumption and high dark current. And overall, limited by the absorption cutoff wavelength of germanium material, the spectral response of the current silicon-based germanium photodetector is mostly below 1.6um, which limits its more extensive application. SUMMARY

[0006] The technical problem to be solved by the present application is to solve the technical problem of low spectral responsivity of the existing silicon-based germanium photodetector.

[0007] The 3D stacked silicon-based germanium detector provided by the present application is composed of first wafer and second wafer flip-chip bonding, the first wafer is provided with MOSFET structure, the second wafer is provided with Ge-on-Si photodiode structure for receiving external light and generating electrons and holes, and the electrons and holes are accumulated in the substrate of the MOSFET structure to change the substrate potential and increase the output current.

[0008] Further improvement, the MOSFET structure includes a doped body region and a first bonding contact connected to the doped body region through an internal conductor, the photodiode structure includes a bottom electrode and a second bonding contact connected to the bottom electrode through an internal conductor, and the first bonding contact is connected to the second bonding contact in a bonding manner through a conductor.

[0009] Further, the MOSFET structure further comprises a substrate doped well region, and a doped body region and a doped drain region prepared in the substrate doped well region;

[0010] The substrate doped well region is provided with a first interlayer dielectric, and a gate insulating layer is arranged between the doped well region and the first interlayer dielectric, and a gate electrode is arranged on the gate insulating layer.

[0011] Further, the MOSFET structure is an N-type MOSFET;

[0012] The substrate doped well region is provided with a deep n-well region to divide the substrate doped well region into an inner region and an outer region, and the doped body region, the doped source region and the doped drain region are all located in the inner region of the substrate doped well region.

[0013] Further, the MOSFET structure is a P-type MOSFET;

[0014] The substrate doped well region is provided with an N-type well region, and the doped body region, the doped source region and the doped drain region are all located in the inner region of the substrate doped well region.

[0015] Further, the photodiode structure further comprises a silicon substrate region, and a top electrode and a second interlayer dielectric layer are sequentially grown along one side of the silicon substrate region;

[0016] An intrinsic germanium layer and a bottom electrode are epitaxially grown on one side of the top electrode.

[0017] Further, the photodiode structure further comprises a silicon substrate region, and a top electrode and a second interlayer dielectric layer are sequentially grown along one side of the silicon substrate region;

[0018] A bottom electrode is epitaxially grown on one side of the top electrode.

[0019] Further, the photodiode structure further comprises a silicon substrate region, and a top electrode and a second interlayer dielectric layer are sequentially grown along one side of the silicon substrate region;

[0020] A bottom electrode and a metal layer are epitaxially grown on one side of the top electrode.

[0021] Further, the photodiode structure further comprises a silicon substrate region, and a second interlayer dielectric layer is sequentially grown along one side of the silicon substrate region;

[0022] A top electrode, an intrinsic germanium layer and a bottom electrode are arranged between the silicon substrate region and the second interlayer dielectric layer.

[0023] Advantages

[0024] The application has the advantages that:

[0025] 1. The application is characterized in that a first wafer and a second wafer are provided, the first wafer and the second wafer are flip-chip bonded, the first wafer is provided with a MOSFET structure, and the second wafer is provided with a Ge-on-Si photodiode structure for receiving external light and forming a photoelectric current, the photoelectric current is input into the substrate of the MOSFET structure to increase the substrate potential and thus increase the output current, and the photo-induced substrate bias effect is used to improve the gain, responsivity and spectral range of the device.

[0026] 2. The first wafer and the second wafer of the application adopt a stacked architecture, the Ge-on-Si photodiode structure and the MOSFET structure are prepared on two different wafers, and then the two wafers are stacked to form a complete device through hybrid bonding, which can improve the fill factor and realize pixel size miniaturization. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a structure schematic diagram of a prior art PIN type silicon-based germanium photodetector;

[0028] Figure 2 It is a structure schematic diagram of a prior art APD type silicon-based germanium photodetector;

[0029] Figure 3 It is a structure schematic diagram of a silicon-based germanium photodetector according to an embodiment of the application;

[0030] Figure 4 It is an equivalent circuit schematic diagram of a silicon-based germanium photodetector according to an embodiment of the application;

[0031] Figure 5 It is a structure schematic diagram of a silicon-based germanium photodetector according to another embodiment of the application;

[0032] Figure 6 It is an equivalent circuit schematic diagram of a silicon-based germanium photodetector according to another embodiment of the application;

[0033] Figure 7 It is a structure schematic diagram of a silicon-based germanium photodetector according to another embodiment of the application;

[0034] Figure 8 It is a structure schematic diagram of a silicon-based germanium photodetector according to another embodiment of the application;

[0035] Figure 9 It is a structure schematic diagram of a silicon-based germanium photodetector according to another embodiment of the application.

[0036] Wherein: 1-first wafer, 2-second wafer, 101-substrate doped well region, 102-deep n well region, 103-doped body region, 104-gate insulating layer, 105-gate electrode, 106-first interlayer dielectric, 107-first barrier layer, 108-first bonding contact, 109-doped source region, 110-doped drain region, 111-N-type well region, 112-source electrode contact, 113-gate electrode contact, 114-drain electrode contact, 201-silicon substrate region, 202-top electrode, 203-intrinsic germanium layer, 204-bottom electrode, 205-second interlayer dielectric layer, 206-second barrier layer, 207-first metal contact, 208-second bonding contact, 209-first bonding contact, 210-metal layer. DETAILED DESCRIPTION

[0037] The application will be further described below in conjunction with the embodiments, but does not constitute any limitation to the application, and any limited number of modifications made by anyone within the scope of the claims of the application is still within the scope of the claims of the application.

[0038] Reference Figures 3-9 , a 3D stacked germanium-on-silicon detector of the application is composed of a first wafer 1 and a second wafer 2 flip-chip bonded, the first wafer 1 is provided with a MOSFET structure, and the second wafer 2 is provided with a Ge-on-Si photodiode structure for receiving external light and generating electrons and holes, the electrons and holes are accumulated in the substrate of the MOSFET structure to change the substrate potential so as to increase the output current through the substrate bias effect.

[0039] As shown in Figure 3 and Figure 5 , the MOSFET structure includes a doped body region 103 and a first bonding contact 108 connected to the doped body region 103 through an internal conductor, and the photodiode structure includes a bottom electrode 204 and a second bonding contact 208 connected to the bottom electrode 204 through an internal conductor. The first bonding contact 108 is connected to the second bonding contact 208 in a bonding manner through a conductor 3.

[0040] The application provides an embodiment one of N-type MOSFET and an embodiment two of P-type MOSFET for the MOSFET structure.

[0041] Embodiment one

[0042] As shown in Figures 3-4 , the MOSFET structure further includes a substrate doped well region 101, and a doped source region 109 and a doped drain region 110 prepared in the substrate doped well region 101.

[0043] The first interlayer dielectric 106 is arranged on the substrate doped well region 101, and the gate insulating layer 104 is arranged between the doped well region 101 and the first interlayer dielectric 106, and the gate electrode 105 is arranged on the gate insulating layer 104.

[0044] The deep n-well region 102 is arranged in the substrate doped well region 101 to divide the substrate doped well region 101 into an inner region and an outer region, and the doped body region 103, the doped source region 109 and the doped drain region 110 are all arranged in the inner region of the substrate doped well region 101.

[0045] The source electrode contact 112, the gate electrode contact 113, the drain electrode contact 114 and the first bonding contact 108 are arranged on the top of the first interlayer dielectric 106, the source electrode contact 112 is an external metal contact connected to the doped source region 109 through an internal conductor, the gate electrode contact 113 is an external metal contact connected to the gate electrode 105 through an internal conductor, and the drain electrode contact 114 is an external metal contact connected to the doped drain region 110 through an internal conductor. The source electrode contact 112, the gate electrode contact 113, the drain electrode contact 114 and the first bonding contact 108 are filled with the first barrier layer 107.

[0046] The photodiode structure further comprises a silicon substrate region 201, and a top electrode 202 and a second interlayer dielectric layer 205 are sequentially grown on one side of the silicon substrate region 201.

[0047] The intrinsic germanium layer 203 and the bottom electrode 204 are epitaxially grown on one side of the top electrode 202.

[0048] The first metal contact 207 and the second bonding contact 208 are arranged on one side of the second interlayer dielectric layer 205, the first metal contact 207 is an external metal contact connected to the top electrode 202 through an internal conductor, and the second bonding contact 208 is an external metal contact connected to the bottom electrode 204 through an internal conductor. The first metal contact 207 and the second bonding contact 208 are filled with the second barrier layer 206, and the first barrier layer 107 and the second barrier layer 206 are made of silicon oxide or silicon nitride.

[0049] When the MOSFET structure is an nMOS structure, the doped body region 103 is a doped body region p + , the bottom electrode 204 is an anode silicon layer p + Si, the doped source region 109 is a doped source region n + , the doped drain region 110 is a doped drain region n + , the bottom electrode 202 is a substrate cathode doped region n + Si.

[0050] Embodiment two

[0051] As Figures 5-6As shown, the MOSFET structure further comprises a substrate doped well region 101, and a doped source region 109 and a doped drain region 110 prepared in the substrate doped well region 101.

[0052] The substrate doped well region 101 is provided with a first interlayer dielectric 106, and a gate insulating layer 104 is provided between the doped well region 101 and the first interlayer dielectric 106, and a gate electrode 105 is provided on the gate insulating layer 104.

[0053] The substrate doped well region 101 is provided with an N-type well region 111, and the doped body region 103, the doped source region 109 and the doped drain region 110 are all located in the internal region of the substrate doped well region 101.

[0054] The top of the substrate doped well region 101 is provided with a source electrode contact 112, a gate electrode contact 113, a drain electrode contact 114 and a first bonding contact 108, the source electrode contact 112 is an external metal contact connected to the doped source region 109 through an internal conductor, the gate electrode contact 113 is an external metal contact connected to the gate electrode 105 through an internal conductor, and the drain electrode contact 114 is an external metal contact connected to the doped drain region 110 through an internal conductor. The source electrode contact 112, the gate electrode contact 113, the drain electrode contact 114 and the first bonding contact 108 are filled with a first barrier layer 107.

[0055] The photodiode structure further comprises a silicon substrate region 201, and a top electrode 202 and a second interlayer dielectric layer 205 grown in sequence on one side of the silicon substrate region 201.

[0056] The top electrode 202 is epitaxially grown with an intrinsic germanium layer 203 and a bottom electrode 204 on one side.

[0057] The second interlayer dielectric layer 205 is provided with a first metal contact 207 and a second bonding contact 208 on one side, the first metal contact 207 is an external metal contact connected to the top electrode 202 through an internal conductor, and the second bonding contact 208 is an external metal contact connected to the bottom electrode 204 through an internal conductor. The first metal contact 207 and the second bonding contact 208 are filled with a second barrier layer 206, and the first barrier layer 107 and the second barrier layer 206 are made of silicon oxide or silicon nitride.

[0058] When the MOSFET structure is a pMOS structure, the doped body region 103 is a doped body region n + , the bottom electrode 204 is a substrate cathode doped region n + Si, the doped source region 109 is a doped source region p + , the doped drain region 110 is a doped drain region p + , the bottom electrode 202 is an anode silicon layer p + Si.

[0059] Based on the above two types, the PD as the photoelectric conversion part can also have other structures. It is particularly pointed out that the structures presented below have both nMOS and pMOS structures, and the essence is that the PD cathode is connected with the pMOS substrate, and the PD anode is connected with the nMOS substrate. The present application provides embodiment three of the PN type structure, embodiment four of the Schottky type structure, and embodiment five of the pure Ge structure for the type of the Ge-on-Si photodiode GeSi-PD.

[0060] Embodiment three

[0061] As shown in Figure 7 , the photodiode structure is a PN type structure.

[0062] The photodiode structure further includes a silicon substrate region 201, and a top electrode 202 and a second interlayer dielectric layer 205 grown in sequence along one side of the silicon substrate region 201.

[0063] The top electrode 202 has a bottom electrode 204 epitaxially grown on one side thereof.

[0064] The second interlayer dielectric layer 205 is provided with a first metal contact 207 and a second bonding contact 208 on one side thereof, the first metal contact 207 being an external metal contact connected with the top electrode 202 through an internal conductor, and the second bonding contact 208 being an external metal contact connected with the bottom electrode 204 through an internal conductor. The first metal contact 207 and the second bonding contact 208 are filled with a second barrier layer 206, and the first barrier layer 107 and the second barrier layer 206 are made of silicon oxide or silicon nitride.

[0065] When the MOSFET structure is an nMOS structure, the doped body region 103 is a doped body region p + , the bottom electrode 204 is an anode germanium layer p + Ge, the doped source region 109 is a doped source region n + , the doped drain region 110 is a doped drain region n + , and the bottom electrode 202 is a substrate cathode doped region n + Si.

[0066] When the MOSFET structure is a pMOS structure, the doped body region 103 is a doped body region n + , the bottom electrode 204 is a substrate cathode doped region n + Si, the doped source region 109 is a doped source region p + , the doped drain region 110 is a doped drain region p + , and the bottom electrode 202 is an anode germanium layer p + Ge.

[0067] Embodiment four

[0068] AsFigure 8 As shown, the photodiode has a PN-type structure.

[0069] The photodiode structure also includes a silicon substrate region 201, and a top electrode 202 and a second interlayer dielectric layer 205 sequentially grown along one side of the silicon substrate region 201.

[0070] A bottom electrode 204 and a metal layer 209 are epitaxially grown on one side of the top electrode 202.

[0071] A first metal contact 207 and a second bonding contact 208 are provided on one side of the second interlayer dielectric layer 205. The first metal contact 207 is an external metal contact connected to the top electrode 202 through an internal conductor, and the second bonding contact 208 is an external metal contact connected to the bottom electrode 204 through an internal conductor. A second barrier layer 206 is filled between the first metal contact 207 and the second bonding contact 208. The first barrier layer 207 and the second barrier layer 206 are made of silicon oxide or silicon nitride.

[0072] When the MOSFET structure is an nMOS structure, the doped body region 103 is the p-doped body region. + The bottom electrode 204 is an anode germanium layer p + Ge, the doped source region 109 is the doped source region n + Doped drain region 110 is doped drain region n + The bottom electrode 202 is the substrate cathode doped region n + Si.

[0073] When the MOSFET structure is a pMOS structure, the doped body region 103 is the doped body region n. + The bottom electrode 204 is the substrate cathode doped region n. + Si, the doped source region 109 is the doped source region p + Doped drain region 110 is a doped drain region p + The bottom electrode 202 is an anode germanium layer p + Ge.

[0074] Example 5

[0075] like Figure 9 As shown, the photodiode structure also includes a silicon substrate region 201 and a second interlayer dielectric layer 205 grown sequentially along one side of the silicon substrate region 201.

[0076] A top electrode 202, an intrinsic germanium layer 203, and a bottom electrode 204 are disposed between the silicon substrate region 201 and the second interlayer dielectric layer 205.

[0077] The second interlayer dielectric layer 205 is provided with a first metal contact 207 and a second bonding contact 208, the first metal contact 207 is an external metal contact connected by an internal conductor to the top electrode 202, and the second bonding contact 208 is an external metal contact connected by an internal conductor to the bottom electrode 204. The first metal contact 207 and the second bonding contact 208 are filled with a second barrier layer 206, and the first barrier layer 107 and the second barrier layer 206 are made of silicon oxide or silicon nitride.

[0078] When the MOSFET structure is an nMOS structure, the doped body region 103 is a doped body region p + , the bottom electrode 204 is a cathode germanium layer n + Ge, the doped source region 109 is a doped source region n + , the doped drain region 110 is a doped drain region n + , and the bottom electrode 202 is an anode germanium layer p + Ge.

[0079] When the MOSFET structure is a pMOS structure, the doped body region 103 is a doped body region n + , the bottom electrode 204 is an anode germanium layer p + Ge, the doped source region 109 is a doped source region p + , the doped drain region 110 is a doped drain region p + , and the bottom electrode 202 is a cathode germanium layer n + Ge.

[0080] When the device is in operation, the Ge-on-Si photodiode structure is in a reverse bias state, external light enters the Ge-on-Si photodiode structure from the bottom surface of the second wafer 2, i.e. the substrate doped well region, and the generated electron-hole pairs are separated to form a photoelectric current under the action of the Ge-on-Si photodiode structure. Since the GeSi-PD is connected to the MOSFET substrate, if the MOSFET structure is an nMOS structure, holes will accumulate in the substrate, causing the substrate potential to rise, the source-substrate junction to be forward biased, and the threshold voltage of the MOSFET structure to decrease, thereby increasing the output current. If the MOSFET structure is a pMOS structure, electrons will accumulate in the substrate, causing the substrate potential to decrease, the source-substrate junction to be forward biased, and the threshold voltage of the MOSFET structure to decrease, thereby increasing the output current. Based on this, the detector proposed in the application can achieve the performance characteristics of high responsivity and wide spectrum. On the other hand, the stacked structure can further improve the fill factor and reduce the pixel size, thereby realizing a low-cost short-wave infrared imaging chip with a large array and small pixels.

[0081] The photodiode structure of the GeSi-PD is connected to the MOSFET structure substrate, and the photo-induced substrate bias effect is used to improve the gain, responsivity and spectral range of the device.

[0082] The GeSi-PD photodiode structure and the MOSFET structure are prepared on two different wafers, and then the complete device is formed by stacking through hybrid bonding, so that the filling factor is improved, and the pixel size is reduced.

[0083] The present application adopts an innovative physical mechanism, i.e., photo-induced contrast effect, to amplify the photoelectric current, realize high gain, and wide spectrum.

[0084] Based on the above-mentioned physical mechanism, a stack architecture is proposed, and the MOSFET structure and the GeSi-PD photodiode structure are prepared separately, which can optimize the performance independently without being limited by the process platform, and based on the pixel array of the architecture, the filling factor can reach almost 100%, and the pixel size is not affected by the circuit part, so that the pixel size can be further reduced.

[0085] The substrate doped well region 101 can be represented as p - The Si, deep n well region 102 can be represented as DNW, the gate insulating layer 104 can be composed of SiO2, the gate electrode 105 can be represented as poly-Si, the first interlayer dielectric 106 and the second interlayer dielectric layer 205 can be represented as ILD, the N-type well region 111 can be represented as n-well, the silicon substrate region 201 can be represented as Si substrates, the intrinsic germanium layer 203 can be represented as i-Ge, and the metal layer 210 can be represented as metal.

[0086] The above-mentioned is only the preferred embodiment of the present application, and it should be pointed out that for those skilled in the art, without departing from the structure of the present application, a number of modifications and improvements can be made, which will not affect the effect of the present application and the practicability of the patent.

Claims

1. A 3D stacked silicon-based germanium detector, characterized in that, It is constructed by flip bonding of a first wafer (1) and a second wafer (2). The first wafer (1) has a MOSFET structure and the second wafer (2) has a Ge-on-Si photodiode structure for receiving external light and generating electrons and holes. The electrons and holes accumulate in the substrate of the MOSFET structure to change the substrate potential and thereby increase the output current.

2. The 3D stacked silicon-based germanium detector according to claim 1, characterized in that, The MOSFET structure includes a doped region (103) and a first bonding contact (108) connected to the doped region (103) through an internal conductor. The photodiode structure includes a bottom electrode (204) and a second bonding contact (208) connected to the bottom electrode (204) through an internal conductor. The first bonding contact (108) is connected to the second bonding contact (208) by a conductor (3) in a bonding manner.

3. A 3D stacked silicon-based germanium detector according to claim 2, characterized in that, The MOSFET structure further includes a substrate doped well region (101), and a doped source region (109) and a doped drain region (110) prepared in the substrate doped well region (101); A first interlayer dielectric (106) is provided on the substrate doped well region (101), and a gate insulating layer (104) is provided between the doped well region (101) and the first interlayer dielectric (106). A gate electrode (105) is provided on the gate insulating layer (104).

4. A 3D stacked silicon-based germanium detector according to claim 3, characterized in that, The MOSFET structure is an N-type MOSFET; The substrate doped well region (101) is provided with a deep n-well region (102) that divides the substrate doped well region (101) into inner and outer regions, wherein the doped body region (103), the doped source region (109) and the doped drain region (110) are all located in the inner region of the substrate doped well region (101).

5. A 3D stacked silicon-based germanium detector according to claim 3, characterized in that, The MOSFET structure is a P-type MOSFET; The substrate doped well region (101) is provided with an N-type well region (111), and the doped body region (103), the doped source region (109) and the doped drain region (110) are all located in the N-type well region (111).

6. A 3D stacked silicon-based germanium detector according to claim 2, characterized in that, The photodiode structure further includes a silicon substrate region (201), and a top electrode (202) and a second interlayer dielectric layer (205) sequentially grown along one side of the silicon substrate region (201); An intrinsic germanium layer (203) and a bottom electrode (204) are epitaxially grown on one side of the top electrode (202).

7. A 3D stacked silicon-based germanium detector according to claim 2, characterized in that, The photodiode structure further includes a silicon substrate region (201), and a top electrode (202) and a second interlayer dielectric layer (205) sequentially grown along one side of the silicon substrate region (201); A bottom electrode (204) is extended on one side of the top electrode (202).

8. A 3D stacked silicon-based germanium detector according to claim 2, characterized in that, The photodiode structure further includes a silicon substrate region (201), and a top electrode (202) and a second interlayer dielectric layer (205) sequentially grown along one side of the silicon substrate region (201); A bottom electrode (204) and a metal layer (209) are epitaxially grown on one side of the top electrode (202).

9. A 3D stacked silicon-based germanium detector according to claim 2, characterized in that, The photodiode structure further includes a silicon substrate region (201) and a second interlayer dielectric layer (205) grown along one side of the silicon substrate region (201); A top electrode (202), an intrinsic germanium layer (203), and a bottom electrode (204) are provided between the silicon substrate region (201) and the second interlayer dielectric layer (205).

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