Semiconductor carrier tape

Abstract

The invention provides a semiconductor carrier tape, which relates to the field of packaging of semiconductor components, is suitable for packaging electronic components with overhanging pins, comprises a carrier tape body, and is characterized in that the carrier tape body is provided with an integrated groove body for placing a plurality of electronic components which are arranged in a linear array along the length direction of the carrier tape body; the two side walls, close to the two side edges of the carrier tape, of the integrated groove body are provided with a plurality of limiting block sets protruding out of the bottom and the side walls of the integrated groove body, and the limiting block sets are used for limiting electronic components to move in the integrated groove body in the length direction of the carrier tape body. Each limiting block set comprises at least two independent limiting blocks which are distributed on the two side walls of the integrated groove body. The large and long single groove with the length basically equal to the length of the carrier tape body is used for containing all electronic components to be woven, a traditional carrier tape structure in which a single pocket is used for containing a single device in the prior art is replaced, the carrier tape utilization rate is greatly increased, and the packaging cost is remarkably reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor component packaging technology, and more specifically to a semiconductor carrier tape. Background Technology

[0002] Semiconductor carrier tape is a strip-shaped material used for packaging and transporting electronic components. It has a specific thickness and is sold in reels. It is primarily used for packaging semiconductor components such as integrated circuits (ICs), transistors, diodes, and rectifier bridges. It is typically made of plastic (such as polyester or polycarbonate), possessing good insulation, heat resistance, and mechanical strength. Existing carrier tape structures invariably feature evenly spaced grooves or pockets for holding semiconductor components and positioning holes for indexing. These ensure component placement and accurately mark component positions on the carrier tape, facilitating correct identification of each electronic component by automated placement machines. After the component is placed in the carrier tape, a cover tape is used to secure each component within the enclosed space formed by the grooves and cover tape, protecting the electronic component from physical damage and electrostatic discharge during transportation and storage. In the manufacturing process, carrier tape material is typically produced through extrusion molding or injection molding, followed by die stamping or punching to form the required grooves and holes.

[0003] The basic structure of the aforementioned carrier tape has become widespread, and this mature product structure has been used for many years. Existing research on related technologies has only focused on solving technical problems such as the inconvenience of disassembling the carrier tape or the inconvenience of retrieving materials from the carrier tape's placement slot. For example, the technical content disclosed in patent documents with publication numbers CN221852795U and CN219428764U, but there has been no research on improving the basic structure of the carrier tape.

[0004] In common carrier tapes, the standard positioning hole size P0 is 4mm. The spacing P1 between two electronic components is usually an integer multiple of P0. There is usually a certain physical gap between two electronic components on the carrier tape (i.e., between two adjacent grooves). Considering the feasibility of demolding the carrier tape mold, the width of the physical gap is generally at least 0.2~0.4mm. This means that when the material size is close to the P0 size, the P1 size usually needs to be set to twice the P0 size. This results in low carrier tape utilization, high product packaging costs, and low product packaging efficiency.

[0005] Therefore, it is necessary to provide a semiconductor carrier tape structure to solve the problems of low carrier tape utilization and low product packaging efficiency in the prior art. At the same time, it is also necessary to ensure the carrier tape itself can fix electronic components such as diodes and rectifier bridges and facilitate mold demolding. Summary of the Invention

[0006] This invention addresses the aforementioned problems in the prior art by providing a semiconductor carrier tape that satisfies the carrier tape's function of fixing electronic components and facilitating mold demolding, while also offering the advantage of high carrier tape utilization.

[0007] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A semiconductor carrier tape, suitable for packaging electronic components with extended leads, includes a carrier tape body, characterized in that the carrier tape body is provided with an integrated groove along its length for placing multiple electronic components arranged in a linear array (carrier tape preload). Multiple limiting block groups (protruding upward from the bottom of the integrated groove and protruding towards the inside of the groove from the side walls of the integrated groove) are provided on the side walls of the integrated groove near the two sides of the carrier tape, for limiting the movement of electronic components in the integrated groove along the length of the carrier tape body; each limiting block group includes at least two mutually independent limiting blocks and is distributed on the two side walls of the integrated groove.

[0008] Furthermore, the limiting block group is used to limit the movement of electronic components along the length of the carrier tape body within the integrated groove by limiting the pins or encapsulation of the electronic components.

[0009] Furthermore, the pins or encapsulation of the electronic component are constrained by the same group of limiting blocks along the length of the carrier tape body, or the upper limit of the pins or encapsulation of the electronic component along the length of the carrier tape body is located between adjacent groups of limiting blocks.

[0010] Furthermore, the limit blocks in each limit block group are symmetrically or asymmetrically arranged on both sides of the integrated tank.

[0011] Furthermore, the limiting block is a strip-shaped protrusion, a dot-shaped protrusion, or a wedge-shaped protrusion.

[0012] Furthermore, the cross-section of the limiting block is rectangular, circular, near-circular, or elliptical.

[0013] Furthermore, the bottom of the integrated tank is provided with negative pressure adsorption holes that correspond one-to-one with the electronic components inside.

[0014] Furthermore, the carrier tape body has a linear array of positioning holes along its length on its surface, and the positioning holes are located on the outside of the integrated groove, close to the side of the carrier tape body.

[0015] Furthermore, the spacing P1 between adjacent electronic components within the integrated groove is equal to the spacing P0 between the positioning holes. Preferably, P0 is 4 mm and P1 is 4 mm.

[0016] Furthermore, the electronic component has a surface-mount package structure.

[0017] The beneficial effects of this invention are as follows: This invention breaks through the existing technological thinking and changes the conventional structure of existing semiconductor carrier tapes. Specifically, it abandons the commonly used semiconductor carrier tape with grooves / pockets evenly distributed along its length to hold semiconductor components. Instead, it innovatively proposes to eliminate the pocket structure used to fix and place electronic components, and instead designs an integrated slot structure. That is, a long single slot with a length basically the same as the length of the carrier tape body is used to hold all the electronic components to be programmed, replacing the traditional carrier tape structure of placing a single component in a single pocket. This carrier tape structure is specifically designed for surface mount packaging electronic components. At the same time, the limiting block structure set at a specific position can reduce the component spacing P1 to the same as the positioning hole spacing P0. Compared with the existing technology, the number of products that can be packaged by a carrier tape of the same size can be doubled, which greatly improves the carrier tape utilization rate, significantly reduces packaging costs, and also greatly improves the work efficiency of product packaging. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention; Figure 2 yes Figure 1 A schematic diagram of the side view structure; Figure 3 This is a schematic diagram of the usage state of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the usage state of Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the usage state of Embodiment 3 of the present invention (product placed horizontally). Figure 6 This is a schematic diagram of the usage state of Embodiment 4 of the present invention (asymmetrical multi-pin product). Figure 7 These are schematic diagrams of the front view and side cross-sectional structure of a carrier belt in existing technology; In the diagram: 1. Carrier tape body, 2. Integrated groove, 3. Limiting block, 4. Positioning hole, 5. Negative pressure adsorption hole, 6. Bottom protrusion, 7. Rectifier bridge, 8. Diode, 9. Pocket. Detailed Implementation

[0019] The principles and features of the present invention are described below. The embodiments given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0020] Example 1 like Figure 1 and Figure 2As shown, the semiconductor carrier tape provided in this embodiment is suitable for packaging electronic components with extended leads, especially for packaging electronic components with surface mount package structures, specifically diodes, rectifier bridges, etc. It includes a carrier tape body 1, which is made of plastic, 12mm wide, and 0.2mm thick. The carrier tape body 1 has an integrated groove 2 along its length for holding multiple linearly arranged electronic components; that is, it adopts a through-body groove structure, which is used to hold all the electronic components carried by the carrier tape. The carrier tape body 1 has a linear array of positioning holes 4 along its length, with a hole diameter of φ1.55mm, which are used to accurately mark the position of components on the carrier tape so that the automated placement machine can correctly identify each electronic component. The positioning holes 4 are located on the outside of the integrated tank 2, close to the side of the carrier tape body 1, and the spacing P0 between adjacent positioning holes 4 is the commercially available 4mm. The bottom of the integrated tank 2 has negative pressure adsorption holes 5 that correspond one-to-one with the electronic components inside (that is, the negative pressure adsorption holes 5 correspond one-to-one with the electronic component placement station, and the placement station is set on the center line of two adjacent positioning holes 4), with a hole diameter of φ1mm, which is convenient to cooperate with the negative pressure adsorption equipment for negative pressure adsorption pre-positioning of electronic components when they are placed in the tank (this is the prior art).

[0021] The integrated groove 2 has multiple sets of limiting blocks protruding from the bottom and side walls of the integrated groove 2 on its two side walls near the carrier tape. These blocks are used to limit the pins or encapsulation of electronic components, restricting their movement along the length of the carrier tape body 1 within the integrated groove 2 and ensuring the stability of their position within the groove. Each limiting block set includes at least two independent limiting blocks 3 distributed on both side walls of the integrated groove 2. The limiting blocks 3 are located on the centerline of adjacent positioning holes 4. In this specific embodiment, the height of the limiting blocks 3 is slightly lower than the groove depth. Each limiting block set includes two limiting blocks 3, which are symmetrically arranged on both side walls of the integrated groove 2. These blocks are used to insert between two adjacent pins on one side of the electronic component to limit its position. In this embodiment, the limiting blocks 3 are wedge-shaped protrusions. In other embodiments, other structural forms that can play a limiting role, such as strip-shaped or dot-shaped protrusions, can also be used, or they can be designed as limiting blocks with rectangular, circular, near-circular, or elliptical cross-sections.

[0022] The working process of this embodiment, taking the packaging of the rectifier bridge device as an example, involves placing the rectifier bridge 7 into the integrated tank 2, as shown below. Figure 3As shown, the rectifier bridge 7 is placed at the placement station. At this time, the two pins on the same side of a single rectifier bridge 7 are located on both sides of the limiting block 3. The limiting block 3 is used to limit the pins of the rectifier bridge 7, thereby restricting the rectifier bridge 7 from moving along the length of the carrier tape body 1 within the integrated tank 2, preventing displacement, and using negative pressure adsorption for pre-positioning before sealing the cover tape. Furthermore, the symmetrically arranged limiting blocks 3 also limit the rectifier bridge in the width direction of the carrier tape.

[0023] Example 2 The semiconductor carrier tape structure in this embodiment is basically the same as in Embodiment 1, except that it is used for packaging diode products. Each limiting block group includes two limiting blocks 3, which correspond to the positioning holes 4 in the width direction of the carrier tape body. The upper limits of the two side leads of the diode in the length direction of the carrier tape body are located between two adjacent limiting block groups. See Figure 4 As shown.

[0024] Example 3 The semiconductor carrier tape structure in this embodiment is the same as in Embodiment 2, except that, during use, the packaged electronic component can be placed horizontally (with the leads arranged along the length of the carrier tape body), so that the upper limit of the encapsulation of the electronic component in the length direction of the carrier tape body is located between two adjacent limiting block groups. See [link to embodiment]. Figure 5 As shown.

[0025] Example 4 The semiconductor carrier tape structure in this embodiment is basically the same as in Embodiment 1, except that each limiting block group includes three limiting blocks 3. Two limiting blocks 3 are located on one side wall of the integrated groove 2 and are arranged at intervals. The third limiting block 3 is located on the other side wall of the integrated groove 2 and is located on the center line of the aforementioned two limiting blocks 3. This is used to accommodate electronic components with asymmetrical multi-pin structures, so that the pins of the electronic components are restricted by the same limiting block group in the length direction of the carrier tape body 1. See Figure 6 As shown.

[0026] In the above implementation case, since an integrated slot structure is used to house multiple electronic components, the pocket structure of the existing carrier tape is eliminated. Therefore, the spacing P1 between electronic components can be reduced, the number of electronic components packaged per unit length of carrier tape can be increased, and the packaging efficiency is improved.

[0027] Therefore, when used for packaging electronic components with a plastic seal size close to P0 (4mm), the integrated groove structure 2 can reduce the distance P1 between adjacent electronic components from twice P0 in the prior art to P0, which is 4mm. This doubles the number of electronic component placement stations that can be set up with the same size carrier tape, thus doubling the number of electronic components that can be packaged, greatly improving the carrier tape utilization rate and packaging production efficiency.

[0028] Based on the above embodiments, in a preferred embodiment of the present invention, see... Figure 1 and Figure 2 As shown, a bottom protrusion 6, measuring 2.55mm x 4.35mm and with a height of 0.6mm, is provided at the bottom of the integrated tank 2, near the electronic component placement station. Its function is to create a structure with a higher center and lower edges when packaging products where there is a height difference between the pins and the surface of the encapsulation, such as rectifier bridge devices with a gull-foot structure. This provides space for the pins and prevents damage to them. Furthermore, the bottom protrusion 4, in conjunction with the limiting block 3, enhances the limiting effect on the electronic components, preventing them from shifting.

[0029] This invention is not limited to the above-described embodiments. Any technical solution formed by equivalent substitution or equivalent transformation falls within the protection scope of this invention.

Claims

1. A semiconductor carrier tape suitable for packaging electronic components with extended leads, comprising a carrier tape body (1), characterized in that, The carrier tape body (1) is provided with an integrated groove (2) along its length for placing multiple linear array electronic components. Multiple limiting block groups protruding from the bottom and side walls of the integrated groove (2) are provided on the side walls near the sides of the carrier tape to restrict the movement of electronic components within the integrated groove (2) along the length of the carrier tape body (1). Each limiting block group includes at least two independent limiting blocks (30) distributed on the side walls of the integrated groove (2).

2. The semiconductor carrier tape according to claim 1, characterized in that: The limiting block group is used to limit the movement of electronic components within the integrated groove (2) along the length direction of the carrier tape body (1) by limiting the pins or plastic package of the electronic components.

3. The semiconductor carrier tape according to claim 2, characterized in that: The pins or encapsulation of the electronic component are restricted to the same group of limiting blocks along the length of the carrier tape body, or the upper limit of the pins or encapsulation of the electronic component along the length of the carrier tape body is located between adjacent groups of limiting blocks.

4. The semiconductor carrier tape according to claim 1, characterized in that: The limit blocks (30) in each limit block group are symmetrically or asymmetrically arranged on both sides of the integrated tank (2).

5. The semiconductor carrier tape according to claim 1, characterized in that: The limiting block (30) is a strip-shaped protrusion, a dot-shaped protrusion, or a wedge-shaped protrusion.

6. The semiconductor carrier tape according to claim 1 or 5, characterized in that: The cross-section of the limiting block (30) is rectangular, circular, near-circular or elliptical.

7. The semiconductor carrier tape according to claim 1, characterized in that: The bottom of the integrated tank (2) is provided with negative pressure adsorption holes (5) that correspond one-to-one with the electronic components inside.

8. The semiconductor carrier tape according to claim 1, characterized in that: The carrier tape body (1) has a linear array of positioning holes (4) along its length direction on its surface. The positioning holes (4) are located on the outside of the integrated groove (2) and on one side close to the carrier tape body (1).

9. The semiconductor carrier tape according to claim 1, characterized in that: The spacing P1 between adjacent electronic components in the integrated groove (2) is equal to the spacing P0 of the positioning holes (4).

10. The semiconductor carrier tape according to claim 1, characterized in that: The electronic components are surface-mount packaged.

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