Processor and access management method for processor

Abstract

The application relates to a processor and an access management method for the processor. According to the embodiments of the application, the processor can automatically detect whether an access request transmitted in an HBM access channel between an HBF and an HBM is abnormal, and can automatically block the abnormal access request, thereby avoiding abnormal access of the HBM; the processor can form a double-channel architecture for SoC-side access of the HBM based on a Flush operation circuit controlled by a host chip, thereby avoiding the single-point limitation of the SoC side on the HBF, and the Flush operation based on the double-channel architecture can reduce the risk of abnormal working state of the HBM after the abnormal access request is blocked; and the processor can ensure the orderliness in the double-channel architecture through internal arbitration on the Flush operation and the access request. In addition, the reliability and robustness of the SoC-side access of the HBM can be improved.

Description

Technical Field

[0001] This application relates to the field of AI (Artificial Intelligence) chips, and in particular to a processor and an access management method for the processor. Background Technology

[0002] Processors used to implement AI functions can include SoC (System on Chip) and HBM (High Bandwidth Memory). The SoC includes a processing core and HBF (High Bandwidth Fabric), and the processing core can initiate access requests to HBM through HBF.

[0003] In practical applications, access requests to HBM may include abnormal access requests. However, the SoC lacks the ability to handle HBM exceptions when abnormal access requests occur. Furthermore, since the SoC's access requests to HBM rely entirely on the HBF (Hardware Frame), the processor cannot provide the SoC with an alternative for handling HBM exceptions. Consequently, the reliability and robustness of the processor's SoC-side access to HBM are not high.

[0004] As can be seen above, how to improve the reliability and robustness of the processor's SoC-side access to HBM has become a technical problem to be solved in related technologies. Summary of the Invention

[0005] This application provides a processor and an access management method for the processor, which helps to improve the reliability and robustness of the processor's SoC-side access to HBM.

[0006] In one embodiment of this application, a processor is provided, comprising:

[0007] HBM particles;

[0008] The HBM controller is used to perform read and write operations on the HBM particles;

[0009] The SoC is used to transmit access requests to the HBM controller via HBF to perform read and write operations on the HBM particle.

[0010] A bus switching array is located in the HBM access path between the HBF and the HBM controller for transmitting access requests based on the on-chip bus;

[0011] The Flush operation circuit is connected to the bus switching array outside the HBM access path;

[0012] An anomaly response circuit is connected to the bus switching array outside the HBM access path;

[0013] The arbitration circuit is located in the HBM access path between the HBF and the bus switching array, and is configured as follows:

[0014] Access requests transmitted from the HBF to the HBM controller are detected;

[0015] If an abnormal access request is detected, the access request is forwarded to the abnormal response circuit using the bus switching array to block the transmission of the abnormal access request to the HBM controller; and an abnormal interrupt is reported to the host chip interconnected with the processor.

[0016] If the host chip responds to the abnormal interrupt and controls the Flush operation circuit to initiate a Flush operation on the HBM particle to the HBM controller through the bus switching array, then the access request currently transmitted from the HBF to the HBM controller is forwarded to the abnormal response circuit using the bus switching array, so as to block the transmission of the access request to the HBM controller during the period of abnormal handling of the HBM particle using the Flush operation.

[0017] If a normal access request is detected when the Flush operation has not occurred, the transmission of the normal access request to the HBM controller is enabled using the bus switching array.

[0018] In some examples, the Flush operation circuit may optionally have an instruction register, and the host chip controls the Flush operation circuit to initiate the Flush operation by performing register configuration operations on the instruction register.

[0019] In some examples, optionally, the Flush operation circuit has a status register; wherein the status register is set to valid when the host chip is ready to control the Flush operation circuit to initiate the Flush operation, and the status register is set to invalid when the host chip controls the Flush operation circuit to complete the Flush operation; the detection arbitration circuit is further configured to determine whether the Flush operation circuit is currently performing the Flush operation by listening to the status register.

[0020] In some examples, the detection arbitration circuit may optionally have an interrupt register that is monitored by the host chip, and the detection arbitration circuit reports the abnormal interrupt to the host chip by configuring the register of the interrupt register.

[0021] In some examples, the exception response circuit is optionally configured to: in response to an access request received from the bus switching array, return an access failure response to the HBF via the on-chip bus; wherein the on-chip bus is an AXI bus, and the access failure response includes a B-channel write status response or an R-channel read failure information of the AXI bus.

[0022] In some examples, optionally, the detection arbitration circuit is specifically configured to perform at least one of the following detection operations on an access request transmitted from the HBF to the HBM controller: detect whether the access address of the access request is within the address range of the HBM particle; if so, determine that the access request is normal; otherwise, determine that the access request is abnormal; detect whether the access type and access address of the access request match; if the access type of the access request is secure access and the access address of the access request is located in the secure area configured in the HBM particle, or if the access type of the access request is insecure access and the access address of the access request is located in the insecure area configured in the HBM particle, then determine that the access request is normal; if the access type of the access request is secure access and the access address of the access request is located in the insecure area configured in the HBM particle, or if the access type of the access request is insecure access and the access address of the access request is located in the secure area configured in the HBM particle, then determine that the access request is abnormal.

[0023] In some examples, the bus switching array optionally has a first master port, a second master port, a first slave port, and a second slave port, wherein: the HBF and the detection arbitration circuit are cascaded on the first master port; the Flush operation circuit is connected to the second master port; the HBM controller is connected to the first slave port; and the exception response circuit is connected to the second slave port.

[0024] In some examples, optionally, the Flush operation in the bus switching array is configured by default to direct from the second master port to the first slave port; the detection arbitration circuit is specifically configured to control the access request sent from the HBF to the first master port to be selectively switched and forwarded to the first slave port or the second slave port through the switching configuration operation of the access request sent from the HBF to the first master port, so as to enable and block the transmission from the first slave port to the HBM controller.

[0025] In some examples, the detection arbitration circuit is optionally configured to: if an abnormal access request is detected, configure the access request to be forwarded from the first master port to the second slave port in the bus switching array via the switching configuration operation, thereby blocking the transmission of the abnormal access request from the first slave port to the HBM controller by forwarding the access request to the abnormal response circuit; during the Flush operation, configure the access request to be forwarded from the first master port to the second slave port in the bus switching array via the switching configuration operation, thereby blocking the transmission of the access request to the HBM controller during the Flush operation by forwarding the access request to the abnormal response circuit; if an access request transmitted from the HBF to the HBM controller is detected to be normal when the Flush operation does not occur, configure the access request to be forwarded from the first master port to the first slave port in the bus switching array via the switching configuration operation, thereby enabling the transmission of the access request from the first slave port to the HBM controller.

[0026] In some examples, optionally, the access address of the access request transmitted from the HBF to the HBM controller includes the access address of the HBM controller on the on-chip bus; the detection arbitration circuit's switching configuration operation for the access request sent from the HBF to the first master port includes: performing an increment operation to add an indicator bit to the access address of the access request sent to the first master port; wherein, the indicator bit added to the access address of the access request is determined based on the detection result of the access request; when the indicator bit added to the access address of the access request is set to a first value, the indicator bit is used to indicate that the destination port for the switching forwarding of the access request in the bus switching array is the first slave port; when the indicator bit added to the access address of the access request is set to a second value, the indicator bit is used to indicate that the destination port for the switching forwarding of the access request in the bus switching array is the second slave port; and the bus switching array is configured to perform a decrement operation to remove the indicator bit on the access address of the access request successfully switched to the destination port.

[0027] In another embodiment of this application, an access management method for a processor is provided. The processor includes an HBM particle, an HBM controller, a SoC, a bus switching array, a flush operation circuit, and an exception response circuit. The HBM controller is used to perform read and write operations on the HBM particle. The SoC is used to transmit access requests for performing read and write operations on the HBM particle to the HBM controller using an HBF. The bus switching array is located in an HBM access path between the HBF and the HBM controller for transmitting access requests based on an on-chip bus. The flush operation circuit and the exception response circuit are both connected to the bus switching array outside the HBM access path. The access management method includes the following steps performed between the HBF and the bus switching array:

[0028] Access requests transmitted from the HBF to the HBM controller are detected;

[0029] If an abnormal access request is detected, the access request is forwarded to the abnormal response circuit using the bus switching array to block the transmission of the abnormal access request to the HBM controller; and an abnormal interrupt is reported to the host chip interconnected with the processor.

[0030] If the host chip responds to the abnormal interrupt and controls the Flush operation circuit to initiate a Flush operation on the HBM particle to the HBM controller through the bus switching array, then the access request currently transmitted from the HBF to the HBM controller is forwarded to the abnormal response circuit using the bus switching array, so as to block the transmission of the access request to the HBM controller during the period of abnormal handling of the HBM particle using the Flush operation.

[0031] If a normal access request is detected when the Flush operation has not occurred, the transmission of the normal access request to the HBM controller is enabled using the bus switching array.

[0032] In some examples, the Flush operation circuit may optionally have an instruction register, and the host chip controls the Flush operation circuit to initiate the Flush operation by performing register configuration operations on the instruction register.

[0033] In some examples, optionally, the Flush operation circuit has a status register that is enabled when the host chip is ready to control the Flush operation circuit to initiate the Flush operation, and disabled when the host chip controls the Flush operation circuit to complete the Flush operation. Furthermore, the access management method further includes: determining whether the Flush operation circuit is currently performing the Flush operation by listening to the status register.

[0034] In some examples, optionally, the access management method further includes an interrupt register in the processor that is monitored by the host chip, and reporting an abnormal interrupt to the host chip includes: reporting the abnormal interrupt to the host chip by configuring the interrupt register.

[0035] In some examples, the exception response circuit is optionally configured to: in response to an access request received from the bus switching array, return an access failure response to the HBF via the on-chip bus; wherein the on-chip bus is an AXI bus, and the access failure response includes a B-channel write status response or an R-channel read failure information of the AXI bus.

[0036] In some examples, optionally, the access management method detects access requests transmitted from the HBF to the HBM controller by performing at least one of the following detection operations on the access request: detecting whether the access address of the access request is within the address range of the HBM particle; if so, determining that the access request is normal; otherwise, determining that the access request is abnormal; detecting whether the access type and access address of the access request match; if the access type of the access request is secure access and the access address of the access request is located in the secure area configured in the HBM particle, or if the access type of the access request is insecure access and the access address of the access request is located in the insecure area configured in the HBM particle, then determining that the access request is normal; if the access type of the access request is secure access and the access address of the access request is located in the insecure area configured in the HBM particle, or if the access type of the access request is insecure access and the access address of the access request is located in the secure area configured in the HBM particle, then determining that the access request is abnormal.

[0037] In some examples, optionally, the bus switching array has a first master port, a second master port, a first slave port, and a second slave port; the HBF is cascaded on the first master port; the Flush operation circuit is connected to the second master port; the HBM controller is connected to the first slave port; and the exception response circuit is connected to the second slave port. The operation instruction of the Flush operation is configured by default in the bus switching array to be switched and forwarded from the second master port to the first slave port. The access management method controls the access request sent from the HBF to the first master port to be selectively switched and forwarded from the first master port to the first slave port or the second slave port by the switching configuration operation, so as to realize the transmission enable and transmission block from the first slave port to the HBM controller.

[0038] In some examples, optionally, the process of the access management method forwarding an access request transmitted from the HBF to the HBM controller to the exception response circuit includes: configuring the access request to be forwarded from the first master port to the second slave port in the bus switching array via the switch configuration operation; and the process of the access management method enabling the transmission of the access request from the HBF to the HBM controller includes: configuring the access request to be forwarded from the first master port to the first slave port in the bus switching array via the switch configuration operation.

[0039] In some examples, optionally, the access address of the access request transmitted from the HBF to the HBM controller includes the access address of the HBM controller on the on-chip bus, and the access management method for the switching configuration operation of the access request sent from the HBF to the first master port includes: performing an increment operation to add an indicator bit to the access address of the access request sent to the first master port; wherein the indicator bit added to the access address of the access request is determined based on the detection result of the access request; when the indicator bit added to the access address of the access request is set to a first value, the indicator bit is used to indicate that the destination port of the exchange forwarding of the access request in the bus switching array is the first slave port; when the indicator bit added to the access address of the access request is set to a second value, the indicator bit is used to indicate that the destination port of the exchange forwarding of the access request in the bus switching array is the second slave port; and the bus switching array is configured to perform a decrement operation to remove the indicator bit on the access address of the access request that has been successfully exchanged and forwarded to the destination port.

[0040] As can be seen above, based on the embodiments of this application, the processor can automatically detect whether the access requests transmitted in the HBM access path between HBF and HBM are abnormal, and can automatically block abnormal access requests, thus avoiding abnormal access to HBM; the processor, based on the Flush operation circuit controlled by the host chip, can form a dual-path architecture for SoC-side access to HBM, thus avoiding the single-point limitation of the SoC side relying solely on HBF, and the Flush operation based on the dual-path architecture can reduce the risk of HBM entering an abnormal working state after abnormal access requests are blocked; the processor can ensure the orderliness in the dual-path architecture through internal arbitration of Flush operations and access requests. Therefore, the embodiments of this application can help to simultaneously improve the reliability and robustness of SoC-side access to HBM. Attached Figure Description

[0041] The following figures are for illustrative purposes only and do not limit the scope of this application:

[0042] Figure 1 This is a schematic diagram of an exemplary structure of the processor in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram illustrating the principle of the processor's abnormal response in the embodiments of this application;

[0044] Figure 3 This is a schematic diagram illustrating the principle of exception handling by the processor in the embodiments of this application;

[0045] Figure 4 This is a schematic diagram illustrating the principle of normal access of the processor in the embodiments of this application;

[0046] Figure 5 This is an exemplary structural diagram of the bus switching array of the processor in the embodiments of this application;

[0047] Figure 6 This is a schematic diagram illustrating the principle of processor configuration switching operation in the embodiments of this application;

[0048] Figure 7 This is an exemplary flowchart illustrating the access management method for a processor in an embodiment of this application.

[0049] Figure 8 This is a schematic diagram of an example flow of the access management method for a processor in an embodiment of this application. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0051] For example, in the embodiments of this application, the processor can be any one of the following integrated circuit chips suitable for artificial intelligence: GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Units).

[0052] Figure 1 This is a schematic diagram illustrating an exemplary structure of the processor in an embodiment of this application. Please refer to... Figure 1 In embodiments of this application, the processor 90 may include a SoC 10, an HBM 30, and an access management circuit 50, and the processor 90 may be deployed in a heterogeneous architecture including a host chip 70.

[0053] For example, in an embodiment of this application, HBM 30 may include HBM particles 300 and HBM controller 350, and HBM 30 may also include HBM PHY (physical layer architecture) 310 for signal transmission between HBM particles 300 and HBM controller 350. HBM PHY 310 is used to enable data stored in HBM particles 300 to be read and written by HBM controller 350 through HBM PHY 310; that is, HBM controller 350 can be used to perform read and write operations on HBM particles 300.

[0054] For example, in an embodiment of this application, the SoC 10 of the processor 90 may include an HBF 150, and the SoC 10 may use the HBF 150 to transmit an access request to the HBM controller 350 to perform read and write operations on the HBM particle 300. Such an access request is a SoC-side access initiated through the HBF 150.

[0055] For example, in the embodiments of this application, the SoC 10 of the processor 90 may further include multiple processing cores (omitted in the figures). The access request (i.e., SoC-side access) transmitted from the HBF 150 to the HBM controller 350 may be initiated by multiple processing cores of the SoC 10. Furthermore, the access request transmitted in the HBM access path between the HBF 150 and the HBM controller 350 may include multiple access requests initiated by multiple processing cores and transmitted sequentially. In this case, the data stored in the HBM particle 300 may include: task instructions for multiple processing cores of the SoC 10 to execute computation tasks after being obtained through read operations; computation data obtained by multiple processing cores of the SoC 10 through read operations when executing computation tasks; and computation results stored by multiple processing cores of the SoC 10 through write operations after executing computation tasks.

[0056] For example, in an embodiment of this application, the memory space of the provider of the task instructions to the processor 90 can be mapped to the HBM particle 300, and the provider of the task instructions can write the task instructions to the HBM particle 300 in a space-mapped manner (i.e., not belonging to SoC-side access implemented through HBF 150) via the inter-chip bus between the processor 90 and the processor 90. Similarly, in an embodiment of this application, the memory space of the receiver of the calculation results obtained from the processor 90 can be mapped to the HBM particle 300, and the receiver of the calculation results can obtain the calculation results from the HBM particle 300 in a space-mapped manner (i.e., not belonging to SoC-side access implemented through HBF 150) via the inter-chip bus between the processor 90 and the processor 90. For example, at least one of the provider of the task instructions and the receiver of the calculation results can be the host chip 70, or it can be another processing chip other than the host chip 70.

[0057] It is understood that the above description of task instructions, task data, and calculation results is merely intended to illustrate an example of the external sources and destinations of data in the HBM 300 that are accessible to the SoC side, and is not intended to impose unnecessary restrictions on the types of data in the HBM 300, or on the external sources and destinations.

[0058] For example, in the embodiments of this application, the access management circuit 50 in the processor 90 is a circuit structure integrated in the processor 90 to improve the reliability and robustness of the processor's SoC-side access to HBM 30. The access management circuit 50 may include a bus switching array (Matrix) 530, a Flush operation circuit 570, an exception response circuit 550, and a detection arbitration circuit 510.

[0059] For example, in an embodiment of this application, the bus switching array 530 may be located in an HBM access path between the HBF 150 and the HBM controller 350 for transmitting access requests based on the on-chip bus, and the bus switching array 530 may support the diversification of transmission paths based on the on-chip bus, thereby enabling the HBM access path to have bus branch paths based on the on-chip bus.

[0060] For example, in an embodiment of this application, the on-chip bus of the processor 90 may be a bus based on the AMBA (Advanced Microcontroller Bus Architecture) protocol, such as the AXI (Advanced eXtensible Interface) bus.

[0061] For example, in an embodiment of this application, the Flush operation circuit 570 is externally connected (e.g., via an on-chip bus) to the bus switching array 530 of the HBM access path between the HBF 150 and the HBM controller 350, and the exception response circuit 550 can also be externally connected (e.g., via an on-chip bus) to the bus switching array 530 of the HBM access path between the HBF 150 and the HBM controller 350. Thus, the Flush operation circuit 570 and the exception response circuit 550 can form a bus branch path that accesses the HBM access path through the bus switching array 530. Furthermore, the two bus branch paths formed by the Flush operation circuit 570 and the exception response circuit 550 have different functions, which will be described in detail below.

[0062] For example, in an embodiment of this application, the detection arbitration circuit 510 is located between the HBF 150 and the bus switching array 530 in the HBM access path between the HBF 150 and the HBM controller 350. The function of the detection arbitration circuit 510 in the HBM access path may include: identifying abnormal access requests to be transmitted to the HBM controller 350 in the HBM access path; bypassing abnormal access requests using the bus branch path formed by the abnormal response circuit 550; sensing Flush operations initiated from the bus branch path formed by the Flush operation circuit 570; arbitrating conflicts between Flush operations and access requests; and bypassing access requests (whether normal or abnormal) using the bus branch path formed by the abnormal response circuit 550 during the occurrence of a Flush operation.

[0063] For example, in an embodiment of this application, the detection arbitration circuit 510 may be configured to detect (e.g., detect the access address of the access request) each access request transmitted from HBF 150 to HBM controller 350 (i.e., the access request to be transmitted to HBM controller 350 in the HBM access path) to determine whether the access request is an abnormal access request.

[0064] For example, in embodiments of this application, an "abnormality" in an access request can refer to an access request whose access behavior does not conform to a set rule (e.g., the access address of the access request does not conform to a set rule), thus being illegal. Accordingly, the detection arbitration circuit 510 can also be a circuit used for illegal access detection and conflict detection. In this case, the detection arbitration circuit 510 can be specifically configured to perform at least one of the following detection operations on the access request generated by HBF 150:

[0065] Check if the access address of the access request is within the address range of the HBM particle 300; if so, determine that the access request is normal; otherwise, determine that the access request is abnormal.

[0066] The system checks whether the access type and access address of the access request match. If the access type of the access request is secure and the access address is located in the secure zone configured in the HBM particle 300, or if the access type of the access request is insecure and the access address is located in the insecure zone configured in the HBM particle 300, then the access request is determined to be normal, i.e., the access request belongs to a legitimate secure access to the secure zone or a legitimate insecure access to the insecure zone. If the access type of the access request is secure and the access address is located in the insecure zone configured in the HBM particle 300, or if the access type of the access request is insecure and the access address is located in the secure zone configured in the HBM particle 300, then the access request is determined to be abnormal, i.e., the access request belongs to an illegal insecure access to the secure zone or an illegal secure access to the insecure zone.

[0067] Figure 2 This is a schematic diagram illustrating the principle of the processor's exception response in an embodiment of this application. Please refer to [link / reference]. Figure 1 Simultaneous combination Figure 2 In embodiments of this application, the detection arbitration circuit 510 can also be configured as follows:

[0068] If an abnormal access request is detected, that is, if any access request (i.e., any access request in the HBM access path that is to be transmitted to the HBM controller 350) is detected to be abnormal, then, if Figure 2 As shown in ①, the access request is forwarded to the exception response circuit 550 using the bus switching array 530, thereby blocking the transmission of the abnormal access request to the HBM controller 350, and as... Figure 2 As shown in ②, the exception response circuit 550 can also respond to an access request received from the bus switching array 530 by returning an access failure response to the HBF 150 via the on-chip bus.

[0069] Therefore, in the embodiments of this application, since the HBM access path between the HBF 150 and the HBM controller 350 of the processor 90 integrates a detection arbitration circuit 510 located between the HBF 150 and the bus switching array 530, the processor 90 can automatically detect whether the access request on the SoC side is abnormal, and can automatically block the transmission of abnormal access requests to the HBM controller 350. Furthermore, by blocking abnormal access requests, the actual occurrence of abnormal access to the HBM 30 can be avoided, thereby improving the reliability of SoC-side access to the HBM 30.

[0070] For example, in an embodiment of this application, if the on-chip bus is an AXI bus, the access failure response returned by the exception response circuit 550 to the HBF 150 may include the B channel write status response or the R channel read failure information (Dead information) of the AXI bus, thereby matching the AXI protocol and taking into account the functional integrity of the SoC side.

[0071] For example, in an embodiment of this application, the detection arbitration circuit 510 can also be configured as follows:

[0072] If an abnormal access request is detected, that is, if any access request (i.e., any access request in the HBM access path that is to be transmitted to the HBM controller 350) is detected to be abnormal, then, if Figure 2 As shown in ③, an abnormal interrupt is reported to the host chip 70 interconnected with the processor 90.

[0073] For example, in an embodiment of this application, as an example of interrupt reporting, the detection arbitration circuit 510 may have an interrupt register that is monitored by the host chip 70, and the detection arbitration circuit 510 may report abnormal interrupts to the host chip 70 by configuring the interrupt register.

[0074] For example, in an embodiment of this application, after receiving an abnormal interrupt, the host chip 70 can determine whether the SoC 10 needs to perform abnormal handling on the HBM 30. For instance, by predicting whether the HBM 30 will experience abnormal operating states such as data integrity and operational stability anomalies, and ECC (Error Checking and Correcting) anomalies after the abnormal access request is blocked, it can determine whether the SoC 10 needs to perform abnormal handling on the HBM 30.

[0075] For example, in an embodiment of this application, if the host chip 70 determines that the SoC 10 needs to perform abnormal processing on the HBM 30 in response to an abnormal interrupt, the control Flush operation circuit 570 initiates a Flush operation on the HBM particle 300 to the HBM controller 350.

[0076] Therefore, in the embodiments of this application, based on the Flush operation circuit 570 controlled by the host chip 70, a dual-path architecture for SoC-side access to HBM can be formed, thereby avoiding the limitation of the SoC side relying solely on the single path or single point of HBF 150, and improving the robustness of SoC-side access to HBM 30.

[0077] For example, in an embodiment of this application, the Flush operation initiated by the Flush operation circuit 570 under the control of the host chip 70 is a forced write operation. Therefore, the Flush operation can perform exception handling on the HBM 30 (e.g., HBM particle 300) by driving the HBM controller 350 to perform a forced write operation on the HBM particle 300. For example, exception handling implemented using the Flush operation may include forcibly writing exception handling data to the HBM particle 300, and the exception handling data is used to avoid or suppress the HBM 30 from entering an abnormal working state after an abnormal access request is blocked. Thus, the Flush operation based on the dual-path architecture can reduce the risk of the HBM 30 entering an abnormal working state after an abnormal access request is blocked. It is understood that the exemplary description of the exception handling data herein is intended to facilitate understanding of the role of the access path extended by the Flush operation circuit 570, and is not intended to unnecessarily limit the specific methods of exception handling.

[0078] For example, in an embodiment of this application, the Flush operation circuit 570 may have an instruction register, and the host chip 70 may control the Flush operation circuit 570 to initiate a Flush operation by performing a register configuration operation on the instruction register of the Flush operation circuit 570.

[0079] For example, in an embodiment of this application, the Flush operation circuit 570 may also have a status register, which can be enabled when the host chip 70 is ready to control the Flush operation circuit 570 to initiate a Flush operation, and can be disabled when the host chip 70 controls the Flush operation circuit 570 to complete the Flush operation. In this case, the detection arbitration circuit 510 may be further configured to determine whether the Flush operation circuit 570 is currently performing a Flush operation by listening to the status register of the Flush operation circuit 570.

[0080] Figure 3 This is a schematic diagram illustrating the principle of exception handling by the processor in an embodiment of this application. Please refer to [link / reference]. Figure 1 Simultaneous combination Figure 3 In embodiments of this application, the detection arbitration circuit 510 can also be configured as follows:

[0081] If the host chip 70 responds to a received abnormal interrupt and controls the Flush operation circuit 570 to initiate a Flush operation on the HBM particle 300 to the HBM controller 350 via the bus switching array 530, such as Figure 3 As shown in ④, the access request currently being transmitted from HBF 150 to HBM controller 350 is forwarded to the exception response circuit 550 using the bus switching array 530, as follows: Figure 3 As shown in ⑤, during the period when abnormal handling of HBM particles 300 is performed using the Flush operation, the transmission of any access requests in the HBM access path to the HBM controller 350 is blocked. That is, based on the arbitration of the detection arbitration circuit 510, the Flush operation circuit 570 can initiate a bypass HBF 150 Flush operation without being disturbed by access requests. Moreover, as Figure 3 As shown in ⑥, the access request forwarded to the exception response circuit 550 can also cause the exception response circuit 550 to return an access failure response to the HBF 150 via the on-chip bus.

[0082] Therefore, in the embodiments of this application, by arbitrating the flush operation and access request, the conflict between the flush operation and access request in the dual-path architecture can be resolved, thereby ensuring the orderliness in the dual-path architecture and avoiding affecting the reliability of SoC-side access to HBM 30 in order to improve the robustness of SoC-side access to HBM 30. That is, it can balance improving the reliability and robustness of SoC-side access to HBM 30, thereby reducing the risk that SoC 10 will lose overall functionality or enter an unpredictable state due to the lack of abnormal handling capability for HBM 30.

[0083] For example, in an embodiment of this application, the detection arbitration circuit 510 can also be configured as follows:

[0084] If the host chip 70, in response to a received exception interrupt, controls the Flush operation circuit 570 to initiate a Flush operation on the HBM particle 300 to the HBM controller 350 via the bus switching array 530, then for each access request forwarded to the exception response circuit 550 during the Flush operation, a conflict interrupt can be reported to the host chip 70 interconnected with the processor 90, for example, by configuring the interrupt register to report a conflict interrupt. The conflict interrupt can be used only to inform the host chip 70 of access requests interrupted due to the Flush operation, and the host chip 70 does not need to respond to the conflict interrupt.

[0085] Figure 4 This is a schematic diagram illustrating the normal access principle of the processor in an embodiment of this application. Please refer to... Figure 1 Simultaneous combination Figure 4 In embodiments of this application, the detection arbitration circuit 510 can also be configured as follows:

[0086] If a normal access request is detected without a flush operation, that is, if any access request (i.e., any access request in the HBM access path to be transmitted to the HBM controller 350) is detected as normal without a flush operation, then, if Figure 4 As shown, the bus switching array 530 enables the normal transmission of access requests to the HBM controller 350.

[0087] Figure 5 This is an exemplary structural diagram of the bus switching array of the processor in an embodiment of this application. Please refer to... Figure 5 Taking a bus switching array 530 including a 2×2 selector as an example, the bus switching array 530 may have a first master port P_M_1, a second master port P_M_2, a first slave port P_S_1, and a second slave port PS_2, wherein:

[0088] HBF 150 and the detection arbitration circuit 510 can be cascaded (e.g., via an on-chip bus) at the first main port P_M_1;

[0089] The Flush operation circuit 570 can be connected (e.g., via the on-chip bus) to the second master port P_M_2;

[0090] The HBM controller 350 can be connected (e.g., via the on-chip bus) to the first slave port P_S_1;

[0091] The exception response circuit 550 can be connected (e.g., via the on-chip bus) to the second slave port P_S_2.

[0092] Exemplarily, in embodiments of this application, based on such Figure 5 In the bus switching array 530 shown, the Flush operation initiated by the Flush operation circuit 570 can be configured by default to redirect from the second master port P_M_2 to the first slave port P_S_1. That is, the operation instruction of the Flush operation in the bus switching array 530 is configured by default to be forwarded from the second master port P_M_2 to the first slave port P_S_1, so that the Flush operation has a mandatory priority for the occupation of the first slave port P_S_1 of the bus switching array 530. In this case, the detection arbitration circuit 510 can be specifically configured to control the access request sent from HBF150 to the first master port P_M_1 to be selectively switched to the first slave port P_S_1 or the second slave port P_S_2 through the switching configuration operation, so as to realize the transmission enable and transmission block of the access request from the first slave port P_S_1 to the HBM controller 350.

[0093] For example, in an embodiment of this application, the detection arbitration circuit 510 can be specifically configured as follows:

[0094] If an abnormal access request is detected, the access request is configured to be forwarded from the first master port P_M_1 to the second slave port P_S_2 in the bus switching array 530 through a switching configuration operation, so as to block the transmission of the abnormal access request from the first slave port P_S_1 to the HBM controller 350 by forwarding the access request to the abnormal response circuit 550.

[0095] During the Flush operation, the access request is configured to be forwarded from the first master port P_M_1 to the second slave port P_S_2 in the bus switching array 530 via a switch configuration operation, so as to block the transmission of the access request to the HBM controller 350 during the Flush operation by forwarding the access request to the exception response circuit 550.

[0096] If the access request generated by HBF 150 is detected as normal when no flush operation occurs, the access request is configured to be forwarded from the first master port P_M_1 to the first slave port P_S_1 in the bus switching array 530 through the switching configuration operation, so as to enable the transmission of the access request from the first slave port P_S_1 to the HBM controller 350.

[0097] Figure 6 This is a schematic diagram illustrating the principle of processor configuration switching operations in an embodiment of this application. Please refer to [link / reference]. Figure 6In embodiments of this application, the access address of the access request generated by HBF 150 includes the access address of HBM controller 350 on the on-chip bus. Furthermore, the switching configuration operation of the detection arbitration circuit 510 for the access request sent from HBF 150 to the first master port P_M_1 may include: performing an increment operation on the access address of the access request sent to the first master port P_M_1 by adding an indicator bit. The indicator bit added to the access address of the access request can be determined based on the detection result of the access request; and the indicator bit added to the access address of the access request can be used to characterize that the destination port for the switching forwarding of the access request in the bus switching array 530 is either the first slave port P_S_1 or the second slave port P_S_2. That is, when the indicator bit added to the access address of the access request is set to a first value (e.g., "0"), the indicator bit is used to indicate that the destination port of the access request in the bus switching array 530 is the first slave port P_S_1, that is, to the HBM controller 350; when the indicator bit added to the access address of the access request is set to a second value (e.g., "1"), the indicator bit is used to indicate that the destination port of the access request in the bus switching array 530 is the second slave port P_S_2, that is, to the exception response circuit 550.

[0098] For example, in an embodiment of this application, the bus switching array 530 may be configured to perform a subtraction operation to remove the indicator bit on the access address of an access request that has been successfully switched and forwarded to the destination port (i.e., the first slave port P_S_1 or the second slave port P_S_2), so that the access request can be sent from the destination port (i.e., the first slave port P_S_1 or the second slave port P_S_2) in an address format that matches the on-chip bus.

[0099] In another embodiment of this application, an access management method for a processor is also provided. The processor to which this access management method is applicable may include an HBM chip, an HBM controller, a SoC, a bus switching array, a flush operation circuit, and an exception response circuit. The HBM controller is used to perform read and write operations on the HBM chip. The SoC is used to transmit access requests for performing read and write operations on the HBM chip to the HBM controller using the HBF. The bus switching array is located in the HBM access path between the HBF and the HBM controller for transmitting access requests based on the on-chip bus. The flush operation circuit and the exception response circuit are both connected to the bus switching array outside the HBM access path.

[0100] Figure 7 This is an exemplary flowchart illustrating an access management method for a processor according to an embodiment of this application. Please refer to... Figure 7In embodiments of this application, the access management method for a processor may include the following steps performed between the HBF and the bus switching array (e.g., performed by the detection arbitration circuit described above):

[0101] S710: When an access request transmitted to the HBM controller is received from the HBF, the access request is detected (e.g., the access address of the access request is detected). That is, the access request transmitted from the HBF to the HBM controller (e.g., the access address of the access request) is detected.

[0102] If an abnormal access request is detected in S710, the process will redirect to S720 and S730.

[0103] If a normal access request is detected in S710, the process will redirect to S750.

[0104] S720: Utilizing a bus switching array, abnormal access requests are forwarded to the exception response circuit to block the transmission of abnormal access requests to the HBM controller. The exception response circuit, in response to the access request received from the bus switching array, returns an access failure response to the HBF via the on-chip bus. If the on-chip bus is an AXI bus, the access failure response may include a write status response from the B channel of the AXI bus or a read failure message from the R channel.

[0105] S730: Reports an abnormal interrupt to the host chip interconnected with the processor.

[0106] For example, in the embodiments of this application, the access management method may further include an interrupt register in the processor that is monitored by the host chip, and S730 may report abnormal interrupts to the host chip by configuring the interrupt register.

[0107] S750: Detects whether a flush operation is currently occurring in the flush operation circuit.

[0108] For example, in an embodiment of this application, the Flush operation circuit may have an instruction register, and the host chip controls the Flush operation circuit to initiate a Flush operation by performing register configuration operations on the instruction register.

[0109] For example, in the embodiments of this application, the Flush operation circuit may also have a status register. The status register is set to valid when the host chip is ready to control the Flush operation circuit to initiate a Flush operation, and is set to invalid when the host chip controls the Flush operation circuit to complete the Flush operation. Furthermore, S750 can determine whether the Flush operation circuit is currently performing a Flush operation by listening to the status register.

[0110] If the host chip responds to an abnormal interrupt and controls the Flush operation circuit to initiate a Flush operation on the HBM chip to the HBM controller via the bus switching array, then jump to S760.

[0111] If no flush operation has occurred in the current flush operation circuit, jump to S770.

[0112] S760: Uses a bus switching array to forward normal access requests to the exception response circuitry to block the transmission of access requests to the HBM controller during the period when exception handling of HBM particles is performed using the Flush operation, and causes the exception response circuitry to return an access failure response to the HBF via the on-chip bus in response to the access request received from the bus switching array.

[0113] S770: Enables the transmission of normal access requests to the HBM controller using the bus switching array when no flush operation occurs. That is, if a normal access request is detected when no flush operation occurs, the transmission of the normal access request to the HBM controller is enabled using the bus switching array.

[0114] As can be seen above, based on the embodiments of this application, the processor can automatically detect whether the access requests transmitted in the HBM access path between HBF and HBM are abnormal, and can automatically block abnormal access requests, thus avoiding abnormal access to HBM; the processor, based on the Flush operation circuit controlled by the host chip, can form a dual-path architecture for SoC-side access to HBM, thus avoiding the single-point limitation of the SoC side relying solely on HBF, and the Flush operation based on the dual-path architecture can reduce the risk of HBM entering an abnormal working state after abnormal access requests are blocked; the processor can ensure the orderliness in the dual-path architecture through internal arbitration of Flush operations and access requests. Therefore, the embodiments of this application can help to simultaneously improve the reliability and robustness of SoC-side access to HBM.

[0115] Exemplarily, in an embodiment of this application, the detection of an access request transmitted from the HBF to the HBM controller by S710 includes performing at least one of the following detection operations on the access request:

[0116] Check if the access address of the access request is within the address range of the HBM particle; if so, determine that the access request is normal; otherwise, determine that the access request is abnormal.

[0117] Check if the access type and access address of the access request match. If the access type of the access request is secure and the access address is located in the secure zone configured in the HBM granule, or if the access type of the access request is insecure and the access address is located in the insecure zone configured in the HBM granule, then the access request is considered normal. If the access type of the access request is secure and the access address is located in the insecure zone configured in the HBM granule, or if the access type of the access request is insecure and the access address is located in the secure zone configured in the HBM granule, then the access request is considered abnormal.

[0118] For example, in an embodiment of this application, the bus switching array may have a first master port, a second master port, a first slave port, and a second slave port. An HBF (Host Bus Filter) is cascaded at the first master port, a Flush operation circuit is connected to the second master port, an HBM (Host Bus Controller) controller is connected to the first slave port, and an exception response circuit is connected to the second slave port. In this case, the operation command of the Flush operation is configured by default in the bus switching array to be switched and forwarded from the second master port to the first slave port. Furthermore, S720, S760, and S770 can control the access request sent from the HBF to the first master port to be selectively switched and forwarded from the first master port to the first slave port or the second slave port through the switching configuration operation, thereby enabling and blocking transmission from the first slave port to the HBM controller.

[0119] For example, in an embodiment of this application, the process of S720 and S760 forwarding the access request transmitted from HBF to HBM controller to the exception response circuit includes: configuring the access request to be forwarded from the first master port to the second slave port in the bus switching array through a switching configuration operation; and the process of S770 enabling the transmission of the access request from HBF to HBM controller includes: configuring the access request to be forwarded from the first master port to the first slave port in the bus switching array through a switching configuration operation.

[0120] For example, in an embodiment of this application, the access address of the access request transmitted from HBF to HBM controller includes the access address of HBM controller on the on-chip bus, and the switching configuration operation for the access request sent from HBF to the first master port in S720, S760 and S770 includes: performing an increment operation to add an indicator bit to the access address of the access request sent to the first master port; wherein, the indicator bit added to the access address of the access request is determined based on the detection result of the access request; the indicator bit added to the access address of the access request is used to characterize that the destination port for the switching forwarding of the access request in the bus switching array is the first slave port or the second slave port. That is, when the indicator bit added to the access address of the access request is set to a first value (e.g., "0"), the indicator bit is used to indicate that the destination port of the access request in the bus switching array is the first slave port, that is, to the HBM controller; when the indicator bit added to the access address of the access request is set to a second value (e.g., "1"), the indicator bit is used to indicate that the destination port of the access request in the bus switching array is the second slave port, that is, to the exception response circuit.

[0121] For example, in an embodiment of this application, the bus switching array can be configured to perform a subtraction operation to remove the indicator bit on the access address of an access request that has been successfully switched and forwarded to the destination port.

[0122] Figure 8 This is a schematic diagram of an example flow of the access management method for a processor in an embodiment of this application.

[0123] S810: When an access request to the HBM controller is received from the HBF, check whether the access address of the access request is within the address range of the HBM particle.

[0124] If so, then proceed to S815;

[0125] Otherwise, determine that the access request is abnormal and redirect to S820 and S830;

[0126] S815: Check if the access type and access address of the access request match.

[0127] If the access type of the access request is secure access and the access address of the access request is located in the secure zone configured in the HBM particle, or if the access type of the access request is insecure access and the access address of the access request is located in the insecure zone configured in the HBM particle, then the access request is determined to be normal and the process jumps to S850.

[0128] If the access request type is secure access and the access address of the access request is located in the non-secure zone configured in the HBM particle, or if the access request type is non-secure access and the access address of the access request is located in the secure zone configured in the HBM particle, then the access request is determined to be abnormal, and the process is redirected to S820 and S830.

[0129] S820: Increments the access address of the access request sent to the first master port of the bus switching array, and the incremented indicator bit points to the second slave port. This causes the abnormal access request to be forwarded from the second slave port to the abnormal response circuit after the bus switching array performs a decrement operation to remove the indicator bit, thereby blocking the transmission of the abnormal access request from the first slave port to the HBM controller. The abnormal response circuit also responds to the access request received from the bus switching array by returning an access failure response to the HBF via the on-chip bus.

[0130] S830: Reports an abnormal interrupt to the host chip interconnected with the processor.

[0131] S850: Detects whether a flush operation is currently occurring in the flush operation circuit.

[0132] If the host chip responds to an abnormal interrupt and controls the Flush operation circuit to initiate a Flush operation on the HBM chip to the HBM controller via the bus switching array, then jump to S860.

[0133] If no flush operation has occurred in the current flush operation circuit, then jump to S870.

[0134] S860: Increments the access address of the access request sent to the first master port of the bus switching array, and the incremented indicator bit points to the second slave port. This causes the normal access request to be forwarded from the second slave port to the exception response circuit after the bus switching array performs a decrement operation to remove the indicator bit. This blocks the transmission of the normal access request from the first slave port to the HBM controller during the exception handling of the HBM chip using the Flush operation. The exception response circuit responds to the access request received from the bus switching array by returning an access failure response to the HBF via the on-chip bus.

[0135] S870: Increments the access address of the access request sent to the first master port of the bus switching array, and points the incremented indicator bit to the first slave port to enable the transmission of a normal access request from the first slave port to the HBM controller when no flush operation occurs. That is, if a normal access request is detected when no flush operation occurs, the transmission of the normal access request to the HBM controller is enabled using the bus switching array.

[0136] It is understood that, in the embodiments of this application, the various parts described by example may be related by an "and / or" relationship. In this document, "and / or" means that the contexts connected by it may be a common "and" relationship or an alternative "or" relationship. Therefore, the various parts having an "and / or" relationship can be understood to include different combinations of situations where the "and / or" between each pair of parts represents a common "and" relationship or an alternative "or" relationship, and such combinations of different situations can be considered substantially equivalent to the scope of "at least one of the parts".

[0137] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A processor, comprising: comprising: an HBM die; an HBM controller configured to perform read and write operations on the HBM die; a SoC configured to transmit, to the HBM controller via an HBF, an access request for performing a read or write operation on the HBM die; a bus switch array located between the HBF and the HBM controller and configured to transmit the access request in an HBM access path based on an on-chip bus; a Flush operation circuit connected to the bus switch array outside the HBM access path; an exception response circuit connected to the bus switch array outside the HBM access path; a detection arbitration circuit located between the HBF and the bus switch array in the HBM access path and configured to: detect the access request transmitted from the HBF to the HBM controller; and if the access request is detected as an exception, forward the access request to the exception response circuit via the bus switch array to block the transmission of the access request to the HBM controller, and report an exception interrupt to a host chip interconnected with the processor; and if the Flush operation circuit is controlled by the host chip to initiate a Flush operation on the HBM die via the bus switch array in response to the exception interrupt, forward the access request currently transmitted from the HBF to the HBM controller to the exception response circuit via the bus switch array to block the transmission of the access request to the HBM controller during the Flush operation; and if a normal access request is detected when the Flush operation is not performed, enable the transmission of the normal access request to the HBM controller via the bus switch array.

2. The processor of claim 1, wherein: the Flush operation circuit has an instruction register, and the host chip controls the Flush operation circuit to initiate the Flush operation by performing a register configuration operation on the instruction register.

3. The processor of claim 1, wherein: the Flush operation circuit has a status register, wherein the status register is set as valid when the host chip is ready to control the Flush operation circuit to initiate the Flush operation, and the status register is set as invalid when the host chip controls the Flush operation circuit to complete the Flush operation; and the detection arbitration circuit is further configured to determine whether the Flush operation is currently performed by the Flush operation circuit by monitoring the status register.

4. The processor of claim 1, wherein: the detection arbitration circuit has an interrupt register monitored by the host chip, and the detection arbitration circuit reports the exception interrupt to the host chip by performing a register configuration operation on the interrupt register.

5. The processor of claim 1, wherein: the exception response circuit is configured to: in response to an access request received from the bus switch array, return an access failure response to the HBF through the on-chip bus; wherein the on-chip bus is an AXI bus, and the access failure response comprises a B-channel write status response or an R-channel read failure information of the AXI bus.

6. The processor of claim 1, wherein the detection arbitration circuit is specifically configured to perform at least one of the following detection operations on an access request transmitted from the HBF to the HBM controller: detect whether an access address of the access request is within an address range of the HBM die; if yes, determine that the access request is normal; otherwise, determine that the access request is abnormal; detect whether an access type and the access address of the access request match; if the access type of the access request is secure access and the access address of the access request is located in a secure region configured in the HBM die, or if the access type of the access request is non-secure access and the access address of the access request is located in a non-secure region configured in the HBM die, determine that the access request is normal; if the access type of the access request is secure access and the access address of the access request is located in the non-secure region configured in the HBM die, or if the access type of the access request is non-secure access and the access address of the access request is located in the secure region configured in the HBM die, determine that the access request is abnormal.

7. The processor of any one of claims 1-6, wherein the bus switch array has a first master port, a second master port, a first slave port, and a second slave port, wherein: the HBF and the detection arbitration circuit are connected in series at the first master port; the Flush operation circuit is connected to the second master port; the HBM controller is connected to the first slave port; the abnormal response circuit is connected to the second slave port.

8. The processor of claim 7, wherein the Flush operation is configured by default in the bus switch array to be directed from the second master port to the first slave port; the detection arbitration circuit is specifically configured to control, through a switch configuration operation of an access request sent from the HBF to the first master port, the access request to be selectively switched and forwarded from the first master port to the first slave port or the second slave port, to enable transmission enablement and transmission blocking from the first slave port to the HBM controller.

9. The processor of claim 8, wherein the detection arbitration circuit is specifically configured to: if an abnormal access request is detected, configure the access request through the switch configuration operation to be switched and forwarded from the first master port to the second slave port in the bus switch array, to block transmission of the abnormal access request from the first slave port to the HBM controller by forwarding the access request to the abnormal response circuit. during the Flush operation, the access request is configured by the switch configuration operation to be switched and forwarded in the bus switch array from the first master port to the second slave port to block the transmission of the access request to the HBM controller during the Flush operation by forwarding the access request to the exception response circuit; if the access request transmitted from the HBF to the HBM controller is detected to be normal when the Flush operation is not performed, the access request is configured by the switch configuration operation to be switched and forwarded in the bus switch array from the first master port to the first slave port to enable the transmission of the access request from the first slave port to the HBM controller.

10. The processor of claim 8, wherein the access address of the access request transmitted from the HBF to the HBM controller comprises an access address of the HBM controller on the on-chip bus; the switch configuration operation of the detection arbitration circuit on the access request sent from the HBF to the first master port comprises an increment operation of adding an indication bit to the access address of the access request sent to the first master port; wherein the indication bit added to the access address of the access request is determined according to the detection result of the access request; when the indication bit added to the access address of the access request is set to a first value, the indication bit is used to represent that the destination port of the switched and forwarded access request in the bus switch array is the first slave port; when the indication bit added to the access address of the access request is set to a second value, the indication bit is used to represent that the destination port of the switched and forwarded access request in the bus switch array is the second slave port; and the bus switch array is configured to perform a decrement operation of removing the indication bit on the access address of the access request successfully switched and forwarded to the destination port.

11. An access management method for a processor, characterized by, The processor comprises an HBM particle, an HBM controller, an SoC, a bus switch array, a Flush operation circuit and an exception response circuit, the HBM controller is configured to perform read and write operations on the HBM particle, the SoC is configured to transmit an access request for performing read and write operations on the HBM particle to the HBM controller using an HBF, the bus switch array is located between the HBF and the HBM controller in an HBM access path for transmitting an access request based on an on-chip bus, the Flush operation circuit and the exception response circuit are connected to the bus switch array outside the HBM access path, and the access management method comprises the following steps performed between the HBF and the bus switch array: detecting the access request transmitted from the HBF to the HBM controller; If an abnormal access request is detected, the bus switch array is used to forward the access request to the exception response circuit to block the transmission of the abnormal access request to the HBM controller; and an exception interrupt is reported to a host chip interconnected with the processor; If the host chip controls the Flush operation circuit to initiate the Flush operation on the HBM particle through the bus switch array in response to the exception interrupt, the bus switch array is used to forward the access request currently transmitted from the HBF to the HBM controller to the exception response circuit to block the transmission of the access request to the HBM controller during the implementation of the exception processing on the HBM particle by using the Flush operation; If a normal access request is detected when the Flush operation is not performed, the bus switch array is used to enable the transmission of the normal access request to the HBM controller.

12. The access management method for a processor according to claim 11, wherein the Flush operation circuit has an instruction register, and the host chip controls the Flush operation circuit to initiate the Flush operation by a register configuration operation on the instruction register; or the Flush operation circuit has a state register, the state register is set to be valid when the host chip is ready to control the Flush operation circuit to initiate the Flush operation, the state register is set to be invalid when the host chip controls the Flush operation circuit to complete the Flush operation, and the access management method further comprises determining whether the Flush operation circuit currently performs the Flush operation by monitoring the state register; or the access management method further comprises that an interrupt register listened by the host chip is arranged in the processor, and reporting the exception interrupt to the host chip comprises reporting the exception interrupt to the host chip by a register configuration operation on the interrupt register; or the exception response circuit is configured to return an access failure response to the HBF through the on-chip bus in response to the access request received from the bus switch array; wherein the on-chip bus is an AXI bus, and the access failure response comprises a B-channel write state response or an R-channel read failure information of the AXI bus.

13. The access management method for a processor according to claim 11, wherein the detection of the access request transmitted from the HBF to the HBM controller by the access management method comprises at least one of the following detection operations on the access request: detecting whether an access address of the access request is located in an address range of the HBM particle; if yes, determining that the access request is normal; otherwise, determining that the access request is abnormal; determining that the access request is normal if the access type of the access request is secure access and the access address of the access request is located in the secure region configured in the HBM die, or if the access type of the access request is non-secure access and the access address of the access request is located in the non-secure region configured in the HBM die; determining that the access request is abnormal if the access type of the access request is secure access and the access address of the access request is located in the non-secure region configured in the HBM die, or if the access type of the access request is non-secure access and the access address of the access request is located in the secure region configured in the HBM die.

14. The access management method for a processor according to any one of claims 11 to 13, characterized in that, the bus switch array has a first master port, a second master port, a first slave port and a second slave port, the HBF is connected to the first master port, the Flush operation circuit is connected to the second master port, the HBM controller is connected to the first slave port, and the abnormal response circuit is connected to the second slave port; the operation instruction of the Flush operation is configured by default in the bus switch array to be switched and forwarded from the second master port to the first slave port; the access management method controls the access request sent from the HBF to the first master port to be selectively switched and forwarded to the first slave port or the second slave port through the switch configuration operation, so as to realize the transmission enablement and the transmission blocking from the first slave port to the HBM controller.

15. The access management method for a processor according to claim 14, characterized in that, the process of forwarding the access request transmitted from the HBF to the HBM controller to the abnormal response circuit by the access management method includes configuring the access request to be switched and forwarded from the first master port to the second slave port in the bus switch array through the switch configuration operation; and the process of enabling the transmission of the access request from the HBF to the HBM controller by the access management method includes configuring the access request to be switched and forwarded from the first master port to the first slave port in the bus switch array through the switch configuration operation; or The access address of an access request transmitted from the HBF to the HBM controller comprises an access address of the HBM controller on the on-chip bus, and the exchange configuration operation of the access management method on the access request sent to the first master port from the HBF comprises: performing an increment operation on the access address of the access request sent to the first master port by adding an indication bit; wherein the indication bit added to the access address of the access request is determined according to the detection result of the access request; when the indication bit added to the access address of the access request is set to a first value, the indication bit is used to represent that the destination port of the exchange forwarding of the access request in the bus exchange array is the first slave port; when the indication bit added to the access address of the access request is set to a second value, the indication bit is used to represent that the destination port of the exchange forwarding of the access request in the bus exchange array is the second slave port; and the bus exchange array is configured to perform a decrement operation on the access address of the access request successfully exchanged and forwarded to the destination port by removing the indication bit.

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