A method for patterning a high aspect ratio silicon via structure and a semiconductor structure

Abstract

The application discloses a high-aspect-ratio silicon via structure patterning method and a semiconductor structure, and comprises the following steps: forming a silicon cavity on a first surface of a silicon substrate; performing a periodic cycle etching process to form a high-aspect-ratio silicon via structure penetrating through the silicon substrate on the bottom surface of the silicon cavity at less than -15 DEG C; the etching process uses SF6 and O2 as deposition gas; the etching process comprises a first etching stage, a second etching stage and a third etching stage connected in sequence, the first etching stage uses F2 and N2 as etching gas, the second etching stage uses F2 and PF3 as etching gas, and the third etching stage uses F2 and CF4 as etching gas. The application can realize the patterning fabrication of the silicon cavity and the silicon via on the same surface of the silicon substrate, simplifies the process, improves the reliability and uniformity when protecting the sidewall, obtains an extremely vertical sidewall morphology, and improves the etching rate.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a patterning method for high aspect ratio silicon through-hole structures and a semiconductor structure obtained using this method. Background Technology

[0002] In manufacturing micro-electro-mechanical system (MEMS) devices, such as MEMS microphones, front and back processes are typically required, etching silicon vias and cavities on the front and back sides of a silicon substrate, respectively. However, this two-sided processing is complex and affects yield, resulting in high costs. Furthermore, as the distribution density and aspect ratio of silicon vias increase, traditional periodic etching processes, due to physical limitations (such as ion shadowing and reactive gas transport efficiency), are unable to meet these extreme aspect ratio requirements. Therefore, it is often necessary to etch interconnected deep holes on both the front and back sides of the silicon substrate to create through-silicon vias. However, nanoscale linewidths are more sensitive to variations in the thickness of the sidewall passivation layer (such as CF polymer). Large variations in the sidewall passivation layer thickness can easily lead to linewidth misalignment and etching tilt. Therefore, the above method not only suffers from overlay errors but also struggles to guarantee perpendicularity. Furthermore, existing etching processes suffer from problems such as plasma chemical residues and localized roughness peaks (Ra > 5 nm) caused by random deposition of CF polymers on the sidewalls. These factors significantly impact the achievement of higher aspect ratios and nanoscale silicon etching. Moreover, under the requirements of higher aspect ratios and nanoscale linewidths, improving the etching rate and enhancing the uniformity of bottom sidewall protection during the etching process are particularly important. Therefore, it is necessary to investigate a process method that can significantly improve the aforementioned problems. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned problems existing in the prior art and provide a patterning method and semiconductor structure for high aspect ratio silicon through-hole structures, which can realize the patterning fabrication of silicon cavities and silicon through-holes on the same side of the silicon substrate, thereby simplifying the process and improving the reliability and uniformity when protecting the sidewalls, while increasing the etching rate.

[0004] To achieve the above objectives, the technical solution of this application is as follows:

[0005] According to a first aspect of this application, embodiments of this application provide a method for patterning high aspect ratio silicon through-hole structures, including:

[0006] Provide silicon substrates;

[0007] A silicon cavity is formed on the first surface of the silicon substrate;

[0008] Multiple organic masks are formed on the bottom surface of the silicon cavity;

[0009] An etching process is performed at a first temperature of less than -15°C, through the organic mask, to etch the silicon substrate exposed on the bottom surface, forming a high aspect ratio silicon through-hole structure that penetrates the silicon substrate on the silicon substrate below the bottom surface.

[0010] The etching process includes multiple periodic cyclic steps sequentially consisting of a deposition step and an etching step. The deposition step uses a first gas as the deposition gas to form a polymer layer on the sidewalls of the high aspect ratio silicon through-hole structure and the exposed surface of the organic mask during formation, thereby protecting the sidewalls and the organic mask during etching. The etching step uses a second gas as the etching gas to etch the polymer layer and the silicon substrate. The first gas includes SF6 and O2, and the second gas includes F2, as well as N2, PF3, and CF4.

[0011] The etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence, which are used to form the top, middle, and bottom of the high aspect ratio silicon through-hole structure, respectively. The first etching stage uses F2 and N2 as etching gases, the second etching stage uses F2 and PF3 as etching gases, and the third etching stage uses F2 and CF4 as etching gases.

[0012] In some embodiments, the polymer layer includes a SiCOF compound layer. During the deposition step, the active groups of F, O, and S generated by reacting O2 in the first gas with SF6 and silicon substrate material respectively react with CO groups sputtered from organic mask material, and co-deposit occurs at -15°C to form the SiCOF compound layer.

[0013] In some embodiments, when performing the deposition step, plasma formed by O2 in the first gas is also used to perform a first treatment on the exposed surface of the organic mask, causing the exposed surface of the organic mask to oxidize below -15°C and be triggered by deep ultraviolet light in the environment to form a first hardened layer. The first hardened layer and the SiCOF compound layer deposited on the exposed surface of the organic mask together form a first protective layer.

[0014] In some embodiments, during the first etching stage, a plasma formed by N2 in the introduced second gas is also used to perform a second treatment on the sidewall, forming a nitride layer on the sidewall to assist in passivation of the sidewall surface.

[0015] In some embodiments, during the second etching stage, a third treatment is performed on the polymer layer using plasma formed by PF3 in the introduced second gas to alter the properties of the polymer layer and enhance its resistance to lateral etching.

[0016] In some embodiments, during the third etching stage, plasma formed by CF4 in the introduced second gas is also used to provide a higher carbon-to-fluorine ratio to suppress lateral etching of the bottom of the sidewall and to perform a fourth treatment on the exposed surface of the organic mask, forming a first carbon-containing protective film on the exposed surface of the organic mask as a second protective layer.

[0017] In some embodiments, the flow rate ratio of SF6 to O2 in the first gas is SF6:O2 = 1:3 to 1:10.

[0018] In some embodiments, when performing the first etching stage, the flow rate ratio of F2 to N2 in the second gas is: F2:N2 = 5:1 to 10:1.

[0019] In some embodiments, when performing the second etching stage, the flow rate ratio of F2 to PF3 in the second gas is: F2:PF3 = 8:1 to 20:1.

[0020] In some embodiments, when performing the third etching stage, the flow rate ratio of F2 to CF4 in the second gas is F2:CF4 = 5:1 to 10:1.

[0021] In some embodiments, the method further includes: after each of one or two consecutive executions of the deposition step and the etching step, performing a fifth treatment on the sidewall at a second temperature less than -15°C, including using HBr and O2 as third gases to remove a portion of the thickness of the polymer layer deposited on the sidewall and reacting it with the silicon substrate material on the surface of the exposed protrusions on the sidewall to generate a reaction product layer, and using CF4 and Ar as fourth gases to remove the reaction product layer to remove at least a portion of the protrusions.

[0022] In some embodiments, when performing the fifth process, a sixth process is performed on the exposed surface of the organic mask using plasma formed by HBr in the third gas to form a modified layer on the surface of the organic mask. A seventh process is also performed using plasma formed by O2 in the third gas to oxidize the exposed surface of the organic mask below -15°C and trigger a reaction by deep ultraviolet light in the environment to form a second hardened layer. The modified layer and the second hardened layer together form a third protective layer. An eighth process is also performed using plasma formed by CF4 in the fourth gas to form a second carbon-containing protective film on the exposed surface of the organic mask as a fourth protective layer.

[0023] In some embodiments, before forming the silicon cavity, the method further includes: bonding a wafer to a second surface of the silicon substrate opposite to the first surface; after forming the high aspect ratio silicon through-hole structure, the method further includes: removing the wafer.

[0024] In some embodiments, when performing the third etching stage, the wafer is used as an etching stop layer so that the bottom of the high aspect ratio silicon through-hole structure stops at the bonding surface of the wafer.

[0025] According to a second aspect of this application, embodiments of this application also provide a semiconductor structure obtained using a patterning method for high aspect ratio silicon through-hole structures as provided in any of the embodiments of the first aspect above.

[0026] The embodiments of this application may have, or at least have, the following advantages:

[0027] (1) By using small molecule gases (first gas and second gas) instead of traditional large molecule gases such as C4F8 and SF6 as deposition and etching gases, the diffusion coefficient can be increased, the gas transport efficiency can be improved, and the etching gas can be diffused more uniformly, which is more conducive to entering the nanoscale high aspect ratio silicon through-hole structure for etching reaction. This achieves better small-size high aspect ratio deep silicon etching and allows the deposition gas to smoothly enter the bottom of the high aspect ratio silicon through-hole structure, achieving more uniform protection of the sidewalls at a smaller size and significantly improving the etching resistance of organic masks. Furthermore, by keeping the temperature (first temperature) during the etching process below -15°C, ultra-low temperature can be used to change chemical kinetics, enhance physical adsorption, and reduce the reaction rate. This allows the polymer layer to be more densely and uniformly adsorbed on the sidewalls, effectively protecting the sidewalls even at the bottom of the high aspect ratio silicon through-hole structure and effectively suppressing lateral etching, avoiding bottom side-cutting, thereby improving the reliability and uniformity of sidewall protection and obtaining extremely vertical sidewall morphology. Meanwhile, small-molecule etching gases can significantly improve etching rate and etching behavior at high depths (>100µm). This application's embodiments can solve the problems of thickness fluctuations in polymers formed by large-molecule C4F8 deposition affecting nanoscale linewidth control, as well as the ion shadowing effect (nanoscale involves atomic dimensions), effectively improving the uniformity and roughness of local CF polymers, achieving better uniformity (uniform dimensions at the top, middle, and bottom of the high aspect ratio silicon through-hole structure), and better sidewall smoothness. This enables deep silicon etching at nanoscale dimensions (e.g., less than 50nm) with higher aspect ratios (e.g., greater than 100:1). Therefore, after forming the silicon cavity, this application's embodiments only require the etching process of this application to form a high aspect ratio silicon through-hole structure penetrating the silicon substrate on the same side of the silicon cavity. This allows for the etching of both the silicon cavity and the high aspect ratio silicon through-hole structure on the same side of the silicon substrate, reducing the number of two-sided crystal processing steps, reducing the number of processes, and improving the yield and productivity of micro / nano fabrication.

[0028] (2) By using a combination of SF6 and O2 as the deposition gas, O2 reacts with SF6 and silicon substrate materials respectively. The resulting active groups of F, O and S react with CO groups sputtered from organic mask materials and co-deposit on the sidewall surface at an ultra-low temperature below -15℃ to form a SiCOF compound layer with higher etch resistance, which improves the protection of the sidewall. At ultra-low temperature, the SiCOF compound layer will be denser, more uniform and better covered. It can form effective protection even at the bottom of the high aspect ratio silicon through-hole structure. Therefore, only a thin deposition thickness is needed to effectively suppress lateral etching and obtain an extremely vertical sidewall morphology.

[0029] (3) By using a mixture of F2 as the etching gas, the high reactivity of F2 can be utilized to provide an abundant main etchant, reducing dependence on physical bombardment and improving the etching rate. Among them, small molecule reactants and products have a longer mean free path, which can reach the bottom of the high aspect ratio silicon through-hole structure, ensuring the bottom etching rate; the generated ions are lighter and have a more concentrated energy distribution, achieving extreme anisotropic etching, and reducing damage to organic masks, resulting in more vertical sidewalls.

[0030] (4) By subdividing the etching process into sequentially connected first, second, and third etching stages, respectively, the top, middle, and bottom of the high aspect ratio silicon through-hole structure are formed. In the first etching stage, a combination of F2 and N2 is used as the etching gas. The addition of N2 creates a stable plasma, mitigating the instability of the sheath layer and the mask edge effect in the early stages of etching, thus effectively ensuring the stability of the critical dimensions at the top. This also reduces ion sputtering damage during the etching process, improves protection of the organic mask, and allows for the formation of extremely thin layers on the sidewalls. The nitride layer provides auxiliary passivation to the sidewall surface, preventing excessive lateral etching and improving the verticality of the sidewall top. In the second etching stage, using a combination of F2 and PF3 as the etching gas, the incorporation of phosphorus (P) alters the properties of the polymer layer, enhancing its resistance to lateral etching and further improving the verticality and dimensional uniformity of the sidewalls. In the third etching stage, using a combination of F2 and CF4 as the etching gas provides a higher carbon-to-fluorine ratio, enhancing deposition and effectively suppressing lateral etching at the bottom of the sidewalls, thus eliminating the problem of bottom side-cutting. Therefore, this staged etching process not only overcomes the limitations of traditional single-stage etching processes in achieving high-precision control but also provides a more refined and controllable etching scheme for manufacturing high-performance devices, effectively expanding the etching process window and facilitating the realization of silicon through-hole structures with higher aspect ratios and nanoscale dimensions.

[0031] (5) By using HBr and O2 as the third gas at a second temperature of less than -15°C after each one or two consecutive deposition and etching steps, a portion of the thickness of the polymer layer deposited on the sidewall is removed and reacted with the silicon substrate material on the surface of the exposed protrusions on the sidewall to generate a reaction product layer. Then, CF4 and Ar are used as the fourth gas to remove the reaction product layer to remove at least part of the protrusions. Thus, by performing the fifth treatment on the sidewall, the thickness uniformity of the polymer layer on the sidewall can be adjusted and the surface of the sidewall can be smoothed. By alternating the periodic cycle of the deposition and etching steps with the fifth treatment, the etching rate and sidewall quality can be balanced, thereby achieving a high etching rate and high etching precision (atomic level precision). It can also effectively improve the uniformity and roughness of the local polymer, solve the linewidth offset (titling) problem, achieve higher verticality (90°±0.2°), and achieve better uniformity (uniform size of the upper, middle and lower positions of the high aspect ratio silicon through-hole structure) and better sidewall smoothness. Furthermore, by employing multiple processing methods to form various protective layers (first to fourth protective layers) on the exposed surface of the organic mask, the consumption rate of the organic mask can be reduced, thereby further improving the selectivity. Therefore, by performing multiple processing steps on the organic mask, the surface quality and dimensional accuracy of the organic mask are effectively guaranteed. This not only significantly improves the selectivity of the organic mask but also yields more vertical sidewalls, thus positively impacting the achievement of higher aspect ratios and smaller dimensions in deep silicon etching.

[0032] Other advantages of this application will be described in the following detailed description. Attached Figure Description

[0033] Figure 1 This is a flowchart illustrating a graphical method for creating a high aspect ratio silicon through-hole structure, according to a preferred embodiment of this application.

[0034] Figure 2 This is a schematic diagram of a structure provided in a preferred embodiment of the present application, showing a substrate bonded to a second surface of a silicon substrate and a first organic mask formed on a first surface of the silicon substrate.

[0035] Figure 3 This is a schematic diagram of the structure after a silicon cavity is formed on the first surface of a silicon substrate, which is a preferred embodiment of this application.

[0036] Figure 4 This is a schematic diagram of the structure after forming a second organic mask on the bottom surface of a silicon cavity, according to a preferred embodiment of this application.

[0037] Figure 5This is a schematic diagram of a structure after forming a silicon through-hole top structure on a silicon substrate at the bottom of a silicon cavity, according to a preferred embodiment of this application.

[0038] Figure 6 This is a schematic diagram of a structure after a middle structure of a silicon through-hole is formed below the top structure of the silicon through-hole, according to a preferred embodiment of this application.

[0039] Figure 7 This is a schematic diagram of a high aspect ratio silicon through-hole structure formed by continuously forming a bottom structure of silicon through-hole below the middle structure of silicon through-hole, which is a preferred embodiment of this application.

[0040] Figure 8 This is a schematic diagram of the structure after removing the second organic mask and the substrate, provided as a preferred embodiment of this application.

[0041] In the figure: 10. Silicon substrate; 11. First etching window; 12. First organic mask; 13. Carrier; 14. Silicon cavity; 15. Second etching window; 16. Second organic mask; 17. Top structure of silicon through-hole; 18. Middle structure of silicon through-hole; 19. Bottom structure of silicon through-hole; 20. High aspect ratio silicon through-hole structure. Detailed Implementation

[0042] To address the shortcomings of existing technologies, embodiments of this application provide a patterning method for high aspect ratio silicon through-hole structures, including:

[0043] Provide silicon substrates;

[0044] A silicon cavity is formed on the first surface of the silicon substrate;

[0045] Multiple organic masks are formed on the bottom surface of the silicon cavity;

[0046] An etching process is performed at a first temperature of less than -15°C, through the organic mask, to etch the silicon substrate exposed on the bottom surface, forming a high aspect ratio silicon through-hole structure that penetrates the silicon substrate on the silicon substrate below the bottom surface.

[0047] The etching process includes multiple periodic cyclic steps sequentially consisting of a deposition step and an etching step. The deposition step uses a first gas as the deposition gas to form a polymer layer on the sidewalls of the high aspect ratio silicon through-hole structure and the exposed surface of the organic mask during formation, thereby protecting the sidewalls and the organic mask during etching. The etching step uses a second gas as the etching gas to etch the polymer layer and the silicon substrate. The first gas includes SF6 and O2, and the second gas includes F2, as well as N2, PF3, and CF4.

[0048] The etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence, which are used to form the top, middle, and bottom of the high aspect ratio silicon through-hole structure, respectively. The first etching stage uses F2 and N2 as etching gases, the second etching stage uses F2 and PF3 as etching gases, and the third etching stage uses F2 and CF4 as etching gases.

[0049] The embodiments of this application can realize the patterned fabrication of silicon cavities and high aspect ratio silicon through-hole structures on the same side of the silicon substrate, simplifying the process; furthermore, the embodiments of this application can improve the reliability and uniformity of sidewall protection, obtain more vertical sidewalls, and improve the etching rate.

[0050] This application also provides a semiconductor structure obtained using the above-described patterning method for high aspect ratio silicon through-hole structures.

[0051] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0052] refer to Figure 1 According to a first aspect of this application, embodiments of this application provide a method for patterning high aspect ratio silicon through-hole structures, comprising the following steps:

[0053] Step S11: Provide a silicon substrate and bond a carrier onto the front side of the silicon substrate.

[0054] refer to Figure 2 In some embodiments, a silicon substrate 10 is used to fabricate silicon cavities and high aspect ratio silicon through-hole structures through the silicon substrate 10 on the same side surface of the silicon substrate 10.

[0055] In some embodiments, an integrated circuit, such as a transistor structure, may be fabricated on the front side (lower surface, second surface) of the silicon substrate 10, and a silicon cavity needs to be fabricated on the back side (upper surface, first surface) of the silicon substrate 10. On the same side of the silicon cavity, a high aspect ratio silicon through-hole structure is fabricated that penetrates from the back side to the front side of the silicon substrate 10, and the high aspect ratio silicon through-hole structure is connected to the bottom surface of the silicon cavity.

[0056] In some embodiments, the silicon substrate 10 may be doped to meet the desired electrical properties.

[0057] In some embodiments, by bonding a carrier 13 to the front side of the silicon substrate 10, the device structure already fabricated on the front side of the silicon substrate 10 can be protected when a silicon cavity is fabricated on the back side of the silicon substrate 10.

[0058] In some embodiments, the carrier 13 may be, for example, a glass (SiO2) carrier.

[0059] Step S12: Form a silicon cavity on the back side of the silicon substrate.

[0060] refer to Figure 2 In some embodiments, the silicon substrate 10 is inverted, such that the carrier 13 is located below the silicon substrate 10. Then, a first organic mask layer is formed on the upper surface of the silicon substrate 10, and the first organic mask layer is patterned to form a plurality of first organic masks 12 on the upper surface of the silicon substrate 10. Figure 2 The illustration only shows two first organic masks 12 formed on the upper surface of the silicon substrate 10 (but is not limited to this). A first etching window 11 is defined between two adjacent first organic masks 12, and the upper surface of the silicon substrate 10 is exposed at the bottom of the first etching window 11.

[0061] In some embodiments, the first organic material includes a first photoresist. That is, the first organic material mask layer includes a first photoresist layer, and the first organic material mask 12 includes a first photoresist mask.

[0062] In some embodiments, a spin coating process is used to form a first photoresist layer on the upper surface of the silicon substrate 10. Then, a photolithography process is used to lithographically model the first photoresist layer, thereby forming a plurality of first photoresist patterns, namely first organic masks 12, on the upper surface of the silicon substrate 10.

[0063] refer to Figure 3 In some embodiments, a silicon cavity patterning process is performed, and using a first organic mask 12 as a mask, the upper surface of the silicon substrate 10 exposed in the first etching window 11 is etched to form a silicon cavity 14 with its bottom located in the silicon substrate 10 on the upper surface of the silicon substrate 10.

[0064] Then, the first organic mask 12 is removed.

[0065] Step S13: Form multiple organic masks (second organic masks) on the bottom surface of the silicon cavity.

[0066] refer to Figure 4 In some embodiments, a second organic mask layer is formed on the upper surface of the silicon substrate 10 after the first organic mask 12 has been removed, such that the second organic mask layer covers the inner wall of the silicon cavity 14, and the second organic mask layer is patterned to form a plurality of second organic masks 16 on the bottom surface of the silicon cavity 14. A second etching window 15 is defined between two adjacent second organic masks 16, and the silicon substrate 10 is exposed at the bottom of the second etching window 15.

[0067] In some embodiments, the second organic material includes a second photoresist. That is, the second organic material mask layer includes a second photoresist layer, and the second organic material mask 16 includes a second photoresist mask.

[0068] In some embodiments, a spin-coating process is used to form a second photoresist layer on the upper surface of the silicon substrate 10. Then, a photolithography process is used to lithographically model the second photoresist layer, thereby forming a plurality of second photoresist patterns, namely second organic masks 16, on the upper surface of the silicon substrate 10.

[0069] Step S14: Perform the first etching stage of the etching process to etch the silicon substrate exposed on the bottom surface of the silicon cavity to form the top structure of the silicon through-hole.

[0070] In some embodiments, by performing an etching process and using a second organic mask 16 as a mask, periodically etching the silicon substrate 10 exposed on the bottom surface of the silicon cavity 14 within the second etching window 15, at a first temperature less than -15°C, to form a high aspect ratio silicon through-hole structure on the silicon substrate 10 below the bottom surface of the silicon cavity 14, extending from the upper surface (back side) to the lower surface (front side) of the silicon substrate 10.

[0071] The etching process includes multiple periodic cyclic steps, sequentially consisting of a deposition step and an etching step. The deposition step involves forming a polymer layer on the sidewalls (surface of the silicon substrate 10) of the forming high aspect ratio silicon through-hole structure and the exposed surfaces (side and top surfaces) of the second organic mask 16 using a first gas as the deposition gas, to protect the sidewalls and the second organic mask 16 during etching. The etching step involves etching the polymer layer and the silicon substrate 10 using a second gas as the etching gas. The etching step may further include a first etching step and a second etching step; the first etching step removes the polymer layer on the bottom surface to allow the second etching step to continue etching downwards onto the silicon substrate 10. By implementing multiple periodic cyclic steps, the silicon substrate 10 is etched multiple times, thereby forming a high aspect ratio silicon through-hole structure on the silicon substrate 10 below the bottom surface of the silicon cavity 14.

[0072] The first gas includes SF6 and O2.

[0073] The second gas includes F2, as well as N2, PF3 and CF4.

[0074] Furthermore, the etching process includes a first etching stage, a second etching stage, and a third etching stage that are sequentially connected, which are used to form the top, middle, and bottom of the high aspect ratio silicon through-hole structure, respectively.

[0075] refer to Figure 5This step is used to perform the first etching stage of the etching process at an ultra-low temperature (first temperature) of less than -15°C, and to perform periodic cyclic etching on the silicon substrate 10 exposed on the bottom surface of the silicon cavity 14 within the second etching window 15 using the second organic mask 16 as a mask, so as to form a silicon through-hole top structure 17 (the top of the high aspect ratio silicon through-hole structure) on the silicon substrate 10 below the bottom surface of the silicon cavity 14.

[0076] In some embodiments, the first etching stage includes multiple periodic cyclic steps formed sequentially by a deposition step and an etching step. During the deposition step, a first gas is used as the deposition gas to deposit a polymer layer (not shown) on the inner wall of the forming silicon through-hole top structure 17 (the surface of the silicon substrate 10) and the exposed surfaces (top and side surfaces) of the second organic mask 16, to protect the silicon substrate 10 and the second organic mask 16 during the subsequent etching step. A plasma of the first gas is obtained by ionizing the first gas introduced into the process chamber, which is then used to deposit the polymer layer.

[0077] In some embodiments, the polymer layer comprises a SiCOF compound layer.

[0078] SF6 and O2 in the first gas are small molecule gases with molecular weights less than C4F8. They are used to deposit a uniform SiCOF compound layer (polymer layer) on the inner wall of the forming silicon perforated top structure 17 and the exposed surface of the second organic mask 16 at ultra-low temperatures below -15°C.

[0079] The traditionally used deposition gas C4F8 is a large molecule gas. In the process of achieving smaller CD (nanometer-scale linewidth) and higher aspect ratio (>100:1), its deposition range on the sidewalls is mainly in the upper part of deep trenches and deep holes, and it is difficult to penetrate to the bottom of deep silicon structures. Therefore, for high aspect ratio etched structures (such as high aspect ratio silicon through-hole structures), it does not provide sufficient protection for the bottom sidewalls.

[0080] This application embodiment utilizes small-molecule SF6 and O2 instead of traditional large-molecule C4F8 as deposition gases, and maintains a deposition temperature below -15°C. This significantly alters the kinetics of etching chemistry during high aspect ratio silicon through-hole structure etching. The low temperature allows byproducts and added gases generated during the reaction to more readily physical adsorb onto the silicon surface of the silicon substrate 10, rather than being immediately desorbed or sputtered away, thus enhancing physical adsorption capacity. Furthermore, the ultra-low temperature reduces the reaction rate; all surface chemical reaction rates are significantly slowed down at ultra-low temperatures.

[0081] During the deposition step, the combination of SF6 and O2 as the deposition gas facilitates the easy access to the bottom of the high aspect ratio silicon through-hole structure being formed. By reacting O2 with SF6 and the silicon substrate material separately, the reaction between O2 and SF6 generates sulfur-containing oxyfluorides such as SO2F2 and SOF4, as well as fluorine radicals; simultaneously, O2 also reacts with the silicon substrate material to generate SiO2 (SiO2). x F y Most importantly, the generated F, O, and S active groups react with CO groups sputtered from the second organic mask material (second photoresist), co-depositing on the ultra-low temperature sidewall surface to form a SiCOF compound layer as a polymer layer. This SiCOF compound is a more complex and etch-resistant Si-COF compound, commonly referred to as SiFO polymer or SiCOF glaze. This SiFO polymer formed at ultra-low temperatures, compared to CF at room temperature... x Polymers with excellent properties:

[0082] (1) Excellent sidewall protection capability.

[0083] (2) Higher etching resistance: SiFO polymer contains Si-O bonds (which are very strong and stable), making it more resistant to etching than pure CF. x The polymer is more resistant to chemical erosion by F free radicals and physical bombardment by ions, which can significantly improve the etching resistance of the second organic mask 16.

[0084] (3) Better coverage and stability: Physical adsorption at low temperature makes the protective film denser and more uniform, and can better cover the sidewalls. It can form effective protection even at the bottom of the high aspect ratio silicon through-hole structure being formed. Therefore, only a thin deposition thickness is needed to effectively suppress lateral etching and avoid bottom side-cutting, thereby improving the reliability and uniformity of sidewall protection and obtaining extremely vertical sidewall morphology.

[0085] Furthermore, when the small molecule deposition gas system of this application embodiment cooperates with the second organic mask 16, the following advantages will also be achieved:

[0086] (1) Reduce the loss of the second organic mask 16:

[0087] In terms of chemistry: the traditional C4F8 deposition gas system generates a large number of F atoms, which chemically erode the second organic mask 16 (the main component of the photoresist is a hydrocarbon polymer), causing the second organic mask 16 to be consumed too quickly. However, in the small molecule system of SF6 and O2 in the embodiments of this application, the number of F atoms is relatively small, and the Si-O bonds contained in the SiCOF compound can better resist the chemical erosion of F free radicals and the physical bombardment of ions, greatly reducing the chemical erosion of the second organic mask 16.

[0088] From a physical perspective: the plasma conditions required for small molecule deposition are generally milder than those for large molecules, with relatively low ion energy, which reduces the physical sputtering of the second organic mask 16.

[0089] (2) Suppressing the bowing morphology:

[0090] The formation mechanism of drum-shaped defects: During the etching process, if the sidewall protective layer (polymer layer) is not strong enough, high-energy particles and free radicals from the plasma will laterally erode the sidewalls from the top opening. The closer to the top, the stronger the bombardment and the cumulative effect over time, causing the sidewalls to be hollowed out, forming a drum shape.

[0091] Therefore, the robust protective layer (SiCOF compound layer) formed by the small molecule deposition gas system in this embodiment can effectively resist this lateral erosion, thus requiring only a thin deposition thickness to effectively avoid lateral etching. Furthermore, since the polymer layer can extend all the way to the bottom, it ensures that the etching rate is anisotropic from top to bottom, thereby maintaining the vertical sidewall morphology.

[0092] In some embodiments, during the deposition step, plasma formed by O2 in the deposition gas is used to perform a first treatment on the exposed surface of the second organic mask 16, causing the exposed surface of the second organic mask 16 to undergo slight oxidation at an ultra-low temperature below -15°C and be triggered by deep ultraviolet light present in the environment to form a first hardened layer.

[0093] During the deposition step, the O2 added to the deposition gas slightly oxidizes and hardens the surface of the photoresist material of the second organic mask 16, forming a thin and durable "crust," i.e., a first hardened layer is formed on the surface of the second organic mask 16. Simultaneously, a SiCOF compound layer is also deposited on the surface of the second organic mask 16 during the deposition step. Thus, the first hardened layer and the SiCOF compound layer deposited on the exposed surface of the second organic mask 16 together form a composite protective layer (the first protective layer). This composite protective layer significantly slows down the erosion rate of F free radicals on the second organic mask 16, thereby significantly improving the selectivity of the second organic mask 16. This means that a thinner second organic mask 16 can be used to etch deeper silicon structures.

[0094] In some embodiments, the flow ratio of SF6 to O2 in the deposition gas is SF6:O2 = 1:3 to 1:10. For example, the flow ratio of SF6 to O2 can be 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9 or 1:10, and the flow ratio of O2 can vary continuously between 3 and 10. However, it is not limited to this.

[0095] After the polymer layer is formed, an etching step is performed at a first temperature, using a small molecule second gas as the etching gas to etch the polymer layer and the silicon substrate 10.

[0096] In some embodiments, at an ultra-low temperature (first temperature) below -15°C, the etching steps included in the etching process are continued, and a combination of F2 and N2 is used as the etching gas to etch the polymer layer and silicon substrate 10 formed in the previous step. By ionizing the F2 and N2 introduced into the process chamber, an F2 and N2 plasma is obtained, which is used to etch the polymer layer and silicon substrate 10. Further, through the first etching step and the bombardment of the F2 and N2 plasma, the polymer layer at the bottom of the second etching window 15 (bottom of the silicon cavity 14) is removed, and then through the second etching step, the exposed silicon substrate 10 is etched downwards using the F2 and N2 plasma. By implementing multiple periodic cycles of the etching process, a silicon through-hole top structure 17 with a certain etching depth is first formed on the upper surface of the silicon substrate 10, such as... Figure 5 As shown (after etching, there are still residual polymer layers on the sides of the second organic mask 16 and the sidewalls of the silicon through-hole top structure 17), Figure 5 (This has been omitted). The formed silicon through-hole top structure 17 corresponds to the top of the high aspect ratio silicon through-hole structure.

[0097] In the first etching stage, when using a combination of F2 and N2 as the etching gas, the main reactive groups are: F•, N•. +N2 + N2 can dilute F2, preventing excessive reaction, and can form a stable plasma. This can mitigate the severe etching behavior in the top region caused by sheath instability and mask edge effects during the initial etching stage, effectively ensuring the stability of critical dimensions at the top. It can also reduce ion sputtering damage during etching, improving the protection of the second organic mask 16. Furthermore, N... + N2 + It is a light ion, which can efficiently transfer energy to the bottom and minimize sputtering damage.

[0098] In some embodiments, during the first etching stage, plasma formed by N2 in the introduced second gas is also used to perform a second treatment on the sidewalls of the forming silicon through-hole top structure 17, forming an extremely thin nitride layer on the sidewalls to assist passivation of the sidewall surface, which can prevent excessive lateral etching, improve the verticality of the sidewall top, and further improve the fidelity of the etched pattern, thus enabling the obtaining of more vertical sidewalls.

[0099] In some embodiments, when using a combination of F2 and N2 as the etching gas, the flow ratio of F2 to N2 is F2:N2 = 5:1 to 10:1. For example, the flow ratio of F2 to N2 can be 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1, and the flow ratio of F2 can vary continuously between 5 and 10. However, it is not limited to this. N2 serves to provide light ions and stabilize the plasma, and within the above flow ratio range, excessive dilution of F2 can be avoided to prevent a decrease in the etching rate.

[0100] Step S15: Perform the second etching stage of the etching process, etch the bottom of the top structure of the silicon through-hole, and then form the middle structure of the silicon through-hole below the top structure of the silicon through-hole.

[0101] refer to Figure 6 This step is used to continue the second etching stage of the etching process at an ultra-low temperature (first temperature) of less than -15°C, and to perform periodic cyclic etching on the silicon substrate 10 exposed on the bottom of the silicon through-hole top structure 17 using the second organic mask 16 as a mask, and to form the silicon through-hole middle structure 18 (the middle part of the high aspect ratio silicon through-hole structure) below the silicon through-hole top structure 17.

[0102] In some embodiments, the second etching stage includes multiple periodic cyclic steps formed sequentially by a deposition step and an etching step. At the start of the deposition step, a first gas is used as the deposition gas to deposit a polymer layer (not shown) on the inner wall of the silicon via top structure 17 (the surface of the silicon substrate 10) and the exposed surfaces (top and side surfaces) of the second organic mask 16, to protect the silicon substrate 10 (etched structure sidewalls) and the second organic mask 16 during the subsequent etching step. Then, using F2 and PF3 as etching gases, the etching step in the etching process is performed to etch the polymer layer and the silicon substrate 10. Specifically, through the first etching step and the bombardment of plasmas from F2 and PF3, the polymer layer on the bottom of the silicon via top structure 17 is first removed. Then, through the second etching step, the exposed silicon material on the bottom of the silicon via top structure 17 is etched downwards using plasmas from F2 and PF3. By performing multiple cyclic etching processes, a middle structure 18 of the silicon through-hole is formed below the top structure 17, as shown below. Figure 6 As shown ( Figure 6 The horizontal dashed line in the image represents the original bottom of the silicon through-hole top structure 17. After the etching step, residual polymer layers remain on the sides of the second organic mask 16 and the sidewalls of the silicon through-hole top structure 17 and the silicon through-hole middle structure 18. Figure 6 (This has been omitted). The central structure 18 of the formed silicon through-hole corresponds to the central structure of the high aspect ratio silicon through-hole structure.

[0103] When using a combination of F2 and PF3 as the etching gas, the main reactive groups are: F•, PF2. + PF + F2 exhibits high reactivity, providing an abundant primary etchant that not only reduces reliance on physical bombardment but also enhances the etching rate. PF x + It is a light ion, which can efficiently transfer energy to the bottom and enhance the etching reaction. At the same time, due to its light weight, it has a lower physical sputtering yield on the material, reducing physical damage to the bottom silicon and back sputtering of the top photoresist.

[0104] In some embodiments, during the second etching stage, plasma formed by PF3 in the introduced second gas is also used to perform a third treatment on the polymer layer to change the properties of the polymer layer by incorporating P element, thereby enhancing the polymer layer's resistance to lateral etching, which can further improve the verticality and dimensional uniformity of the sidewalls and improve the quality of the etched middle section.

[0105] In some embodiments, when the etching gas uses a combination of F2 and PF3, the flow ratio of F2 to PF3 is F2:PF3 = 8:1 to 20:1. For example, the flow ratio of F2 to PF3 can be 8:1, 9:1, 10:1, 12:1, 15:1, 18:1, or 20:1, and the flow ratio of F2 can vary continuously between 8 and 20. However, it is not limited to this. PF3 is mainly used to introduce phosphorus (P) and light ions.

[0106] Step S16: Perform the third etching stage of the etching process to etch the bottom of the central structure of the silicon through-hole and form the bottom structure of the silicon through-hole below the central structure of the silicon through-hole to form a high aspect ratio silicon through-hole structure that penetrates the silicon substrate.

[0107] refer to Figure 7 This step is used to continue the third etching stage of the etching process at an ultra-low temperature (first temperature) of less than -15°C, and to perform periodic cyclic etching on the silicon substrate 10 exposed on the bottom of the silicon through-hole middle structure 18 using the second organic mask 16 as a mask, and to form the silicon through-hole bottom structure 19 (the bottom of the high aspect ratio silicon through-hole structure) below the silicon through-hole middle structure 18.

[0108] In some embodiments, the third etching stage includes multiple periodic cyclic steps formed sequentially by a deposition step and an etching step. At the start of the deposition step, a first gas is used as the deposition gas to deposit a polymer layer (not shown) on the inner walls (surface of the silicon substrate 10) of the top structure 17 of the silicon through-hole, the middle structure 18 of the silicon through-hole, and the exposed surfaces (top and side surfaces) of the second organic mask 16. This protects the silicon substrate 10 (etched structure sidewalls) and the second organic mask 16 during the subsequent etching step. Then, F2 and CF4 are used as etching gases to etch the polymer layer and the silicon substrate 10. Specifically, through the first etching step and the bombardment of F2 and CF4 plasma, the polymer layer at the bottom of the middle structure 18 of the silicon through-hole is removed. Then, through the second etching step, the plasma of F2 and CF4 continues to etch downwards to the exposed silicon material at the bottom of the middle structure 18 of the silicon through-hole. By performing multiple cyclic etching processes, a bottom structure 19 of the silicon through-hole is formed below the middle structure 18, as shown below. Figure 7 As shown ( Figure 7 Two horizontal dashed lines represent the original bottoms of the top structure 17 and the middle structure 18 of the silicon through-hole (SIoT). After the etching step, residual polymer layers remain on the sides of the second organic mask 16 and the sidewalls of the top, middle, and bottom structures 19 of the SIoT. Figure 7(Omitted). The formed silicon through-hole bottom structure 19 corresponds to the bottom of the high aspect ratio silicon through-hole structure. Thus, a high aspect ratio silicon through-hole structure 20, consisting of a successive silicon through-hole top structure 17, a silicon through-hole middle structure 18, and a silicon through-hole bottom structure 19, is formed on the silicon substrate 10, as shown in the figure. Figure 7 As shown.

[0109] In some embodiments, when performing the third etching stage, the wafer 13 is used as an etching stop layer, so that the bottom of the formed high aspect ratio silicon through-hole structure 20 (the bottom of the silicon through-hole bottom structure 19) stops on the bonding surface of the wafer 13, forming a high aspect ratio silicon through-hole structure 20 that penetrates the back and front sides of the silicon substrate 10.

[0110] In some embodiments, during the third etching stage, plasma formed by CF4 in the introduced second gas is also used to provide a higher carbon-to-fluorine ratio to suppress lateral etching of the bottom sidewall of the high aspect ratio silicon through-hole structure 20, thereby eliminating the problem of bottom side-cutting and allowing a fourth treatment of the exposed surface of the second organic mask 16 to form a first carbon-containing protective film on the exposed surface of the second organic mask 16 as a second protective layer, which can reduce the consumption rate of the second organic mask 16 and further improve the selectivity.

[0111] Therefore, the embodiments of this application, by performing the etching process in stages, not only overcome the limitations of traditional single etching processes in achieving high-precision control, but also provide a more refined and controllable etching scheme for the manufacturing of high-performance devices, effectively expanding the etching process window.

[0112] In some embodiments, when the etching gas uses a combination of F2 and CF4, the flow rate ratio of F2 to CF4 is F2:CF4 = 5:1 to 10:1. For example, the flow rate ratio of F2 to CF4 can be 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1, and the flow rate ratio of F2 can vary continuously between 5 and 10. However, it is not limited to this. CF4 can provide carbon for slight passivation. Within the above ratio range, the phenomenon of switching from the etching mode to the deposition mode and causing etching to stop can be avoided.

[0113] In some embodiments, the first temperature is -80°C to -15°C. For example, the first temperature can be -80°C, -70°C, -60°C, -50°C, -40°C, -30°C, -20°C, or -15°C, or any value between any two of the aforementioned temperature values. However, it is not limited to this.

[0114] In some embodiments, the deposition step is performed over a period of 0.1 s to 2 s. For example, the deposition step can be performed over a period of 0.1 s, 0.2 s, 0.3 s, 0.4 s, 0.5 s, 0.7 s, 0.9 s, 1 s, 1.2 s, 1.5 s, 1.8 s, or 2 s, or any value between any two of the aforementioned time values. However, it is not limited to these values.

[0115] In some embodiments, the pressure during the deposition step is 5 mTorr to 200 mTorr. For example, the pressure can be 5 mTorr, 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the aforementioned pressure values. However, it is not limited to these.

[0116] In some embodiments, the source power is 500W to 3000W when performing the deposition step. For example, the source power can be 500W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the aforementioned source power values. However, it is not limited to these.

[0117] In some embodiments, the bias power is 10W to 200W when performing the deposition step. For example, the bias power can be 10W, 20W, 50W, 70W, 100W, 130W, 160W, 180W, or 200W, or any value between any two of the aforementioned bias power values. However, it is not limited to this.

[0118] In some embodiments, the total time for performing the etching step is 0.2s to 4s, wherein the time for the first etching step and the second etching step are 0.1s to 2s, respectively. For example, the time for performing the first etching step or the second etching step can be 0.1s, 0.2s, 0.3s, 0.4s, 0.5s, 0.7s, 0.9s, 1s, 1.2s, 1.5s, 1.8s, or 2s, or any value between any two of the aforementioned time values. However, it is not limited to these values.

[0119] In some embodiments, the pressure during the etching step is 5 mTorr to 200 mTorr. For example, the pressure can be 5 mTorr, 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the aforementioned pressure values. However, it is not limited to these.

[0120] In some embodiments, the source power is 500W to 3000W when performing the etching step. For example, the source power can be 500W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the aforementioned source power values. However, it is not limited to these.

[0121] In some embodiments, the bias power is 10W to 200W when performing the etching step. For example, the bias power can be 10W, 20W, 50W, 70W, 100W, 130W, 160W, 180W, or 200W, or any value between any two of the aforementioned bias power values. However, it is not limited to this.

[0122] When this application uses smaller molecule fluorine gas (F2) and its mixtures (combinations of F2 and N2, F2 and PF3, and F2 and CF4) as etching gases to replace the traditional large molecule SF6 gas, the diffusion is more uniform, which is more conducive to reaching the bottom for etching reaction. By mixing F2 with other gases (nitrogen or fluorine-containing gases), various etching gases with different effects can be formed, thus achieving superior etching depth. Furthermore, although SF6 has six F atoms, only one F ion can dissociate to participate in the etching reaction; the remaining SF5 does not participate in the reaction and is thus extracted. F2 gas, on the other hand, can dissociate to produce two F ions, participating in more reactants than SF6, which can increase the etching rate, especially for etching structures at high depths (e.g., greater than 100 µm), significantly improving the machine's throughput.

[0123] Therefore, by employing the aforementioned small-molecule etching and deposition gases, this embodiment effectively increases the diffusion coefficient, improves the transport efficiency of the reactive gas, and solves the problem of the influence of thickness fluctuations of large-molecule C4F8 polymers on the control of sidewall perpendicularity. This effectively improves the uniformity and roughness of the local polymer, thereby achieving etching of silicon through-hole structures with superior uniformity, better sidewall smoothness, higher aspect ratio, and nanoscale dimensions. Simultaneously, using a mixed gas of F2 as the etching gas significantly improves the etching rate and etching behavior at high depths.

[0124] This application embodiment, by changing the etching gas from traditional SF6 to a combination of small-molecule F2 mixed gases, can better adapt to the needs of advanced processes. By optimizing reaction chemistry and plasma physics, significant performance improvements are achieved in molecular transport, reaction efficiency, and morphology control, which is a key technical path to achieve ultra-high aspect ratio etching.

[0125] The differences between using a mixture of F2 and other gases as an etching gas and using traditional SF6 as an etching gas include:

[0126] (1) It can efficiently generate high-density F atoms: it provides abundant main etchant (F atoms) through a more efficient dissociation path.

[0127] (2) Excellent deep-hole transport capability: Small molecule reactants and products have a longer mean free path, which can reach the bottom of the deep hole and ensure the bottom etching rate.

[0128] (3) Precise control of ion energy and angle: The generated ions are lighter and have a more concentrated energy distribution, achieving the ultimate anisotropic etching and reducing damage to the second organic mask 16.

[0129] (4) It can suppress defects such as bowing and obtain more vertical sidewalls.

[0130] The common advantage mechanism of small molecule groups in the etching gas of the above-described embodiments of this application in the etching step may include:

[0131] (1) Higher F atom density and deep hole penetration capability: The dissociation energy of small molecule gases is usually lower than that of SF6. Under the same plasma conditions, a higher concentration of F atoms can be generated. F atoms and small molecule ions are lightweight and have a long mean free path, which can effectively diffuse to the bottom of the deep hole, maintain the etching rate at the bottom, and avoid "etching stop".

[0132] (2) Better Ion-Assisted Etching: The essence of etching is "ion-enhanced chemical etching". Removal of the bottom silicon requires: a) chemical reaction by F atoms; b) ion bombardment to provide energy, break Si-Si bonds, and sputter away byproducts. Light ions (such as CF3) + ) compared to SF x + Heavy ions can transfer energy to the bottom surface more effectively, enhancing the etching reaction; at the same time, due to their light weight, the physical sputtering yield of the material is lower, reducing physical damage to the bottom silicon and back sputtering of the top second organic mask 16.

[0133] (3) Suppressing drum-shaped morphology: The formation of drum-shaped morphology includes local failure of the sidewall protective layer, leading to lateral etching of silicon by F atoms and ions from the sides. The advantages of small molecule systems are: a) Higher F atom density means that the deposition step can be switched more quickly, avoiding lateral etching caused by long etching steps; b) It can assist in sidewall passivation (e.g., N2); c) A more concentrated vertical ion beam reduces laterally scattered ions. The combined effect of these three factors ensures that etching is carried out primarily in the vertical direction.

[0134] (4) Reduced consumption of the second organic mask 16 due to physical bombardment: The ions generated by the small molecule system are lighter and have lower momentum than the heavy ions generated by SF6 under the same bias voltage. Therefore, the physical sputtering rate of the second organic mask 16 is significantly reduced, resulting in less consumption of the second organic mask 16 and improved pattern fidelity.

[0135] (5) Reduce the consumption of the second organic mask 16 due to chemical erosion: Although F atoms will erode the second organic mask 16, the small molecule system shortens the overall process time through higher etching efficiency, which indirectly reduces the cumulative exposure time of the second organic mask 16.

[0136] In some embodiments, after each consecutive deposition and etching step, scallop-shaped stripes (not shown) are regularly formed on the sidewall. Each scallop-shaped stripe has a recess at its bottom and a protrusion at the junction of two scallop-shaped stripes, resulting in a rough surface morphology on the sidewall. Therefore, in this embodiment, after each one or two consecutive deposition and etching steps, a fifth treatment step is embedded at a second temperature below -15°C to promptly remove excess polymer layer on the sidewall, preventing uneven etching caused by excessive polymer thickness. This fifth treatment also removes at least some of the protrusions, reducing the roughness of the sidewall and improving its smoothness.

[0137] In some embodiments, the fifth process specifically includes: using plasma of HBr and O2 (a third gas) to react with the polymer layer, removing a portion of the thickness of the polymer layer deposited on the sidewall to adjust the thickness uniformity of the polymer layer on the sidewall, and reacting with the silicon material on the surface of the exposed protrusions on the sidewall to generate a silicon tetrabromide layer and a silicon dioxide layer (reaction product layer); subsequently, stopping the introduction of HBr and O2, and using plasma of CF4 and Ar (a fourth gas) to bombard the sidewall to etch and remove the silicon dioxide on the protrusions, and to desorb the tetrabromosilane and remove it from the sidewall, thereby removing at least a portion of the protrusions by removing the reaction product layer, and forming a smoother new sidewall, making the sidewall smoother, thereby reducing the roughness of the sidewall surface, and effectively avoiding the local roughness peaks (Ra > 5 nm) caused by the random deposition of polymer on the sidewall in the past.

[0138] By alternating between the periodic cycles of deposition and etching steps and the fifth processing step, the etching rate and sidewall quality can be balanced, thereby achieving high etching rate and high etching precision (atomic level precision). It can also effectively improve the uniformity and roughness of local polymers, solve the linewidth offset (titling) problem, achieve higher perpendicularity (90°±0.2°), and achieve better uniformity (uniform size of the upper, middle and lower positions of the high aspect ratio silicon through-hole structure) and better sidewall smoothness.

[0139] In some embodiments, when performing the fifth process, plasma formed by HBr in the third gas can also be used to perform a sixth process on the exposed surface of the second organic mask 16, causing the chemical bonds in the second organic mask material on the surface to break and recombine, forming polymer chains, and forming a modified layer on the surface of the second organic mask 16, so as to improve the etching resistance of the second organic mask 16 by changing the C / H ratio on the surface of the second organic mask material.

[0140] Furthermore, plasma formed by O2 in the third gas can be used to perform a seventh treatment on the exposed surface of the second organic mask 16, causing the exposed surface of the second organic mask 16 to undergo slight oxidation below -15°C and be triggered by deep ultraviolet light in the environment to form a second hardened layer. The modified layer and the second hardened layer can together form a third protective layer.

[0141] Furthermore, plasma formed by CF4 in the fourth gas can be used to perform an eighth treatment on the exposed surface of the second organic mask 16, forming a second carbon-containing protective film on the exposed surface of the second organic mask 16 as a fourth protective layer.

[0142] By performing the aforementioned multiple treatments on the second organic mask 16, the consumption rate of the second organic mask 16 can be reduced, and its etching barrier capability can be improved. Therefore, the surface quality and dimensional accuracy of the second organic mask 16 are effectively guaranteed. This not only significantly improves the selectivity of the second organic mask 16 but also enables the acquisition of more vertical sidewalls, thus positively impacting the achievement of higher aspect ratios and smaller dimensions in deep silicon etching.

[0143] In some embodiments, the second temperature is -80°C to -15°C. For example, the second temperature can be -80°C, -70°C, -60°C, -50°C, -40°C, -30°C, -20°C, or -15°C, or any value between any two of the aforementioned temperature values. However, it is not limited to these.

[0144] In some embodiments, the fifth process is performed for 2 to 4 seconds. Furthermore, the time for introducing HBr and O2 is the same as the time for introducing CF4 and Ar, each for 1 to 2 seconds. However, this is not a limitation.

[0145] In some other embodiments, the silicon cavity patterning process used to form the silicon cavity 14 can be performed with reference to the etching process used to form the high aspect ratio silicon through-hole structure 20. That is, the silicon cavity patterning process can also include multiple periodic cyclic steps formed sequentially by deposition and etching steps; the deposition step uses a first gas as the deposition gas, and the etching step uses a second gas as the etching gas; and the silicon cavity patterning process can also include a first etching stage, a second etching stage, and a third etching stage connected in sequence, used to form the sequentially connected top, middle, and bottom of the silicon cavity 14, respectively, and the first etching stage uses F2 and N2 as etching gases, the second etching stage uses F2 and PF3 as etching gases, and the third etching stage uses F2 and CF4 as etching gases.

[0146] Step S17: Remove the organic mask and substrate.

[0147] refer to Figure 8 In some embodiments, after forming the high aspect ratio silicon through-hole structure 20, the upper surface of the silicon substrate 10 is bombarded with a plasma of a fifth gas to remove the second organic mask 16. The plasma of the fifth gas is obtained by ionizing the fifth gas introduced into the process chamber.

[0148] In some embodiments, the fifth gas includes an oxidizing gas. The oxidizing gas may be, for example, oxygen, and nitrogen may be introduced simultaneously as a diluent gas.

[0149] Next, remove slide 13.

[0150] After removing the second organic mask 16 and the carrier 13, a silicon cavity 14 formed by the above-described single-sided process is obtained on the upper surface (back side) of the silicon substrate 10, and a high aspect ratio silicon through-hole structure 20 is formed on the bottom surface of the silicon cavity 14. The upper end of the high aspect ratio silicon through-hole structure 20 is exposed from the bottom surface of the silicon cavity 14, and the lower end of the high aspect ratio silicon through-hole structure 20 is exposed from the lower surface (front side) of the silicon substrate 10. Figure 8 As shown.

[0151] According to a second aspect of this application, embodiments of this application also provide a semiconductor structure obtained using a patterning method for high aspect ratio silicon through-hole structures as provided in any of the embodiments of the first aspect above.

[0152] refer to Figure 8In some embodiments, the semiconductor structure includes a silicon substrate 10, a silicon cavity 14 formed on the upper surface (back side) of the silicon substrate 10, and a high aspect ratio silicon through-hole structure 20 formed on the same side of the silicon cavity 14 and located on the bottom surface of the silicon cavity 14. The upper end of the high aspect ratio silicon through-hole structure 20 is exposed from the bottom surface of the silicon cavity 14, and the lower end of the high aspect ratio silicon through-hole structure 20 is exposed from the lower surface (front side) of the silicon substrate 10.

[0153] In some embodiments, the semiconductor structure (high aspect ratio silicon through-hole structure 20) can be applied to MEMS devices (such as MEMS microphones, etc.).

[0154] In a third aspect, embodiments of this application also provide a plasma processing apparatus for performing the patterning method for the high aspect ratio silicon through-hole structure corresponding to the above embodiments to form the high aspect ratio silicon through-hole structure 20 (semiconductor structure) corresponding to the above embodiments. The plasma processing apparatus includes inductively coupled plasma (ICP) etching equipment or capacitively coupled plasma (CCP) etching equipment, etc.

[0155] In other aspects, embodiments of this application also provide an electronic device, including a high aspect ratio silicon through-hole structure 20 (semiconductor structure) obtained using the patterning method for high aspect ratio silicon through-hole structures described in the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, electronic instrument, television, artificial intelligence device, etc.

[0156] In summary, this application embodiment uses small molecule gases (first gas and second gas) instead of traditional large molecule gases such as C4F8 and SF6 as deposition and etching gases. By keeping the etching temperature (first temperature) below -15°C, it can improve the reliability and uniformity of sidewall protection at smaller dimensions, significantly improve the etching resistance of organic masks, and obtain extremely vertical sidewall morphologies. This enables the realization of high aspect ratio silicon through-hole structures 20 with higher aspect ratios (e.g., greater than 100:1) and nanoscale dimensions (e.g., less than 50 nm). Simultaneously, the small molecule etching gas can significantly improve the etching rate and etching behavior at high depths (>100 µm). Therefore, in this embodiment of the application, after forming the silicon cavity 14, only the etching process of this application is required to form a high aspect ratio silicon through-hole structure 20 that penetrates the silicon substrate 10 on the same side of the silicon cavity 14. This allows the etching of the silicon cavity 14 and the high aspect ratio silicon through-hole structure 20 to be achieved on the same side of the silicon substrate 10, reducing the two-sided processing steps of the crystal plane, reducing the number of processes, simplifying the process, and improving the yield and productivity of micro-nano fabrication.

[0157] The above are merely preferred embodiments of this application. These embodiments are not intended to limit the scope of protection of this application. Therefore, any equivalent changes made based on the description and drawings of this application should also be included within the scope of protection of this application.

Claims

1. A method for patterning high aspect ratio silicon through-hole structures, characterized in that, include: Provide silicon substrates; A silicon cavity is formed on the first surface of the silicon substrate; Multiple organic masks are formed on the bottom surface of the silicon cavity; An etching process is performed at a first temperature of less than -15°C, through the organic mask, to etch the silicon substrate exposed on the bottom surface, forming a high aspect ratio silicon through-hole structure that penetrates the silicon substrate on the silicon substrate below the bottom surface. The etching process includes multiple periodic cyclic steps formed sequentially by deposition and etching steps; The deposition step uses a first gas as the deposition gas to form a polymer layer on the sidewalls of the high aspect ratio silicon through-hole structure and the exposed surface of the organic mask during the formation of the structure, so as to protect the sidewalls and the organic mask during etching. The etching step uses a second gas as the etching gas to etch the polymer layer and the silicon substrate; the first gas includes SF6 and O2, and the second gas includes F2, as well as N2, PF3 and CF4; The etching process includes a first etching stage, a second etching stage, and a third etching stage connected in sequence, which are used to form the top, middle, and bottom of the high aspect ratio silicon through-hole structure, respectively. The first etching stage uses F2 and N2 as etching gases, the second etching stage uses F2 and PF3 as etching gases, and the third etching stage uses F2 and CF4 as etching gases.

2. The patterning method for high aspect ratio silicon through-hole structures according to claim 1, characterized in that, The polymer layer includes a SiCOF compound layer. During the deposition step, the active groups of F, O, and S generated by reacting O2 in the first gas with SF6 and silicon substrate material respectively react with CO groups sputtered from organic mask material, and co-deposit occurs below -15°C to form the SiCOF compound layer.

3. The patterning method for high aspect ratio silicon through-hole structures according to claim 2, characterized in that, During the deposition step, plasma formed by O2 in the first gas is also used to perform a first treatment on the exposed surface of the organic mask, causing the exposed surface of the organic mask to oxidize below -15°C and be triggered by deep ultraviolet light in the environment to form a first hardened layer. The first hardened layer and the SiCOF compound layer deposited on the exposed surface of the organic mask together form a first protective layer.

4. The patterning method for high aspect ratio silicon through-hole structures according to claim 1, characterized in that, During the first etching stage, plasma formed from N2 in the introduced second gas is used to perform a second treatment on the sidewall, forming a nitride layer on the sidewall to assist in passivation of the sidewall surface; and / or, during the second etching stage, plasma formed from PF3 in the introduced second gas is used to perform a third treatment on the polymer layer to change the properties of the polymer layer and enhance its resistance to lateral etching; and / or, during the third etching stage, plasma formed from CF4 in the introduced second gas is used to provide a higher carbon-to-fluorine ratio to suppress lateral etching of the bottom of the sidewall, and a fourth treatment is performed on the exposed surface of the organic mask to form a first carbon-containing protective film as a second protective layer.

5. The patterning method for high aspect ratio silicon through-hole structures according to claim 1, characterized in that, The flow rate ratio of SF6 to O2 in the first gas is SF6:O2 = 1:3 to 1:10; and / or, during the first etching stage, the flow rate ratio of F2 to N2 in the second gas is F2:N2 = 5:1 to 10:1; and / or, during the second etching stage, the flow rate ratio of F2 to PF3 in the second gas is F2:PF3 = 8:1 to 20:1; and / or, during the third etching stage, the flow rate ratio of F2 to CF4 in the second gas is F2:CF4 = 5:1 to 10:

1.

6. The patterning method for high aspect ratio silicon through-hole structures according to claim 1, characterized in that, Also includes: After each of the deposition and etching steps performed consecutively once or twice, a fifth treatment is performed on the sidewall at a second temperature less than -15°C. This treatment includes using HBr and O2 as third gases to remove a portion of the thickness of the polymer layer deposited on the sidewall and reacting it with the silicon substrate material on the exposed surface of the protrusions on the sidewall to generate a reaction product layer. Then, using CF4 and Ar as fourth gases, the reaction product layer is removed to remove at least a portion of the protrusions.

7. The patterning method for high aspect ratio silicon through-hole structures according to claim 6, characterized in that, During the fifth process, plasma formed by HBr in the third gas is used to perform a sixth process on the exposed surface of the organic mask, forming a modified layer on the surface of the organic mask. Additionally, plasma formed by O2 in the third gas is used to perform a seventh process on the exposed surface of the organic mask, causing oxidation at -15°C and triggering a reaction by deep ultraviolet light in the environment to form a second hardened layer. The modified layer and the second hardened layer together form a third protective layer. Furthermore, plasma formed by CF4 in the fourth gas is used to perform an eighth process on the exposed surface of the organic mask, forming a second carbon-containing protective film on the exposed surface of the organic mask as a fourth protective layer.

8. The patterning method for high aspect ratio silicon through-hole structures according to claim 1, characterized in that, Before forming the silicon cavity, the method further includes: bonding a wafer to a second surface of the silicon substrate opposite to the first surface; after forming the high aspect ratio silicon through-hole structure, the method further includes: removing the wafer.

9. The patterning method for high aspect ratio silicon through-hole structures according to claim 8, characterized in that, During the third etching stage, the wafer is used as an etching stop layer so that the bottom of the high aspect ratio silicon through-hole structure stops on the bonding surface of the wafer.

10. A semiconductor structure, characterized in that, It is obtained using the patterning method for high aspect ratio silicon through-hole structures as described in any one of claims 1-9.

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