High aspect ratio deep silicon etch structure and patterning method thereof

Abstract

The application discloses a high aspect ratio deep silicon etching structure and a patterning method thereof. The method comprises the following steps: providing a substrate with silicon as a material; forming a plurality of photoresist patterns on the surface of the substrate, and the adjacent two photoresist patterns have an opening; using a first gas plasma to bombard the interface of the substrate at the inner bottom corner of the opening at a first ultra-low temperature to form a first protective film; using a second gas plasma to deposit a polymer layer on the substrate, the photoresist pattern and the first protective film at a second ultra-low temperature to protect; using a third gas plasma to etch the polymer layer and the substrate at a third ultra-low temperature; repeating the steps of depositing the polymer layer and etching until the high aspect ratio deep silicon etching structure is formed on the substrate; and removing the photoresist pattern. The application can realize uniform protection of the sidewall at a smaller size and a higher aspect ratio, and can improve the etching rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor processing, in particular to a high aspect ratio deep silicon etching structure patterning method and a high aspect ratio deep silicon etching structure obtained by using the method. BACKGROUND

[0002] In the rapidly developing field of advanced packaging, higher density interconnection is required, which drives deep silicon etching (DSE) to be able to meet the requirements of nanoscale line width (less than 50 nm) and higher aspect ratio (greater than 100:1). Due to the influence of corresponding physical limitations (such as ion shadow effect, reaction gas transmission efficiency), the traditional periodic cyclic etching process has been difficult to meet the above limit aspect ratio requirements. At the same time, nanoscale line width is more sensitive to the thickness fluctuation of the sidewall passivation layer (such as C-F polymer), when the thickness fluctuation of the sidewall passivation layer is large, it is easy to cause line width deviation and etching tilt (three-dimensional through silicon via and memory stack require etching verticality error less than ±0.2°) problems. In addition, the existing etching process also has the problems of plasma chemical residue and local rough peaks (Ra>5nm) caused by random deposition of C-F polymer on the sidewall, which have important influence on the realization of higher aspect ratio and nanoscale deep silicon etching. And under the requirements of higher aspect ratio and nanoscale line width, how to improve the etching rate and how to improve the uniformity of the protection of the bottom sidewall during the etching process is particularly important. Therefore, it is necessary to study a process method which can significantly improve the above problems. SUMMARY

[0003] The present application aims to overcome the above problems existing in the prior art, and provides a high aspect ratio deep silicon etching structure and a patterning method thereof.

[0004] To achieve the above-mentioned purpose, the technical solutions of the present application are as follows:

[0005] According to the first aspect of the present application, the embodiment of the present application provides a high aspect ratio deep silicon etching structure patterning method, comprising:

[0006] providing a substrate made of silicon;

[0007] forming a plurality of photoresist patterns on the surface of the substrate, and the adjacent two photoresist patterns have an opening therebetween;

[0008] performing a first processing step, using a first gas plasma to bombard the interface of the substrate at the inner bottom corner of the opening at a first ultra-low temperature, to form a first protective film;

[0009] performing a second processing step, depositing a polymer layer on the substrate, the photoresist pattern and the first protective film using a plasma of a second gas at a second ultra-low temperature to protect the substrate and the photoresist pattern during etching;

[0010] performing a third processing step, etching the polymer layer and the substrate using a plasma of a third gas at a third ultra-low temperature;

[0011] sequentially repeating the second processing step and the third processing step until a high-aspect-ratio deep silicon etching structure is formed on the substrate;

[0012] wherein the first ultra-low temperature, the second ultra-low temperature and the third ultra-low temperature are less than -20℃, the first gas comprises Ar, the first protective film comprises a carbon-containing protective film, the second gas comprises SF6 and O2, the polymer layer comprises a SiCOF compound layer, and the third gas comprises F2 and CF4.

[0013] In some embodiments, when performing the second processing step, F, O and S active groups generated by reacting the O2 with the SF6 and substrate material respectively react with C atoms sputtered from the photoresist material to form the SiCOF compound layer by co-deposition at the second ultra-low temperature.

[0014] In some embodiments, when performing the second processing step, a fourth processing is performed on the exposed surface of the photoresist pattern using a plasma formed by the O2 in the second gas to oxidize the exposed surface of the photoresist pattern at the second ultra-low temperature and trigger a reaction by ambient deep ultraviolet light to form a hardened layer.

[0015] In some embodiments, when performing the second processing step, the O2 in the second gas is first introduced to bombard the exposed surface of the photoresist pattern using the oxygen plasma formed thereby to form the hardened layer and sputter C atoms from the photoresist material, and then the SF6 in the second gas is continuously introduced to form the SiCOF compound layer.

[0016] In some embodiments, the flow rate of the SF6 is 10sccm-30sccm.

[0017] In some embodiments, the flow rate of the O2 is 30sccm-100sccm.

[0018] In some embodiments, the flow rate ratio of the SF6 to the O2 is SF6:O2=1:3-1:10.

[0019] In some embodiments, when performing the third processing step, the exposed surface of the photoresist pattern is further processed by a fifth processing using a plasma formed by the CF4 in the third gas, and a second protective film is formed on the exposed surface of the photoresist pattern, wherein the second protective film comprises a carbon-containing protective film.

[0020] In some embodiments, the flow rate of the F2 is 100-400 sccm.

[0021] In some embodiments, the flow rate of the CF4 is 10-80 sccm.

[0022] In some embodiments, the flow rate ratio of the F2 and the CF4 is F2:CF4=5:1-10:1.

[0023] In some embodiments, the third gas further comprises N2, and when performing the third processing step, a sixth processing is performed on the sidewall of the high aspect ratio deep silicon etching structure under formation by using a plasma formed by the N2 introduced.

[0024] In some embodiments, the first ultra-low temperature is -85℃ to -20℃.

[0025] In some embodiments, the second ultra-low temperature is -85℃ to -20℃.

[0026] In some embodiments, the third ultra-low temperature is -85℃ to -20℃.

[0027] According to a second aspect of the present application, the embodiments of the present application further provide a high aspect ratio deep silicon etching structure obtained by using the patterning method of the high aspect ratio deep silicon etching structure according to any one of the embodiments of the first aspect.

[0028] The embodiments of the present application can have / at least have the following advantages:

[0029] (1) By using small molecule second gas (SF6 and O2) and third gas (F2 and CF4) to replace traditional large molecule gas C4F8 and SF6 as deposition gas and etching gas respectively, the diffusion coefficient can be increased, the gas transmission efficiency can be improved, the etching gas can be more uniformly diffused and more easily enter the nanoscale high aspect ratio deep silicon etching structure (deep trench, deep hole or via) to carry out etching reaction, more excellent small size high aspect ratio deep silicon etching can be realized, and the deposition gas can smoothly enter the bottom of the high aspect ratio deep silicon etching structure to realize more uniform protection of the sidewall at a smaller size. Moreover, by making the temperature (second ultra-low temperature, third ultra-low temperature) when the second processing step and the third processing step are performed less than -20°C, the ultra-low temperature can be utilized to change the chemical kinetics, enhance the physical adsorption, and reduce the reaction rate, so that the formed polymer layer (SiCOF compound layer) can be more dense and more uniformly adsorbed on the sidewall, effective protection of the sidewall can be formed even at the bottom of the high aspect ratio deep silicon etching structure, lateral etching can be effectively inhibited, and extremely vertical sidewall morphology can be obtained. Therefore, the application can solve the problem of the influence of the thickness fluctuation of the polymer formed by using large molecule C4F8 deposition on the control of nanoscale line width, and the ion shadow effect problem (nanoscale involves atomic size level), effectively improve the uniformity and roughness of the local C-F polymer, realize more excellent uniformity (uniform size of upper, middle and lower positions of the high aspect ratio deep silicon etching structure), better sidewall smoothness, and further realize higher aspect ratio nanoscale size deep silicon structure etching. At the same time, the small molecule etching gas can significantly improve the etching rate and etching behavior at high depth (>100µm).

[0030] (2) By using the combination of SF6 and O2 as a deposition gas, O2 reacts with SF6 and silicon (Si) of the substrate material respectively, the active groups of F, O and S produced react with C atoms sputtered from the photoresist material, and co-deposition occurs on the sidewall surface at ultra-low temperature to form a SiCOF compound layer with higher etching resistance, which improves the protection ability of the sidewall. At ultra-low temperature, the SiCOF compound layer will be more dense, more uniform and have better coverage, so effective protection can be formed even at the bottom of the high aspect ratio deep silicon etching structure, thereby effectively inhibiting lateral etching and obtaining extremely vertical sidewall morphology.

[0031] (3) By using the combination of F2 and CF4 as etching gas, the high reactivity of F2 can be utilized to provide abundant primary etchant, reduce the dependence on physical bombardment, and improve the etching rate; the light ions generated by CF4 can efficiently transfer energy to the bottom, which is beneficial to the etching of the bottom. Among them, the small molecule reactants and products have a longer average free path, which can directly reach the bottom of the high aspect ratio deep silicon etching structure, ensuring the etching rate of the bottom and avoiding "etching stop"; the generated ions have lighter mass and more concentrated energy distribution, achieving extreme anisotropic etching, and reducing damage to the photoresist pattern to obtain a more vertical sidewall.

[0032] (4) By using the plasma of Ar, the interface of the substrate is bombarded to form a carbon-containing protective film (first protective film) at the junction of the bottom of the photoresist pattern and the surface of the substrate (i.e. at the inner bottom corner of the opening), which can effectively protect the topography of the etching top during subsequent etching of the substrate, prevent abnormal excessive lateral etching behavior from occurring at the top, and ensure the size uniformity at different depths of the upper, middle and lower positions during subsequent high aspect ratio etching, that is, the perpendicularity of the sidewall is ensured. By using the plasma of O2 in the second gas, the exposed surface of the photoresist pattern is subjected to a fourth treatment, so that the exposed surface of the photoresist pattern is slightly oxidized at ultra-low temperature and is triggered to react by the deep ultraviolet light existing in the environment, forming a thin and durable "crust" (hardened layer) on the surface of the photoresist pattern, and at the same time, a SiCOF compound layer is deposited on the surface of the photoresist pattern, thereby forming a composite protective layer, greatly slowing down the erosion rate of F radicals on the photoresist pattern, greatly reducing the consumption rate of the photoresist pattern, and significantly improving the selectivity ratio. This means that thinner photoresist patterns can be used to etch deeper high aspect ratio deep silicon etching structures. By using the plasma of CF4 in the third gas, the exposed surface of the photoresist pattern is subjected to a fifth treatment to form a carbon-containing protective film (second protective film) on the exposed surface of the photoresist pattern, which can also reduce the consumption rate of the photoresist pattern, thereby improving the selectivity ratio. By treating the photoresist pattern in multiple ways, the surface quality and size accuracy of the photoresist pattern are effectively ensured, which not only significantly improves the selectivity ratio of the photoresist pattern, but also obtains a more vertical sidewall, thereby having a positive significance for realizing higher aspect ratio and nanoscale size deep silicon etching.

[0033] (5) By further adding N2 in the third gas, the plasma formed by N2 can be used to treat the sidewall of the high aspect ratio deep silicon etching structure being formed (sixth treatment), forming an extremely thin nitrided layer on the sidewall to achieve the effect of auxiliary passivation of the surface of the sidewall, thereby further improving the fidelity of the pattern.

[0034] Other advantages of the present application will be described in the specific embodiments described below. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating a graphical method for creating a high aspect ratio deep silicon etched structure, according to a preferred embodiment of this application.

[0036] Figure 2 This is a schematic diagram of the structure after a photoresist pattern has been formed on a substrate, according to a preferred embodiment of this application.

[0037] Figure 3 This is a schematic diagram of a structure after a polymer layer has been deposited on a substrate and a photoresist pattern, according to a preferred embodiment of this application.

[0038] Figure 4 This is a schematic diagram of the structure after a first etched structure is formed on a substrate, according to a preferred embodiment of this application.

[0039] Figure 5 This is a schematic diagram of a structure after a polymer layer is re-deposited on a substrate and a photoresist pattern, according to a preferred embodiment of this application.

[0040] Figure 6 This is a schematic diagram of a structure after a second etched structure is formed on a substrate, according to a preferred embodiment of this application.

[0041] Figure 7 This is a schematic diagram of a high aspect ratio deep silicon etched structure formed on a substrate, provided as a preferred embodiment of this application.

[0042] Figure 8 This is a schematic diagram of the structure after removing the photoresist pattern, provided as a preferred embodiment of this application.

[0043] In the figure: 10. Substrate; 11. Opening; 12. Photoresist pattern; 13. First protective film; 14. Polymer layer; 15. First etched structure; 16. Second etched structure; 17. High aspect ratio deep silicon etched structure. Detailed Implementation

[0044] To address the shortcomings of existing technologies, embodiments of this application provide a patterning method for high aspect ratio deep silicon etched structures, including:

[0045] Provide a substrate made of silicon;

[0046] Multiple photoresist patterns are formed on the surface of the substrate, with an opening between two adjacent photoresist patterns;

[0047] The first processing step is performed by bombarding the interface of the substrate located at the inner bottom corner of the opening with plasma of a first gas at a first ultra-low temperature to form a first protective film.

[0048] performing a second processing step, depositing a polymer layer on the substrate, the photoresist pattern and the first protective film using a plasma of a second gas at a second ultra-low temperature to protect the substrate and the photoresist pattern during etching;

[0049] performing a third processing step, etching the polymer layer and the substrate using a plasma of a third gas at a third ultra-low temperature;

[0050] sequentially repeating the second processing step and the third processing step until a high-aspect-ratio deep silicon etching structure is formed on the substrate;

[0051] wherein the first ultra-low temperature, the second ultra-low temperature and the third ultra-low temperature are less than -20℃, the first gas comprises Ar, the first protective film comprises a carbon-containing protective film, the second gas comprises SF6 and O2, the polymer layer comprises a SiCOF compound layer, and the third gas comprises F2 and CF4.

[0052] The embodiments of the present application use small-molecule second gas (SF6 and O2) and third gas (F2 and CF4) to replace the traditional large-molecule gas C4F8 and SF6 as deposition gas and etching gas respectively, which can increase the diffusion coefficient, improve the gas transmission efficiency, make the etching gas diffuse more uniformly and more easily enter the nanoscale high-aspect-ratio deep silicon etching structure (deep trench, deep hole or via) for etching reaction, achieve more excellent small-size high-aspect-ratio deep silicon etching, and make the deposition gas enter the bottom of the high-aspect-ratio deep silicon etching structure smoothly to achieve more uniform protection of the sidewall at a smaller size. Moreover, by making the temperature (second ultra-low temperature, third ultra-low temperature) during the execution of the second processing step and the third processing step less than -20℃, the ultra-low temperature can be used to change the chemical kinetics, enhance the physical adsorption and reduce the reaction rate, so that the formed polymer layer (SiCOF compound layer) can be more dense and more uniformly adsorbed on the sidewall, effectively protect the sidewall at the bottom of the high-aspect-ratio deep silicon etching structure, effectively inhibit lateral etching, obtain an extremely vertical sidewall morphology, and further achieve high-aspect-ratio nanoscale deep silicon structure etching. At the same time, the small-molecule etching gas can significantly improve the etching rate and etching behavior at high depth (>100µm).

[0053] The embodiments of the present application also provide a high-aspect-ratio deep silicon etching structure obtained by a patterning method using the above high-aspect-ratio deep silicon etching structure.

[0054] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0055] Reference Figure 1According to a first aspect of the present application, the embodiments of the present application provide a patterning method of high aspect ratio deep silicon etching structure, which comprises the following steps in sequence:

[0056] Step S11: providing a substrate with silicon as the material.

[0057] Reference Figure 2 In some embodiments, a substrate 10 with silicon as the material (i.e. a silicon substrate) is used to form a required high aspect ratio deep silicon etching structure on the substrate 10 by the patterning method of high aspect ratio deep silicon etching structure provided by the embodiments of the present application.

[0058] In some embodiments, the high aspect ratio deep silicon etching structure comprises a deep trench, a DeepVia or a Through Via, etc.

[0059] In some embodiments, a silicon wafer can be used as the substrate 10.

[0060] In some embodiments, the silicon wafer can be subjected to a doping process to provide the substrate 10 with required electrical properties.

[0061] In some embodiments, integrated circuits such as transistor structures can be fabricated on the substrate 10 to realize required vertical interconnection by filling conductive materials after the formation of the high aspect ratio deep silicon etching structure.

[0062] Step S12: forming a plurality of photoresist patterns on the surface of the substrate, with an opening between any two adjacent photoresist patterns.

[0063] Reference Figure 2 In some embodiments, a spin coating process can be used to form a photoresist layer on the upper surface of the substrate 10, and the photoresist layer is subjected to photolithographic patterning to form a plurality of photoresist patterns 12 on the upper surface of the substrate 10. Any two adjacent photoresist patterns 12 have an opening 11 as an etching window, and the surface of the substrate 10 between the two adjacent photoresist patterns 12 is exposed on the bottom of the opening 11.

[0064] It should be noted that, Figure 2 In the above embodiments, only the case where two photoresist patterns 12 are formed on the upper surface of the substrate 10 is shown. However, it should be understood that more photoresist patterns can be formed on the upper surface of the substrate 10, such as three photoresist patterns, four photoresist patterns, ten photoresist patterns, etc., and the number of photoresist patterns is not limited to the above.

[0065] Step S13: using a plasma of a first gas to bombard the interface of the substrate at the inner bottom corner of the opening at a first ultra-low temperature to form a first protective film.

[0066] ReferenceFigure 2 In some embodiments, before etching the substrate 10, a first processing step is performed, and a first protective film 13 is formed at the interface between the photoresist pattern 12 and the substrate 10. The first processing step is performed at a first ultra-low temperature below -20°C, using a plasma of a first gas (a plasma of argon (Ar)), to bombard the interface (upper surface) of the substrate 10 at the inner bottom corner of the opening, thereby forming the first protective film 13 at the interface between the bottom of the photoresist pattern 12 and the upper surface of the substrate 10 (i.e., at the inner bottom corner of the opening 11), to effectively protect the top of the etching during subsequent etching of the substrate 10, prevent abnormal over-etching behavior at the top, and thus ensure uniformity of the size at different depths (i.e., the verticality of the sidewall) during subsequent high aspect ratio etching. The first protective film 13 is a carbon-containing protective film (a protective film of a carbon-based material containing C, N, and O).

[0067] In some embodiments, during the first processing step, the first ultra-low temperature is -85°C to -20°C, the pressure is 50 mTorr to 800 mTorr, the source power is 50 W to 100 W, the bias power is 10 W to 50 W, and the time is 5 s to 20 s. However, the present application is not limited thereto.

[0068] Step S14: depositing a polymer layer on the substrate, the photoresist pattern, and the first protective film using a plasma of a second gas at a second ultra-low temperature, to protect the substrate and the photoresist pattern during etching.

[0069] In some embodiments, a high aspect ratio deep silicon etching structure is formed on the substrate by performing an etching process. The etching process includes a deposition step (second processing step) and an etching step (third processing step) in sequence. The deposition step and the etching step can be repeatedly performed in sequence multiple times until the high aspect ratio deep silicon etching structure is formed on the substrate.

[0070] Reference Figure 3 In some embodiments, during the second processing step (deposition step), a second gas including SF6 and O2 is used as a deposition gas to deposit a SiCOF compound layer (second processing) as the polymer layer 14 on the exposed surface of the substrate 10 (the sidewall of the high aspect ratio deep silicon etching structure being formed), the exposed surface of the photoresist pattern 12 (the side surface and the top surface), and the first protective film 13, to protect the substrate 10 (the sidewall of the high aspect ratio deep silicon etching structure being formed) and the photoresist pattern 12 during etching.

[0071] The SF6 and O2 in the second gas, which is a small molecule gas with a molecular weight less than the molecular weight of C4F8, is used to deposit a uniform polymer layer 14 on the exposed surface of the substrate 10 and the exposed surface of the photoresist pattern 12 at an ultra-low temperature less than -20°C. By ionizing the second gas flowing into the process chamber, a plasma of the second gas is obtained for depositing a SiCOF compound layer as the polymer layer 14.

[0072] The deposition gas C4F8 used in the prior art is a large molecule gas. In the implementation of a smaller CD (nanometer level line width) and a higher aspect ratio (>100:1), the deposition of the large molecule gas C4F8 on the sidewall is mainly in the upper half of the deep trench and the deep hole, and it is difficult to enter the bottom of the deep silicon structure. Therefore, the large molecule gas C4F8 cannot sufficiently protect the bottom sidewall for the high aspect ratio deep silicon etching structure.

[0073] In the embodiment of the present application, the small molecule SF6 and O2 are used to replace the large molecule C4F8 as the deposition gas, and the second ultra-low temperature is less than -20°C. In the high aspect ratio deep silicon etching, the kinetics of etching chemistry can be greatly changed. The low temperature makes the by-products generated in the reaction and the added gas more easily physically adsorbed on the silicon material surface of the substrate 10, rather than immediately desorbed or sputtered off, thereby enhancing the physical adsorption capacity. Moreover, the ultra-low temperature reduces the reaction rate, and all surface chemical reaction rates are significantly slowed down at the ultra-low temperature.

[0074] In the second processing step, the combination of SF6 and O2 is used as the deposition gas, which can easily reach the bottom of the high aspect ratio deep silicon etching structure. By reacting O2 with SF6 and the silicon of the substrate material, O2 reacts with SF6 to generate SO2F2, SOF4, and other sulfur-oxygen-fluoride compounds, and fluorine radicals; at the same time, O2 also reacts with the silicon of the substrate 10 material to generate SiO2 (SiO x F y ). Most importantly, the active groups of F, O, and S react with the C atoms (or C-O groups) sputtered from the photoresist material of the photoresist pattern, and co-deposition occurs on the sidewall surface at the ultra-low temperature, thereby forming a SiCOF compound layer. This SiCOF compound is a more complex and more etch-resistant Si-C-O-F compound, which is commonly referred to as SiFO polymer or SiCOF glaze. The SiFO polymer formed at the ultra-low temperature has excellent performance compared to the CF x polymer at room temperature:

[0075] (1) Excellent sidewall protection capability.

[0076] (2) Higher etch resistance: The SiFO polymer contains Si-O bonds (very strong and stable), which makes it more etch-resistant than pure CFx Polymers are more resistant to chemical attack by F radicals and physical bombardment by ions.

[0077] (3) Better coverage and stability: The physical adsorption at low temperature makes the protective film denser and more uniform, and better covers the sidewall, even at the bottom of high aspect ratio deep silicon etching structure, to form effective protection. This can effectively inhibit lateral etching and obtain extremely vertical sidewall morphology.

[0078] In some embodiments, when performing the second processing step, O2 in the deposition gas is also used to perform a fourth processing on the exposed surface of the photoresist pattern 12, so that the exposed surface of the photoresist pattern 12 is oxidized at a second ultra-low temperature and is triggered to react by the deep ultraviolet light existing in the environment to form a hardened layer.

[0079] When performing the deposition step, the O2 added in the deposition gas slightly oxidizes and hardens the surface of the photoresist pattern 12 (photoresist) to form a thin and durable "crust", that is, a hardened layer on the surface of the photoresist pattern 12. At the same time, during the deposition step, SiFO polymer (SiCOF compound) is also deposited on the surface of the photoresist pattern 12, so that the SiFO polymer (polymer layer 14) forms a composite protective layer together with the hardened layer. This composite protective layer greatly slows down the etching rate of F radicals on the photoresist pattern 12, and thus can significantly improve the selectivity of the photoresist pattern 12. This means that thinner photoresist can be used to etch deeper silicon structures.

[0080] In some embodiments, when performing the second processing step, O2 in the second gas (without SF6) is introduced into the process chamber, and the formed oxygen plasma is used to bombard the exposed surface of the photoresist pattern 12 to form a hardened layer and sputter C atoms from the photoresist material. Then, under the condition of continuously introducing O2, SF6 in the second gas is introduced to form the SiCOF compound layer as described above.

[0081] In some embodiments, the flow rate of SF6 in the deposition gas is 10sccm-30sccm. For example, the flow rate of SF6 can be 10sccm, 12sccm, 15sccm, 20sccm, 25sccm or 30sccm, or any value between any two of the foregoing flow rates. However, it can not be limited to this.

[0082] In some embodiments, the flow rate of O2 in the deposition gas is 30sccm-100sccm. For example, the flow rate of O2 can be 30sccm, 35sccm, 40sccm, 50sccm, 75sccm or 100sccm, or any value between any two of the foregoing flow rates. However, it can not be limited to this.

[0083] In some embodiments, the flow ratio of SF6and O2in the deposition gas is SF6:O2= 1:3-1:10. For example, the flow ratio of SF6and O2may be 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10, and the flow ratio of O2may vary continuously between 3-10. However, the application is not limited thereto.

[0084] In some embodiments, the second ultra-low temperature is -85°C to -20°C. For example, the second ultra-low temperature can be -85°C, -80°C, -70°C, -60°C, -50°C, -40°C, -30°C, or -20°C, or any value between any two of the foregoing. However, the application is not limited thereto.

[0085] In some embodiments, the time for performing the second processing step is 0.1s-2s. For example, the time for performing the second processing step can be 0.1s, 0.2s, 0.3s, 0.4s, 0.5s, 0.7s, 0.9s, 1s, 1.2s, 1.5s, 1.8s, or 2s, or any value between any two of the foregoing. However, the application is not limited thereto.

[0086] In some embodiments, the time for introducing SF6when performing the second processing step is one-half to two-thirds of the total time for performing the second processing step. However, the application is not limited thereto.

[0087] In some embodiments, the pressure when performing the second processing step is 5mTorr-200mTorr. For example, the pressure can be 5mTorr, 10mTorr, 20mTorr, 50mTorr, 80mTorr, 100mTorr, 130mTorr, 150mTorr, 190mTorr, or 200mTorr, or any value between any two of the foregoing. However, the application is not limited thereto.

[0088] In some embodiments, the source power when performing the second processing step is 500W-3000W. For example, the source power can be 500W, 1000W, 1500W, 2000W, 2500W, or 3000W, or any value between any two of the foregoing. However, the application is not limited thereto.

[0089] In some embodiments, the bias power when performing the second processing step is 10W-200W. For example, the bias power can be 10W, 20W, 50W, 70W, 100W, 130W, 160W, 180W, or 200W, or any value between any two of the foregoing. However, the application is not limited thereto.

[0090] Step S15: Etching the polymer layer and the substrate using a plasma of a third gas at a third ultra-low temperature.

[0091] Reference Figure 4 This step is used to continue the third processing step at an ultra-low temperature (third ultra-low temperature) less than -20°C after the second processing step is performed, and to form a first etching structure 15 on the substrate 10 by etching (third processing) the polymer layer 14 (SiCOF compound layer) and the substrate 10 formed in the previous step using F2 and CF4 (third gas) as etching gas (without SF6) (after the etching step, there is still a remaining polymer layer 14 on the side of the photoresist pattern 12, Figure 4 The third gas is ionized to form a plasma of the third gas for etching the polymer layer 14 and the substrate 10. Further, the etching step includes a first etching step and a second etching step, the polymer layer 14 on the bottom of the opening 11 is removed by performing the first etching step and by the bombardment of the plasma of the third gas, and then the exposed substrate 10 is etched downward by performing the second etching step to form the first etching structure 15.

[0092] When etching the substrate 10, the presence of the first protective film 13 prevents the top from being excessively laterally etched when forming the first etching structure 15, so that the size of the first etching structure 15 is relatively uniform, thereby laying a foundation for ensuring the uniform size of the entire high aspect ratio deep silicon etching structure at different positions on the top, middle and bottom.

[0093] When a mixture of fluorine gas (F2) and CF4 with smaller molecules is used as etching gas instead of the traditional SF6 large molecule gas, the diffusion is more uniform, which is more conducive to entering the nanoscale deep trench or hole for etching reaction, so that a more excellent small-size high aspect ratio deep silicon etching can be achieved. In addition, although SF6 has 6 F, only one F ion can be dissociated for etching reaction, and the remaining SF5 does not participate in the reaction and is then removed. However, F2 dissociation can produce two F ions, more reactants are involved than SF6, which can improve the etching rate, especially for etching deep silicon structures with high depth (more than 100µm), which can significantly improve the throughput of the machine.

[0094] Therefore, by using the small molecule etching gas and deposition gas, the diffusion coefficient is effectively increased, the reaction gas transmission efficiency is improved, the influence of the thickness fluctuation of the previous macromolecular C4F8 polymer on the control of the nanoscale line width and the ion shadow effect problem are solved, the uniformity and roughness of the local C-F polymer are effectively improved, and thus the nanoscale size deep silicon structure etching with better uniformity, better sidewall smoothness and higher aspect ratio is realized. Meanwhile, the mixed gas of F2 and CF4 is used as the etching gas, and the etching rate and the etching behavior at high depth (greater than 100 µm) can be significantly improved.

[0095] By switching the etching gas from the traditional SF6 to the combination of the mixed gas of F2 and CF4, the demand of the advanced process can be better met, the performance is significantly improved in molecular transport, reaction efficiency and morphology control through optimizing the reaction chemistry and plasma physics, and it is a key technical path to realize the ultra-high aspect ratio etching.

[0096] The difference of using the combination of the mixed gas of F2 and CF4 as the etching gas compared with using the traditional SF6 as the etching gas can include:

[0097] (1) High-density F atoms can be efficiently generated: through a more efficient dissociation path, abundant main etching agent (F atoms) is provided.

[0098] (2) Excellent deep hole transport capability: small molecule reactants and products have a longer mean free path, which can reach the bottom of the deep hole, ensuring the bottom etching rate.

[0099] (3) Precise ion energy and angle control: the generated ions are lighter and have a more concentrated energy distribution, realizing extreme anisotropic etching and reducing damage to the photoresist pattern 12.

[0100] (4) Bowing and other defects can be inhibited, and a more vertical sidewall can be obtained.

[0101] Wherein, when the combination of F2 and CF4 is used as the etching gas, the main reaction groups are: F•, CF3 + F2 has high reactivity and can provide abundant main etching agents, which not only reduces the dependence on physical bombardment, but also improves the etching rate. CF3 + is a light ion, which can efficiently transfer energy to the bottom and enhance the etching reaction. At the same time, due to its light mass, the physical sputtering yield of the material is low, which reduces the physical damage to the bottom silicon and the back sputtering of the top photoresist. In addition, CF4 can provide a carbon source, introduce a small amount of C during the etching step, balance the deposition and etching, and cooperate with the deposition step to realize more precise sidewall morphology control.

[0102] In some embodiments, when performing the third processing step, the exposed surface of the photoresist pattern 12 is further processed by a fifth processing using a plasma formed by CF4in the third gas, and a second protective film (not shown) is formed on the exposed surface of the photoresist pattern 12, further promoting the degree of protection of the photoresist pattern 12. The second protective film includes a carbon-containing protective film.

[0103] In some embodiments, the flow rate of F2in the etching gas (the third gas) is 100 sccm to 400 sccm. For example, the flow rate of F2may be 100 sccm, 120 sccm, 150 sccm, 200 sccm, 300 sccm, 350 sccm, or 400 sccm, or any value between any two of the foregoing. However, the disclosure is not limited thereto.

[0104] In some embodiments, the flow rate of CF4in the etching gas is 10 sccm to 80 sccm. For example, the flow rate of CF4may be 10 sccm, 15 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, or 80 sccm, or any value between any two of the foregoing. However, the disclosure is not limited thereto.

[0105] In some embodiments, the flow rate ratio of F2to CF4in the etching gas is F2:CF4= 5:1 to 10:1. For example, the flow rate ratio of F2to CF4may be 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1. However, the disclosure is not limited thereto. CF4may provide carbon for slight passivation. Within the above ratio range, the phenomenon of switching from etching mode to deposition mode and causing etching to stop can be avoided.

[0106] In some embodiments, the third ultra-low temperature is -85°C to -20°C. For example, the third ultra-low temperature can be -85°C, -80°C, -70°C, -60°C, -50°C, -40°C, -30°C, or -20°C, or any value between any two of the foregoing. However, the disclosure is not limited thereto.

[0107] In some embodiments, the total time for performing the third processing step is 0.2 s to 4 s, and the time for performing the first etching step and the second etching step is 0.1 s to 2 s, respectively. For example, the time for performing the first etching step or the second etching step can be 0.1 s, 0.2 s, 0.3 s, 0.4 s, 0.5 s, 0.7 s, 0.9 s, 1 s, 1.2 s, 1.5 s, 1.8 s, or 2 s, or any value between any two of the foregoing. However, the disclosure is not limited thereto.

[0108] In some embodiments, the pressure during the third processing step is 5 mTorr to 200 mTorr. For example, the pressure can be 5 mTorr, 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the foregoing pressure values. However, the application is not limited thereto.

[0109] In some embodiments, the source power during the third processing step is 500 W to 3000 W. For example, the source power can be 500 W, 1000 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the foregoing source power values. However, the application is not limited thereto.

[0110] In some embodiments, the bias power during the third processing step is 10 W to 200 W. For example, the bias power can be 10 W, 20 W, 50 W, 70 W, 100 W, 130 W, 160 W, 180 W, or 200 W, or any value between any two of the foregoing bias power values. However, the application is not limited thereto.

[0111] In some embodiments, the third gas further includes N2, i.e., the third gas includes F2, CF4, and N2. During the third processing step, the plasma formed by the N2 in the third gas is also used to perform a sixth processing on the sidewall of the high aspect ratio deep silicon etching structure being formed (at this step, the sidewall of the first etching structure 15), to form an extremely thin nitride layer on the sidewall, which can assist in passivating the surface of the sidewall, thereby further improving the fidelity of the etching pattern, and thus a more vertical sidewall can be obtained.

[0112] In some embodiments, during the third processing step, any one of NF3, BF3, PF3, C2F6, etc. can be added to the F2 and CF4 of the third gas.

[0113] When NF3 is added to the etching gas, more F ions can be generated, thus providing a high-efficiency fluorine source; and the dissociated NF2 and other groups also help to passivate the sidewall and inhibit the formation of a drum-shaped defect.

[0114] When BF3 is added to the etching gas, the BF x + is a light ion, which is beneficial to bottom etching and sidewall modification. The B element can also be doped into the polymer layer 14 on the sidewall, to change the properties thereof, and further enhance the etching resistance of the polymer layer 14 (the case when PF3 is added is similar).

[0115] When C2F6 is added to the etching gas, a higher C / F ratio can be provided, which can be used for etching conditions requiring stronger passivation.

[0116] The small molecule group in the etching gas, the dominant mechanism in the etching step can include:

[0117] (1) Higher F atom density and deep hole penetration ability: the dissociation energy of small molecule gas is usually lower than that of SF6, and under the same plasma conditions, a higher concentration of F atoms can be produced. F atoms and small molecule ions are light in mass and have long mean free paths, which can effectively diffuse to the bottom of the deep hole to maintain the etching rate at the bottom and avoid "etching stop".

[0118] (2) Better ion-assisted etching: the essence of etching is "ion-enhanced chemical etching". The removal of the bottom silicon requires: a) F atoms for chemical reaction; b) ion bombardment to provide energy to break Si-Si bonds and sputter off byproducts. Light ions (such as CF3 + ) can more effectively transfer energy to the bottom surface than SF x + heavy ions, enhancing the etching reaction; at the same time, due to their light mass, the physical sputtering yield of the material is low, reducing the physical damage to the bottom silicon and the back sputtering of the top photoresist pattern 12.

[0119] (3) Inhibit drum-shaped morphology: the cause of drum-shaped morphology includes local failure of the sidewall protection layer, leading to lateral etching of silicon from the side by F atoms and ions. The advantages of small molecule systems are: a) higher F atom density means faster switching to deposition step, avoiding lateral etching caused by long etching step time; b) assisting sidewall passivation; c) more concentrated vertical ion beam reduces lateral scattering ions. The three work together to ensure that etching is basically in the vertical direction.

[0120] (4) Reduce photoresist pattern 12 consumption caused by physical bombardment: the ions produced by the small molecule system are lighter in mass, and at the same bias, their momentum is lower than that of the heavy ions produced by SF6. Therefore, the physical sputtering rate of the photoresist pattern 12 is significantly reduced, resulting in reduced photoresist pattern 12 consumption and improved pattern fidelity.

[0121] (5) Reduce photoresist pattern 12 consumption caused by chemical erosion: although F atoms will erode the photoresist pattern 12, the small molecule system reduces the overall process time through higher etching efficiency, indirectly reducing the cumulative exposure time of the photoresist pattern 12.

[0122] Step S16: Steps S14 and S15 are repeatedly performed until a high aspect ratio deep silicon etching structure is formed on the substrate.

[0123] Reference Figure 5In some embodiments, the above step S14 is repeatedly performed, and the polymer layer 14 is again deposited on the exposed surface of the substrate 10 (i.e. the inner wall of the first etching structure 15 formed in the previous step) and the exposed surface of the photoresist pattern 12, so as to protect the sidewall of the first etching structure 15 and the photoresist pattern 12 when the third processing step is performed again in the next time.

[0124] Then, the above step S15 is repeatedly performed to etch the polymer layer 14 and the substrate 10, and a second etching structure 16 is successively formed below the first etching structure 15, as shown in Figure 6 Figure 6 The original bottom of the first etching structure 15 is indicated by a horizontal dashed line in the figure. After the etching in this step, the polymer layer 14 remains on the sidewall of the photoresist pattern 12 and the sidewall of the first etching structure 15, Figure 6 which is omitted in the figure.

[0125] By repeating the above steps S14 and S15, a third etching structure, a fourth etching structure, etc. (not shown in the figure) can be successively formed below the second etching structure 16, and finally a high-aspect-ratio deep silicon etching structure 17 with a target aspect ratio is formed on the substrate 10, which is composed of the successively formed etching structures (the first etching structure 15, the second etching structure 16, the third etching structure, the fourth etching structure, etc.), as shown in Figure 7

[0126] In some embodiments, when the process of steps S14 and S15 is performed once, a scallop-shaped stripe is regularly formed on the sidewall, the bottom of each scallop-shaped stripe has a concave part, and the junction of two scallop-shaped stripes has a convex part, so that the sidewall has a rough surface topography. Therefore, in the embodiments of the present application, after each cycle of steps S14 and S15 is performed once, or after each cycle of steps S14 and S15 is performed twice, a seventh processing step of the sidewall is embedded at a third ultra-low temperature, the excess polymer layer 14 on the sidewall is timely removed, the etching non-uniformity caused by the excessive thickness of the polymer is prevented, and at least part of the convex part is removed by the seventh processing, so as to reduce the roughness of the sidewall and improve the smoothness of the sidewall.

[0127] ​​In some embodiments, the seventh process specifically includes: using plasma of HBr and O2 to react with polymer layer 14 to remove part of the thickness of polymer layer 14 deposited on the sidewall, so as to adjust the thickness uniformity of polymer layer 14 on the sidewall, and reacting with silicon material on the surface of the exposed protrusions on the sidewall to generate silicon tetrabromide layer and silicon dioxide layer; subsequently, stopping the introduction of HBr and O2, and using plasma of CF4 and Ar to bombard the sidewall to etch and remove silicon dioxide on the protrusions, and desorbing tetrabromosilane and removing it from the sidewall, thereby removing at least part of the protrusions and forming a smoother new sidewall, making the sidewall smoother, thereby reducing the roughness of the sidewall surface, and effectively avoiding the local rough peaks (Ra>5nm) caused by the random deposition of polymer on the sidewall in the past.

[0128] In some embodiments, the time for performing the seventh process is 1 to 4 seconds. For example, the time can be 1 second, 1.2 seconds, 1.4 seconds, 1.6 seconds, 1.8 seconds, 2 seconds, 2.4 seconds, 3 seconds, 3.6 seconds, or 4 seconds, or any value between any two of the aforementioned time values. However, it is not limited to these.

[0129] In some embodiments, when performing the seventh process, the timing of introducing HBr and O2 may be the same as or different from the timing of introducing CF4 and Ar.

[0130] In some embodiments, during the seventh process, HBr is also used to perform an eighth process on the exposed surface of the photoresist pattern 12. This process causes the chemical bonds in the photoresist pattern 12 material to break and recombine, forming polymer chains. By changing the C / H ratio on the surface of the photoresist pattern 12 material, the etching resistance of the photoresist pattern 12 is improved. Therefore, the etching barrier capability of the upper photoresist pattern 12 is improved during deep silicon etching, i.e., the etching selectivity of the photoresist pattern 12 is increased. The eighth process is performed simultaneously with the seventh process.

[0131] In some embodiments, during the seventh process, O2 is also used to perform a ninth process on the exposed surface of the photoresist pattern 12, causing the exposed surface of the photoresist pattern 12 to oxidize at a third ultra-low temperature and be triggered by deep ultraviolet light in the environment to form a hardened layer. This improves the etching barrier capability of the upper photoresist pattern 12 during deep silicon etching, i.e., it increases the etching selectivity of the photoresist pattern 12. The ninth process is performed simultaneously with the seventh process.

[0132] Step S17: Remove the photoresist pattern.

[0133] In some embodiments, after the high aspect ratio deep silicon etching structure 17 is formed, the surface of the substrate 10 is bombarded by plasma of a fourth gas to remove the photoresist pattern 12 and the first protective film 13 on the surface of the substrate 10. After the photoresist pattern 12 and the first protective film 13 are removed, the substrate 10 with the surface exposed and the high aspect ratio deep silicon etching structure 17 formed is obtained, as shown in FIG. 3C. Figure 8

[0134] In some embodiments, the fourth gas includes an oxidizing gas. The oxidizing gas can be, for example, oxygen, and nitrogen can be introduced as a dilution gas at the same time.

[0135] The second processing step and the third processing step are repeatedly performed in sequence until the high aspect ratio deep silicon etching structure is formed on the substrate.

[0136] In other embodiments, another implementation of the high aspect ratio deep silicon etching structure is that the process of repeatedly performing the second processing step and the third processing step in sequence until the high aspect ratio deep silicon etching structure is formed on the substrate is divided into a first etching stage, a second etching stage and a third etching stage connected in sequence, which are respectively used to form the top, middle and bottom of the high aspect ratio deep silicon etching structure in sequence, and the first etching stage can use F2 and N2 as etching gases, the second etching stage can use F2 and PF3 (or F2 and BF3) as etching gases, and the third etching stage can use F2 and C2F6 (or F2 and CF4) as etching gases. When the first etching stage is performed, a stable plasma can be formed by adding N2, which can reduce the severe etching behavior of the top region caused by unstable sheath layer and mask edge effect in the early stage of etching, effectively ensure the stability of the top critical dimension, reduce ion sputtering damage in the etching process, improve the protection of the photoresist pattern, and also form an extremely thin nitrided layer on the sidewall to assist in passivation of the surface of the sidewall, prevent excessive lateral etching, and improve the perpendicularity of the top of the sidewall. By using the combination of F2 and PF3 (or F2 and BF3) as etching gases in the second etching stage, the properties of the polymer layer can be changed by the incorporation of P (or B) elements, so as to enhance the lateral etching resistance of the polymer layer, thereby further improving the perpendicularity of the sidewall and the uniformity of the size. By using the combination of F2 and C2F6 (or F2 and CF4) as etching gases in the third etching stage, a higher fluorocarbon ratio can be provided to enhance the deposition, which can effectively suppress the lateral etching of the bottom of the sidewall, thereby eliminating the problem of bottom side digging. Therefore, by performing the etching process in stages, not only the limitations of the traditional single etching process that cannot achieve high-precision control are overcome, but also a more precise and controllable etching scheme is provided for the manufacture of high-performance devices, effectively expanding the etching process window.

[0137] ​According to a second aspect of this application, embodiments of this application also provide a high aspect ratio deep silicon etched structure, which is obtained using a patterning method for high aspect ratio deep silicon etched structures as provided in any of the embodiments of the first aspect above.

[0138] refer to Figure 8 In some embodiments, a high aspect ratio deep silicon etched structure 17 is formed on the surface of the substrate 10. The critical dimension of the high aspect ratio deep silicon etched structure 17 can be below 50 nm, and the aspect ratio can be greater than or equal to 100:1. The high aspect ratio deep silicon etched structure 17 can be, for example, a deep trench, a deep via, or a through-hole.

[0139] In some embodiments, the high aspect ratio deep silicon etched structure 17 can be applied to MEMS devices (such as accelerometers, gyroscopes, pressure sensors, etc.), 3D integration and advanced packaging (such as through-silicon via (TSV) fabrication, chip stacking, etc.), optical devices (such as optical waveguides, diffraction gratings, etc.), and power devices (such as trench structures of insulated gate bipolar transistors (IGBTs) and power metal-oxide-semiconductor field-effect transistors (MOSFETs, etc.).

[0140] In a third aspect, embodiments of this application also provide a plasma processing apparatus for performing the patterning method for the high aspect ratio deep silicon etched structure corresponding to the above embodiments to form the high aspect ratio deep silicon etched structure 17 corresponding to the above embodiments. The plasma processing apparatus includes inductively coupled plasma (ICP) etching apparatus or capacitively coupled plasma (CCP) etching apparatus, etc.

[0141] In other aspects, embodiments of this application also provide an electronic device, including a high aspect ratio deep silicon etched structure 17 (e.g., deep trench, deep hole, or through hole, etc.) obtained using the patterning method for high aspect ratio deep silicon etched structures described in the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, electronic instrument, television, artificial intelligence device, etc.

[0142] In summary, by using small molecule second gas (SF6 and O2) and third gas (F2 and CF4) to replace the traditional large molecule gas C4F8 and SF6 as deposition gas and etching gas respectively, the diffusion coefficient can be increased, the gas transmission efficiency can be improved, the etching gas can be more uniformly diffused and more easily enter the nanoscale high aspect ratio deep silicon etching structure 17 (deep trench, deep hole or via) to perform etching reaction, more excellent small size high aspect ratio deep silicon etching can be achieved, the deposition gas can smoothly enter the bottom of the high aspect ratio deep silicon etching structure 17, more uniform protection of the sidewall at a smaller size can be achieved. Moreover, by making the temperature (second ultra-low temperature, third ultra-low temperature) when performing the second processing step and the third processing step less than -20℃, the ultra-low temperature can be used to change the chemical kinetics, enhance the physical adsorption, and reduce the reaction rate, so that the formed polymer layer (SiCOF compound layer) can be more dense and more uniformly adsorbed on the sidewall, even at the bottom of the high aspect ratio deep silicon etching structure 17, effective protection of the sidewall can be formed, lateral etching can be effectively inhibited, an extremely vertical sidewall morphology can be obtained, and further, high aspect ratio nanoscale size deep silicon structure etching can be achieved. At the same time, the small molecule etching gas can significantly improve the etching rate and etching behavior at high depth (>100µm).

[0143] The above merely describes the preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Any equivalent changes made according to the content of the specification and drawings of the present application shall also be included in the protection scope of the present application.

Claims

1. A method for patterning high aspect ratio deep silicon etched structures, characterized in that, include: Provide a substrate made of silicon; Multiple photoresist patterns are formed on the surface of the substrate, with an opening between two adjacent photoresist patterns; The first processing step is performed by bombarding the interface of the substrate located at the inner bottom corner of the opening with plasma of a first gas at a first ultra-low temperature to form a first protective film. A second processing step is performed, in which a polymer layer is deposited on the substrate, the photoresist pattern, and the first protective film using a plasma of a second gas at a second ultra-low temperature to protect the substrate and the photoresist pattern during etching. The third processing step involves etching the polymer layer and the substrate using plasma of a third gas at a third ultra-low temperature. The second and third processing steps are repeated sequentially until a high aspect ratio deep silicon etched structure is formed on the substrate. Wherein, the first ultra-low temperature, the second ultra-low temperature, and the third ultra-low temperature are all less than -20°C, the first gas includes Ar, the first protective film includes a carbon-containing protective film, the second gas includes SF6 and O2, the polymer layer includes a SiCOF compound layer, and the third gas includes F2 and CF4.

2. The patterning method for high aspect ratio deep silicon etched structures according to claim 1, characterized in that, When performing the second processing step, the active groups of F, O, and S generated by reacting O2 with SF6 and substrate material respectively react with C atoms sputtered from photoresist material and co-deposit at the second ultra-low temperature to form the SiCOF compound layer.

3. The patterning method for high aspect ratio deep silicon etched structures according to claim 2, characterized in that, When performing the second processing step, plasma formed by the O2 in the second gas is also used to perform a fourth processing on the exposed surface of the photoresist pattern, so that the exposed surface of the photoresist pattern is oxidized at the second ultra-low temperature and triggered by deep ultraviolet light in the environment to form a hardened layer.

4. The patterning method for high aspect ratio deep silicon etched structures according to claim 3, characterized in that, When performing the second processing step, O2 in the second gas is first introduced to bombard the exposed surface of the photoresist pattern using the formed oxygen plasma to form the hardened layer and C atoms are sputtered from the photoresist material. Then, SF6 in the second gas is introduced to form the SiCOF compound layer.

5. The patterning method for high aspect ratio deep silicon etched structures according to claim 1, characterized in that, The flow rate of SF6 is 10 sccm to 30 sccm, and the flow rate of O2 is 30 sccm to 100 sccm; or, the flow rate ratio of SF6 to O2 is SF6:O2 = 1:3 to 1:

10.

6. The patterning method for high aspect ratio deep silicon etched structures according to claim 1, characterized in that, When performing the third processing step, the plasma formed by the CF4 in the third gas is also used to perform a fifth processing on the exposed surface of the photoresist pattern to form a second protective film on the exposed surface of the photoresist pattern. The second protective film includes a carbon-containing protective film.

7. The patterning method for high aspect ratio deep silicon etched structures according to claim 1, characterized in that, The flow rate of F2 is 100 sccm to 400 sccm, and the flow rate of CF4 is 10 sccm to 80 sccm; or, the flow rate ratio of F2 to CF4 is F2:CF4 = 5:1 to 10:

1.

8. The patterning method for high aspect ratio deep silicon etched structures according to claim 1, characterized in that, The third gas also includes N2. When performing the third processing step, plasma formed by the introduced N2 is also used to perform a sixth processing on the sidewalls of the high aspect ratio deep silicon etched structure being formed, forming a nitride layer on the sidewalls to assist in passivation of the sidewall surface.

9. The patterning method for high aspect ratio deep silicon etched structures according to claim 1, characterized in that, -85℃≤first ultra-low temperature<-20℃; and / or, -85℃≤second ultra-low temperature<-20℃; and / or, -85℃≤third ultra-low temperature<-20℃.

10. A high aspect ratio deep silicon etching structure, characterized in that, It is obtained using the patterning method for high aspect ratio deep silicon etched structures as described in any one of claims 1-9.

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