A packaging structure with selective copper-coated and chip-integrated units and a manufacturing method thereof

Abstract

The application discloses a packaging structure with a selective copper-coated and chip-integrated unit and a preparation method thereof, and relates to the technical field of electronic packaging. The preparation method comprises the following steps: patterning a ceramic substrate, and attaching a first green body layer and a second green body layer to the surface of a first metallized layer of the patterning ceramic substrate and the surface of a heat dissipation plate, respectively; the first green body layer and the second green body layer are composed of solid-state diffusible metal particles, the conductive circuit area is stacked with a copper sheet through the first green body layer, the chip attaching area is stacked with a chip through the first green body layer, and bagging, sealing and sintering are performed. The four process steps of patterning a ceramic substrate, attaching a chip, copper-coating a conductive circuit and integrating a substrate and a heat dissipation plate are integrated into a one-time pressure sintering process, integrated packaging is realized, the packaging process is simplified, the production efficiency is improved, the thermal stress control is excellent, and the device performance and reliability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic packaging, in particular to a packaging structure with a chip integrated unit with selective copper cladding and a preparation method thereof. BACKGROUND

[0002] In power semiconductor module packaging, ceramic copper-clad plate as a key insulating and heat-conducting substrate, its structure design and preparation process directly affect the current carrying capacity, heat dissipation efficiency and reliability of the module. The ceramic copper-clad plate prepared by the traditional DBC or AMB process is uniformly cladded with copper on both sides, and the circuit is formed by subsequent photoetching and etching. The power chip is attached to the circuit by solder or sintered silver paste, and finally the entire substrate is welded to the heat sink. This multi-step process is complicated, and introduces multiple high-temperature processes and multiple interfaces, resulting in high cumulative thermal resistance, high thermal stress, and many parasitic parameters, which has become a bottleneck restricting the development of high-power density devices. Therefore, there is an urgent need for a new integrated packaging solution that can integrate chip attachment, circuit interconnection and heat dissipation management to simplify the process and improve performance and reliability.

[0003] The manufacturing method of a novel semiconductor heat dissipation integrated packaging structure of patent application CN117894689A, by vacuum brazing mode, copper foil A, copper substrate A, ceramic substrate and copper foil B are welded at one time, only one sintering is needed in total, the sintering frequency is less, the production efficiency is improved, at the same time, the air holes in the solder layer are less, the sealing performance is improved, the heat dissipation efficiency is improved, and the whole combination of copper foil A, copper substrate A, ceramic substrate and copper foil B has higher thermal conductivity, the thermal resistance is reduced, and the heat dissipation efficiency is improved. However, the one-time welding process of this scheme depends on vacuum brazing welding, and large-area brazing is used between the thick copper cladding and the ceramic substrate. When the solder melts under the action of copper cladding, air bubbles are sealed, which can easily cause the problem of interface air hole rate. In addition, the brazing welding process requires the welding temperature to be above the melting point of the filler metal, and the welding temperature is often as high as 950 DEG C. Due to the difference in thermal expansion coefficient of each component, under the action of high temperature in the welding process, the thermal mismatch of the assembly will generate a large internal stress, which will eventually affect the reliability of the device. SUMMARY

[0004] The purpose of the present application is to overcome the defects and deficiencies of the existing packaging structure, and to provide a preparation method of a packaging structure with a chip integrated unit with selective copper cladding, which can realize integrated packaging, simplify the packaging process, and has excellent thermal stress control, and improve the performance and reliability of the device.

[0005] Another purpose of the present application is to provide a packaging structure with a chip integrated unit with selective copper cladding.

[0006] The above-mentioned purpose of the present application is realized by the following technical solutions:

[0007] The application protects a preparation method of a packaging structure with a chip integrated unit selectively covered with copper, comprising the following steps:

[0008] S1, patterned ceramic substrate preparation: taking a ceramic substrate with upper and lower surfaces respectively formed with a first metallization layer and a second metallization layer, etching a circuit pattern on the first metallization layer to obtain a patterned ceramic substrate;

[0009] S2, green layer mounting: mounting a first green layer and a second green layer on the first metallization layer surface of the patterned ceramic substrate and the heat sink surface respectively; the materials of the first green layer and the second green layer are metal particles capable of solid-state diffusion;

[0010] S3, stacking: stacking the heat sink, the patterned ceramic substrate, the copper sheet and the chip; wherein the heat sink is in contact with the second metallization layer through the second green layer, the circuit pattern of the first metallization layer comprises a conductive circuit area and a chip mounting area, the copper sheet is stacked through the first green layer in the conductive circuit area, and the chip is stacked through the first green layer in the chip mounting area;

[0011] S4, bagging and sealing: bagging the stacked part obtained in step S3, and sealing after vacuumizing;

[0012] S5, sintering: sintering the bagged stacked part obtained in step S4 to solid-state diffusion of the green layer, to obtain the packaging structure with the chip integrated unit selectively covered with copper.

[0013] Specifically, the preparation method of the application has the following effects:

[0014] 1. Process integration: four process steps of patterned ceramic substrate preparation, chip mounting, conductive circuit copper covering and substrate and heat sink integration are integrated into one-time pressure sintering process, realizing integrated packaging, simplifying the packaging process and improving production efficiency.

[0015] 2. Heat dissipation path optimization: the heat generated by the chip can be directly conducted to the heat sink through the ceramic substrate and the sintered layer below, forming the shortest vertical heat dissipation channel, effectively reducing the overall thermal resistance.

[0016] 3. Flexible structure: the selective structure of "chip mounting area without copper + conductive circuit area with thick copper" not only ensures efficient heat dissipation of the chip, but also realizes large current bearing by using the copper sheet, and helps to reduce parasitic inductance.

[0017] 4. Excellent thermal stress control: one-time sintering avoids the accumulation of thermal cycle stress caused by multiple high-temperature processes, and the low-temperature sintering connection layer after solid-state diffusion has good thermal fatigue resistance, improving the long-term reliability of the module under temperature cycle conditions.

[0018] Further, the packaging structure of the present application realizes high-strength, high-thermal-conductivity connection between the chip and the ceramic substrate, low-resistance, large-current-carrying capacity connection between the copper sheet and the front-line of the ceramic substrate, and high-strength, low-thermal-resistance connection between the ceramic substrate and the heat sink through low-temperature sintering connection layer by solid-state diffusion, with low sintering temperature, small thermal stress, and further ensured reliability of the device.

[0019] The surface metallized ceramic substrate of the present application can be self-made or purchased, and the ceramic metallization process of the present application is not particularly limited, and the conventional solder vacuum brazing process in the field of semiconductor packaging can be used.

[0020] In some embodiments, the ceramic metallization of the present application is: after coating the surface of the ceramic substrate with active solder, the surface of the ceramic substrate is metallized by melting the solder through vacuum brazing, and the temperature of the vacuum brazing is 800-900℃.

[0021] The active solder refers to solder doped with a small amount of high-activity metal elements, which reacts with the ceramic material under the action of high-activity metal elements to realize firm metallurgical bonding. The active solder of the present application is not particularly limited, and the commercially available active solder applied to ceramic substrates can achieve the purpose of the present application. Preferably, the main material of the active solder is Ag and / or Cu, and the active element is selected from any one of titanium (Ti), zirconium (Zr) or hafnium (Hf), preferably Ti element, and the doping amount is 1.5-5%. Alternatively, the active solder is Ag-Cu-Ti solder paste; exemplarily, the active solder can be selected from Ag 68.8 Cu 26.7 Ti 4.5 or Ag 70.5 Cu 27.5 Ti2.

[0022] In some embodiments, the thickness of the active solder is 5-30um, and preferably the thickness of the active solder is 15-25um.

[0023] The ceramic substrate of the present application is not particularly limited, and the conventional ceramic substrate material in the field of semiconductors can be used; preferably, the ceramic substrate material is selected from any one or a combination of two or more of AlN, Si3N4, Al2O3, or SiC.

[0024] The etching process of the patterned ceramic substrate of the present application is not particularly limited, and conventional photolithography and / or chemical etching in the art can be used; alternatively, the present application uses Film exposure and chemical etching to form line patterns and chip patterns.

[0025] The present application forms a firm metallization layer on the surface of a ceramic substrate, and then obtains a required front side circuit pattern through fine etching. The circuit pattern defines a subsequent conductive circuit area and a chip mounting area. Since the thickness of the metallization layer is very small, compared with the process of directly covering thick copper by using high-temperature active soldering, the thermal stress of the patterned ceramic substrate can be greatly reduced, and the reliability of the patterned ceramic substrate can be greatly improved. Meanwhile, compared with thick copper patterned circuit etching, the thin metal layer does not have obvious side etching problem, and the circuit etching precision is higher.

[0026] In some embodiments, the green layer in step S2 is a sintering paste printing layer and / or a pre-sintering film layer.

[0027] Preferably, when the green layer is a sintering paste printing layer, the sintering paste printing layer is obtained by sintering paste printing and low-temperature drying; the sintering paste is micron / nano composite copper paste or micron / nano composite silver paste.

[0028] The sintering paste of the present application refers to a paste-like mixture composed of metal micron / nano powder and organic carrier. By applying pressure at a temperature lower than the melting point of the metal, firm connection between particles is achieved through solid-state atomic diffusion, and finally a high-density, high-melting-point metal layer is formed. The sintering paste of the present application is not particularly limited and can be self-made or purchased on the market; preferably, the micron / nano composite copper paste is composed of 1-5um and 50-500nm copper powder, and the micron / nano composite silver paste is composed of 1-5um and 50-500nm silver powder, with a compounding ratio of (3-4):(6-7).

[0029] Preferably, the temperature of the low-temperature drying is 80-120℃, and the time is 10-30min.

[0030] Preferably, when the green layer is a pre-sintering film layer, the sintering paste printing layer is obtained by pre-sintering film mounting; the pre-sintering film is a pre-sintering nano silver film and / or a pre-sintering nano copper film. The pre-sintering nano silver film or pre-sintering nano copper film is formed by sintering paste printing, and the pre-sintering film of the present application is not particularly limited and can be self-made or purchased on the market.

[0031] Preferably, the thickness of the green layer is 0.01-0.2mm.

[0032] Preferably, the patching action can refer to the patching use method of conventional nano copper / silver sintering paste or nano copper / silver sintering film; specifically, the present application uses a patching machine to heat patch to ensure pre-fixing after patching.

[0033] The green layer of the present application is composed of solid diffusion metal particles, the metal particles are micron / nanometer particles, and the metal particles are preferably silver particles and / or copper particles, which form a dense connection layer during pressure-assisted low-temperature (<500℃) sintering. The micro-nano particles have extremely high specific surface area and surface energy, which enhances the driving force of sintering, and solid-state diffusion (especially surface diffusion and grain boundary diffusion) is dominant, and under the joint driving of specific pressure and thermal energy, the process of particle neck growth, pore shrinkage and densification is realized, so that a dense microstructure can be formed at low temperature, and the forming temperature is much lower than the temperature required for the melting of the solder in the brazing process (>800℃), thereby avoiding the great internal stress caused by thermal mismatch during high-temperature brazing, which affects the reliability of the device.

[0034] In some embodiments, the conductive circuit area of the first metallization layer has the same shape as the copper sheet in step S3. The process of the present application can realize selective copper plating, that is, the conductive circuit area is covered with copper to ensure large current carrying capacity, while the chip mounting area is not covered with copper, thereby reducing the interface heat dissipation thermal resistance, and also avoiding the problem of thermal expansion mismatch stress between the chip and the thick copper connection after the chip position is covered with thick copper.

[0035] In some embodiments, the heat dissipation plate has a thickness of 2-10 mm.

[0036] In some embodiments, the ceramic substrate has a thickness of 0.1-1.5 mm.

[0037] In some embodiments, the copper sheet has a thickness of 0.2-0.8 mm.

[0038] In some embodiments, the chip is selected from at least one of a silicon-based IGBT, a silicon carbide MOSFET, or a gallium nitride HEMT semiconductor chip.

[0039] In step S4, the bagging is preferably carried out using a flexible aluminum foil bag in some embodiments.

[0040] In step S4, the vacuum degree after vacuumizing and sealing is preferably ≤5×10 -2 Pa.

[0041] In step S5, the sintering conditions are as follows: under the protection of inert atmosphere or air atmosphere, the sintering temperature is 200-500℃, the pressure is 5-40 MPa, and the holding time is 3-60 min.

[0042] Preferably, the sintering temperature is 250-320℃, the pressure is 15-30 MPa, and the holding time is 25-40 min.

[0043] The steps S4 and S5 of the present application adopt vacuum sealing and combine high-temperature-gas-pressure sintering process, without mechanical pressure head, and are easy to realize batch process production, and the hot isostatic pressing provided by the present application can well adapt to the sintering of structures with local height difference, and the sintering uniformity is good, and the sintering quality is good. Under certain temperature and pressure, the green body layer is densified and sintered, so that high-strength connection between the heat dissipation plate, the patterned ceramic substrate, the copper sheet and the chip and other components is realized in a single process cycle.

[0044] The present application also protects a packaging structure with a selective copper-coated and chip-integrated unit, comprising:

[0045] a heat dissipation plate;

[0046] a second sintering connection layer, which is sintered by solid-state diffusible metal particles and is connected with the surface of the heat dissipation plate;

[0047] a patterned ceramic substrate, which comprises a ceramic substrate and a first metallization layer and a second metallization layer located on the upper and lower sides of the ceramic substrate, the first metallization layer has a preset circuit and chip pattern, and the second metallization layer is connected with the second sintering connection layer;

[0048] a first sintering connection layer, which is sintered by solid-state diffusible metal particles and is connected with the surface of the first metallization layer;

[0049] a chip, which is connected with the chip mounting area of the patterned ceramic substrate through the first sintering connection layer;

[0050] a copper sheet, which is connected with the conductive circuit area of the patterned ceramic substrate through the first sintering connection layer.

[0051] In some embodiments, the chip and the copper sheet are distributed in a spaced manner between the ceramic substrate.

[0052] In some embodiments, the packaging structure with the selective copper-coated and chip-integrated unit is made by the preparation method.

[0053] Compared with the prior art, the present application has the following beneficial effects:

[0054] The present application provides a preparation method of a packaging structure with a selective copper-coated and chip-integrated unit, which integrates four process steps of patterned ceramic substrate preparation, chip mounting, conductive circuit copper coating and substrate and heat dissipation plate integration into a one-time pressure sintering process, realizes integrated packaging, simplifies the packaging process and improves the production efficiency. At the same time, the connection structure is optimized, high-temperature active brazing treatment is not needed, the whole process only needs one-time sintering to avoid thermal cycle stress accumulation caused by multiple high-temperature processes, the thermal stress control is excellent, and the device performance and reliability are improved. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 A structural schematic diagram of a packaging structure with a chip integrated unit selectively coated with copper according to the present application.

[0056] Figure 2 A process flow chart of a preparation method of a packaging structure with a chip integrated unit selectively coated with copper according to the present application.

[0057] In the figure, 1 is a patterned ceramic substrate; 11 is a ceramic substrate; 12 is an active soldering material metallization layer; 2 is a heat dissipation plate; 3 is a first sintered connecting layer; 31 is a first green body layer; 4 is a second sintered connecting layer; 41 is a second green body layer; 5 is a chip; 6 is a copper sheet; and 7 is a flexible aluminum foil bag. DETAILED DESCRIPTION

[0058] In order to more clearly and completely describe the technical solutions of the present application, the present application is further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. Various changes can be made within the scope of the present application.

[0059] It should be understood that the orientations or positional relationships indicated by terms such as "upper", "lower", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation. Therefore, the terms describing the positional relationships in the drawings are only used for illustrative purposes, and cannot be understood as limiting the present patent. For those skilled in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0060] Unless specifically stated or defined otherwise, "first", "second", etc. used herein are only used to distinguish different devices, elements or components, and are not used to indicate or imply the relative importance, quantity or order of the indicated devices, elements or components.

[0061] Example 1

[0062] A packaging structure with a chip integrated unit selectively coated with copper, as shown in Figure 1 the figure, includes, from bottom to top, a heat dissipation plate 2, a second sintered connecting layer 4, a patterned ceramic substrate 1 and a first sintered connecting layer 3, the surface of the first sintered connecting layer 3 is respectively connected with a copper sheet 6 and a chip 5, and the copper sheet 6 and the chip 5 are distributed in intervals.

[0063] The heat dissipation plate 2 is a copper plate, the patterned ceramic substrate 1 comprises a ceramic substrate 11 and an active brazing filler metalization layer 12 on the surface of the ceramic substrate 11, the ceramic substrate 11 is Si3N4, the active brazing filler metalization layer 12 comprises a first metalization layer and a second metalization layer on the front and back surfaces of the ceramic substrate 11 respectively, the first metalization layer has a preset circuit pattern, the circuit pattern of the first metalization layer comprises a conductive circuit area and a chip mounting area, the conductive circuit area is connected to the copper sheet 6 through the first sintering connecting layer 3, the conductive circuit area of the first metalization layer is consistent with the shape of the copper sheet 6, and the low-resistance and large-current-carrying capacity connection between the copper sheet 6 and the front surface circuit of the ceramic substrate 11 can realize large-current carrying by using the copper sheet 6, and at the same time, it is helpful to reduce the parasitic inductance; the chip mounting area is connected to the chip 5 of the MOSFET structure through the first sintering connecting layer 3 with high strength and high thermal conductivity, so as to ensure the high-efficiency heat dissipation of the chip 5.

[0064] The first sintering connecting layer 3 and the second sintering connecting layer 4 are sintered from solid-state diffusible metal particles, and specifically, the first sintering connecting layer 3 and the second sintering connecting layer 4 are sintered into shape by screen printing nano-silver paste and low-temperature sintering.

[0065] In the packaging structure of the embodiment, the conductive circuit area covered by the copper sheet 6 does not need to be welded by brazing filler metal, and the problem of interface cavity rate caused by bubbles generated when the solder melts does not occur. At the same time, the chip 5 is directly connected to the patterned ceramic substrate 1 through the first sintering connecting layer 3, so that the heat generated by the chip 5 can be directly conducted to the heat dissipation bottom plate through the ceramic substrate 11 and the sintering connecting layer below, forming the shortest vertical heat dissipation channel, and effectively reducing the overall thermal resistance.

[0066] The preparation method of the packaging structure with the selective copper-coated and chip-integrated unit comprises the following steps: Figure 2

[0067] S1, the patterned ceramic substrate 1 is prepared: the upper and lower surfaces of the ceramic substrate 11 are respectively ceramic metalized to form a first metalization layer and a second metalization layer, then the circuit pattern and the chip 5 pattern are etched on the first metalization layer to obtain the patterned ceramic substrate 1;

[0068] Specifically, a 0.32mm-thick Si3N4 ceramic substrate 11 is selected, and Ag-Cu-Ti solder paste (Ag 68.8 Cu 26.7 Ti 4.5 ​). In a vacuum brazing furnace, the metallization is completed by cooling after holding at 850°C for 15 minutes, thereby forming an active brazing metal metallization layer 12 on the surface of the ceramic substrate 11, which includes a first metallization layer and a second metallization layer on the front and back surfaces of the ceramic substrate 11 respectively. Subsequently, a designed circuit pattern is formed on the first metallization layer of the front surface by film exposure, development and chemical etching, thereby obtaining a patterned ceramic substrate 1.

[0069] S2, green layer assembly: a first green layer 31 and a second green layer 41 are respectively assembled on the surface of the first metallization layer of the patterned ceramic substrate 1 and the surface of the heat sink;

[0070] Specifically, the first green layer 31 and the second green layer 41 are formed by screen printing micron / nanometer composite silver paste (Xianyi Electronics Co., Ltd., XY-ASP-NM250P) on the circuit pattern area of the first metallization layer of the patterned ceramic substrate 1 and the corresponding connecting surface of the heat sink 2 (thickness 5 mm) with a printing thickness of 0.1 mm, and then dried in an oven at 100°C for 20 minutes.

[0071] S3, stacking: the heat sink 2, the patterned ceramic substrate 1, the copper sheet 6 and the chip 5 are stacked; wherein the heat sink 2 is in contact with the second metallization layer, the chip pattern area of the first metallization layer is stacked with the chip 5, and the circuit pattern area of the first metallization layer is stacked with the copper sheet 6;

[0072] Specifically, the heat sink 2 printed with the second green layer 41 is stacked from the bottom up in the following order: the patterned ceramic substrate 1 printed with the first green layer 31 (the second metallization layer of the back surface faces down) → the silicon carbide MOSFET chip 5 (placed in the chip mounting area on the front surface of the ceramic substrate) → the copper sheet 6 (thickness 0.4 mm, placed in the conductive circuit area) matching the shape and circuit pattern.

[0073] S4, bagging and sealing: the stacked part obtained in step S3 is bagged, vacuumed and sealed;

[0074] Specifically, the stacked part obtained in step S3 is placed in a flexible aluminum foil bag 7, vacuumed to 100 Pa and heat-sealed.

[0075] S5, sintering: the bagged stacked part obtained in step S4 is sintered to solid-state diffusion of the green layer, thereby obtaining the packaging structure of the selective copper-coated and chip-integrated unit.

[0076] Specifically, the bagged and stacked piece after step S4 sealing is put into a high-temperature pressure sintering furnace, a pressure of 20 MPa is applied by using a nitrogen positive pressure atmosphere, and heating is performed to a temperature of 280 DEG C, heat preservation and pressure preservation are performed for 30 min, the furnace is cooled down, and after being taken out, the packaging structure with the selective copper-coated and chip integrated unit is obtained.

[0077] In the preparation method of the embodiment, four process steps of patterned ceramic substrate preparation, chip mounting, conductive circuit copper coating, and substrate and heat sink integration are integrated into a one-time pressure sintering process, integrated packaging is achieved, the packaging process is simplified, and the production efficiency is improved. The overall process only needs one-time sintering to avoid thermal cycle stress accumulation caused by multiple high-temperature processes, the thermal stress control is excellent, and the device performance and reliability are improved.

[0078] Embodiment 2

[0079] A packaging structure with a selective copper-coated and chip integrated unit, as shown in Figure 1 , includes, from bottom to top, a heat sink 2, a second sintering connection layer 4, a patterned ceramic substrate 1, and a first sintering connection layer 3, the surface of the first sintering connection layer 3 is respectively connected with a copper sheet 6 and a chip 5, and the copper sheet 6 and the chip 5 are spaced apart.

[0080] The heat sink 2 is a copper plate, the patterned ceramic substrate 1 includes a ceramic substrate 11 and an active brazing filler metalized layer 12 on the surface of the ceramic substrate 11, the ceramic substrate 11 is AlN, the active brazing filler metalized layer 12 includes a first metalized layer and a second metalized layer on the front and back surfaces of the ceramic substrate 11, respectively, the first metalized layer has a preset circuit pattern, the circuit pattern of the first metalized layer includes a conductive circuit area and a chip mounting area, the conductive circuit area is connected with the copper sheet 6 through the first sintering connection layer 3, the conductive circuit area of the first metalized layer is consistent with the shape of the copper sheet 6, the low-resistance and large-current-carrying-capability connection between the copper sheet 6 and the front circuit of the ceramic substrate 11 can realize large-current carrying by using the copper sheet 6, and at the same time, it is helpful to reduce the parasitic inductance; the chip mounting area is connected with the gallium nitride HEMT chip 5 through the first sintering connection layer 3 with high strength and high thermal conductivity, and the efficient heat dissipation of the chip 5 is ensured.

[0081] The first sintering connection layer 3 and the second sintering connection layer 4 are sintered from solid-state diffusible metal particles, specifically, the first sintering connection layer 3 and the second sintering connection layer 4 in the embodiment are sintered into shape by screen printing nano-copper paste at low temperature.

[0082] In the packaging structure of the present application, the conductive circuit area covered by the copper sheet 6 does not need to be soldered, and there will be no problem of interface cavity rate caused by bubbles generated when the solder melts. At the same time, the chip 5 is directly connected with the patterned ceramic substrate 1 through the first sintering connection layer 3, so that the heat generated by the chip 5 can be directly conducted to the heat dissipation bottom plate through the ceramic substrate 11 and the sintering connection layer below, forming the shortest vertical heat dissipation channel, and effectively reducing the overall thermal resistance.

[0083] The preparation method of the packaging structure with the selective copper-coated and chip-integrated unit, as shown in Figure 2 The preparation method of the packaging structure with the selective copper-coated and chip-integrated unit, as shown in

[0084] S1, patterned ceramic substrate 1 preparation: the upper and lower surfaces of the ceramic substrate 11 are respectively subjected to ceramic metallization to form a first metallized layer and a second metallized layer, then a circuit pattern and a chip 5 pattern are etched on the first metallized layer to obtain a patterned ceramic substrate 1;

[0085] Specifically, an AlN ceramic substrate 11 with a thickness of 1.0 mm is selected, and Ag-Cu-Ti solder paste (Ag 70.5 Cu 27.5 Ti2) with a thickness of 20 um is screen printed on the front and back surfaces of the ceramic substrate 11. The metallization is completed by cooling after holding at 880℃ for 15 minutes in a vacuum soldering furnace, so as to form an active solder metallization layer 12 on the surface of the ceramic substrate 11, which includes a first metallized layer and a second metallized layer respectively located on the front and back surfaces of the ceramic substrate 11. Subsequently, the designed circuit pattern is formed on the first metallized layer of the front surface by film exposure and development and chemical etching to obtain a patterned ceramic substrate 1.

[0086] S2, green layer assembly: the first green layer 31 and the second green layer 41 are respectively assembled on the surface of the first metallized layer of the patterned ceramic substrate 1 and the surface of the heat dissipation plate;

[0087] Specifically, the micron / nanometer composite copper paste is screen printed on the circuit pattern area of the first metallized layer of the patterned ceramic substrate 1 and the corresponding connecting surface of the heat dissipation plate 2 (thickness 8 mm), and the printing thickness is 0.15 mm, and then dried in an oven at 110℃ for 15 min to form the first green layer 31 and the second green layer 41.

[0088] S3, stacking: the heat dissipation plate 2, the patterned ceramic substrate 1, the copper sheet 6 and the chip 5 are stacked; wherein the heat dissipation plate 2 is in contact with the second metallized layer, the chip pattern area of the first metallized layer is stacked with the chip 5, and the circuit pattern area of the first metallized layer is stacked with the copper sheet 6;

[0089] Specifically, the following are stacked from bottom to top: the heat sink 2 printed with the second green layer 41 → the patterned ceramic substrate 1 printed with the first green layer 31 (with the second metallization layer on the back facing down) → the gallium nitride HEMT chip 5 (placed on the chip mounting area on the front of the ceramic substrate) → the copper sheet 6 (0.6 mm thick) shaped to match the circuit pattern (placed on the conductive circuit area).

[0090] S4, bagging and sealing: the stacked parts obtained in step S3 are bagged, vacuumed, and sealed.

[0091] Specifically, the stacked parts obtained in step S3 are placed in a flexible aluminum foil bag 7, vacuumed to 100 Pa, and heat-sealed.

[0092] S5, sintering: the bagged stacked parts obtained in step S4 are sintered to solid diffusion of the green layers, to obtain the packaging structure with the selective copper-coated and chip-integrated unit.

[0093] Specifically, the bagged stacked parts after sealing in step S4 are placed in a high-temperature pressure sintering furnace, a pressure of 25 MPa is applied using a nitrogen atmosphere, and the temperature is heated to 300°C, the temperature is kept for 25 min, the furnace is cooled down, and the packaging structure with the selective copper-coated and chip-integrated unit is obtained after removal.

[0094] In the preparation method of the embodiment, the four process steps of patterned ceramic substrate preparation, chip mounting, conductive circuit copper coating, and substrate and heat sink integration are integrated into a one-time pressure sintering process, realizing integrated packaging, simplifying the packaging process, and improving production efficiency. The overall process only needs one-time sintering to avoid thermal cycle stress accumulation caused by multiple high-temperature processes, excellent thermal stress control, improved device performance and reliability.

[0095] Example 3

[0096] A packaging structure with a selective copper-coated and chip-integrated unit, as shown in Figure 1 includes, from bottom to top, a heat sink 2, a second sintering connection layer 4, a patterned ceramic substrate 1, and a first sintering connection layer 3, the surface of the first sintering connection layer 3 is respectively connected with a copper sheet 6 and a chip 5, and the copper sheet 6 and the chip 5 are distributed in intervals.

[0097] The heat dissipation plate 2 is a copper plate The patterned ceramic substrate 1 comprises a Si3N4 ceramic substrate 11 and an active brazing filler metalization layer 12 on the surface of the ceramic substrate 11, the ceramic substrate 11 is Si3N4, and the active brazing filler metalization layer 12 comprises a first metalization layer and a second metalization layer on the front and back surfaces of the ceramic substrate 11 respectively, the first metalization layer has a preset circuit pattern, the circuit pattern of the first metalization layer comprises a conductive circuit area and a chip mounting area, the conductive circuit area is connected to the copper sheet 6 through a first sintering connecting layer 3, the conductive circuit area of the first metalization layer is consistent with the shape of the copper sheet 6, and the low-resistance and large-current-carrying-capability connection between the copper sheet 6 and the front surface circuit of the ceramic substrate 11 can realize large-current carrying by using the copper sheet 6, and at the same time, helps to reduce the parasitic inductance; the chip mounting area is connected to the chip 5 of the silicon-based IGBT structure through the first sintering connecting layer 3 with high strength and high thermal conductivity, and the high-efficiency heat dissipation of the chip 5 is ensured.

[0098] The first sintering connecting layer 3 and the second sintering connecting layer 4 are sintered from solid-state diffusible metal particles, and specifically, the first sintering connecting layer 3 and the second sintering connecting layer 4 are sintered into shape by screen printing nano-silver paste and low-temperature sintering.

[0099] In the packaging structure of the embodiment, the conductive circuit area covered by the copper sheet 6 does not need to be welded by brazing filler metal, and the problem of air bubbles caused by the melting of the brazing filler metal and leading to the interface void rate does not occur. At the same time, the chip 5 is directly connected to the patterned ceramic substrate 1 through the first sintering connecting layer 3, so that the heat generated by the chip 5 can be directly conducted to the heat dissipation bottom plate through the ceramic substrate 11 and the sintering connecting layer below, forming the shortest vertical heat dissipation channel, and effectively reducing the overall thermal resistance.

[0100] The preparation method of the packaging structure with the selective copper-coated and chip-integrated unit comprises the following steps: Figure 2 as shown in the figure, comprising the following steps:

[0101] S1, the patterned ceramic substrate 1 is prepared: the upper and lower surfaces of the ceramic substrate 11 are respectively ceramic metalized to form a first metalization layer and a second metalization layer, then the circuit pattern and the chip 5 pattern are etched on the first metalization layer to obtain the patterned ceramic substrate 1;

[0102] Specifically, a 0.25mm-thick Si3N4 ceramic substrate 11 is selected, and Ag-Cu-Ti solder paste (Ag 68.8 Cu 26.7 Ti 4.5). In a vacuum brazing furnace, the metallization is completed by cooling after holding at 820℃ for 15 minutes, thereby forming an active brazing metal metallization layer 12 on the surface of the ceramic substrate 11, which includes a first metallization layer and a second metallization layer respectively on the front and back surfaces of the ceramic substrate 11. Subsequently, a designed circuit pattern is formed on the first metallization layer of the front surface by film exposure, development and chemical etching, thereby obtaining a patterned ceramic substrate 1.

[0103] S2, green layer assembly: a first green layer 31 and a second green layer 41 are respectively assembled on the surface of the first metallization layer of the patterned ceramic substrate 1 and the surface of the heat sink;

[0104] Specifically, the first green layer 31 and the second green layer 41 are formed by screen printing nano-silver paste on the circuit pattern area of the first metallization layer of the patterned ceramic substrate 1 and the corresponding connecting surface of the heat sink 2 (thickness 3mm) with a printing thickness of 0.15mm, and then dried in an oven at 90℃ for 25min.

[0105] S3, stacking: the heat sink 2, the patterned ceramic substrate 1, the copper sheet 6 and the chip 5 are stacked; wherein the heat sink 2 is in contact with the second metallization layer, the chip 5 is stacked in the chip pattern area of the first metallization layer, and the copper sheet 6 is stacked in the circuit pattern area of the first metallization layer;

[0106] Specifically, the following are stacked from bottom to top in the following order: the heat sink 2 with the printed second green layer 41→ the patterned ceramic substrate 1 with the printed first green layer 31 (the second metallization layer of the back surface faces down)→ the chip 5 of the silicon-based IGBT structure (placed in the chip mounting area on the front surface of the ceramic substrate)→ the copper sheet 6 with a shape matching the circuit pattern (thickness 0.2mm, placed in the conductive circuit area).

[0107] S4, bagging and sealing: the stacked assembly obtained in step S3 is bagged, vacuumed and sealed;

[0108] Specifically, the stacked assembly obtained in step S3 is placed in a flexible aluminum foil bag 7, vacuumed to 5×10 -2 and heat-sealed.

[0109] S5, sintering: the bagged stacked assembly obtained in step S4 is sintered to solid-state diffusion of the green layers, thereby obtaining the packaging structure with the selective copper-coated and chip-integrated unit.

[0110] Specifically, the bagged stacked assembly after sealing in step S4 is placed in a high-temperature pressure sintering furnace, a pressure of 15MPa is applied by using a nitrogen positive pressure atmosphere, heated to a temperature of 260℃, held for 35min, and then cooled in the furnace. After taking out, the packaging structure with the selective copper-coated and chip-integrated unit is obtained.

[0111] In the preparation method of the embodiment, four process steps of preparing a patterned ceramic substrate, chip mounting, copper cladding of a conductive circuit, and integration of the substrate and a heat sink are integrated into a one-time pressure sintering process, integrated packaging is realized, the packaging process is simplified, and the production efficiency is improved.

[0112] The above embodiments of the present application are merely examples for clearly illustrating the present application, and are not intended to limit the implementation modes of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. All the implementation modes do not need to be exhausted here. Any modification, equivalent replacement, and improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the claims of the present application.

Claims

1. A method for fabricating a packaging structure with selective copper plating and chip integration units, characterized in that, The method comprises the following steps: S1, patterning ceramic substrate preparation: taking a ceramic substrate with upper and lower surfaces respectively metallized to form a first metallized layer and a second metallized layer, etching a circuit pattern on the first metallized layer to obtain a patterned ceramic substrate; S2, green layer assembly: assembling a first green layer and a second green layer on the surface of the first metallized layer of the patterned ceramic substrate and the surface of the heat sink respectively; the materials of the first green layer and the second green layer are solid-state diffusible metal particles; S3, stacking: stacking the heat sink, the patterned ceramic substrate, the copper sheet and the chip; wherein the heat sink is in contact with the second metallized layer through the second green layer, the circuit pattern of the first metallized layer comprises a conductive circuit area and a chip assembly area, the copper sheet is stacked through the first green layer in the conductive circuit area, and the chip is stacked through the first green layer in the chip assembly area; S4, bagging and sealing: bagging the stacked part obtained in step S3, and sealing after vacuumizing; S5, sintering: sintering the bagged stacked part obtained in step S4 to solid-state diffusion of the green layer to obtain the packaging structure with selective copper coating and chip integration unit.

2. The method of claim 1, wherein the method further comprises: In step S1, the ceramic metallization is: coating the surface of the ceramic substrate with active solder, and then vacuum brazing the solder to melt the solder and metallize the surface of the ceramic substrate; the temperature of the vacuum brazing is 800-900℃.

3. The method of claim 1, wherein the method further comprises: forming a first dielectric layer on the first substrate; forming a second dielectric layer on the second substrate; and forming a third dielectric layer on the first dielectric layer and the second dielectric layer. In step S2, the green layer is a sintering paste printing layer and / or a pre-sintering film layer; When the green layer is a sintering paste printing layer, the sintering paste printing layer is printed by sintering paste, and the sintering paste is micron / nanometer composite copper paste or micron / nanometer composite silver paste; When the green layer is a pre-sintering film layer, the sintering paste printing layer is assembled by a pre-sintering film, and the pre-sintering film is a pre-nanometer silver sintering film and / or a pre-nanometer copper sintering film.

4. The method of claim 1, wherein the method further comprises: In step S3, the conductive circuit area of the first metallized layer has the same shape as the copper sheet.

5. The method of claim 1 or 4, wherein the method further comprises: The thickness of the copper sheet is 0.2-0.8mm.

6. The method of claim 1, wherein the method further comprises: The chip is selected from at least one of silicon-based IGBT, silicon carbide MOSFET or gallium nitride HEMT semiconductor chip.

7. The method of claim 1, wherein the method further comprises: forming a first dielectric layer on the first substrate; forming a second dielectric layer on the second substrate; and forming a third dielectric layer on the first dielectric layer and the second dielectric layer. In step S5, the sintering conditions are: under the protection of inert atmosphere or air atmosphere, the sintering temperature is 200-500℃, the gas pressure is 5-40MPa, and the holding time is 3-60min.

8. The package structure with the selective copper-coated and chip-integrated unit is prepared by the method for preparing the package structure with the selective copper-coated and chip-integrated unit according to any one of claims 1-7, characterized in that, It comprises: a heat sink; a second sintering connection layer, which is sintered by solid-state diffusible metal particles and connected to the surface of the heat sink; a patterned ceramic substrate, which comprises a ceramic substrate and first and second metallized layers on the upper and lower surfaces of the ceramic substrate, the first metallized layer has a preset circuit pattern, the circuit pattern comprises a chip assembly area and a conductive circuit area, and the second metallized layer is connected to the second sintering connection layer; a first sintering connection layer, which is sintered by solid-state diffusible metal particles and connected to the surface of the first metallized layer; a chip, which is connected to the chip assembly area of the patterned ceramic substrate through the first sintering connection layer; a copper sheet, which is connected to the conductive circuit area of the patterned ceramic substrate through the first sintering connection layer.

9. The package structure with selective copper-coated and chip-integrated unit according to claim 8, wherein, The chip is spaced apart from the copper sheet.

10. The package structure with selective copper-coated and chip-integrated unit of claim 8, wherein, The package structure with the selective copper-coated and chip-integrated unit is prepared by the method of any one of claims 1-7.

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