Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which aims at forming a reliable tungsten plug structure connected with a top layer aluminum metal wire to replace the traditional aluminum bump connection. The process includes: depositing an adhesion layer on a passivation layer; etching a high aspect ratio through hole penetrating through the adhesion layer, the passivation layer and the interlayer dielectric layer to the aluminum wire; depositing a barrier layer; the through hole is filled through the steps of two times of tungsten deposition and one time of middle etch-back, part filling is conducted in the first time of deposition, the morphology of the hole opening is improved through etch-back, and filling is completed in the second time of deposition; and finally, removing the adhesion layer and redundant metal through planarization treatment such as chemical mechanical polishing and the like, and stopping on the passivation layer to form the tungsten plug. The adhesion layer is introduced to prevent the barrier layer from falling off, and a secondary filling and back etching combined strategy is adopted, so that the problem of void-free tungsten filling of the high-aspect-ratio through hole is effectively solved, and the filling quality and the structural reliability are improved. The process can improve electrical and heat dissipation performance, is suitable for high reliability requirements of vehicle gauge level and the like, and is compatible with advanced packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] In semiconductor integrated circuit manufacturing, as device feature sizes continue to shrink and integration density continues to increase, the requirements for interconnect technology are also becoming more stringent. Especially in BCD (Bipolar-CMOS-DMOS) technology, the performance of the back end of line (BEOL) interconnect structure is crucial to the overall performance of the chip.

[0003] Traditional BCD back-end processes typically use aluminum (Al) as the top-layer metal interconnects and employ bump technology to connect the chip to external components. For example, copper (Cu) bumping (CU) interconnect technology is used. However, as integrated circuits enter the era of large-scale and ultra-large-scale integration, the requirements for device performance, reliability, and heat dissipation are becoming increasingly stringent, especially in high-reliability applications such as automotive electronics (automotive-grade). The traditional aluminum interconnect combined with copper bumps may encounter problems such as decreased electrical contact performance, reliability challenges, and heat dissipation bottlenecks when facing smaller bump pitches.

[0004] To meet ever-increasing performance demands, the industry has begun exploring new interconnect materials and structures. Tungsten (W), as a metallic material, possesses excellent electrical and thermal conductivity, while also exhibiting good high-temperature stability and corrosion resistance. Applying tungsten to interconnect structures, such as replacing traditional bump fill materials or filling contact holes / vias, is expected to improve the physical and electrical properties of the structure, increase packaging density, and enhance the long-term reliability of devices.

[0005] For example, in advanced flip-chip packaging processes, metal-filled vias (such as VAC, ViaAfter Contact) connecting the top layer metal and bumps are a common structure. Using tungsten to fill these high aspect ratio (HAR) vias directly leverages the advantages of tungsten. However, in actual production, especially on large 12-inch wafers, achieving defect-free (void-free) tungsten filling of HAR vias presents numerous challenges. For instance, single-pass tungsten chemical vapor deposition (CVD) may be limited by equipment capabilities (e.g., a single-pass deposition thickness of approximately 6000 angstroms, or 600 nm, on a 12-inch W Dep machine), making it difficult to fill the large aspect ratio vias in one pass. This can easily lead to incomplete filling or voids forming in the center of the vias, affecting electrical performance and reliability. In addition, the tungsten filling process also needs to consider the compatibility with adjacent materials (such as barrier layers and dielectric layers), the selectivity of etching processes, and the control precision of subsequent planarization processes (such as chemical mechanical polishing, CMP).

[0006] Therefore, there is an urgent need to develop a stable and reliable process to achieve effective tungsten filling of high aspect ratio vias, especially in applications where the vias are connected to the top layer of aluminum metal, so as to meet the needs of high-performance, high-reliability integrated circuits, especially automotive-grade products. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing a semiconductor device to solve the problem of achieving defect-free (e.g., void-free) tungsten filling of high aspect ratio (HAR) vias in actual production, especially on 12-inch large-size wafers.

[0008] To achieve the above and other related objectives, the present invention provides a method for manufacturing a semiconductor device, wherein the method is used to form tungsten-filled vias connecting top-layer metal interconnects in a BCD process, replacing the method of directly forming bumps on the top-layer metal interconnects for connection to the outside of the chip, characterized in that it includes:

[0009] Step 1: Deposit an adhesion layer on the passivation layer on the substrate containing the top metal interconnect;

[0010] Step 2: Etch the adhesion layer and the passivation layer to form a high aspect ratio via penetrating the adhesion layer and the passivation layer, the high aspect ratio via exposing the underlying top metal interconnect;

[0011] Step 3: Deposit a barrier layer on the sidewalls and bottom of the high aspect ratio through-hole and on the surface of the adhesion layer;

[0012] Step 4: Perform the first tungsten deposition to partially fill the high aspect ratio vias;

[0013] Step 5: Etch back the tungsten layer formed by the first tungsten deposition;

[0014] Step 6: Perform a second tungsten deposition to further fill the high aspect ratio vias;

[0015] Step 7: Perform planarization to remove excess tungsten and the barrier layer from the surface of the adhesion layer, so that tungsten fills the high aspect ratio via to form a tungsten plug. The tungsten plug is used to electrically connect the top metal interconnect for subsequent connection to the outside of the chip.

[0016] Preferably, in step one, the adhesion layer is a silicon dioxide layer.

[0017] Preferably, the thickness of the silicon dioxide layer is 400 to 600 angstroms.

[0018] Preferably, in step two, the passivation layer is a silicon nitride layer.

[0019] Preferably, in step three, the barrier layer comprises a titanium layer and / or a titanium nitride layer.

[0020] Preferably, in step seven, the planarization process is chemical mechanical polishing, which stops on the adhesion layer to ensure that there is no tungsten residue on the adhesion layer.

[0021] Preferably, the manufacturing method is applied to a 12-inch BCD wafer.

[0022] Preferably, the material of the top metal interconnect is aluminum.

[0023] As described above, the method for manufacturing the semiconductor device of the present invention has the following beneficial effects:

[0024] A reliable method for manufacturing high aspect ratio tungsten-filled vias connecting top-layer aluminum wires is provided. This method not only solves the technical challenges of filling high aspect ratio structures, improving fill quality and reliability, but also optimizes the physical and electrical properties of bumps by using a superior tungsten material to replace traditional methods, thereby increasing package density and reliability. Attached Figure Description

[0025] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.

[0026] Figure 2 The diagram shown is a schematic representation of the deposition adhesion layer of the present invention.

[0027] Figure 3 The diagram shown illustrates the formation of a high aspect ratio through-hole according to the present invention.

[0028] Figure 4 The diagram shown is a schematic diagram of the deposition barrier layer of the present invention;

[0029] Figure 5 The diagram shows the first tungsten deposition process according to the present invention.

[0030] Figure 6 This is a schematic diagram of the etch-back process of the tungsten layer formed by the first tungsten deposition according to the present invention.

[0031] Figure 7 The diagram shows a second tungsten deposition process according to the present invention.

[0032] Figure 8 The diagram shown illustrates the planarization process used in this invention to form a tungsten plug. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Please see Figure 1 This invention provides a method for manufacturing a semiconductor device, which involves forming tungsten-filled vias connecting a top-layer metal interconnect 101 in a BCD process, replacing the traditional method of directly forming bumps on the top-layer metal interconnect 101 (e.g., aluminum) for external chip connection. This alternative aims to leverage the superior physical and electrical properties of tungsten to overcome the challenges of forming bumps on aluminum in reducing bump spacing, improving reliability, and heat dissipation, especially in demanding applications such as automotive-grade applications.

[0035] Prior to the execution of the process described in this invention, a substrate typically already contains devices and multilayer interconnect structures. This invention focuses on the top metal interconnect 101 (typically aluminum or an aluminum alloy) and the connection structures thereon. At this stage, a protective layer 102 may be formed on the upper surface of the top metal interconnect 101. Furthermore, an interlayer dielectric (ILD), also known as an inter-metal dielectric (IMD), covers the top metal interconnect 101 and fills the spaces between the metal lines. This interlayer dielectric 103 serves to isolate adjacent metal lines and the layers above and below it. Subsequently, a passivation layer 104 is typically deposited on the interlayer dielectric 103 as final protection for the device.

[0036] In some embodiments, the protective layer 102 on the upper surface of the top aluminum interconnect can be an anti-reflective coating (ARC) or a hard mask residue layer used during aluminum wire etching, such as titanium nitride (TiN), titanium oxynitride (TixON), silicon oxynitride (SiON), or other thin layers of metal or dielectric material. This protective layer 102 may sometimes be an intentionally deposited thin layer, such as cobalt (Co) or titanium (Ti), to improve the electromigration properties of the aluminum wire or as a barrier layer 106 or contact improvement layer for subsequent processes. The selection of a suitable protective layer 102 material and its presence or absence depend on the specific process flow design.

[0037] In some embodiments, the interlayer dielectric layer 103 may include various dielectric materials. For example, it may be a single silicon dioxide layer or a stack of multiple dielectric materials. The interlayer dielectric layer 103 may be a stacked structure comprising a silicon dioxide layer formed by tetraethoxysilane (TEOS) chemical vapor deposition and a silicon rich oxide (SRO) layer. More broadly, the interlayer dielectric layer 103 may be selected from silicon dioxide formed by atmospheric pressure or plasma enhanced chemical vapor deposition (APCVD, PECVD) (such as USG, BPSG, PSG), silicon dioxide formed by high-density plasma chemical vapor deposition (HDP-CVD), spin-coated glass (SOG), silicon fluoride glass (FSG), or various low-k materials, such as carbon-doped silicon oxide (SiOC, etc.), organic polymers (such as polyimide, etc.), or porous dielectric materials. In some cases, the interlayer dielectric layer 103 may also contain a thin layer of silicon nitride (SiN) or silicon oxynitride (SiON) as an etch stop layer or barrier layer 106. The choice of which interlayer dielectric layer 103 material and structure to use is mainly based on a comprehensive consideration of capacitance, insulation strength, mechanical strength, thermal stability and process integration compatibility.

[0038] The process includes:

[0039] Step 1: Deposit an adhesion layer 105 on the passivation layer 104 on a substrate containing the top metal interconnect 101 (e.g., aluminum) to form an adhesion layer 105. Figure 2 The structure shown is such that the main purpose of this adhesion layer 105 is to improve the bonding force between the subsequently deposited barrier layer 106 and the underlying passivation layer 104.

[0040] In some embodiments, the passivation layer 104 is a silicon nitride layer. The silicon nitride layer is typically used as the final passivation layer 104 in the later stages of semiconductor device manufacturing. It can effectively protect the underlying devices and metal layers from environmental factors such as moisture and ions, and has good density and chemical stability.

[0041] In some embodiments, the adhesion layer 105 is a silicon dioxide layer. Using silicon dioxide (e.g., silicon dioxide formed by TEOS source chemical vapor deposition) as the adhesion layer 105 can provide a surface with good interfacial adhesion to the subsequently deposited barrier layer 106 (e.g., Ti / TiN).

[0042] In some embodiments, in step one, the thickness of the silicon dioxide layer is 400 to 600 angstroms. For example, a thickness of 500 angstroms is relatively thin while effectively achieving its adhesion-enhancing function, reducing the time and complexity required for subsequent etching of the layer and helping to control the overall thermal budget.

[0043] In some embodiments, in step one, depositing the adhesion layer 105 (e.g., a silicon dioxide layer) is to prevent the barrier layer 106 deposited in step three from directly contacting the passivation layer 104 (e.g., a silicon nitride layer). If the barrier layer 106 (e.g., Ti / TiN) subsequently used for tungsten filling is directly deposited on the silicon nitride passivation layer 104, the adhesion between the two may not be ideal, or adverse interface reactions may occur during subsequent high-temperature processing. There is a risk that the barrier layer 106, or even the entire tungsten plug 109 structure, may peel off or detach from the silicon nitride layer, which would seriously affect the device yield and long-term reliability. By depositing an additional silicon dioxide adhesion layer 105 on top of the passivation layer 104, a better and more stable interface can be provided for the barrier layer 106, thereby significantly improving the bonding strength and reliability of the entire filling structure.

[0044] Step 2: Etch the adhesion layer 105 and the passivation layer 104 to form a high aspect ratio via penetrating the adhesion layer 105 and the passivation layer 104. The high aspect ratio via exposes the underlying top metal interconnect 101, forming a structure like... Figure 3The structure is shown. This step is typically performed using photolithography (to define the via pattern) and dry etching (such as reactive ion etching, RIE). The etching process requires precise control to ensure the vertical profile and dimensional accuracy of the vias, and to completely remove the passivation layer 104 and adhesion layer 105 at the bottom of the vias, cleanly exposing the surface of the underlying top metal interconnect 101 to ensure good subsequent electrical contact. Simultaneously, the etching needs to have good selectivity for the top aluminum metal to avoid or minimize damage to the aluminum layer (sufficient loss).

[0045] In some embodiments, the aspect ratio of high aspect ratio vias is greater than or equal to 10:1. Such a high aspect ratio (i.e., the depth of the via is much greater than its opening width) is a typical feature of achieving high-density interconnects at current advanced process nodes, but it also poses a significant challenge to subsequent filling processes, as voids or seams can easily form within the vias during the filling process. The subsequent secondary filling strategy adopted in this invention is precisely to solve this technical problem. Forming such high aspect ratio vias and filling them with tungsten can effectively reduce the footprint of the interconnect structure, significantly reduce the critical dimension (CD), thereby achieving smaller bump pitch and improving chip integration.

[0046] Step 3: Deposit a barrier layer 106 on the sidewalls and bottom of the high aspect ratio through-hole and on the surface of the adhesion layer 105 to form a barrier layer 106. Figure 4 The structure is shown. The barrier layer 106 plays a crucial role, as it needs to form an effective physical and chemical barrier between the tungsten and the surrounding materials (aluminum at the bottom, dielectric passivation layer 104 / adhesion layer 105 on the sidewalls). The adhesion layer 105 provides a good substrate for the deposition of the barrier layer 106.

[0047] In some embodiments, in step three, the barrier layer 106 includes a titanium (Ti) layer and / or a titanium nitride (TiN) layer. A stacked structure of Ti and TiN is typically used (e.g., a thin Ti layer is deposited first, followed by a TiN layer). The bottom Ti layer can form a good low-resistance ohmic contact with aluminum and can effectively adhere to the surfaces of dielectric layers such as silicon dioxide (adhesion layer 105) and silicon nitride (passivation layer 104). The Ti layer can also reduce oxides that may be present on the aluminum surface. The TiN layer above it has excellent barrier properties, effectively preventing tungsten atoms from interdiffusion or reaction with the underlying aluminum during subsequent high-temperature tungsten deposition (e.g., forming a high-resistance aluminum-tungsten alloy), and also preventing tungsten deposition byproducts (such as fluorine) from eroding the dielectric or aluminum layers, thereby ensuring the electrical performance stability and long-term reliability of the tungsten plug 109 structure.

[0048] Step 4: Perform the first tungsten deposition to partially fill the high aspect ratio vias, forming a structure like... Figure 5The structure is shown. Due to the high aspect ratio of the vias and the limited single-pass deposition capability of existing 12-inch production line tungsten chemical vapor deposition (W-CVD) equipment (e.g., a single-pass deposition thickness may be around 6000 angstroms), achieving defect-free filling in a single pass is very difficult. Therefore, a first tungsten deposition is used to partially fill the vias, for example, filling them to a certain depth or forming a conformal tungsten layer of a certain thickness covering the inner wall and bottom of the via.

[0049] Step 5: Etch back the tungsten layer 107 formed by the first tungsten deposition to form a layer as shown in the figure. Figure 6 The structure shown is as follows. After the first tungsten deposition, especially at the opening of a high aspect ratio hole, the tungsten deposition rate may be faster, which can easily lead to overhang or narrowing or even closure of the hole opening. This morphology can severely hinder the entry of reactive gas into the depth of the hole during subsequent tungsten deposition, resulting in the formation of a cavity in the center of the hole during the second deposition.

[0050] In some embodiments, step five involves etch-back to improve the filling effect of the second tungsten deposition. By performing an etch-back step (e.g., using anisotropic or isotropic plasma etching), a portion of the first-deposited tungsten can be selectively removed, particularly removing or reducing buildup and overhangs at the via opening, essentially "reopening" or "refining" the via entrance morphology. This creates more favorable conditions for the subsequent second tungsten deposition, making it easier for the tungsten precursor to enter the bottom and center of the via, thereby significantly improving the final filling density and greatly reducing the risk of central void formation. The degree of etch-back needs to be precisely controlled, aiming to improve the entrance morphology while ensuring that a tungsten layer remains inside the via (without being etched open) to serve as a good starting layer for the second deposition.

[0051] Step Six: Perform a second tungsten deposition, using the tungsten layer 108 formed in the first deposition, to further fill the high aspect ratio vias, forming a layer like... Figure 7 The structure is shown. After morphology reshaping, a second tungsten deposition is performed. This deposition aims to completely fill the partially filled and re-etched vias. Combining the first deposition and re-etching steps, the secondary filling strategy significantly improves the success rate of achieving void-free and gapless filling in high aspect ratio vias.

[0052] Step 7: Perform planarization to remove the adhesion layer 105 and the excess tungsten and barrier layer 106 covering it, so that tungsten fills the high aspect ratio via to form a tungsten plug 109, and the surface of the passivation layer 104 is exposed in the area outside the via, forming a... Figure 8In the structure shown, the tungsten plug 109 is used to electrically connect the top metal interconnect 101 for subsequent connection to the outside of the chip. After two tungsten depositions, the tungsten not only fills the vias but also covers the adhesion layer 105 across the entire wafer surface (below the passivation layer 104). A planarization process is needed to remove this excess tungsten, the underlying barrier layer 106, and the adhesion layer 105 itself, leaving only the tungsten within the vias to form a separate tungsten plug 109, whose top is flush with the surface of the surrounding exposed passivation layer 104.

[0053] In some embodiments, in step seven, the planarization process is chemical mechanical polishing (CMP). CMP is currently the standard process for achieving global planarization in semiconductor manufacturing. Through the synergistic effect of chemical etching and mechanical polishing, tungsten, barrier layer 106 material (Ti / TiN), and adhesion layer 105 (such as TEOS silicon dioxide) on the wafer surface can be removed efficiently and uniformly to obtain a highly flat surface.

[0054] In some embodiments, in step seven, chemical mechanical polishing (CMP) removes the adhesion layer 105 and stops at the passivation layer 104 to ensure that no tungsten, barrier layer 106, or adhesion layer 105 remains on the passivation layer 104. Precise CMP endpoint control is crucial for process success. This requires the use of slurries and process parameters that selectively remove tungsten, barrier layer 106, and adhesion layer 105, and have a high selectivity (i.e., a removal rate to the passivation layer 104 is much lower than the removal rate to the overlying material) upon reaching the passivation layer 104 (e.g., a silicon nitride layer). The endpoint detection system (e.g., monitoring changes in friction, optical signals, or eddy currents during the polishing process) is used to ensure that polishing is precisely stopped when the tungsten, barrier layer 106, and adhesion layer 105 are completely removed. This avoids excessive polishing that could lead to excessive loss of the passivation layer 104 or denting of the tungsten plug 109. It also ensures that the surface of the finally exposed passivation layer 104 is clean and free of metal or adhesion layer 105 residue, preventing potential leakage or short circuit risks and providing a suitable surface for subsequent possible process steps (such as operations performed directly on the passivation layer 104).

[0055] This process is particularly suitable for the manufacture of 12-inch BCD wafers. Processing and filling high aspect ratio structures on large 12-inch wafers places higher demands on process uniformity, stability, and control precision. The process flow provided by this invention, which includes secondary tungsten deposition and intermediate etch-back steps, offers an effective technical approach for achieving reliable high aspect ratio tungsten filling on 12-inch BCD products.

[0056] In some embodiments, the BCD process is a Bipolar-CMOS-DMOS (Bipolar-Complementary Metal-Oxide-Semiconductor-Double-Diffused Metal-Oxide-Semiconductor) process. BCD technology integrates bipolar transistors for processing analog signals, CMOS logic circuits for processing digital signals, and DMOS devices for processing power, and is widely used in power management integrated circuits (PMICs), automotive electronics, industrial control, and other fields. These applications often have high requirements for the power handling capability, operating temperature range, and long-term reliability of the devices. This invention uses tungsten, which has excellent electrical and thermal conductivity and good high-temperature stability, to fill the interconnect vias, replacing the traditional aluminum / copper bump structure, thus better meeting the needs of BCD devices in these high-performance, high-reliability application scenarios.

[0057] In summary, this invention provides a method for reliably manufacturing high aspect ratio tungsten-filled vias connecting top-layer aluminum traces in a 12-inch BCD process. This method involves introducing an adhesion layer 105 (to improve adhesion between the barrier layer 106 and the passivation layer 104), employing the barrier layer 106, and a specially designed secondary tungsten deposition combined with an etch-back filling strategy. Finally, it includes the removal of the adhesion layer 105 and planarization treatment on the passivation layer 104. This method not only solves the technical challenges of filling high aspect ratio structures and improves filling quality and reliability, but also improves device integration, electrical performance, heat dissipation, and overall reliability by using a higher-performance tungsten material instead of traditional methods. It is directly compatible with advanced flip-chip packaging and other subsequent processes, demonstrating promising application prospects.

[0058] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising forming tungsten-filled vias connecting top-layer metal interconnects in a BCD process, instead of directly forming bumps on the top-layer metal interconnects for connection to the outside of the chip, characterized in that, At least including: Step 1: Deposit an adhesion layer on the passivation layer on the substrate containing the top metal interconnect; Step 2: Etch the adhesion layer and the passivation layer to form a high aspect ratio via penetrating the adhesion layer and the passivation layer, the high aspect ratio via exposing the underlying top metal interconnect; Step 3: Deposit a barrier layer on the sidewalls and bottom of the high aspect ratio through-hole and on the surface of the adhesion layer; Step 4: Perform the first tungsten deposition to partially fill the high aspect ratio vias; Step 5: Etch back the tungsten layer formed by the first tungsten deposition; Step 6: Perform a second tungsten deposition to further fill the high aspect ratio vias; Step 7: Perform planarization to remove the adhesion layer and the excess tungsten and barrier layer covering it, so that tungsten fills the high aspect ratio via to form a tungsten plug, and the surface of the passivation layer is exposed in the area outside the via. The tungsten plug is used to electrically connect the top metal interconnect for subsequent connection to the outside of the chip.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step one, the adhesion layer is a silicon dioxide layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that: The thickness of the silicon dioxide layer is 400 to 600 angstroms.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, the passivation layer is a silicon nitride layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, the aspect ratio of the high aspect ratio through hole is greater than or equal to 10:

1.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step three, the barrier layer includes a titanium layer and / or a titanium nitride layer.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step five, the back etching is performed to improve the filling effect of the second tungsten deposition.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step seven, the planarization process is chemical mechanical polishing, which is stopped on the passivation layer to ensure that there is no tungsten residue on the passivation layer.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The manufacturing method is applied to 12-inch BCD wafers.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The material of the top metal interconnect is aluminum.

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