Ultrahigh-density three-dimensional stacked packaging structure

Abstract

The invention provides an ultrahigh-density three-dimensional stacked packaging structure. The ultrahigh-density three-dimensional stacked packaging structure comprises a substrate, a stacked structure and a stacked chip. According to the invention, the bottom substrate is arranged, and the stacking structure composed of a plurality of stacked silicon wafers is connected above the substrate. And processing a mounting cavity for mounting a chip between two adjacent stacked silicon wafers on the same layer by adopting a high-precision cavity etching technology. According to the invention, the electroplated layers are arranged on the two side surfaces of each stacked silicon wafer, so that the metal shielding of the upper and lower sides of the mounting cavities is realized, and the plurality of first metal through holes are arranged between the two adjacent mounting cavities in an array manner. And the plurality of first metal through holes form a shielding wall, so that the phenomenon of mutual interference of chip signals in two adjacent mounting cavities can be avoided. And the shielding effect between the chips is improved, so that the whole stacked packaging structure is compact, the electromagnetic isolation degree is high, a complex circuit architecture can be used, and the application range of stacked packaging is widened.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip packaging, and particularly relates to a super-high-density three-dimensional stacked packaging structure. BACKGROUND

[0002] With the rapid development of semiconductor materials and processing manufacturing processes, the maturity of millimeter wave monolithic integrated circuit technology is also higher and higher, and the application of millimeter wave devices is also more and more extensive. In order to realize high integration characteristics, a new generation of electronic communication systems require that the spacing between radio frequency transceiver elements is smaller and smaller, and thus the size of the radio frequency transceiver front end is smaller and smaller, that is, the integration is higher and higher.

[0003] The existing ceramic packaging stacked structure or glass packaging stacked structure is difficult to independently divide the cavities of the chips in the same layer, the electromagnetic isolation degree between the chips in the same layer is poor, and the adjacent chips are prone to mutual interference, which is difficult to be applied to complex circuit architectures, thereby limiting the application range of the chips. SUMMARY

[0004] The embodiment of the application provides a super-high-density three-dimensional stacked packaging structure, which aims to solve the problems of poor electromagnetic isolation degree of the chips in the same layer in the chip packaging stacked structure in the prior art and small application range.

[0005] To achieve the above-mentioned purpose, the technical scheme adopted by the application is as follows: a super-high-density three-dimensional stacked packaging structure is provided, comprising: a substrate; a stacked structure installed on the substrate, the stacked structure comprising: a plurality of stacked silicon chips, the plurality of stacked silicon chips being connected in sequence and stacked, and the upper and lower sides of each stacked silicon chip being provided with a metal layer, a plurality of installation cavities for installing chips being formed between two adjacent stacked silicon chips, and a first metal through hole being arranged in an array between two adjacent installation cavities.

[0006] In a possible implementation manner, a shielding silicon chip is further arranged between two adjacent stacked silicon chips forming the installation cavity, and the first metal through hole penetrates the shielding silicon chip.

[0007] In a possible implementation manner, an installation groove for installing a chip is concavely arranged on each of the two adjacent stacked silicon chips forming the installation cavity.

[0008] In a possible implementation manner, the chips installed in the upper and lower installation grooves in the same installation cavity are respectively a control chip and a radio frequency chip.

[0009] In a possible implementation manner, the upper and lower sides of the shielding silicon chip are provided with metal layers.

[0010] In a possible implementation, two adjacent silicon wafers or between the silicon wafer and the shielding silicon wafer are used to install a passive structure.

[0011] In a possible implementation, a plurality of installation sites are arranged inside the stacked structure, and the plurality of installation sites are arranged in sequence in the vertical direction, and the outer side of the plurality of installation sites is provided with an array of second metal vias.

[0012] In a possible implementation, a solder ball is installed between the substrate and the lowermost silicon wafer of the stacked structure.

[0013] In a possible implementation, a plurality of stacked structures are arranged on the substrate, and the plurality of stacked structures are sequentially stacked and connected together.

[0014] In a possible implementation, a third metal via is arranged on the stacked structure, and the third metal via penetrates all the stacked silicon wafers and the shielding silicon wafer.

[0015] Compared with the prior art, the scheme shown in the embodiment of the application has the bottom substrate, and the stacked structure composed of a plurality of stacked silicon wafers is connected above the substrate. The installation cavity for installing the chip is processed between the two adjacent stacked silicon wafers in the same layer by using high-precision cavity etching technology, so that the number of stacked chips is increased without increasing the substrate. In the application, the electroplated layer is arranged on both sides of each stacked silicon wafer, the metal shielding of the upper and lower sides of the installation cavity is realized, and a plurality of first metal vias are arranged in an array between the adjacent two installation cavities. The plurality of first metal vias form a shielding wall, which can avoid the mutual interference of the chip signals in the adjacent two installation cavities. The shielding effect between the chips is improved, the overall stacked packaging structure is compact, the electromagnetic isolation degree is high, the complex circuit architecture can be used, and the application range of the stacked packaging is expanded. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The structure schematic diagram of the super-high-density three-dimensional stacked packaging structure provided by the embodiment of the application is shown. Figure 2 The structure schematic diagram of the super-high-density three-dimensional stacked packaging structure provided by another embodiment of the application is shown.

[0017] Figure 3 The installation structure schematic diagram of another passive structure provided by the embodiment of the application is shown.

[0018] Explanation of reference signs: 1, substrate; 2, stacked structure; 21, stacked silicon chip; 22, shielding silicon chip; 3, control chip; 4, radio frequency chip; 5, first metal through hole; 6, passive structure; 7, solder ball; 8, second metal through hole; 9, third metal through hole. DETAILED DESCRIPTION

[0019] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and not to limit the present application.

[0020] Please refer to Figures 1 to 3 , now the super high density three-dimensional stacked packaging structure provided by the present application will be described. The super high density three-dimensional stacked packaging structure comprises a substrate 1, a stacked structure 2 and a stacked silicon chip 21. The stacked structure 2 is mounted on the substrate 1, and the stacked structure 2 comprises a plurality of stacked silicon chips 21, the plurality of stacked silicon chips 21 are connected in sequence, and the upper and lower sides of the stacked silicon chip 21 are provided with a metal layer, a plurality of mounting cavities for mounting chips are formed between adjacent two stacked silicon chips 21, and a first metal through hole 5 is arranged in an array between adjacent two mounting cavities.

[0021] The super high density three-dimensional stacked packaging structure provided by the present embodiment, compared with the prior art, by providing a bottom substrate 1, a stacked structure 2 composed of a plurality of stacked silicon chips 21 is connected above the substrate 1. A mounting cavity for mounting a chip is processed between two adjacent stacked silicon chips 21 in the same layer by using high-precision cavity etching technology, thereby increasing the number of stacked layers of chips without increasing the substrate 1. In the present application, an electroplated layer is provided on both sides of each stacked silicon chip 21, which realizes the metal shielding of the upper and lower sides of the mounting cavity, and a plurality of first metal through holes 5 are arranged in an array between adjacent two mounting cavities. The plurality of first metal through holes 5 form a shielding wall, which can avoid the mutual interference of the signals of the chips inside the adjacent two mounting cavities. The shielding effect between the chips is improved, the overall stacked packaging structure is compact, the electromagnetic isolation degree is high, complex circuit architecture can be used, and the application range of the stacked packaging is expanded.

[0022] Specifically, in the present embodiment, the plurality of first metal through holes 5 are arranged in an array to form a shielding wall, and the shielding wall is located between two mounting cavities. Thus, the signal shielding inside the adjacent two mounting cavities in the same layer direction is realized. Meanwhile, a metal layer is provided on the upper and lower sides of each layer of stacked silicon chip 21, which can shield the signals in the stacking direction, and reduce the signal interference of the chips inside the independent mounting cavity by the chips inside other mounting cavities.

[0023] Preferably, in this embodiment, the spacing between two adjacent first metal vias 5 is less than 1 / 10 of the signal wavelength, thereby improving the signal shielding effect of the first metal vias 5.

[0024] In some embodiments, the stacking structure 2 described above may employ, as follows: Figure 1 , Figure 2 The structure shown. See also... Figure 1 , Figure 2 A shielding silicon wafer 22 is also provided between two adjacent stacked silicon wafers 21 forming the mounting cavity, and a first metal through-hole 5 penetrates the shielding silicon wafer 22. The shielding silicon wafer 22 connects the two stacked silicon wafers 21 forming the mounting cavity. The design of the shielding silicon wafer 22 increases the height of the mounting cavity, providing sufficient mounting space for the chips located on the upper and lower sides of the cavity. Simultaneously, the first metal through-hole 5 penetrating the shielding silicon wafer 22 further enhances the shielding effect between two adjacent mounting cavities.

[0025] Specifically, in this embodiment, the chip is connected to the metal layer of the stacked chips through pins to realize signal transmission. The shielding silicon wafer 22 can support the two stacked chips. At the side wall of the mounting cavity, the cross-sectional size of the shielding silicon wafer 22 is smaller than the cross-sectional size of the stacked silicon wafer 21, thereby providing mounting space for the pins to connect to the stacked silicon wafer 21, which facilitates the installation of the chip.

[0026] In some embodiments, the stacked silicon wafers 21 described above can be employed as follows: Figure 1 , Figure 2 The structure shown. See also... Figure 1 , Figure 2 The two adjacent stacked silicon wafers 21 forming the mounting cavity each have recessed mounting grooves for mounting chips. These grooves are fabricated on the sides of the stacked chips using high-precision cavity etching technology. The mounting grooves on the two adjacent stacked silicon wafers 21 are positioned opposite each other to form the mounting cavity. Chips are mounted inside both mounting grooves, making full use of the mounting space within the cavity.

[0027] Specifically, in this embodiment, the chip is attached to the bottom of the mounting slot and connects to the metal layer on the side of the stacked chips through pins to achieve signal transmission. This makes good use of the internal space of the mounting slot and allows multiple functional chips to be installed in a single-layer package.

[0028] In some embodiments, the chip described above may employ, for example... Figure 1 , Figure 2 The structure shown. See also... Figure 1 , Figure 2The chips installed in the upper and lower mounting slots within the same mounting cavity are a control chip 3 and an RF chip 4, respectively. The mounting cavity consists of mounting slots arranged opposite each other on two stacked silicon wafers 21. The chips installed inside the mounting cavity include the control chip 3 and the RF chip 4. By installing individual RF chips 4 and control chips 3 in separate mounting cavities, the mutual interference between control chip 3 and RF chip 4 is low. By installing individual RF chips 4 and control chips 3 in the same mounting cavity, the mutual interference between chips within the same mounting cavity can be reduced.

[0029] Specifically, in this embodiment, multiple mounting cavities are provided on the same layer stacked silicon wafer 21 for classifying and mounting chips. On the one hand, multiple groups of chips can be mounted on the same layer, and on the other hand, signal interference between chips can be avoided by the shielding of the surface metal layer of the stacked silicon wafer 21 and the first metal via 5, thus meeting the usage requirements of complex circuit architecture.

[0030] In some embodiments, the shielding silicon wafer 22 may be adopted as follows: Figure 1 The structure shown. See also Figure 1 Metal layers are provided on both the top and bottom sides of the shielding silicon wafer 22. The metal layers on both sides of the shielding silicon wafer 22 further enhance the shielding effect against interference signals. Simultaneously, the first metal via 5 penetrates the shielding silicon wafer 22, allowing signal transmission through it. This improves the flexibility of chip placement. Furthermore, the metal layers on both sides of the shielding silicon wafer 22 enable interconnection between multi-layer stacked silicon wafers 21. The first metal via 5 facilitates signal transmission between the stacked silicon wafers 21 and the shielding silicon wafer 22, simplifying the subsequent layout of chips and passive structures 6.

[0031] In some embodiments, the stacked silicon wafers 21 described above can be employed as follows: Figure 1 , Figure 3 The structure shown. See also... Figure 1 , Figure 3 The passive structure 6 is mounted between two adjacent stacked silicon wafers 21 or between a stacked silicon wafer 21 and a shielding silicon wafer 22. This achieves three-dimensional stacking of the functional chip and the passive structure 6 within a single-layer package.

[0032] Specifically, in this embodiment, the passive structure 6 in this application includes resistors, capacitors, inductors, filters, etc. Conventional single-layer packages can only stack a single-layer chip with the passive structure 6, while the stacking structure 2 in this application allows for free selection of the mounting position of the passive structure 6, realizing three-dimensional stacking of the chip and the passive structure, which greatly improves the integration of the package.

[0033] In some embodiments, the passive structure 6 described above can be adopted as follows: Figure 1 , Figure 3 The structure shown. See also... Figure 1 , Figure 3 The stacked structure 2 has multiple mounting positions arranged vertically at intervals. An array of second metal vias 8 are located on the outer sides of each mounting position. These mounting positions are used to mount multiple passive structures 6, either different or identical. The mounting positions are arranged sequentially along the stacking direction of the stacked silicon wafers 21, allowing multiple passive structures 6 to be mounted along this direction. The second metal vias 8 on the outer sides of the mounting positions create a signal shielding wall, preventing interference signals generated by the passive structures from passing through. Furthermore, the arrangement of the multiple passive structures 6 along the stacking direction, using two rows of metal vias, effectively shields against interference signals.

[0034] Specifically, in this embodiment, the second metal through-hole 8 penetrates between the two stacked silicon wafers 21 that form the mounting position or between the stacked silicon wafer 21 and the shielding silicon wafer 22, thereby achieving shielding of the interference signal of the passive structure 6. At the same time, the second metal through-hole 8 can be combined with the first metal through-hole 5 or the third metal through-hole 9 to form a shielding wall for shielding the interference signal of the passive structure 6, so as to reduce the number of processing steps for the second metal through-hole 8.

[0035] Specifically, in this embodiment, the passive structure 6 is installed below the mounting cavity, and the interference signal is shielded by stacking the metal layer on the surface of the silicon wafer 21. Further shielding is achieved through the second metal via 8, thereby improving the shielding effect against interference signals.

[0036] Specifically, in this embodiment, along the arrangement direction of the multiple mounting cavities, a first metal through hole 5 is provided on both sides of the mounting cavity, and a second metal through hole 8 is provided on both sides of the mounting position.

[0037] In some embodiments, the substrate 1 may be as follows: Figure 1 , Figure 2 The structure shown. See also... Figure 1 , Figure 2 Solder balls 7 are installed between substrate 1 and the bottommost stacked silicon wafer 21 of stacked structure 2. The bottommost stacked chip of stacked structure 2 is connected to substrate 1 through solder balls 7 to realize signal transmission. Three-dimensional stacking of chips is realized on the same substrate 1.

[0038] In some embodiments, the stacking structure 2 described above may employ, as follows: Figure 1 , Figure 2 The structure shown. See also... Figure 1 , Figure 2The substrate 1 has multiple stacked structures 2, which are sequentially stacked and connected together. There can be multiple stacked structures 2, which are sequentially stacked together along the stacking direction. Additional packages or functions can be expanded by continuously stacking upwards on top of the stacked structures 2.

[0039] Specifically, this application can be widely applied in the fields of high-performance CPU design, high-performance RAM design, and high-performance RF front-end design. It allows different functional chips to be placed in one cavity, reducing transmission distance and providing advantages such as faster signal transmission and lower loss. At the same time, the original hard connections between different package units can be replaced with the intermediate solder ball 7, achieving a low-cost, lightweight, and high-speed reliable connection.

[0040] In some embodiments, the stacking structure 2 described above may employ, as follows: Figure 1 , Figure 2 The structure shown. See also... Figure 1 , Figure 2 A third metal via 9 is provided on the stacked structure 2, penetrating all the stacked silicon wafers 21 and the shielding silicon wafer 22. This via 9 enables signal transmission throughout the stacked structure 2, facilitating subsequent layout of chips and the passive structure 6. Furthermore, when chips are further stacked on top of the passive structure, signal transmission between the stacked chips can be achieved. This improves the ease of future package expansion.

[0041] Specifically, in this embodiment, there are multiple third metal vias 9. These multiple third metal vias 9 are the same as the first metal vias 5 and the second metal vias 8, and are arranged in an array to form a shielding wall for shielding interference signals. Meanwhile, the mounting cavity for mounting the passive structure 6 or for mounting the chip is located between the first metal vias 5 and the third metal vias 9.

[0042] Specifically, this application also includes a packaging stacking process, comprising the following steps: Step 1: Multiple stacked silicon wafers 21 and shielding silicon wafers 22 are etched and sputtered to form structures such as metal patterns, vias, and cavities. The linewidth / spacing of the metal patterns can reach 30μm / 30μm, and the diameter of the vias can reach 30μm~60μm. The designed metal patterns can form a passive structure 6. Multiple stacked silicon wafers 21 and shielding silicon wafers 22 are reliably stacked using thermo-press bonding or eutectic bonding processes. Step 2: The control chip 3 can be fixed in the bottom mounting slot by adhesive bonding, and the RF chip 4 can be fixed in the top mounting slot by adhesive bonding. Both the control chip 3 and the RF chip 4 can be interconnected with the silicon wafer by bonding wire. Step 3: Reliably stack the structure equipped with the control chip 3 and the structure equipped with the radio frequency chip 4 through thermo-press bonding or eutectic bonding processes; Step 4: Reliably stack and interconnect the two single-layer packages using the intermediate solder ball 7; Step 5: Reliably interconnect the stacked structure with the substrate 1 through the bottom solder balls 7.

[0043] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An ultra-high density three-dimensional stacked packaging structure, characterized in that, include: base(1); A stacked structure (2) is mounted on the substrate (1), the stacked structure (2) comprising: Multiple stacked silicon wafers (21) are stacked and connected in sequence, and metal layers are provided on both the upper and lower sides of each stacked silicon wafer (21). Multiple mounting cavities for mounting chips are formed between two adjacent stacked silicon wafers (21), and first metal through holes (5) are arranged in an array between two adjacent mounting cavities.

2. The ultra-high density three-dimensional stacked packaging structure as described in claim 1, characterized in that, A shielding silicon wafer (22) is also provided between the two adjacent stacked silicon wafers (21) that make up the mounting cavity, and the first metal through hole (5) is provided through the shielding silicon wafer (22).

3. The ultra-high density three-dimensional stacked packaging structure as described in claim 1, characterized in that, The two adjacent stacked silicon wafers (21) that make up the mounting cavity are each provided with mounting grooves for mounting chips.

4. The ultra-high density three-dimensional stacked packaging structure as described in claim 3, characterized in that, The chips installed inside the upper and lower mounting slots within the same mounting cavity are a control chip (3) and a radio frequency chip (4), respectively.

5. The ultra-high density three-dimensional stacked packaging structure as described in claim 2, characterized in that, The shielding silicon wafer (22) has metal layers on both the top and bottom sides.

6. The ultra-high density three-dimensional stacked packaging structure as described in claim 5, characterized in that, The two adjacent stacked silicon wafers (21) or the stacked silicon wafers (21) and the shielding silicon wafer (22) form a mounting position for mounting the passive structure (6).

7. The ultra-high density three-dimensional stacked packaging structure as described in claim 6, characterized in that, The stacked structure (2) has multiple mounting positions inside, and the multiple mounting positions are arranged sequentially at intervals along the vertical direction. The outer side of the multiple mounting positions is provided with an array of second metal through holes (8).

8. The ultra-high density three-dimensional stacked packaging structure as described in claim 2, characterized in that, Solder balls (7) are installed between the substrate (1) and the stacked silicon wafer (21) at the bottom of the stacked structure (2).

9. The ultra-high density three-dimensional stacked packaging structure as described in claim 8, characterized in that, The substrate (1) is provided with a plurality of stacked structures (2), and the plurality of stacked structures (2) are stacked and connected together in sequence.

10. The ultra-high density three-dimensional stacked packaging structure as described in claim 9, characterized in that, The stacked structure (2) is provided with a third metal via (9), which penetrates all the stacked silicon wafers (21) and the shielding silicon wafer (22).

Images