High-temperature-resistant semiconductor laser chip and preparation method thereof

Abstract

The invention provides a high-temperature-resistant semiconductor laser chip and a preparation method thereof. The high-temperature-resistant semiconductor laser chip sequentially comprises a substrate, an N limiting layer, a lower N waveguide layer, a carrier collection layer I, an upper N waveguide layer, a quantum well layer, a lower P waveguide layer, a carrier collection layer II, an upper P waveguide layer, a P limiting layer and an ohmic contact layer from bottom to top. The carrier collection layers are arranged in the waveguide layer on the two sides of the quantum well layer respectively, free carriers escaping from the quantum well at high temperature are effectively consumed, the internal loss coefficient of the waveguide layer is remarkably reduced, the net gain coefficient of the chip at high temperature is improved, and then the high-temperature performance of the chip is improved; the carrier collection layer provided by the invention can migrate a light field to the direction of the quantum well active region at a high temperature, so that the light limiting factor of the quantum well active region at the high temperature is improved, the gain of a chip at the high temperature is further improved, and finally, the high-temperature performance of the chip is further improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor laser chip preparation, and particularly relates to a high-temperature-resistant semiconductor laser chip and a preparation method thereof. BACKGROUND

[0002] Semiconductor lasers can directly realize photoelectric conversion, are fully solid, have high efficiency, and are widely used in industrial processing, medical and cosmetic treatment, military scientific research, communication, sensing, and the like.

[0003] An important application field of semiconductor laser chips is as a pump source of fiber lasers or solid-state lasers. In this field, the actual environmental temperature of semiconductor laser chips is quite different due to the influence of the use environment temperature and packaging, resulting in a large difference in the temperature of the light-emitting active region of semiconductor laser chips, which is from 25 DEG C to 100 DEG C, and even exceeds 100 DEG C in some special applications. The semiconductor laser chip has the remarkable feature that the performance parameters such as output power, efficiency and beam quality deteriorate sharply with the increase of temperature, which eventually leads to the deterioration of the pump efficiency, service life and reliability of the semiconductor laser.

[0004] The fundamental reason for the performance deterioration of semiconductor laser chips caused by high temperature is that the net gain becomes small due to the increase of loss and the decrease of gain at high temperature. The increase of loss is caused by the escape of free carriers in the quantum well active region to the waveguide layer at high temperature, and the decrease of gain is caused by the broadening of the gain spectrum at high temperature, which makes the product of the light confinement factor and the gain coefficient (gain = light confinement factor x gain coefficient) small. There are also patents related to improving the gain and temperature stability of semiconductor lasers. For example, Chinese Patent Document CN116826524A relates to a laser epitaxial wafer with a multi-dimensional composite light-emitting region structure, which comprises, from bottom to top: a buffer layer, an Al x1 Ga 1-x1 As N confinement layer, an Al x2 Ga 1-x2 As lower waveguide layer, a GaAs lower barrier layer, an In x3 Ga 1-x3 As lower quantum well, an In x4 Ga 1-x4 As quantum dot light-emitting layer, an In x5 Ga 1-x5 As upper quantum well, a GaAs upper barrier layer, an Al y1 Ga 1-y1 As upper waveguide layer, an Al y2 Ga 1-y2As P restriction layer, ohmic contact layer. Wherein: 0.2≤x1≤0.5, 0.1≤x2≤0.3, 0.15≤x3≤0.2, 0.2≤x4≤0.3, 0.15≤x5≤0.2, 0.1≤y1≤0.3, 0.6≤y2≤0.9. But the laser epitaxial wafer adopts quantum dot light emitting + quantum well mode, which causes quantum well to become a radiation recombination center, and the laser epitaxial wafer cannot regulate the optical gain at high temperature, but only collects carriers through quantum well.

[0005] Therefore, it is urgent to study a method for improving the high-temperature performance of a semiconductor laser chip by reducing carrier overflow at high temperature and improving the gain at high temperature. SUMMARY

[0006] In view of the deficiencies of the prior art, especially in view of the deficiencies of the prior art semiconductor laser chip in that the performance at high temperature is deteriorated due to increased loss and decreased gain at high temperature, the application provides a high-temperature-resistant semiconductor laser chip and a preparation method thereof. The application sets a carrier collection layer in the waveguide layer on both sides of the quantum well layer, which can consume free carriers leaking into the waveguide layer, because the free carriers are the main source of optical loss in the waveguide layer, and the carrier collection layer can regulate the optical confinement factor. Due to the overflow of carriers at high temperature, the carrier density of the carrier collection layer increases, and the increase in the carrier density further increases the effective refractive index of the layer, which causes the light field to migrate to the layer, and finally increases the optical confinement factor of the quantum well, which compensates for the decrease in the gain of the semiconductor laser chip at high temperature, thereby greatly improving the high-temperature performance of the semiconductor laser.

[0007] The technical scheme of the application is as follows:

[0008] A high-temperature-resistant semiconductor laser chip comprises, from bottom to top, a substrate, an N restriction layer, a lower N waveguide layer, a carrier collection layer I, an upper N waveguide layer, a quantum well layer, a lower P waveguide layer, a carrier collection layer II, an upper P waveguide layer, a P restriction layer and an ohmic contact layer.

[0009] According to the application, the band gap of the carrier collection layer I is greater than that of the quantum well layer and less than that of the N waveguide layer, the N waveguide layer comprises a lower N waveguide layer and an upper N waveguide layer, the band gaps of the lower N waveguide layer and the upper N waveguide layer are the same, and the band gap difference between the carrier collection layer I and the N waveguide layer is 40-80meV.

[0010] According to the application, preferably, the band gap of the carrier collection layer II is greater than that of the quantum well layer and less than that of the P waveguide layer; the P waveguide layer comprises a lower P waveguide layer and an upper P waveguide layer, the band gap of the lower P waveguide layer and the upper P waveguide layer is the same; the difference between the band gap of the carrier collection layer II and the P waveguide layer is 40-80 meV.

[0011] According to the application, preferably, the difference between the band gap of the carrier collection layer I or the carrier collection layer II and the quantum well layer is 20-60 meV.

[0012] According to the application, preferably, the distance between the carrier collection layer I or the carrier collection layer II and the quantum well layer is 30-100 nm.

[0013] According to the application, preferably, the thickness of the carrier collection layer I or the carrier collection layer II is 10-50 nm.

[0014] According to the application, preferably, the high-temperature-resistant semiconductor laser chip comprises one or more of the following conditions:

[0015] (i) the substrate is a GaAs substrate;

[0016] (ii) the N confinement layer is an Al x1 Ga 1-x1 As N confinement layer, 0.2≤x1≤0.5; the thickness is 500-800 nm;

[0017] (iii) the lower N waveguide layer is an Al x2 Ga 1-x2 As lower N waveguide layer, 0.4≤x2≤0.6; the thickness is 500-600 nm;

[0018] (iv) the carrier collection layer I is an Al x3 Ga 1-x3 As carrier collection layer I, 0.15≤x3≤0.3; the thickness is 10-50 nm;

[0019] (v) the upper N waveguide layer is an Al x2 Ga 1-x2 As upper N waveguide layer, 0.4≤x2≤0.6; the thickness is 30-100 nm;

[0020] (vi) the quantum well layer is an In x4 Ga 1-x4 As quantum well layer, 0.05≤x4≤0.1; the thickness is 5-10 nm;

[0021] (vii) the lower P waveguide layer is an Al x5 Ga 1-x5As lower P waveguide layer, 0.4≤x5≤0.6; thickness 30-100 nm;

[0022] (viii) the carrier collection layer II is Al x6 Ga 1-x6 As carrier collection layer II, 0.15≤x6≤0.3; thickness 10-50 nm;

[0023] (ix) the upper P waveguide layer is Al x5 Ga 1-x5 As upper P waveguide layer, 0.4≤x5≤0.6; thickness 500-600 nm;

[0024] (x) the P confinement layer is Al x7 Ga 1-x7 As P confinement layer, 0.7≤x7≤0.9; thickness 500-700 nm;

[0025] (xi) the ohmic contact layer is a GaAs ohmic contact layer; thickness 500-1000 nm.

[0026] According to the application, preferably, the material of the Al x1 Ga 1-x1 As N confinement layer is Al x1 Ga 1-x1 As doped with Si, the doping concentration of Si atoms being 5x10 17 -3x10 18 atoms / cm 3 , further preferably 1x10 18 atoms / cm 3 .

[0027] According to the application, preferably, the material of the Al x2 Ga 1-x2 As lower N waveguide layer is Al x2 Ga 1-x2 As doped with Si, the doping concentration of Si atoms being 1x10 17 -2x10 18 atoms / cm 3 , further preferably 5x10 17 atoms / cm 3 .

[0028] According to the application, preferably, the material of the Al x3 Ga 1-x3 As carrier collection layer I is Al x3 Ga 1- x3 As doped with Si, the doping concentration of Si atoms being 5x10 16- 3 x 10 17 atoms / cm 3 , further preferably 1 x 10 17 atoms / cm 3 .

[0029] According to the application, preferably, the material of the upper N waveguide layer of Al x2 Ga 1-x2 As is the same as the material of the lower N waveguide layer of Al x2 Ga 1-x2 As.

[0030] According to the application, preferably, the material of the lower P waveguide layer of Al x5 Ga 1-x5 As is a carbon-doped Al x5 Ga 1-x5 As material, the doping concentration of carbon atoms being in the range of 1 x 10 17 - 1 x 10 18 atoms / cm 3 , further preferably 5 x 10 17 atoms / cm 3 .

[0031] According to the application, preferably, the material of the carrier collection layer II of Al x6 Ga 1-x6 As is a carbon-doped Al x6 Ga 1- x6 As material, the doping concentration of carbon atoms being in the range of 5 x 10 16 - 2 x 10 17 atoms / cm 3 , further preferably 1 x 10 17 atoms / cm 3 .

[0032] According to the application, preferably, the material of the upper P waveguide layer of Al x5 Ga 1-x5 As is the same as the material of the lower P waveguide layer of Al x5 Ga 1-x5 As.

[0033] According to the application, preferably, the material of the P confinement layer of Al x7 Ga 1-x7 As is a carbon-doped Al x7 Ga 1-x7 As material, the doping concentration of carbon atoms being in the range of 2 x 10 18 - 6 x 10 18 atoms / cm 3 , further preferably 5 x 10 18 atoms / cm3 .

[0034] According to the application, preferably, the material of the GaAs ohmic contact layer is carbon-doped GaAs material, the doping concentration of carbon atoms is 1×10 18 -5×10 19 atoms / cm 3 , and further preferably 3×10 19 atoms / cm 3 .

[0035] The preparation method of the high-temperature-resistant semiconductor laser chip comprises the following steps: performing surface heat treatment on a substrate in a MOCVD growth chamber, and using MOCVD technology to epitaxially grow, from bottom to top, an N confinement layer, a lower N waveguide layer, a carrier collection layer I, an upper N waveguide layer, a quantum well layer, a lower P waveguide layer, a carrier collection layer II, an upper P waveguide layer, a P confinement layer, and an ohmic contact layer on the substrate.

[0036] According to the application, the epitaxial growth method can be used in the prior art; preferably, the preparation method of the high-temperature-resistant semiconductor laser chip comprises the following steps:

[0037] (1) placing a GaAs substrate in a MOCVD device growth chamber, baking the GaAs substrate at 730-750℃ for 20-40 minutes in an H2 environment, and then introducing AsH3 to perform high-temperature heat treatment on the GaAs substrate to remove water and oxygen on the surface of the substrate;

[0038] (2) reducing the temperature of the reaction chamber to 650-690℃, and introducing TMAl, TMGa, and AsH3 to grow an Al x1 Ga 1-x1 As N confinement layer on the GaAs substrate;

[0039] (3) maintaining the temperature of the reaction chamber at 650-690℃, and introducing TMAl, TMGa, and AsH3 to grow an Al x1 Ga 1-x1 As lower N waveguide layer on the Al x2 Ga 1-x2 As N confinement layer after step (2) is completed;

[0040] (4) maintaining the temperature of the reaction chamber at 650-690℃, and introducing TMAl, TMGa, and AsH3 to grow an Al x2 Ga 1-x2 As carrier collection layer I on the Al x3 Ga 1-x3 As lower N waveguide layer after step (3) is completed;

[0041] (5) Keep the temperature of the reaction chamber at 650-690°C, after step (4) is completed, introduce TMAl, TMGa and AsH3, grow Al x3 Ga 1-x3 As on the N waveguide layer of step (4); and x2 Ga 1-x2 As on the N waveguide layer of step (4); and

[0042] (6) Reduce the temperature of the reaction chamber to 530-570°C, after step (5) is completed, introduce TMIn, TMGa and AsH3, grow In x2 Ga 1-x2 As on the N waveguide layer of step (5); and x4 Ga 1-x4 As on the N waveguide layer of step (5); and

[0043] (7) Raise the temperature of the reaction chamber to 650-690°C, after step (6) is completed, introduce TMAl, TMGa and AsH3, grow Al x4 Ga 1-x4 As on the In x5 Ga 1-x5 As quantum well layer of step (6); and

[0044] (8) Keep the temperature of the reaction chamber at 650-690°C, after step (7) is completed, introduce TMAl, TMGa and AsH3, grow Al x5 Ga 1-x5 As on the In x6 Ga 1-x6 As quantum well layer of step (7); and

[0045] (9) Keep the temperature of the reaction chamber at 650-690°C, after step (8) is completed, introduce TMAl, TMGa and AsH3, grow Al x6 Ga 1-x6 As on the In x5 Ga 1-x5 As quantum well layer of step (8); and

[0046] (10) Keep the temperature of the reaction chamber at 650-690°C, after step (9) is completed, introduce TMAl, TMGa and AsH3, grow Al x5 Ga 1-x5 As on the In x7 Ga 1-x7 As quantum well layer of step (9); and

[0047] (11) Keep the temperature of the reaction chamber at 650-690°C, after step (10) is completed, introduce TMGa and AsH3, grow GaAs ohmic contact layer on the Al x7 Ga 1-x7 As P confinement layer of step (10).

[0048] Further preferably, the Al x1 Ga 1-x1 The doping source of the N confinement layer is Si2H6.

[0049] Further preferably, the Al x2 Ga 1-x2 The doping source of the lower N waveguide layer is Si2H6.

[0050] Further preferably, the Al x3 Ga 1-x3 The doping source of the carrier collection layer I is Si2H6.

[0051] Further preferably, the Al x2 Ga 1-x2 The doping source of the upper N waveguide layer is Si2H6.

[0052] Further preferably, the Al x5 Ga 1-x5 The doping source of the lower P waveguide layer is CBr4.

[0053] Further preferably, the Al x6 Ga 1-x6 The doping source of the carrier collection layer II is CBr4.

[0054] Further preferably, the Al x5 Ga 1-x5 The doping source of the upper P waveguide layer is CBr4.

[0055] Further preferably, the doping source of the GaAs ohmic contact layer in step (10) is CBr4.

[0056] The invention is not limited in detail.

[0057] The technical features and beneficial effects of the invention are as follows:

[0058] 1. The present invention inserts a carrier collection layer in the N waveguide layer and the P waveguide layer, effectively consuming the free carriers escaped from the quantum well at high temperature, significantly reducing the internal loss coefficient of the waveguide layer, improving the net gain coefficient of the chip at high temperature, and further improving the high temperature performance of the chip.

[0059] 2. The carrier collection layer proposed in the present invention can migrate the light field to the quantum well active region at high temperature, thereby improving the light confinement factor of the quantum well active region at high temperature, improving the gain of the chip at high temperature, and further improving the high temperature performance of the chip.

[0060] 3、The inserted carrier collection layer, the thickness of the carrier collection layer is much larger than the thickness of the quantum well, and there is a certain interval distance between the carrier collection layer and the quantum well layer, which will not become a radiation recombination center. The carrier collection layer of the application can effectively regulate the light field, increase the light confinement factor at high temperature, and achieve the purpose of increasing the optical gain. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 A schematic diagram of the cross section of the semiconductor laser chip obtained in Example 1,

[0062] Wherein 101 is the substrate, 102 is the N confinement layer, 103 is the lower N waveguide layer, 104 is the carrier collection layer I, 105 is the upper N waveguide layer, 106 is the quantum well layer, 107 is the lower P waveguide layer, 108 is the carrier collection layer II, 109 is the upper P waveguide layer, 110 is the P confinement layer, and 111 is the ohmic contact layer.

[0063] Figure 2 A photoelectric conversion efficiency diagram of the semiconductor laser chip of Example 1 and Comparative Example 1 at high temperature (60℃). DETAILED DESCRIPTION

[0064] The application will be further described below by specific examples in conjunction with the drawings, but is not limited thereto.

[0065] The raw materials used in the examples are conventional raw materials and can be purchased on the market unless otherwise specified. The methods used in the examples are prior art unless otherwise specified.

[0066] Example 1

[0067] A preparation method of a high-temperature-resistant semiconductor laser chip, comprising the following steps:

[0068] (1) Put the GaAs substrate in the growth chamber of the MOCVD equipment, heat to 740℃ in H2 environment for 30 minutes, then pass in AsH3, and perform high-temperature heat treatment on the GaAs substrate to remove water and oxygen on the surface of the substrate;

[0069] (2) Reduce the temperature of the reaction chamber to 670℃, pass in TMAl, TMGa and AsH3, and grow Al 0.23 Ga 0.77 As N confinement layer on the GaAs substrate; the doping source of the Al 0.23 Ga 0.77 As N confinement layer is Si2H6, and the doping concentration of Si atoms is 1×10 18 atoms / cm 3 ; the doping source of the Al 0.23 Ga 0.77The thickness of the As confinement layer is 600 nm;

[0070] (3) Maintain the reaction chamber temperature at 670℃. After step (2) is completed, introduce TMAl, TMGa and AsH3 into the Al. 0.23 Ga 0.77 Al grown on N-confinement layer 0.5 Ga 0.5 As under the N-waveguide layer; Al 0.5 Ga 0.5 The doping source for the As-based N-waveguide layer is Si₂H₆, and the Si atom doping concentration is 5 × 10⁻⁶. 17 atoms / cm 3 Al 0.5 Ga 0.5 The thickness of the As-based N-waveguide layer is 600 nm.

[0071] (4) Maintain the reaction chamber temperature at 670℃. After step (3) is completed, introduce TMAl, TMGa and AsH3 into the Al. 0.5 Ga 0.5 Al is grown on the lower N-waveguide layer of As. 0.25 Ga 0.75 As carrier collection layer I; Al 0.25 Ga 0.75 The doping source for As carrier collection layer I is Si₂H₆, and the doping concentration of Si atoms is 1×10⁻⁶. 17 atoms / cm 3 Al 0.25 Ga 0.75 The thickness of As carrier collection layer I is 15 nm;

[0072] (5) Maintain the reaction chamber temperature at 670℃. After step (4) is completed, introduce TMAl, TMGa and AsH3 into Al. 0.25 Ga 0.75 Al is grown on As carrier collection layer I 0.5 Ga 0.5 As with N-waveguide layer; Al 0.5 Ga 0.5 The doping source for the N-waveguide layer on As is Si₂H₆, and the doping concentration of Si atoms is 5 × 10⁻⁶. 17 atoms / cm 3 Al 0.5 Ga 0.5 The thickness of the N-waveguide layer on As is 80 nm;

[0073] (6) Lower the reaction chamber temperature to 550℃. After step (5) is completed, introduce TMI, TMGa and AsH3 into Al. 0.5 Ga 0.5 In grown on the N-waveguide layer of As0.1 Ga 0.9 As quantum well layer, In 0.1 Ga 0.9 The thickness of the As quantum well layer is 8 nm;

[0074] (7) The temperature of the reaction chamber is raised to 670°C, TMAl, TMGa and AsH3 are introduced after step (6) is completed, and an Al 0.1 Ga 0.9 As quantum well layer is grown on the In 0.5 Ga 0.5 As lower P waveguide layer, Al 0.5 Ga 0.5 The doping source of the As lower P waveguide layer is CBr4, and the doping concentration of C atoms is 5 x 1019 atoms / cm 17 3 , Al 0.5 Ga 0.5 The thickness of the As lower P waveguide layer is 50 nm;

[0075] (8) The temperature of the reaction chamber is maintained at 670°C, TMAl, TMGa and AsH3 are introduced after step (7) is completed, and an Al 0.5 Ga 0.5 As lower P waveguide layer is grown on the In 0.25 Ga 0.75 As carrier collection layer II; Al 0.25 Ga 0.75 The doping source of the As carrier collection layer II is CBr4, and the doping concentration of C atoms is 1 x 1019 atoms / cm 17 3 , Al 0.25 Ga 0.75 The thickness of the As carrier collection layer II is 15 nm;

[0076] (9) The temperature of the reaction chamber is maintained at 670°C, TMAl, TMGa and AsH3 are introduced after step (8) is completed, and an Al 0.25 Ga 0.75 As carrier collection layer II is grown on the In 0.5 Ga 0.5 As upper P waveguide layer, Al 0.5 Ga 0.5 The doping source of the As upper P waveguide layer is CBr4, and the doping concentration of C atoms is 5 x 1019 atoms / cm 17 3 , Al 0.5 Ga 0.5 The thickness of the As upper P waveguide layer is 600 nm;

[0077] ​​​(10) keeping the temperature of the reaction chamber at 670℃, after step (9) is completed, TMAl, TMGa and AsH3 are introduced, and Al 0.5 Ga 0.5 As P waveguide layer is grown on Al 0.8 Ga 0.2 As P confinement layer, the doping source of Al 0.8 Ga 0.2 As P confinement layer is CBr4, and the doping concentration of C atom is 5×10 18 atoms / cm 3 , Al 0.8 Ga 0.2 As P confinement layer is 600nm thick;

[0078] (11) keeping the temperature of the reaction chamber at 670℃, after step (10) is completed, TMGa and AsH3 are introduced, and GaAs ohmic contact layer is grown on Al 0.8 Ga 0.2 As P confinement layer, the doping source of GaAs ohmic contact layer is CBr4, and the doping concentration of C atom is 3×10 19 atoms / cm 3 , and the thickness of GaAs ohmic contact layer is 800nm.

[0079] The schematic diagram of the high-temperature-resistant semiconductor laser chip prepared by the method is shown in Figure 1 , from bottom to top, including: substrate, N confinement layer, lower N waveguide layer, carrier collection layer I, upper N waveguide layer, quantum well layer, lower P waveguide layer, carrier collection layer II, upper P waveguide layer, P confinement layer, and ohmic contact layer; the specific composition is shown in Table 1, wherein the band gap difference between the carrier collection layer I and the quantum well layer is 30meV, the band gap difference between the carrier collection layer I and the N waveguide layer is 50meV, the band gap difference between the carrier collection layer II and the quantum well layer is 30meV, and the band gap difference between the carrier collection layer II and the P waveguide layer is 50meV.

[0080] Name Composition Thickness (nm) Ohmic contact layer GaAs 800 P confining layer Al 0.8 Ga 0.2 As 600 Upper P waveguide layer Al 0.5 Ga 0.5 As 600 Carrier collection layer II Al 0.25 Ga 0.75 As 15 Lower P waveguide layer Al 0.5 Ga 0.5 As 50 Quantum well layer In 0.1 Ga 0.9 As]]> 8 Upper N waveguide layer Al 0.5 Ga 0.5 As 80 Carrier collection layer I Al 0.25 Ga 0.75 As 15 Lower N waveguide layer Al 0.5 Ga 0.5 As 600 N confining layer Al 0.23 Ga 0.77 As 600 Substrate GaAs

[0081] Comparative Example 1

[0082] A method for preparing a high-temperature-resistant semiconductor laser chip, comprising the following steps:

[0083] (1) placing a GaAs substrate in a growth chamber of a MOCVD device, baking at 740℃ for 30 minutes in H2 environment, and then introducing AsH3 to perform high-temperature heat treatment on the GaAs substrate to remove water and oxygen on the surface of the substrate;

[0084] (2) reducing the temperature of the reaction chamber to 670℃, introducing TMAl, TMGa and AsH3, and growing Al 0.23Ga 0.77 As N confining layer; Al 0.23 Ga 0.77 The doping source of the As N confining layer is Si2H6, and the doping concentration of Si atoms is 1 x 10 18 atoms / cm 3 ; Al 0.23 Ga 0.77 The thickness of the As confining layer is 600 nm;

[0085] (3) The temperature of the reaction chamber is kept at 670 °C, and TMAl, TMGa and AsH3 are introduced after step (2) is completed, to grow Al 0.23 Ga 0.77 As N confining layer on the Al 0.5 Ga 0.5 As N waveguide layer; Al 0.5 Ga 0.5 The doping source of the As N waveguide layer is Si2H6, and the doping concentration of Si atoms is 5 x 10 17 atoms / cm 3 ; Al 0.5 Ga 0.5 The thickness of the As N waveguide layer is 680 nm;

[0086] (4) The temperature of the reaction chamber is lowered to 550 °C, and TMIn, TMGa and AsH3 are introduced after step (3) is completed, to grow In 0.5 Ga 0.5 As quantum well layer on the Al 0.1 Ga 0.9 As quantum well layer; In 0.1 Ga 0.9 The thickness of the As quantum well layer is 8 nm;

[0087] (5) The temperature of the reaction chamber is raised to 670 °C, and TMAl, TMGa and AsH3 are introduced after step (4) is completed, to grow Al 0.5 Ga 0.5 As P waveguide layer; Al 0.5 Ga 0.5 The doping source of the As P waveguide layer is CBr4, and the doping concentration of C atoms is 5 x 10 17 atoms / cm 3 , Al 0.5 Ga 0.5 The thickness of the lower As P waveguide layer is 650 nm;

[0088] (6) The temperature of the reaction chamber is kept at 670 °C, and TMAl, TMGa and AsH3 are introduced after step (5) is completed, to grow Al 0.5 Ga 0.5Al grown on P waveguide layer 0.8 Ga 0.2 As P confinement layer, Al 0.8 Ga 0.2 The doping source for the As P confinement layer is CBr4, and the doping concentration of C atoms is 5 × 10⁻⁶. 18 atoms / cm 3 Al 0.8 Ga 0.2 The thickness of the As P confinement layer is 600 nm;

[0089] (7) Maintain the reaction chamber temperature at 670℃. After step (6) is completed, introduce TMGa and AsH3 into Al. 0.8 Ga 0.2 A GaAs ohmic contact layer is grown on an As P confinement layer. The doping source of the GaAs ohmic contact layer is CBr4, and the doping concentration of C atoms is 3 × 10⁻⁶. 19 atoms / cm 3 The thickness of the GaAs ohmic contact layer is 800 nm.

[0090] The resulting semiconductor laser chip, from bottom to top, comprises: a substrate, an N-confinement layer, an N-waveguide layer, a quantum well layer, a P-waveguide layer, a P-confinement layer, and an ohmic contact layer; the specific composition is shown in Table 1.

[0091] Name Composition Thickness (nm) Ohmic contact layer GaAs 800 P confining layer Al 0.8 Ga 0.2 As 600 P waveguide layer Al 0.5 Ga 0.5 As 650 Quantum well layer In 0.1 Ga 0.9 As]]> 8 N waveguide layer Al 0.5 Ga 0.5 As 680 N confining layer Al 0.23 Ga 0.77 As 600 Substrate GaAs

[0092] Comparative Example 2

[0093] A method for fabricating a semiconductor laser chip is described in Example 1, except that the thickness of the upper N-waveguide layer is 20 nm and the thickness of the lower P-waveguide layer is 20 nm.

[0094] Comparative Example 3

[0095] A method for fabricating a semiconductor laser chip is described in Example 1, except that the thickness of the upper N-waveguide layer is 150 nm and the thickness of the lower P-waveguide layer is 150 nm.

[0096] The comprehensive analysis is as follows:

[0097] The photoelectric conversion efficiency of the semiconductor laser chips obtained in Example 1 and Comparative Example 1 at high temperature (60°C) is shown in the figure below. Figure 2 As shown, by Figure 2 It can be seen that by adopting the structure of the present invention, the photoelectric conversion efficiency at high temperature (60°C) is significantly improved, from 56% in Comparative Example 1 to 64%, an improvement of 8%.

[0098] The semiconductor laser chip obtained in Example 1 has an internal loss of 0.6 cm at 60°C. -1Comparative Examples 1-3 are 0.9 cm -1 , 0.8 cm -1 , and 0.7 cm -1 , which are obviously higher than the present application.

[0099] The present application effectively reduces the number of carriers escaping from the waveguide layer at high temperature by adding a carrier collection layer in the conventional structure, thereby effectively reducing the internal loss coefficient of the chip at high temperature. Meanwhile, the layer has a refractive index regulation effect, which makes the light field shift towards the quantum well layer at high temperature, thereby increasing the light confinement factor of the quantum well and effectively compensating for the gain degradation problem caused by the decrease of the gain coefficient at high temperature. Finally, the high-temperature performance of the chip is significantly improved.

Claims

1. A high-temperature resistant semiconductor laser chip, characterized in that, From bottom to top, it includes: substrate, N-confinement layer, lower N-waveguide layer, carrier collection layer I, upper N-waveguide layer, quantum well layer, lower P-waveguide layer, carrier collection layer II, upper P-waveguide layer, P-confinement layer, and ohmic contact layer.

2. The high-temperature resistant semiconductor laser chip according to claim 1, characterized in that, The bandgap of the carrier collection layer I is greater than that of the quantum well layer and smaller than that of the N waveguide layer; the difference in bandgap between the carrier collection layer I and the N waveguide layer is 40–80 meV.

3. The high-temperature resistant semiconductor laser chip according to claim 1, characterized in that, The bandgap of the carrier collection layer II is greater than that of the quantum well layer and smaller than that of the P-waveguide layer; the difference in bandgap between the carrier collection layer II and the P-waveguide layer is 40–80 meV.

4. The high-temperature resistant semiconductor laser chip according to claim 1, characterized in that, The bandgap difference between the carrier collection layer I or II and the quantum well layer is 20–60 meV.

5. The high-temperature resistant semiconductor laser chip according to claim 1, characterized in that, The distance between the carrier collection layer I or the carrier collection layer II and the quantum well layer is 30–100 nm; the thickness of the carrier collection layer I or the carrier collection layer II is 10–50 nm.

6. The high-temperature resistant semiconductor laser chip according to claim 1, characterized in that, The high-temperature resistant semiconductor laser chip includes one or more of the following conditions: (i) The substrate is a GaAs substrate; (ii) The N-confining layer is Al x1 Ga 1-x1 As N confinement layer, 0.2≤x1≤0.5; thickness 500~800nm; (iii) The lower N waveguide layer is Al x2 Ga 1-x2 As under the N waveguide layer, 0.4≤x2≤0.6; thickness is 500~600nm; (iv) Carrier collection layer I is Al x3 Ga 1-x3 As carrier collection layer I, 0.15≤x3≤0.3; thickness is 10~50nm; (v) The upper N-waveguide layer is Al x2 Ga 1-x2 An N-waveguide layer on As, 0.4 ≤ x2 ≤ 0.6; thickness 30–100 nm; (vi) The quantum well layer is In x4 Ga 1-x4 As quantum well layer, 0.05≤x4≤0.1; thickness 5~10nm; (vii) The lower P-waveguide layer is Al x5 Ga 1-x5 As under the P waveguide layer, 0.4≤x5≤0.6; thickness is 30~100nm; (viii) Carrier collection layer II is Al x6 Ga 1-x6 As carrier collection layer II, 0.15≤x6≤0.3; thickness 10~50nm; (ix) The upper P-waveguide layer is Al x5 Ga 1-x5 As-based P-waveguide layer, 0.4≤x5≤0.6; thickness 500~600nm; (x)P is confined by Al x7 Ga 1-x7 As P confinement layer, 0.7≤x7≤0.9, thickness 500~700nm; (xi) The ohmic contact layer is a GaAs ohmic contact layer with a thickness of 500–1000 nm.

7. The high-temperature resistant semiconductor laser chip according to claim 6, characterized in that, Includes one or more of the following conditions: (a) The Al x1 Ga 1-x1 The N-confinement layer is made of Si-doped Al. x1 Ga 1-x1 As material, the Si atom doping concentration is 5 × 10⁻⁶. 17 -3×10 18 atoms / cm 3 Preferably 1×10 18 atoms / cm 3 ; (b) The Al x2 Ga 1-x2 The N-waveguide layer under As is made of Si-doped Al. x2 Ga 1-x2 As material, the doping concentration of Si atoms is 1×10⁻⁶. 17 -2×10 18 atoms / cm 3 Preferably 5×10 17 atoms / cm 3 ; (c) The Al x3 Ga 1-x3 The carrier collection layer I is made of Si-doped Al. x3 Ga 1-x3 As material, the Si atom doping concentration is 5 × 10⁻⁶. 16 -3×10 17 atoms / cm 3 Preferably 1×10 17 atoms / cm 3 ; (d) The Al x2 Ga 1-x2 The material of the N-waveguide layer on As and Al x2 Ga 1-x2 The material of the N-waveguide layer under As is the same; (e) the Al x5 Ga 1-x5 The material of the As-below-P waveguide layer is carbon-doped Al. x5 Ga 1-x5 As material, the carbon atom doping concentration is 1×10⁻⁶. 17 -1×10 18 atoms / cm 3 Preferably 5×10 17 atoms / cm 3 ; (f) The Al x6 Ga 1-x6 The carrier collection layer II is made of carbon-doped Al. x6 Ga 1-x6 As material, the carbon atom doping concentration is 5 × 10⁻⁶. 16 -2×10 17 atoms / cm 3 Preferably 1×10 17 atoms / cm 3 ; (g) The Al x5 Ga 1-x5 The material of the P-waveguide layer on As and Al x5 Ga 1-x5 The material of the lower P waveguide layer is the same; (h) The Al x7 Ga 1-x7 The As P confinement layer is made of carbon-doped Al. x7 Ga 1-x7 As material, the carbon atom doping concentration is 2×10⁻⁶. 18 -6×10 18 atoms / cm 3 Preferably 5×10 18 atoms / cm 3 ; (i) The material of the GaAs ohmic contact layer is carbon-doped GaAs material, and the carbon atom doping concentration is 1×10⁻⁶. 18 -5×10 19 atoms / cm 3 Preferably 3×10 19 atoms / cm 3 .

8. A method for fabricating a high-temperature resistant semiconductor laser chip according to any one of claims 1-7, comprising the steps of: performing surface heat treatment on a substrate in an MOCVD growth chamber, and epitaxially growing an N-confinement layer, a lower N-waveguide layer, a carrier collection layer I, an upper N-waveguide layer, a quantum well layer, a lower P-waveguide layer, a carrier collection layer II, an upper P-waveguide layer, a P-confinement layer, and an ohmic contact layer sequentially from bottom to top on the substrate using MOCVD technology.

9. The method for fabricating a high-temperature resistant semiconductor laser chip according to claim 8, characterized in that, The steps include the following: (1) Place the GaAs substrate in the growth chamber of the MOCVD equipment, heat the H2 environment to 730-750℃ and bake for 20-40 minutes, then introduce AsH3 to perform high-temperature heat treatment on the GaAs substrate to remove water and oxygen from the substrate surface. (2) The reaction chamber temperature was lowered to 650–690 °C, and TMAl, TMGa, and AsH3 were introduced to grow Al on the GaAs substrate. x1 Ga 1-x1 As N confinement layer; (3) Maintain the reaction chamber temperature at 650–690°C. After step (2) is completed, introduce TMAl, TMGa, and AsH3 into the Al. x1 Ga 1- x1 Al grown on N-confinement layer x2 Ga 1-x2 As under the N-waveguide layer; (4) Maintain the reaction chamber temperature at 650–690°C. After step (3) is completed, introduce TMAl, TMGa, and AsH3 into the Al. x2 Ga 1- x2 Al is grown on the lower N-waveguide layer of As. x3 Ga 1-x3 As carrier collection layer I; (5) Maintain the reaction chamber temperature at 650–690°C. After step (4) is completed, introduce TMAl, TMGa, and AsH3 into the Al. x3 Ga 1- x3 Al is grown on As carrier collection layer I x2 Ga 1-x2 As with N-waveguide layer; (6) Reduce the reaction chamber temperature to 530–570°C. After step (5) is completed, introduce TMI, TMGa, and AsH3 into the Al. x2 Ga 1- x2 In grown on the N-waveguide layer of As x4 Ga 1-x4 As a quantum well layer; (7) Raise the reaction chamber temperature to 650–690°C. After step (6) is completed, introduce TMAl, TMGa, and AsH3 into In. x4 Ga 1-x4 Al grown on As quantum well layer x5 Ga 1-x5 As under P waveguide layer; (8) Maintain the reaction chamber temperature at 650–690°C. After step (7) is completed, introduce TMAl, TMGa, and AsH3 into the Al. x5 Ga 1- x5 Al grown on the lower P waveguide layer x6 Ga 1-x6 As carrier collection layer II; (9) Maintain the reaction chamber temperature at 650–690°C. After step (8) is completed, introduce TMAl, TMGa, and AsH3 into the Al. x6 Ga 1- x6 Al is grown on As carrier collection layer II x5 Ga 1-x5 As on P waveguide layer; (10) Maintain the reaction chamber temperature at 650–690°C. After step (9) is completed, introduce TMAl, TMGa, and AsH3 into the Al. x5 Ga 1- x5 Al grown on P waveguide layer of As x7 Ga 1-x7 As P confinement layer; (11) Maintain the reaction chamber temperature at 650–690 °C. After step (10) is completed, introduce TMGa and AsH3 into the Al. x7 Ga 1-x7 GaAs ohmic contact layers are grown on As P confinement layers.

10. The method for fabricating a high-temperature resistant semiconductor laser chip according to claim 9, characterized in that, In step (2), the Al mentioned x1 Ga 1-x1 The doping source for the As N confinement layer is Si2H6; The Al mentioned in step (3) x2 Ga 1-x2 The doping source for the As-based N-waveguide layer is Si2H6; The Al mentioned in step (4) x3 Ga 1-x3 The doping source for As carrier collection layer I is Si2H6; In step (5), the Al mentioned x2 Ga 1-x2 The doping source for the N-waveguide layer on As is Si2H6; The Al mentioned in step (7) x5 Ga 1-x5 The doping source for the As-based P-waveguide layer is CBr4. The Al mentioned in step (8) x6 Ga 1-x6 The doping source for As carrier collection layer II is CBr4; The Al mentioned in step (9) x5 Ga 1-x5 The doping source for the As-on-P waveguide layer is CBr4; The doping source for the GaAs ohmic contact layer in step (10) is CBr4.

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