Self-adaptive multistage gate driving circuit and driving method for silicon carbide power device

Abstract

The invention relates to a self-adaptive multi-stage gate drive circuit for a silicon carbide power device, and the core idea of the circuit is that a single switching process (switching on or switching off) is decomposed into a plurality of key stages, and the optimal gate drive intensity (namely drive impedance) is matched for each stage. The circuit comprises a main driving unit for providing basic driving capability; the programmable gate impedance network consists of a plurality of resistor circuits which are connected in parallel and can be independently controlled by an electric switch (such as a small-signal MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)); the state monitoring unit is used for monitoring a physical quantity capable of reflecting a switching process in real time through a high-speed comparator or an ADC (Analog to Digital Converter), preferably gate-source voltage Vgs; and the digital control unit (such as an FPGA or a CPLD) is used as the core of the whole adaptive control. The invention also relates to a self-adaptive multistage gate driving method for driving the silicon carbide power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, in particular to a gate drive circuit and a driving method for a wide bandgap semiconductor power device, especially a silicon carbide (SiC) MOSFET. BACKGROUND

[0002] With the increasing demand for energy efficiency and power density, wide bandgap semiconductor devices represented by silicon carbide (SiC) MOSFETs are gradually replacing traditional silicon (Si) based power devices and are widely used in new energy vehicles, photovoltaic inverters, data center power supplies, industrial motor drives and other fields. SiC MOSFETs have the advantages of fast switching speed, low on-resistance and high temperature resistance, which enable them to operate at higher frequencies and higher voltages.

[0003] However, the extremely fast switching speed of SiC MOSFETs (dV / dt and dl / dt can reach tens of kV / μs and several kA / μs) also brings a series of severe technical challenges, mainly concentrated in the gate drive design:

[0004] 1. Voltage overshoot and oscillation: extremely high dl / dt will generate a huge induced voltage (V=Lσ*dl / dt) on the parasitic inductance (Lσ) of the power loop, which is superimposed on the DC bus voltage, resulting in a serious voltage overshoot across the drain and source of the SiC device, which may exceed its rated breakdown voltage, causing permanent damage to the device. At the same time, the output capacitance of the device and the loop parasitic inductance form a resonance, causing high-frequency oscillation.

[0005] 2. Electromagnetic interference (EMI): the high-speed changing voltage (dV / dt) and current (dl / dt) are strong sources of EMI radiation, which can interfere with the normal operation of other electronic devices in the system, increasing the design difficulty, cost and volume of the EMI filter.

[0006] 3. Miller effect and parasitic conduction: in a half-bridge topology, when a SiC device in one bridge arm is turned on at high speed, its rapidly rising drain-source voltage (high dV / dt) will be coupled to its gate through the Miller capacitance (Cgd) of the device in the other bridge arm (off state), generating a positive displacement current. The current produces a voltage drop across the impedance of the gate drive circuit, which may cause the gate voltage to accidentally rise above the threshold voltage, causing the upper and lower bridge arms to be "parasitically conducted" at the same time, causing a short circuit failure.

[0007] 4. Contradiction between switching loss and driving speed: In order to suppress voltage overshoot and EMI, traditional methods usually employ a large gate resistance (Rg) to slow down the switching speed. However, this will significantly increase the switching loss (E_sw) of the device, reducing the system efficiency. Conversely, using a small gate resistance in pursuit of low switching loss will exacerbate the overshoot and EMI problems. This inherent design contradiction limits the full play of SiC device performance.

[0008] Some existing improvement techniques, such as simple active Miller clamping, can prevent parasitic conduction to some extent, but cannot solve the overshoot problem during switching. The driving scheme with fixed gate resistance is essentially a "one-size-fits-all" compromise, which cannot achieve optimal control at different stages of the switching process. Therefore, there is an urgent need for a gate drive scheme that can intelligently and dynamically adapt to the switching characteristics of SiC devices to synergistically optimize switching speed, loss, reliability, and EMI performance. SUMMARY

[0009] The first object of the present application is to provide an adaptive multi-stage gate drive circuit for silicon carbide power devices, the core idea of which is to divide a single switching process (turn-on or turn-off) into multiple key stages and match the optimal gate drive strength (i.e. driving impedance) for each stage. The circuit includes: a main drive unit providing basic driving capability; a programmable gate impedance network composed of multiple parallel paths of independently controllable resistors through electrical switches (such as small signal MOSFETs); a state monitoring unit that monitors physical quantities reflecting the switching process in real time through high-speed comparators or ADCs, preferably gate-source voltage Vgs; a digital control unit (such as FPGA or CPLD) as the core of the entire adaptive control.

[0010] When the digital control unit receives an external PWM turn-on command, it first selects a very low driving impedance through the programmable impedance network to achieve rapid charging of the gate. When the state monitoring unit detects that Vgs rises to the start of the Miller plateau, the digital control unit immediately adjusts the impedance network to switch to a higher driving impedance. This will slow down the rate of Vds decrease (dV / dt), thereby suppressing current overshoot and voltage overshoot. When the state monitoring unit further detects that Vgs has crossed the Miller plateau, the digital control unit switches back to low driving impedance again to ensure that the gate is quickly and fully charged to the steady-state on-voltage to achieve the lowest on-resistance. The turn-off process adopts a similar but reversed multi-stage control strategy.

[0011] An adaptive multi-stage gate drive circuit for silicon carbide power devices, comprising,

[0012] a main drive unit, the output end of which is connected to the gate of the silicon carbide power device, for providing a gate drive signal;

[0013] A programmable gate impedance network, connected in parallel with the output of the main drive unit, is used to adjust the drive current applied to the gate of the silicon carbide power device; the programmable gate impedance network includes at least two parallel resistor branches controlled by independent switches.

[0014] A state monitoring unit, connected to at least one electrode of the silicon carbide power device, is used to monitor at least one physical quantity characterizing the switching state in real time during the switching transient process and generate a state feedback signal.

[0015] A digital control unit receives an externally input pulse width modulation signal and a status feedback signal from the status monitoring unit at its input terminal, and controls the independent switches in the programmable gate impedance network at its output terminal. The digital control unit is configured to, upon receiving the rising or falling edge of the pulse width modulation signal, turn the independent switches on or off in stages during a single switching process according to the status feedback signal, so as to dynamically adjust the total impedance of the programmable gate impedance network.

[0016] Specifically, the state monitoring unit is configured to monitor the gate-source voltage of the silicon carbide power device and identify the stage of the switching process by comparing the gate-source voltage of the silicon carbide power device with a plurality of preset voltage thresholds.

[0017] Specifically, the preset voltage threshold includes a first threshold for identifying the starting point of the Miller platform and a second threshold for identifying the ending point of the Miller platform.

[0018] Specifically, the status monitoring unit includes a high-speed voltage comparator or an analog-to-digital converter for converting the monitored physical quantity into a digital signal and transmitting it to the digital control unit.

[0019] Specifically, the programmable gate impedance network includes a low-resistance branch and a high-resistance branch; the digital control unit turns on the switch corresponding to the low-resistance branch at the beginning and end of the turn-on period to achieve fast charging, and turns off the switch corresponding to the low-resistance branch and turns on the switch corresponding to the high-resistance branch during the Miller plateau to slow down dV / dt.

[0020] Specifically, it also includes an active Miller clamping unit, which the digital control unit activates in the later stages of the shutdown process to prevent parasitic conduction caused by the Miller effect.

[0021] Specifically, the digital control unit is a field-programmable gate array, a complex programmable logic device, or a microcontroller with integrated dedicated logic circuits.

[0022] The second objective of this invention is to provide an adaptive multi-stage gate driving method for driving silicon carbide power devices, comprising the following steps:

[0023] S1. Receive externally input PWM signals to initiate the turn-on or turn-off process;

[0024] S2. During the transient period of the turn-on or turn-off process, monitor in real time at least one physical quantity characterizing the switching state of the silicon carbide power device.

[0025] S3. Based on the monitored physical quantities, identify the current stage of the switching process, wherein the stage includes at least the pre-Miller plateau stage, the Miller plateau stage, and the post-Miller plateau stage;

[0026] S4. Based on the identified stage, dynamically adjust the driving impedance applied to the gate of the silicon carbide power device to provide different driving current intensities for different stages.

[0027] Specifically, during the activation process,

[0028] In the Miller platform stage, low drive impedance is used to quickly boost the gate-source voltage to the Miller voltage;

[0029] During the Miller plateau phase, a high drive impedance is used to slow down the rate of decrease in drain-source voltage;

[0030] In the later stages after the Miller platform, low drive impedance is used again to quickly charge the gate to the target turn-on voltage.

[0031] Specifically, the turn-off process includes turning off with a negative bias voltage and activating an active Miller clamp in the later stage of turn-off to enhance the reliability of turn-off.

[0032] The adaptive multi-stage gate drive circuit and its fabrication process for silicon carbide power devices of the present invention have the following advantages compared with the prior art:

[0033] (1) Collaborative Performance Optimization: This invention breaks the fixed trade-off between switching speed and voltage overshoot. By "intelligently slowing down" in the critical Miller plateau region and "fully accelerating" in other stages, collaborative optimization of switching losses and voltage overshoot is achieved. Experimental data shows that, compared with a fixed resistor scheme, voltage overshoot can be reduced by more than 50% while increasing switching losses by no more than 5%.

[0034] (2) Reduce EMI level: By actively controlling the peak values ​​of dV / dt and dl / dt, the generation of high-frequency noise is suppressed from the source, effectively reducing the electromagnetic radiation and conducted interference of the system and simplifying the design of EMI filters;

[0035] (3) Improve system reliability: Effectively suppressed voltage overshoot allows SiC devices to have a larger operating voltage margin, reducing the risk of damage due to overvoltage; at the same time, the integrable active Miller clamp function further enhances the system's anti-interference capability under bridge topology and prevents shoot-through short circuits.

[0036] (4) Flexibility and configurability: Since the control logic is implemented in the digital control unit, the drive characteristics (such as the impedance value of each stage and the switching threshold) can be easily configured by software or firmware, so that it can flexibly adapt to different types of SiC devices and different operating conditions (such as load current and bus voltage), and has strong versatility. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the circuit structure in Example 1;

[0038] Figure 2 Here is the adaptive control flowchart for the opening process in Example 1;

[0039] Figure 3 This is a schematic diagram comparing the drain-source voltage (Vds) waveforms of a traditional fixed resistor drive and the adaptive drive in Example 1. Detailed Implementation

[0040] The specific embodiments of this invention will be further described in detail below with reference to the accompanying drawings.

[0041] Example 1

[0042] Please refer to Figure 1 This illustrates the circuit structure of a preferred embodiment of the present invention. The circuit drives a SiC MOSFET (not shown, its gate is connected to the "To Gate" output terminal). The circuit mainly includes: a main drive unit 101, a programmable gate impedance network 102, a status monitoring unit 103, and a digital control unit 104.

[0043] The main drive unit 101 can be a commercially available isolated gate driver IC, such as TI's UCC21520 or ADI's ADuM4135. It is responsible for providing basic push-pull output stages, isolation functions, and protection functions such as undervoltage lockout (UVLO). Its inputs receive drive enable signals from the digital control unit 104, and its outputs are connected to the programmable gate impedance network 102.

[0044] The programmable gate impedance network 102 is the core actuator of this invention. In this embodiment, it consists of two parallel branches: a low-resistance branch containing a resistor R_L and a control switch S_L; and a high-resistance branch containing a resistor R_H and a control switch S_H. Switches S_L and S_H are preferably small-signal N-channel MOSFETs with extremely low on-resistance, and their gates are directly controlled by the digital control unit 104. For example, R_L can be 1Ω and R_H can be 10Ω. By combining the on / off states of S_L and S_H, three total drive impedances can be achieved: R_L (1Ω) when only S_L is on, R_H (10Ω) when only S_H is on, and R_L / R_H (approximately 0.9Ω) when both are on. In practical applications, it can be expanded to include more branches to achieve finer impedance adjustment.

[0045] The state monitoring unit 103 is responsible for "sensing" the switching state of the SiC MOSFET. In this embodiment, it directly monitors the voltage Vgs at the gate node (i.e., the output of the main drive unit 101). This unit can be composed of one or more high-speed voltage comparators, with their inverting inputs connected to the gate node and their non-inverting inputs connected to a preset reference voltage (threshold voltage). For example, two comparators can be set, with reference voltages of a first threshold Vth1 (e.g., 5V, corresponding to the start point of the Miller plateau) and a second threshold Vth2 (e.g., 8V, corresponding to the end point of the Miller plateau). When Vgs crosses these thresholds, the comparator output state flips, sending an interrupt or level change signal to the digital control unit 104.

[0046] The digital control unit 104 is the "brain" of the entire adaptive control system. It is typically implemented using an FPGA or CPLD due to its nanosecond-level response delay and parallel processing capabilities. It receives the main PWM signal from the external controller and generates control signals for the switches S_L and S_H, as well as the main drive unit 101, in real time based on the feedback generated by the state monitoring unit 103.

[0047] Now combined Figure 2 A detailed description of the turn-on process of a SiC MOSFET:

[0048] Step S1 (Start): The digital control unit 104 receives the rising edge of the external PWM signal;

[0049] Step S2 (Stage 1: Pre-charge): The controller immediately turns on the main drive unit 101, simultaneously closing switch S_L and opening switch S_H. At this time, the total gate resistance is R_L (1Ω), and a large drive current flows to the gate, causing Vgs to rise rapidly from the negative bias voltage (e.g., -5V). The goal of this stage is to quickly overcome the nonlinear region of the input capacitor Ciss and reach the Miller plateau.

[0050] Step S3 (Stage Judgment 1): The state monitoring unit 103 continuously monitors Vgs. The controller waits until it detects that Vgs exceeds the first threshold Vth1 (5V), which indicates that the Miller platform is about to start and Vds is about to drop rapidly;

[0051] Step S4 (Stage 2: Miller Platform Control): Once Vgs > Vth1, the controller reacts immediately (with a delay typically within 10-20 ns), disconnecting switch S_L while maintaining (or keeping on) switch S_H. The total gate resistance switches to R_H (10Ω). The drive current decreases, thereby slowing down the charging rate of the Miller capacitor Cgd, which directly leads to effective control of the decreasing slope (dV / dt) of Vds. Figure 3 As shown, compared to the steep drop and severe overshoot of the traditional drive (blue dashed line), the Vds waveform of the present invention (red solid line) drops more gently in this stage, and the peak overshoot is significantly suppressed.

[0052] Step S5 (Stage Judgment 2): The controller continues to wait for feedback from the status monitoring unit 103 until it detects that Vgs exceeds the second threshold Vth2 (8V), which indicates that the Miller platform has ended and Vds has dropped to near zero;

[0053] Step S6 (Phase 3: Full Turn-On): Once Vgs > Vth2, the controller closes switch S_L again, bringing the total gate resistance back to its minimum value R_L. A strong current is injected again, quickly charging the gate to the final turn-on voltage (e.g., +18V), ensuring that the SiC MOSFET can turn on quickly and fully, achieving the lowest on-resistance Rds(on).

[0054] Step S7 (End): The enable process is complete, and the controller maintains this state until the falling edge of the PWM arrives.

[0055] like Figure 3 As shown, Figure 3 As shown: Blue dashed line (conventional drive): Represents the drive method using a conventional fixed gate resistor (Rg). The waveform shows a very steep drop in Vds voltage, corresponding to an extremely high dV / dt. While this fast switching reduces some switching losses, its main drawback is the severe voltage overshoot and high-frequency oscillations generated in the parasitic inductance of the power circuit. As described in the "Background Art" section, this can exceed the device's rated breakdown voltage, leading to device damage and generating strong electromagnetic interference (EMI). Red solid line (adaptive drive of this invention): Represents the adaptive multi-stage drive scheme proposed in this invention. Compared to the conventional scheme, its Vds waveform is smoother in the drop phase, indicating that dV / dt is effectively controlled. The most significant improvement is that the peak voltage overshoot at the end of the waveform is significantly suppressed, and the oscillation amplitude is also greatly reduced.

[0056] Figure 3 This intuitively demonstrates the significant advantages of the adaptive multi-stage drive circuit of this invention. Through optimization of the Vds waveform, this technology brings the following core benefits:

[0057] 1. Improve system reliability: Effectively suppressing voltage overshoot allows for a larger operating voltage margin for SiC devices, reducing the risk of damage due to overvoltage.

[0058] 2. Reduce electromagnetic interference (EMI): Active control of dV / dt suppresses the generation of high-frequency noise at the source, which helps to simplify the design of EMI filters and reduce system cost and size.

[0059] 3. Synergistic performance optimization: This technology breaks the traditional "either / or" dilemma between switching speed and voltage overshoot, and achieves synergistic optimization of switching losses and voltage overshoot, giving full play to the high performance potential of SiC devices.

[0060] The turn-off process is similar, but the control logic is reversed. For example, a low-resistance rapid discharge is used in the initial turn-off phase, switching to high resistance in the Miller plateau region (the rising region of Vds) to control dV / dt and prevent interference to the other bridge arm device. Finally, a low resistance is used to pull the gate to a negative bias. Furthermore, when Vgs drops to near the threshold voltage, a parallel Miller clamp switch can be activated to provide an ultra-low impedance bypass for the Miller current, completely eliminating the risk of parasitic conduction.

[0061] In summary, this invention precisely controls the switching behavior of SiC devices at different stages by performing multi-level, intelligent drive impedance adjustment based on real-time feedback within the nanosecond time of a single switch, thereby solving a series of problems caused by high-speed switching at the source and achieving a comprehensive improvement in efficiency, reliability, and EMI performance.

[0062] Those skilled in the art should understand that various modifications and variations can be made to the above embodiments without departing from the spirit and scope of the present invention, such as using the slope of Vds as a feedback signal or employing more stages of impedance networks, etc., all of which should fall within the protection scope of the present invention.

Claims

1. An adaptive multi-stage gate drive circuit for silicon carbide power devices, characterized in that, include, The main drive unit, whose output is connected to the gate of the silicon carbide power device, is used to provide the gate drive signal; A programmable gate impedance network, connected in parallel with the output of the main drive unit, is used to adjust the drive current applied to the gate of the silicon carbide power device; the programmable gate impedance network includes at least two parallel resistor branches controlled by independent switches. A state monitoring unit, connected to at least one electrode of the silicon carbide power device, is used to monitor at least one physical quantity characterizing the switching state in real time during the switching transient process and generate a state feedback signal. A digital control unit receives an externally input pulse width modulation signal and a status feedback signal from the status monitoring unit at its input terminal, and controls the independent switches in the programmable gate impedance network at its output terminal. The digital control unit is configured to, upon receiving the rising or falling edge of the pulse width modulation signal, turn the independent switches on or off in stages during a single switching process according to the status feedback signal, so as to dynamically adjust the total impedance of the programmable gate impedance network.

2. The adaptive multi-stage gate drive circuit for silicon carbide power devices according to claim 1, characterized in that, The status monitoring unit is configured to monitor the gate-source voltage of the silicon carbide power device and identify the stage of the switching process by comparing the gate-source voltage of the silicon carbide power device with a plurality of preset voltage thresholds.

3. The adaptive multi-stage gate drive circuit for silicon carbide power devices according to claim 2, characterized in that, The preset voltage thresholds include a first threshold for identifying the starting point of the Miller platform and a second threshold for identifying the ending point of the Miller platform.

4. An adaptive multi-stage gate drive circuit for silicon carbide power devices according to any one of claims 1, characterized in that, The status monitoring unit includes a high-speed voltage comparator or an analog-to-digital converter, used to convert the monitored physical quantity into a digital signal and transmit it to the digital control unit.

5. The adaptive multi-stage gate drive circuit for silicon carbide power devices according to claim 1, characterized in that, The programmable gate impedance network includes a low-resistance branch and a high-resistance branch; the digital control unit turns on the switch corresponding to the low-resistance branch at the beginning and end of the turn-on period to achieve fast charging, and turns off the switch corresponding to the low-resistance branch and turns on the switch corresponding to the high-resistance branch during the Miller plateau to slow down dV / dt.

6. The adaptive multi-stage gate drive circuit for silicon carbide power devices according to claim 1, characterized in that, It also includes an active Miller clamping unit, which the digital control unit activates in the later stages of the shutdown process to prevent parasitic conduction caused by the Miller effect.

7. The adaptive multi-stage gate drive circuit for silicon carbide power devices according to claim 1, characterized in that, The digital control unit is a field-programmable gate array, a complex programmable logic device, or a microcontroller with integrated special purpose logic circuits.

8. An adaptive multi-stage gate driving method for driving silicon carbide power devices, characterized in that, Includes the following steps, S1. Receive externally input PWM signals to initiate the turn-on or turn-off process; S2. During the transient period of the turn-on or turn-off process, monitor in real time at least one physical quantity characterizing the switching state of the silicon carbide power device. S3. Based on the monitored physical quantities, identify the current stage of the switching process, wherein the stage includes at least the pre-Miller plateau stage, the Miller plateau stage, and the post-Miller plateau stage; S4. Based on the identified stage, dynamically adjust the driving impedance applied to the gate of the silicon carbide power device to provide different driving current intensities for different stages.

9. The adaptive multi-stage gate driving method for driving silicon carbide power devices according to claim 8, characterized in that, During the activation process In the Miller platform stage, low drive impedance is used to quickly boost the gate-source voltage to the Miller voltage; During the Miller plateau phase, a high drive impedance is used to slow down the rate of decrease in drain-source voltage; In the later stages after the Miller platform, low drive impedance is used again to quickly charge the gate to the target turn-on voltage.

10. The fabrication process of an adaptive multi-stage gate drive circuit for silicon carbide power devices according to claim 9, characterized in that, The shutdown process includes negative bias shutdown and activation of active Miller clamp in the later stage of shutdown to enhance the reliability of shutdown.

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