Hardware decoding device and method for implementing sliding window iterative decoding

Abstract

The application relates to the field of electronic information technology and discloses a hardware decoding device and a method for realizing iterative decoding of the hardware decoding device, which can improve decoding efficiency and maximum throughput. The hardware decoding device comprises a data storage unit, which stores W data blocks {B j , B i+1 , …, B j+w‑1} input in time sequence; a data selector, which forms a component code set according to a group of associated data blocks in the W data blocks, the group of associated data blocks having L+1 data blocks; and a component code decoder, which reads multiple component code sets from the data selector for decoding, repeats an iteration once, decodes the component code sets in the order from small to large according to the associated data block numbers, selectively inserts the decoding of associated data blocks irrelevant to the data blocks involved in the two groups of associated data blocks in a non-current decoding iteration process between the decoding of the two groups of associated data blocks, and writes the decoding result into the corresponding position of the data block in the data storage unit after completing the decoding.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and more specifically to a hardware decoding device and a method for implementing iterative decoding thereon. Background Technology

[0002] In hardware decoding within the field of electronic information technology, the decoding method employed significantly impacts the performance of the decoding device. Spatial coupled codes are currently commonly used, and almost all traditional codes, such as BCH codes and RS codes, can be used as component codes for spatial coupled codes. Generally, using spatial coupled codes outperforms using only component codes, and low-latency sliding window iterative decoding algorithms can be employed to further improve decoding efficiency.

[0003] However, due to the latency in the component code decoder in hardware, the sliding window iterative decoding process for spatially coupled codes is not fast or efficient enough. There is room for further reduction in latency and improvement in decoding efficiency.

[0004] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not intended to imply that it is prior art that has been disclosed, simply because it is included in this section. Summary of the Invention

[0005] The purpose of this invention is to provide a hardware decoding device and a method for implementing iterative decoding, which can reduce latency and improve decoding efficiency.

[0006] In this invention, a hardware decoding device is provided, comprising:

[0007] A data storage device, wherein W data blocks {B} are input sequentially in time. i B i+1 , ..., B i+W-1}, where W represents the decoding window length and i represents the sequence number of the earliest data block that entered the current decoding window;

[0008] A data selector, wherein the data selector constructs a component code set based on a set of associated data blocks from the W data blocks, wherein the set of associated data blocks has L+1 data blocks, where L represents the memory depth, and L+1 < W; and

[0009] A component code decoder reads multiple component code sets from the data selector, decodes each component code set, and repeats this process I times, where XY j0 Y j1 …Y jL X represents the decoding number of the component code set in the decoding process, X represents the iteration number within the current decoding window, and Y represents the decoding number of the component code set in the decoding process. j0 Yj1 …Y jL This indicates that the component code set is associated with L+1 data blocks B. j0 B j1 ... B jL Associated, where X∈[0, I-1], jp∈[i, i+W-1], p∈[0, L], and jp-1<jp<jp+1, in each decoding iteration of each decoding window, according to the associated data block B j0 B j1 ... B jL The component code set is decoded sequentially from smallest to largest in the middle jp. Between the decoding of two sets of associated data blocks, the decoding of associated data blocks that are not related to the data blocks involved in the current decoding iteration process is selectively inserted. After the component code decoder completes the decoding of the component code set associated with each data block, the decoding result is written to the corresponding position of the data block in the data storage.

[0010] In a preferred embodiment, selectively inserting the decoding of an associated data block that is not part of the current decoding iteration and is unrelated to the data blocks involved in the two sets of associated data blocks between the decoding of the two sets of associated data blocks specifically includes:

[0011] Selectively insert the decoding of associated data blocks that are unrelated to the data blocks involved in the last decoding iteration of the previous decoding window between the decoding of the two sets of associated data blocks; or,

[0012] The decoding of associated data blocks that are unrelated to the data blocks involved in the two sets of associated data blocks is selectively inserted between the decoding of the two sets of associated data blocks in the next decoding iteration of the current decoding window.

[0013] In a preferred embodiment, selectively inserting the decoding of an associated data block that is not part of the current decoding iteration and is unrelated to the data blocks involved in the two sets of associated data blocks between the decoding of the two sets of associated data blocks specifically includes:

[0014] The decoding of associated data blocks formed by adjacent data blocks that are not related to the data blocks involved in the two sets of associated data blocks is selectively inserted between the decoding of the two sets of two associated data blocks.

[0015] In a preferred embodiment, the memory depth L is 1, and each component code set is associated with two adjacent associated data blocks, where XY j Y j+1 X represents the decoding number of the component code set in the decoding process, X represents the iteration number within the current decoding window, and Y represents the decoding number of the component code set in the decoding process. j Yj+1 This indicates that the component code set and the two associated data blocks B j and B j+1 Associated, X∈[0, I-1], j∈[i, ​​i+W-2], in each decoding iteration of each decoding window, according to the associated data block B j B j+1 The component code sets are decoded sequentially from smallest to largest. Between two sets of associated data blocks, associated data blocks that are not related to the data blocks involved in the two sets of associated data blocks in the next iteration are decoded.

[0016] In a preferred embodiment, the decoding window length W is 6, the number of iterations I is 3, and the memory depth L = 1.

[0017] When i = 1, the data block in the decoding window is {B1, B2, ..., B6};

[0018] When i = 2, the data block in the decoding window is {B2, B3, ..., B7};

[0019] When i = 3, the data block in the decoding window is {B3, B4, ..., B8};

[0020] When i = 4, the data block in the decoding window is {B4, B5, ..., B9};

[0021] When i = 5, the data block within the decoding window is {B5, B6, ..., B}. a};

[0022] When i = 2 to i = 4, the decoding number is:

[0023] 0-23, 2-56, 0-34, Delay, 0-45, 1-23, 0-56, 1-34, 0-67, 1-45, 2-23, 1-56, 2-34, 1-67, 2-45, Delay, 2-56;

[0024] 0-34, 2-67, 0-45, Delay, 0-56, 1-34, 0-67, 1-45, 0-78, 1-56, 2-34, 1-67, 2-45, 1-78, 2-56, Delay, 2-67;

[0025] 0-45, 2-78, 0-56, Delay, 0-67, 1-45, 0-78, 1-56, 0-89, 1-67, 2-45, 1-78, 2-56, 1-89, 2-67, Delay, 2-78, 0-56, 2-89.

[0026] In a preferred embodiment, it includes:

[0027] The delay includes the decoding delay of the component code set, the delay of reading the data block from the data memory, and the delay of writing the decoding result of the component code set into the data memory. The component code decoder requires n cycles to decode each associated data block, and the delay occupies m cycles, where n > m.

[0028] In a preferred embodiment, the decoding window length W is 7, the number of iterations I is 3, and the memory depth L = 1.

[0029] When i = 1, the data block in the decoding window is {B1, B2, ..., B7};

[0030] When i = 2, the data block in the decoding window is {B2, B3, ..., B8};

[0031] When i = 3, the data block in the decoding window is {B3, B4, ..., B9};

[0032] When i = 4, the data block within the decoding window is {B4, B5, ..., B}. a};

[0033] When i = 5, the data block within the decoding window is {B5, B6, ..., B}. b};

[0034] When i = 2 to i = 4, the decoding number is:

[0035] 0-23, 2-56, 0-34, 2-67, 0-45, 1-23, 0-56, 1-34, 0-67, 1-45, 0-78, 2-23, 1-56, 2-34, 1-67, 2-45, 1-78, 2-56:

[0036] 0-34, 2-67, 0-45, 2-78, 0-56, 1-34, 0-67, 1-45, 0-78, 1-56, 0-89, 2-34, 1-67, 2-45, 1-78, 2-56, 1-89, 2-67;

[0037] 0-45, 2-78, 0-56, 2-89, 0-67, 1-45, 0-78, 1-56, 0-89, 1-67, 0-9a, 2-45, 1-78, 2-56, 1-89, 2-67, 1-9a, 2-78, 0-56, 2-9a.

[0038] In a preferred embodiment, it also includes:

[0039] The data output module is coupled to the output of the data memory, and the data memory stores the B... i The decoding result of the data block is output to the data output module.

[0040] In a preferred embodiment, it also includes:

[0041] A data input module, coupled to the input of the data storage device, stores the B data in the data storage device. i After the decoding result of the data block is output to the data output module, the data input module inputs a new data block to the data memory.

[0042] This application also discloses a sliding window iterative decoding method, including:

[0043] Input W data blocks {B} according to time. i B i+1 , ..., B i+W-1} To the data storage, W represents the decoding window length, and i represents the sequence number of the earliest data block that entered within the current decoding window;

[0044] The data selector constructs a component code set based on a set of associated data blocks from W data blocks in the data storage, wherein the set of associated data blocks has L+1 data blocks, where L represents the memory depth, and L+1 < W; and

[0045] The component code decoder reads multiple component code sets from the data selector, decodes each component code set, and repeats this process I times, where XY j0 Y j1 …Y jL X represents the decoding number of the component code set in the decoding process, X represents the iteration number within the current decoding window, and Y represents the decoding number of the component code set in the decoding process. j0 Y j1 …Y jL This indicates that the component code set is associated with L+1 data blocks B. j0 B j1 ... B jL Associative, X∈[0, I-1], jp∈[i, i+W-1], p∈[0, L], and jp-1<jp<jp+1, in each decoding iteration of each decoding window, according to the associated data block B j0 B j1 ... B jL The component code sets are decoded sequentially from smallest to largest in the middle JP. Between the decoding of two sets of associated data blocks, the decoding of associated data blocks that are not part of the current decoding iteration and are unrelated to the data blocks involved in the two sets of associated data blocks is selectively inserted; and

[0046] After the component code decoder completes the decoding of the component code set associated with each data block, it writes the decoding result to the corresponding location of the data block in the data storage.

[0047] The main differences and effects of the embodiments of the present invention compared with the prior art are as follows:

[0048] This application enables the decoding of other data blocks by utilizing the delay idle time of the component code decoder of the spatially coupled code during sequential decoding in the hardware decoding device. This saves the total decoding time for each decoding window, improves decoding efficiency, and increases the maximum throughput that the entire hardware decoding device can support.

[0049] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of three spatially coupled codes.

[0052] Figure 2 These are schematic diagrams of the structures of two types of decoding windows.

[0053] Figure 3(a) is a schematic diagram of the decoding process by sliding the decoding window to the right.

[0054] Figure 3(b) is a schematic diagram of the decoding process by sliding the decoding window to the left.

[0055] Figure 4 This is a decoding timing diagram with L=1, I=3, and W=6.

[0056] Figure 5 This is a schematic diagram of the operational structure of a hardware decoding device according to one embodiment of this application.

[0057] Figure 6 This is a decoding timing diagram with L=1, I=3, and W=6 according to one embodiment of this application.

[0058] Figure 7This is a decoding timing diagram with L=1, I=1, and W=6 according to one embodiment of this application;

[0059] Figure 8 This is a decoding timing diagram with L=1, I=3, and W=6 according to one embodiment of this application.

[0060] Figure 9 This is a decoding timing diagram with L=1, I=3, and W=7 according to one embodiment of this application.

[0061] Figure 10 This is a hardware implementation clock diagram with L=1, I=3, and W=6 according to one embodiment of this application.

[0062] The labels in each of the attached figures are as follows:

[0063] 1-Data storage;

[0064] 101 - Decoding Window;

[0065] 2-Data Selector;

[0066] 3-component code decoder. Detailed Implementation

[0067] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0068] Terminology Explanation:

[0069] A hardware decoding device, also known as a decoding unit, is a logic circuit. It converts input encoded data that is affected by noise into decoded output data, thereby recovering the encoded data. It has wide applications in communication systems, digital circuits, and computer systems.

[0070] Spatial coupled codes are a method for constructing new codes based on traditional coding techniques. They are long codes with convolutional structures obtained through operations such as interleaving and superposition of component codes. The coding concept of spatial coupled codes combines block coding and recursive convolutional coding. In spatial coupled codes, the two component codes are not independent but are "coupled" together through a certain relationship.

[0071] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments in the prior art will be described in further detail below with reference to the accompanying drawings.

[0072] Figure 1The diagrams show the structures of three different spatially coupled codes. The relationships between the data block, the spatially coupled code, the component code, and the decoding window 101 are explained in detail below:

[0073] {B i B i+1 , ..., B i+W-1 The entire group, ..., is used to represent a spatially coupled code, where B... i B i+1 ... B i+W-1 Each of the following represents a data block. To reduce decoding latency, spatially coupled codes typically employ a sliding window strategy for decoding, for example, sequentially decoding W data blocks {B}. i B i+1 , ..., B i+W-1 The input is within the decoding window 101, where W represents the length of the decoding window (i.e., the number of data blocks within the decoding window 101), and i represents the sequence number of the earliest data block entering the current decoding window 101. During the decoding process, the earliest data block entering the decoding window 101 is output, and new data blocks are added. See the following section for a more detailed description of the sliding window iterative decoding process.

[0074] W data blocks {B} within decoding window 101 i B i+1 , ..., B i+W-1 Component codes are constructed through encoding. For example, a set of associated data blocks is selected from W data blocks to form a set of component codes. This set of associated data blocks has L+1 data blocks, where L represents the memory depth. A portion of data is selected from each data block in this set of associated data blocks to form a component code. All bits in this set of associated data blocks can form N component codes (a set of component codes), and each set of component codes is associated with this set of associated data blocks.

[0075] Taking a memory depth of L=1 as an example, this means that one component code set is associated with two data blocks, and these two associated data blocks can be adjacent. For example... Figure 1 As shown in (a) in the figure, B i and B i+1 Each represents a data block. From B i and B i+1 Take some bits from each of the two blocks to form one component code; then take some more bits from each block to form another component code. All the bits from these two blocks can form N component codes (a set of component codes). Similarly, B... i+1 and B i+2 All the bits in the code also constitute N component codes (another set of component codes). For example, B i and B i+1 The bits represented by the blue portion are extracted to form the first component code; Bi and B i+1 The bits represented by the yellow portion are extracted to form the second component code; B i+1 and B i+2 The bits represented by the red portion are extracted to form the third component code. It should be understood that one bit represents a minimum unit of information. B i+1 and B i+2 It is two associated data blocks related to N component codes, B i+1 and B i+2 These form a set of associated data blocks. Similarly, every two subsequent data blocks can form N component codes. From another perspective, the bits in each data block are simultaneously protected by two different component codes from the preceding and following component code sets, thus improving the performance of this error-correcting code.

[0076] Taking a memory depth of L=2 as an example, this means that one component code set is associated with three data blocks. These three associated data blocks can be consecutive and adjacent, such as... Figure 1 As shown in (b) above. Three associated data blocks B i B i+1 and B i+2 They are consecutively adjacent, B i B i+1 and B i+2 The bits represented by the blue portion are extracted to form the fourth component code. In another embodiment, these three associated data blocks can be non-contiguous and adjacent, such as... Figure 1 As shown in (c) above. Three associated data blocks B i B i+1 and B i+3 B is not consecutively adjacent. i B i+1 and B i+3 The bits represented by the blue portion are extracted to form the fifth component code, B. i+1 B i+2 and B i+4 The bits represented by the yellow portion are extracted to form the sixth component code.

[0077] from Figure 1 As can be seen, the number of bits in the first to sixth component codes is the same. That is to say, at different memory depths L, the number of bits selected in each associated data block may be different, but the total number is consistent.

[0078] Within decoding window 101, iterative decoding is performed on each component code set. The sliding window iterative decoding process is as follows: Figure 2 As shown, where Figure 2 In (a), the decoding window length is W, the number of iterations is I, and the current decoding window 101 corresponds to {B}.i B i+1 , ..., B i+w-1}. B i B is the earliest data block to enter within decoding window 101. i+w-1 The latest data block within decoding window 101, and the earliest data block B within the current decoding window 101. i After decoding is complete, output B. i Enter B at the same time i+w Input new data blocks in sequence, and slide the decoding window 101 to the right, corresponding to {B i+1 B i+2 , ..., B i+w Then, perform the above decoding process again.

[0079] In another embodiment, such as Figure 2 As shown in (b), the current decoding window 101 corresponds to {B} i-W+1 , ..., B i-2 B i-1 B i}. Among them, B i-w+1 B is the earliest data block to enter within decoding window 101. i The latest data block within decoding window 101, and the earliest data block B within the current decoding window 101. i-w+1 After decoding is complete, output B. i-w+1 Enter B at the same time i+1 The decoding window 101 slides to the left, corresponding to {B} i-W+1 , ..., B i-2 B i-1 B i Then, the above decoding process is repeated. This continues, sequentially outputting the earliest data block entering the decoding window 101; different decoding windows 101 are defined depending on the different data blocks within the decoding window 101.

[0080] Slide the decoding window 101 to the right (e.g.) Figure 2 The decoding of each group of associated data blocks within the decoding window 101 is shown in Figure 3(a). During the decoding process, the data blocks {B} within the decoding window 101 are decoded... i B i+1 , ..., B i+W-1 The component code set formed by the encoding is input into the component code decoder 3 for decoding. For example, taking L=1 as an example, the component code set is formed by encoding two consecutive adjacent data blocks, that is, [B i B i+1 ]、[B i+1 B i+2 ]、…、[B i+w-2 B i+w-1The encoding constitutes a set of (W-1)N component codes. Once all (W-1)N component codes are decoded, one iteration is complete. Repeating this process once completes all decoding within the current decoding window 101, outputting B. i Similarly, the decoding window 101 slides to the left (as shown). Figure 2 The decoding of each group of associated data blocks in the decoding window 101 is shown in Figure 3(b).

[0081] In the hardware implementation, due to the decoding delay of component code decoder 3, in Figure 3(a), decoding window 101 slides to the right, [B i B i+1 The decoded result must be written back to the data block before [B] can be processed. i+1 B i+2 The decoding of [B]. In Figure 3(b), the decoding window 101 slides to the left, [B] i B i-1 The decoded result must be written back to the data block before [B] can be processed. i-1 B i-2 The decoding order is as follows. For example, assuming W = 6 and I = 3, when i = 2, the data blocks in decoding window 101 are B2, B3, B4, B5, B6, and B7. When i = 3, the data blocks in decoding window 101 are B3, B4, B5, B6, B7, and B8. The decoding order in decoding window 101 when i = 3 is as follows: Figure 4 As shown, using XY j Y j+1 Indicates the decoding number (corresponding to respectively) Figure 4 (a colored square in the matrix), where X represents the iteration number, Y... j Y j+1 Indicates two data blocks B j B j+1 The associated component code set, X∈[0, I-1], j∈[i, ​​i+W-2]. For example, 0-23 represents the 0th decoding iteration of the component code set associated with data blocks B2 and B3, 0-34 represents the 0th decoding iteration of the component code set associated with data blocks B3 and B4, and so on. Between each two component code sets, there exists a delay DLY (corresponding to...) Figure 4 The gray square in the image is because the decoding result of the previous component code set needs to be written to the corresponding data block before the decoding of the next associated data block can be performed, and both writing and reading take time.

[0082] Suppose there is a RAM that stores W data blocks, the decoding device will... Figure 4The clock sequence number is used to read data from two adjacent data blocks in RAM for component code decoder 3 to decode. That is, in each decoding iteration of each decoding window 101, after decoding, the corrected data is written back to the same address in RAM. However, in this decoding method, there is a delay DLY between every two decoding frames.

[0083] In one embodiment, the delay DLY includes the sum of the decoding delay of the component code set, the delay of reading the data block from the data memory 1, and the delay of writing the data block to the data memory 1. The component code decoder 3 requires n cycles to decode each component code set, and the delay occupies m cycles, generally n > m. The duration of DLY can be calculated using the decoding window length W, the number of iterations I, the n cycles required to decode each associated data block, and the m cycles occupied by one DLY. Combining the above parameters, the total time consumed within a decoding window 101 is (W-1)*In + (W-2)*Im, where (W-2)*Im is the number of cycles occupied by all DLYs in this decoding, which are not used and are wasted.

[0084] This reveals that when performing sequential decoding using spatially coupled codes in hardware, the decoding of component codes suffers from DLY (Dependency-Like) issues, resulting in insufficient speed and efficiency.

[0085] To address the issue of insufficient decoding speed and efficiency caused by DLY in component code decoding, this application proposes a method for decoding other data blocks using DLY, thereby reducing the decoding time of each decoding window 101, improving decoding efficiency, and increasing the maximum throughput that the entire decoding device can support.

[0086] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0087] One embodiment of this application relates to a hardware decoding device, the structure of which is as follows: Figure 5 As shown, the device includes: a data memory 1, a data selector 2, and a component code decoder 3.

[0088] The data memory 1 is connected to the data selector 2, and the data selector 2 is connected to the component code decoder 3.

[0089] Data memory 1 stores W data blocks {B} input sequentially in time. i B i+1 , ..., B i+W-1}, where W represents the decoding window length, and i represents the sequence number of the earliest data block entered within the current decoding window 101. The term "decoding window length" can be understood as the number of data blocks within the decoding window 101. The W data blocks input sequentially are as follows: Figure 1As shown in Figure 3(a), the relationship between the decoding window 101 and the data blocks is illustrated. "In chronological order" means that the data blocks enter the decoding window 101 sequentially according to their chronological order for decoding.

[0090] Data selector 2 constructs a component code set based on a set of associated data blocks from W data blocks, and selects multiple sets of associated data blocks to construct multiple component code sets. Each component code set is associated with a set of associated data blocks from W data blocks, where a set of associated data blocks has L+1 data blocks, where L represents the memory depth, and L+1 < W.

[0091] Component code decoder 3 reads multiple component code sets involved in multiple sets of associated data blocks from data selector 2, decodes each component code set, and repeats the process I times, where XY j0 Y j1 …Y jL X represents the decoding number of the component code set during the decoding process, X represents the iteration number within the current decoding window 101, and Y represents the decoding sequence number. j0 Y j1 …Y jL This indicates that the component code set is associated with L+1 data blocks B. j0 B j1 ... B jL Associative, X∈[0, I-1], jp∈[i, i+W-1], p∈[0, L], and jp-1<jp<jp+1, in each decoding iteration of each decoding window 101, according to the associated data block B j0 B j1 ... B jL The component code set is decoded sequentially from smallest to largest in the middle jp. Between the decoding of the two sets of associated data blocks, the decoding of associated data blocks that are not in the current decoding iteration process and are not related to the data blocks involved in the two sets of associated data blocks is selectively inserted. After the component code decoder 3 completes the decoding of the component code set associated with each data block, it writes the decoding result to the corresponding position of the data block in the data memory 1.

[0092] Specifically, in one embodiment, it is assumed that there is a set of component codes, where a single decoding of the set of component codes is represented as XY. j0 Y j1 …Y jL This involves L+1 associated data blocks B. j0 B j1 ... B jL These associated data blocks are listed as a set of associated data blocks. There is another set of component codes, where a single decoding of this set of component codes is represented as XY. j1 Y j2 …Y jL+1This involves L+1 associated data blocks B. j1 B j2 ... B jL+1 These associated data blocks are listed as another set of associated data blocks, and there is a delay between the decoding of these two sets of associated data blocks.

[0093] Given the decoding time required for a decoding window of 101, it can be calculated using the decoding window length W, the number of iterations I, the n time steps required to decode each associated data block, and the m time steps occupied by a DLY. Delaying the DLY would result in a waste of (W-2)*Im time steps. Therefore, this application proposes performing decoding unrelated to the preceding and following associated data blocks during certain DLY times. That is, selectively inserting the decoding of associated data blocks that are not in the current decoding iteration process and are unrelated to the data blocks involved in either of the two sets of associated data blocks between the decoding of two adjacent sets of associated data blocks. Several embodiments are provided to illustrate this step of selectively inserting the decoding of associated data blocks that are not in the current decoding iteration process and are unrelated to the data blocks involved in either of the two sets of associated data blocks between the decoding of two sets of associated data blocks:

[0094] In one embodiment, the decoding of an associated data block that is unrelated to the data blocks involved in either set of associated data blocks is selectively inserted between the decoding of the two sets of associated data blocks, during the last decoding iteration of the previous decoding window 101. Figure 6 In the illustrated embodiment, when i = 2, 2-56 is inserted between 0-23 and 0-34.

[0095] In another embodiment, the decoding of associated data blocks that are unrelated to the data blocks involved in either set of associated data blocks is selectively inserted between the decoding of the two sets of associated data blocks, during the next decoding iteration of the current decoding window 101. Figure 6 In the example shown, when i = 2, 1-23 is inserted between 0-45 and 0-56.

[0096] In another embodiment, the decoding of an associated data block, which is not related to the data blocks involved in either of the two sets of associated data blocks but is formed by adjacent data blocks, is selectively inserted between the decoding of the two sets of associated data blocks. Figure 6 In the example, when i=2, 2-56 is inserted between 0-23 and 0-34 instead of 2-67.

[0097] Specifically, in the case of L=1, in one embodiment, each component code set is associated with two associated data blocks, where XY j Y j+1 X represents the decoding number of the component code set during the decoding process, X represents the iteration number within the current decoding window 101, and Y represents the decoding sequence number. j Y j+1This represents the component code set and two associated data blocks B. j and B j+1 Associated, X∈[0, i-1], j∈[i, ​​i+w-2], in each decoding iteration of each decoding window 101, according to the associated data block B j B j+1 The component code sets are decoded sequentially from smallest to largest. Between two sets of associated data blocks, associated data blocks that are not related to the data blocks involved in the two sets of associated data blocks in the next iteration are decoded.

[0098] Figure 6 This is a decoding timing diagram when W=6 according to one embodiment of this application. The following is a... Figure 6 In a detailed description, in one embodiment, the decoding window length W is 6, the number of iterations I is 3, and the memory depth L = 1.

[0099] When i = 1, the data block within the decoding window 101 is {B1, B2, ..., B6}. Figure 6 The center is displayed in red;

[0100] When i = 2, the data block within the decoding window 101 is {B2, B3, ..., B7}. Figure 6 It is displayed in green;

[0101] When i = 3, the data block within decoding window 101 is {B3, B4, ..., B8}. Figure 6 It is displayed in yellow;

[0102] When i = 4, the data block within decoding window 101 is {B4, B5, ..., B9}. Figure 6 The center is displayed in blue;

[0103] When i = 5, the data block within the decoding window 101 is {B5, B6, ..., B...} 10},exist Figure 6 It is displayed in purple;

[0104] When i = 2 to i = 4, the decoding number is:

[0105] 0-23, 2-56, 0-34, Delay, 0-45, 1-23, 0-56, 1-34, 0-67, 1-45, 2-23, 1-56, 2-34, 1-67, 2-45, Delay, 2-56;

[0106] 0-34, 2-67, 0-45, Delay, 0-56, 1-34, 0-67, 1-45, 0-78, 1-56, 2-34, 1-67, 2-45, 1-78, 2-56, Delay, 2-67;

[0107] 0-45, 2-78, 0-56, Delay, 0-67, 1-45, 0-78, 1-56, 0-89, 1-67, 2-45, 1-78, 2-56, 1-89, 2-67, Delay, 2-78, 0-56, 2-89.

[0108] and Figure 4 The comparison reveals that the green blocks 0-23 and 0-34 were originally DLY, but the red blocks 2-56 were inserted because B5, B6, B2, B3, and B4 in the previous iteration are unrelated. The DLY between the green blocks 0-45 and 0-56 can be used to process the green blocks 1-23 because data blocks B2 and B3 are unrelated to data blocks B4, B5, and B6. Data blocks B2 and B3 do not need to wait for the decoding results of data blocks B4 and B5 to be written back before decoding.

[0109] Based on this idea, most of the time spent on DLYs in existing technologies can be used to decode component code sets of other associated data blocks. In the decoding timing proposed in this application, the number of DLYs in each decoding window 101 can be reduced to 2, and the total time can be reduced to (W-1)In+2m. Most data between adjacent decoding frames are unrelated, therefore DLYs do not need to be inserted.

[0110] Figure 7 The detailed decoding process is shown when i=1 and W=6. It can be seen that there is no overlap in the horizontal direction between the rounded rectangles of every two adjacent numbers, so there is no timing conflict.

[0111] Figure 8 The diagram illustrates the detailed decoding process from i=2 to i=4, with the index of each rounded rectangle corresponding to... Figure 6 The serial numbers match, and the color of the rounded rectangle also matches. Figure 6 Consistently, the horizontal position of the rounded rectangles is aligned with the sequence number of the corresponding associated data block. It can be seen that there is no horizontal overlap between any two adjacent rounded rectangles, therefore there are no timing conflicts.

[0112] Figure 9 This is a decoding timing diagram when W=7 according to one embodiment of this application. The following is a... Figure 9 In a detailed description, in one embodiment, the decoding window length W is 7, the number of iterations I is 3, and the memory depth L = 1.

[0113] When i = 1, the data block within the decoding window 101 is {B1, B2, ..., B7}. Figure 9 The center is displayed in red;

[0114] When i = 2, the data block within the decoding window 101 is {B2, B3, ..., B8}. Figure 9 It is displayed in green;

[0115] When i = 3, the data block within decoding window 101 is {B3, B4, ..., B9}. Figure 9 It is displayed in yellow;

[0116] When i = 4, the data block within the decoding window 101 is {B4, B5, ..., B...} a},exist Figure 9 The center is displayed in blue;

[0117] When i = 5, the data block within the decoding window 101 is {B5, B6, ..., B...} b},exist Figure 9 It is displayed in purple;

[0118] When i = 2 to i = 4, the decoding number is:

[0119] 0-23, 2-56, 0-34, 2-67, 0-45, 1-23, 0-56, 1-34, 0-67, 1-45, 0-78, 2-23, 1-56, 2-34, 1-67, 2-45, 1-78, 2-56;

[0120] 0-34, 2-67, 0-45, 2-78, 0-56, 1-34, 0-67, 1-45, 0-78, 1-56, 0-89, 2-34, 1-67, 2-45, 1-78, 2-56, 1-89, 2-67;

[0121] 0-45, 2-78, 0-56, 2-89, 0-67, 1-45, 0-78, 1-56, 0-89, 1-67, 0-9a, 2-45, 1-78, 2-56, 1-89, 2-67, 1-9a, 2-78, 0-56, 2-9a.

[0122] In this situation, all DLYs were utilized.

[0123] In one embodiment, the hardware decoding device further includes: a data output module (not shown in the figure), the data output module being coupled to the output of the data memory 1, the data memory 1 storing B i The decoding result of the data block is output to the data output module.

[0124] In one embodiment, the hardware decoding device further includes: a data input module (not shown in the figure), the data input module being coupled to the input of the data memory 1, wherein the data memory 1 stores B iAfter the decoding result of the data block is output to the data output module, the data input module inputs a new data block into the data memory 1.

[0125] The hardware implementation of the pressing structure diagram is as follows: Figure 10 As shown in the figure. Assuming n=6 and DLY=5, it can be seen that the decoding of sequence number 22 requires a total of 6 cycles. When the decoding of each cycle is completed and needs to be written back to RAM, the data block corresponding to the write address and the read address of the same cycle does not conflict.

[0126] This application also discloses an iterative decoding method, which includes the following steps:

[0127] Step 1, input W data blocks {B} according to time. i B i+1 , ..., B i+W-1} To data memory 1, W represents the decoding window length, and i represents the sequence number of the earliest data block that entered within the current decoding window 101;

[0128] Step 2: The data selector 2 constructs a component code set based on a set of associated data blocks from the W data blocks in the data storage 1. Each component code set is associated with a set of associated data blocks from the W data blocks, where a set represents L+1 blocks, L represents the memory depth, and L+1 < W.

[0129] Step 3: Component code decoder 3 reads multiple component code sets involved in multiple sets of associated data blocks from data selector 2, decodes each component code set, and repeats this process I times, where XY j0 Y j1 …Y jL X represents the decoding number of the component code set in component code decoder 3, X represents the iteration number within the current decoding window 101, and Y represents the decoding number within the component code decoder 3. j0 Y j1 …Y jL Indicates L+1 associated data blocks B j0 B j1 ... B jL Associative, X∈[0, I-1], jp∈[i, i+W-1], p∈[0, L], and jp-1<jp<jp+1, in each decoding iteration of each decoding window 101, according to the associated data block B j0 B j1 ... B jL In the middle JP, the component code sets are decoded sequentially from smallest to largest. Between the decoding of the two sets of associated data blocks, the decoding of associated data blocks that are not in the current decoding iteration process and are not related to the data blocks involved in the two sets of associated data blocks is selectively inserted.

[0130] Step 4: After the component code decoder 3 completes the decoding of the component code set associated with each data block, it writes the decoding result to the corresponding location of the data block in the data memory 1.

[0131] It should be noted that in the claims and specification of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0132] All documents mentioned in this invention are incorporated herein by reference as if each document were individually incorporated by reference. Furthermore, it should be understood that after reading the foregoing teachings of this invention, those skilled in the art can make various alterations or modifications to this invention, and these equivalent forms also fall within the scope defined by the appended claims.

Claims

1. A hardware decoding device, characterized in that, The method comprises the following steps: a data storage storing W data blocks {B i , B i+1 , ……,B i+W-1} inputted in time sequence, W represents the length of the decoding window, and i represents the serial number of the data block entering the earliest in the current decoding window; a data selector selects a component code set according to a group of associated data blocks in the W data blocks, wherein the group of associated data blocks has L+1 data blocks, L represents a memory depth, and L+1 In addition, the method selectively inserts the decoding of the associated data blocks which are not related to the data blocks involved in the decoding of the two groups of associated data blocks in the non-current decoding iteration process between the decoding of the two groups of associated data blocks, and specifically comprises the following steps: Component code decoder, which reads multiple sets of component codes from the data selector, decodes each set of component codes, and repeats the iteration I times, where X - Y j0 Y j1 …Y jL represents the decoding number of the set of component codes during the decoding process, X represents the iteration sequence number within the current decoding window, Y j0 Y j1 …Y jL represents that the set of component codes is associated with L + 1 associated data blocks B j0 、B j1 、……、B jL where X ∈ [0, I - 1], jp represents j0 to j L , jp ∈ [i, i + W - 1], p ∈ [0, L], and jp - 1 < jp < jp + 1. During each decoding iteration of each decoding window, the sets of component codes are decoded in ascending order of jp in the associated data blocks B j0 、B j1 、……、B jL . The decoding of an associated data block that is not in the current decoding iteration and is not related to any of the data blocks involved in the two sets of associated data blocks is selectively inserted between the decoding of the two sets of associated data blocks. Moreover, after the component code decoder completes the decoding of the set of component codes associated with each data block, the decoding result is written to the corresponding location of the data block in the data memory.

2. The hardware decoding device of claim 1, wherein, In addition, the method selectively inserts the decoding of the associated data blocks which are not related to the data blocks involved in the decoding of the two groups of associated data blocks in the non-current decoding iteration process between the decoding of the two groups of associated data blocks, and specifically comprises the following steps: In addition, the method selectively inserts the decoding of the associated data blocks which are not related to the data blocks involved in the decoding of the two groups of associated data blocks in the non-current decoding iteration process between the decoding of the two groups of associated data blocks, and specifically comprises the following steps: In addition, the method selectively inserts the decoding of the associated data blocks which are not related to the data blocks involved in the decoding of the two groups of associated data blocks in the non-current decoding iteration process between the decoding of the two groups of associated data blocks, and specifically comprises the following steps:

3. The hardware decoding device of claim 1, wherein, The length of the decoding window W is 6, the number of iterations I is 3, the memory depth L=1, When i=1, the data blocks in the decoding window are {B1, B2, ……, B6}; 4. The hardware decoding device of claim 1, wherein, The memory depth L is 1, each component code set is associated with two adjacent associated data blocks, wherein, X-Y j Y j+1 represents the decoding number of the component code set in the decoding process, X represents the iteration sequence number in the current decoding window, Y j Y j+1 represents that the component code set is associated with two associated data blocks B j and B j+1 , X∈[0, I-1], j∈[i, i+W-2], in each decoding iteration process of each decoding window, the component code set is decoded in the order of j from small to large in the associated data blocks B j , B j+1 , between the two groups of associated data blocks, the associated data blocks which are not related to the data blocks involved in the two groups of associated data blocks in the next iteration process are decoded.

5. The hardware decoding device of claim 4, wherein, When i=2, the data blocks in the decoding window are {B2, B3, ……, B7}; When i=3, the data blocks in the decoding window are {B3, B4, ……, B8}; When i=4, the data blocks in the decoding window are {B4, B5, ……, B9}; The decoding numbers of the decoding performed when i=2 to i=4 are 0-23, 2-56, 0-34, delay, 0-45, 1-23, 0-56, 1-34, 0-67, 1-45, 2-23, 1-56, 2-34, 1-67, 2-45, delay, 2-56; When i = 5, the data blocks in the coding window are {B5, B6, ……, B a} 0-34, 2-67, 0-45, delay, 0-56, 1-34, 0-67, 1-45, 0-78, 1-56, 2-34, 1-67, 2-45, 1-78, 2-56, delay, 2-67; 0-45, 2-78, 0-56, delay, 0-67, 1-45, 0-78, 1-56, 0-89, 1-67, 2-45, 1-78, 2-56, 1-89, 2-67, delay, 2-78, 0-56, 2-89. The method comprises the following steps: The delay comprises the sum of the decoding delay of the component code set, the delay of reading the data blocks from the data storage, and the delay of writing the decoding result of the component code set into the data storage, the time length required by the component code decoder for decoding each associated data block is n, and the time length of the delay is m, wherein n>m.

6. The hardware decoding device of claim 5, wherein, ​ ​ 7. The hardware decoding device of claim 4, wherein, The coding window length W is 7, the iteration number I is 3, and the memory depth L = 1, When i = 1, the data blocks in the coding window are {B1, B2, ……, B7}; When i = 2, the data blocks in the coding window are {B2, B3, ……, B8}; When i = 3, the data blocks in the coding window are {B3, B4, ……, B9}; When i = 4, the data blocks in the coding window are {B4, B5, ……, B a} When i = 5, the data blocks in the coding window are {B5, B6, ……, B b} The coding number of coding when i = 2 to i = 4 is 0-23、2-56、0-34、2-67、0-45、1-23、0-56、1-34、0-67、1-45、0-78、2-23、1-56、2-34、1-67、2-45、1-78、2-56； 0-34、2-67、0-45、2-78、0-56、1-34、0-67、1-45、0-78、1-56、0-89、2-34、1-67、2-45、1-78、2-56、1-89、2-67； 0-45, 2-78, 0-56, 2-89, 0-67, 1-45, 0-78, 1-56, 0-89, 1-67, 0-9a, 2-45, 1-78, 2-56, 1-89, 2-67, 1-9a, 2-78, 0-56, 2-9a.

8. The hardware decoding device of claim 1, wherein, Also includes: a data output module coupled to an output of the data store that outputs the B i The decoding results of the data blocks are output to the data output module.

9. The hardware decoding device of claim 8, wherein, Also includes: a data input module coupled to an input of the data store to input the B i After the decoding result of the data block is output to the data output module, the data input module inputs a new data block to the data store.

10. A method of sliding window iterative decoding, characterized by, Includes: W data blocks {B i , B i+1 , ……, B i+W-1} are inputted into the data memory according to time, wherein W represents the length of the decoding window, and i represents the serial number of the data block entering the earliest in the current decoding window. The data selector forms a component code set according to a set of associated data blocks in the W data blocks of the data memory, wherein the set of associated data blocks has L+1 data blocks, L represents the memory depth, and L+1 < W; And The component code decoder reads multiple sets of component codes from the data selector, decodes each set of component codes, and repeats the iteration I times, where X - Y j0 Y j1 …Y jL represents the decoding number of the set of component codes in the decoding process, X represents the iteration number within the current decoding window, Y j0 Y j1 …Y jL represents that the set of component codes is associated with L + 1 associated data blocks B j0 、B j1 、……、B jL is associated with, X ∈ [0, I - 1], jp represents j0 to j L , jp ∈ [i, i + W - 1], p ∈ [0, L], and jp - 1 < jp < jp + 1. In each decoding iteration of each decoding window, the sets of component codes are decoded in ascending order of jp in the associated data blocks B j0 、B j1 、……、B jL , and the decoding of an associated data block that is not in the current decoding iteration and is not related to the data blocks involved in the two sets of associated data blocks is selectively inserted between the decoding of the two sets of associated data blocks; And After the component code decoder completes the decoding of the component code set associated with each data block, the decoding result is written to the corresponding position of the data block in the data memory.

Images