Asynchronous first-in first-out memory verification method, device, equipment and medium
By employing an automated verification method for asynchronous FIFO memory, utilizing timing path tracing and formal assertions, the problems of missing pointer synchronization chains and insufficient hierarchy are solved, achieving efficient automated verification, improving verification efficiency and completeness, and reducing redundant test resources.
Patent Information
- Application Number
- CN202511414715.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-28
- Publication Date
- 2025-12-16
AI Technical Summary
Existing technologies cannot efficiently and automatically verify asynchronous FIFO memories. They suffer from missing or insufficient pointer synchronization chains, rely on manual code review which is inefficient and prone to missing errors, have insufficient coverage of functional scenarios, and are time-consuming to verify heterogeneous designs and prone to missing cross-instance errors. The lack of coverage-driven test optimization leads to redundant testing and wasted resources.
By analyzing the register transfer language code of the first-in-first-out (FIFO) memory, timing path tracing technology and formal assertions are used to verify the clock domain attribution of the read/write pointer generation logic. Test cases are constructed and coverage heatmaps are generated. Combined with abstract syntax tree parsing and fuzzy matching technology, memory entities are automatically identified to achieve automated verification.
It achieves automated identification and feature extraction of asynchronous first-in-first-out (FIFO) memory, covering all structural and functional risks, improving the convergence speed of verification completeness, reducing the consumption of redundant test resources, reducing manual intervention, and freeing up engineer resources for higher-order verification tasks.
Smart Images
Figure CN121144098A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design and verification technology, and in particular to an asynchronous first-in-first-out (FIFO) memory verification method, apparatus, device, and medium. Background Technology
[0002] Asynchronous FIFO (First Input First Output) is a core component for solving cross-clock domain data communication, primarily used for data transmission between modules with different clock frequencies or independent phases. Typical scenarios include: intra-chip multi-clock domain interaction, communication protocol conversion, image processing systems, and data sharing between cores in multi-core systems. Its core advantages are reflected in three aspects: by using Gray code-encoded pointers and synchronizer chains, multi-bit signal transitions are reduced to single-bit changes, significantly reducing the risk of metastability; the predictive empty / full flag mechanism prevents data overflow / read empty and supports pipelined operations to improve throughput; and parameterized design can flexibly adapt to data width and entry depth, achieving a balance between resource consumption and performance.
[0003] Asynchronous FIFOs, as a core component for cross-clock domain data transmission, must meet strict synchronization requirements to avoid metastability risks. However, some verification techniques suffer from the following key problems, making it difficult to locate structural defects: Read and write pointers are not encoded using Gray code, leading to multiple bit flips during cross-clock domain comparisons; pointer synchronization chains are missing or have insufficient hierarchy. Functional scenario coverage is insufficient: traditional dynamic simulation relies on manually written test cases, making it difficult to cover extreme scenarios such as full / empty boundary conditions; formal verification tools cannot automatically identify FIFO instances, requiring manual configuration of assertion constraints. Verification efficiency is low: when heterogeneous designs contain multiple asynchronous FIFOs, manual verification is time-consuming and prone to missing cross-instance errors; the lack of coverage-driven test optimization leads to redundant testing and resource waste.
[0004] It is evident that how to perform efficient and automated verification of asynchronous FIFOs is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide an asynchronous first-in-first-out (FIFO) memory verification method, apparatus, device, and medium, which can solve the problems of existing technologies that cannot automatically detect missing or insufficient pointer synchronization chains, require manual code review, are inefficient, and are prone to overlooking errors. The specific solution is as follows:
[0006] In a first aspect, the present invention discloses an asynchronous first-in-first-out (FIFO) memory verification method, comprising:
[0007] The temporary register transfer language code of the first-in-first-out (FIFO) memory is analyzed. Based on the analysis results, the completeness of the declaration of the FIFO memory storage entity and the consistency of the bit width and depth parameters of the storage cell with the design specifications are checked to obtain the corresponding test results.
[0008] The clock domain attribution of the read / write pointer generation logic of the first-in-first-out memory was verified using timing path tracing technology, and the first verification result was obtained.
[0009] The synchronization chain hierarchy, Gray code encoding, and clock domain isolation of the first-in-first-out memory are verified using formal assertions to obtain the corresponding second verification results;
[0010] Test cases are constructed based on the first-in-first-out memory, and the data integrity and error handling mechanism are verified through the test cases to obtain the corresponding third verification results.
[0011] A coverage heatmap is determined based on the coverage data generated from the test cases, and the completeness of the test cases is verified based on the coverage data and adjustments to the test stimuli to obtain the fourth verification result; the coverage data includes row coverage, flip coverage, and condition coverage;
[0012] A verification report is generated based on the test results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous first-in-first-out memory.
[0013] Optionally, the temporary register transfer language code of the FIFO memory is analyzed. Based on the analysis results, the completeness of the FIFO memory storage entity declaration and the consistency of the bit width and depth parameters of the storage cells with the design specifications are checked to obtain the corresponding detection results, including:
[0014] A hardware description language parser is built by using a parser. The parser is then used to perform lexical and syntactic analysis on the language code passed to the register to generate an abstract syntax tree.
[0015] Traverse the nodes of the abstract syntax tree to identify the target structure; the target structure includes register array declarations, memory macro instantiations, and exception branches for missing memory entities;
[0016] The target structure is used to determine whether the declaration of the first-in-first-out memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications, so as to obtain the corresponding test results.
[0017] During the lexical and syntactic analysis of the temporary register passing language code, a signal naming rule base is constructed using a fuzzy matching algorithm. Based on the naming rule base, different names of the same code in the temporary register passing language code are unified.
[0018] Optionally, timing path tracing technology is used to verify the clock domain attribution of the read / write pointer generation logic of the first-in-first-out memory, obtaining the first verification result, including:
[0019] Based on timing path tracing technology, static timing analysis is used to analyze the signal propagation path of the first-in-first-out (FIFO) memory to verify the clock domain attribution of the FIFO read / write pointer generation logic, thus obtaining the first verification result.
[0020] Optionally, the synchronization chain hierarchy, Gray code encoding, and clock domain isolation of the FIFO memory are verified based on formal assertions to obtain the corresponding second verification results, including:
[0021] Formal assertions based on pointer signals and synchronization chain structure are used to verify whether the read / write pointer synchronization chain is a two-stage synchronizer structure, whether the pointer signal has been converted to Gray code and satisfies the single-bit flip constraint before being transmitted across clock domains, and whether there is cross-coupling in the clock domain of the read / write pointer generation logic, so as to obtain the corresponding second verification results.
[0022] Optionally, test cases can be constructed based on the first-in-first-out (FIFO) memory depth, including:
[0023] Test cases are constructed using test case template files based on the first-in-first-out (FIFO) memory depth. Test cases include full-state write test cases, empty-state read test cases, and pointer wrap-around test cases.
[0024] Optionally, asynchronous first-in-first-out memory verification methods also include:
[0025] By randomly shifting the clock phase and modulating the frequency, the propagation path of metastability in the synchronization chain is simulated, and the timing visualization of cross-clock domain events is performed based on the propagation path and waveform capture technology.
[0026] The distributed scheduler allocates an independent verification environment for each asynchronous first-in-first-out memory instance and isolates simulation resources.
[0027] Optionally, asynchronous first-in-first-out memory verification methods also include:
[0028] The simulated assertion failure events during the test are bound to the waveform signals with corresponding timestamps so that assertion failure events can be queried based on the waveform signals, and the full / empty flag transition times of the first-in-first-out memory are highlighted in the waveform viewer.
[0029] Secondly, the present invention discloses an asynchronous first-in-first-out memory verification device, comprising:
[0030] The detection result acquisition module is used to analyze the temporary register transfer language code of the first-in-first-out memory, and detect whether the declaration of the first-in-first-out memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications, so as to obtain the corresponding detection results.
[0031] The first verification result acquisition module is used to verify the clock domain attribution of the read and write pointer generation logic of the first-in-first-out memory using timing path tracing technology, and obtain the first verification result.
[0032] The second verification result acquisition module is used to verify the synchronization chain level, Gray code encoding and clock domain isolation of the first-in-first-out memory according to formal assertions, so as to obtain the corresponding second verification result.
[0033] The third verification result acquisition module is used to construct test cases based on the depth of the first-in-first-out memory, verify the data integrity and error handling mechanism through the test cases, and obtain the corresponding third verification result.
[0034] The fourth verification result acquisition module is used to determine the coverage heatmap based on the coverage data generated based on the test cases, and to verify the completeness of the test cases based on the coverage data and the adjustment of the test incentives, so as to obtain the fourth verification result; the coverage data includes row coverage, flip coverage and condition coverage;
[0035] The verification report generation module is used to generate a verification report based on the detection results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous first-in-first-out memory.
[0036] Thirdly, the present invention discloses an electronic device, comprising:
[0037] Memory, used to store computer programs;
[0038] A processor is used to execute computer programs to implement the steps of the asynchronous first-in-first-out memory verification method as described above.
[0039] Fourthly, the present invention discloses a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the aforementioned asynchronous first-in-first-out memory verification method.
[0040] This invention first analyzes the register transfer language code of the FIFO memory. Based on the analysis results, it checks whether the declaration of the FIFO memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications, thus obtaining corresponding detection results. Timing path tracing technology is used to verify the clock domain attribution of the FIFO memory's read / write pointer generation logic, resulting in a first verification result. Formal assertions are used to verify the FIFO memory's synchronization chain hierarchy, Gray code encoding, and clock domain isolation, resulting in a second verification result. Test cases are constructed based on the FIFO memory depth, and the data integrity and error handling mechanism are verified through these test cases, resulting in a third verification result. A coverage heatmap is determined based on the coverage data generated from the test cases, and the completeness of the test cases is verified based on the coverage data and adjustments to the test stimuli, resulting in a fourth verification result. The coverage data includes row coverage, flip coverage, and conditional coverage. Finally, a verification report is generated based on the detection results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous FIFO memory.
[0041] Beneficial Effects: This invention achieves automatic identification and feature extraction of asynchronous first-in-first-out (FIFO) memory instances through abstract syntax tree parsing and fuzzy matching techniques, solving the inefficiency problem of traditional methods relying on manual annotation. A collaborative mechanism of formal verification and dynamic simulation covers all structural and functional risks. A coverage heatmap-driven adaptive feedback mechanism is constructed, achieving targeted reinforcement verification of uncovered logic through dynamic insertion of directional tests and constrained random stimuli, improving the convergence speed of verification completeness and significantly reducing the consumption of redundant test resources. The automated verification process reduces manual intervention, freeing up engineer resources for higher-order verification tasks. Attached Figure Description
[0042] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 A flowchart of an asynchronous first-in-first-out (FIFO) memory verification method provided in an embodiment of the present invention;
[0044] Figure 2 A flowchart of RTL static pre-inspection provided in an embodiment of the present invention;
[0045] Figure 3 This is a schematic diagram illustrating the construction of a signal naming rule library according to an embodiment of the present invention;
[0046] Figure 4 This is a schematic diagram of a formal assertion generation method provided in an embodiment of the present invention;
[0047] Figure 5 This is a schematic diagram of a synchronization chain verification method provided in an embodiment of the present invention;
[0048] Figure 6 This is a schematic diagram of a test case construction method provided in an embodiment of the present invention;
[0049] Figure 7 A schematic diagram of a verification report provided in an embodiment of the present invention;
[0050] Figure 8 A schematic diagram of a key signal annotation code provided in an embodiment of the present invention;
[0051] Figure 9 A schematic diagram of a full-process verification system for asynchronous FIFO provided in an embodiment of the present invention;
[0052] Figure 10 A schematic diagram of an asynchronous first-in-first-out memory verification device provided in an embodiment of the present invention;
[0053] Figure 11 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0055] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.
[0056] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0057] Some verification techniques suffer from the following key problems: structural defects are difficult to locate: read and write pointers are not encoded using Gray code, leading to multiple bit flips during cross-clock domain comparisons; pointer synchronization chains are missing or have insufficient levels. Functional scenario coverage is insufficient: traditional dynamic simulation relies on manually written test cases, making it difficult to cover extreme scenarios such as full / empty boundary conditions; formal verification tools cannot automatically identify FIFO instances, requiring manual configuration of assertion constraints. Verification efficiency is low: when heterogeneous designs contain multiple asynchronous FIFOs, manual verification is time-consuming and prone to missing cross-instance errors; the lack of coverage-driven test optimization leads to redundant testing and resource waste. To address these technical problems, this invention discloses an asynchronous first-in-first-out (FIFO) memory verification method, apparatus, device, and medium, which can solve the problems of existing technologies failing to automatically detect missing or insufficient pointer synchronization chains, requiring manual code review, resulting in low efficiency and easy error omission.
[0058] See Figure 1 As shown, this embodiment of the invention provides an asynchronous first-in-first-out (FIFO) memory verification method, including:
[0059] Step S11: Analyze the temporary register transfer language code of the first-in-first-out (FIFO) memory, and check whether the declaration of the FIFO memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications based on the analysis results, so as to obtain the corresponding detection results.
[0060] In this embodiment of the invention, firstly, static pre-detection and feature extraction using RTL (register transfer language) are performed, such as... Figure 2 As shown. In this process, based on Abstract Syntax Tree (AST) parsing and fuzzy matching algorithms, static analysis is performed on the RTL code to check the declaration integrity of FIFO storage entities. By identifying the instantiation logic of register files or memory macros, it is ensured that the bit width and depth parameters of the storage cells are consistent with the design specifications, avoiding the risk of data loss caused by undefined storage.
[0061] Specifically, a hardware description language (HDL) parser is constructed using a parser. This parser performs lexical and syntactic analysis on the language code passed to the registers to generate an abstract syntax tree (AST). The AST nodes are traversed to identify the target structure, which includes register array declarations, memory macro instantiation, and abnormal branches indicating missing storage entities. The target structure is used to determine the completeness of the FIFO memory entity declarations and whether the bit width and depth parameters of the memory cells match the design specifications, yielding corresponding detection results. During the lexical and syntactic analysis of the language code passed to the registers, a fuzzy matching algorithm is used to construct a signal naming rule base. Based on this rule base, different names for the same code in the language code passed to the registers are standardized.
[0062] In one specific implementation, the AST parsing process uses ANTLR (Another Tool for Language Recognition) to build a Verilog parser, performing lexical and syntactic analysis on the RTL code to generate an Abstract Syntax Tree (AST). By traversing the AST nodes, the following key structures are identified:
[0063] 1. Register array declaration (reg [DATA_WIDTH1:0] mem [0:DEPTH1]);
[0064] 2. Memory macro instantiation (e.g., SRAM_16x8 mem_inst(.clk(wr_clk),.addr(wr_ptr),.data(data_in)));
[0065] 3. Abnormal branches with missing storage entities (such as FIFO controllers with uninstantiated storage modules).
[0066] At the same time, such as Figure 3 The fuzzy matching rule base shown is used to construct a signal naming rule base to resolve naming differences in heterogeneous designs.
[0067] Step S12: Use timing path tracing technology to verify the clock domain attribution of the read / write pointer generation logic of the first-in-first-out memory and obtain the first verification result.
[0068] In this embodiment of the invention, timing path tracing technology is employed to analyze the clock domain affiliation of the read and write pointer generation logic. Through signal propagation path analysis and clock tree topology mapping, it is verified that the write pointer is strictly driven by the write clock domain and the read pointer is driven by the read clock domain, ensuring the timing isolation of the cross-clock domain synchronization chain.
[0069] Specifically, timing path tracing technology utilizes static timing analysis to analyze the signal propagation path of the FIFO memory, verifying the clock domain attribution of the FIFO read / write pointer generation logic and obtaining the first verification result. More specifically, timing path tracing uses a static timing analysis (STA) engine to analyze the signal propagation path and verify the clock domain attribution of the read / write pointer generation logic.
[0070] The write pointer generation logic is driven only by the write clock (wr_clk) and has no cross-clock domain combinational logic;
[0071] The read pointer generation logic is driven only by the read clock (rd_clk) and the cross-clock domain path is isolated by a synchronization chain.
[0072] Step S13: Verify the synchronization chain hierarchy, Gray code encoding, and clock domain isolation of the first-in-first-out memory according to formal assertions to obtain the corresponding second verification result.
[0073] In this embodiment of the invention, formal verification is performed, including synchronization chain level verification. Based on formal assertions (SystemVerilog Assertions, SVA), the logical structure of the read-write pointer synchronization chain is verified to ensure that the integrity and timing constraints of the two-stage synchronizer meet the design specifications. Gray code encoding verification is performed by formal model checking to prove that the pointer signal has been converted to Gray code before being transmitted across clock domains, and that adjacent states only have single-bit flips, eliminating the risk of metastability propagation caused by multi-bit transitions. Clock domain isolation verification is performed by constructing a formal constraint model to verify that the clock domains of the read-write pointer generation logic are strictly isolated, preventing race conditions caused by cross-clock domain logic coupling.
[0074] Specifically, formal assertions based on pointer signals and synchronization chain structures are used to verify whether the read / write pointer synchronization chain is a two-stage synchronizer structure, whether the pointer signal has been converted to Gray code and satisfies the single-bit flip constraint before being transmitted across clock domains, and whether there is cross-coupling in the clock domains of the read / write pointer generation logic, so as to obtain the corresponding second verification results.
[0075] In one specific embodiment, SVA assertions are automatically generated, dynamically generating formal assertions such as those based on identified pointer signals and synchronization chain structures. Figure 4 As shown, the synchronization chain is verified hierarchically. A formal constraint model is constructed to verify that the synchronization chain is a two-stage trigger (2FF) structure. Figure 5 As shown.
[0076] Step S14: Construct test cases based on the first-in-first-out memory depth, and verify data integrity and error handling mechanisms through test cases to obtain the corresponding third verification results.
[0077] In this embodiment of the invention, dynamic simulation is performed. During this process, boundary condition test sequences are generated. Based on the FIFO depth parameters, directional test sequences are dynamically constructed using test case template files to forcibly trigger critical states such as full and empty states, and inject illegal operations (such as writing to a full state and reading from an empty state) to verify data integrity and error handling mechanisms. Metastable state propagation analysis is performed by integrating a commercial simulator. Through random clock phase offset and frequency modulation, the propagation path of metastable states in the synchronization chain is simulated, and waveform capture technology is used to achieve timing visualization of cross-clock domain events. Multi-instance parallel verification adopts a distributed scheduling strategy, allocating an independent verification environment to each asynchronous FIFO instance. Resource isolation and priority scheduling avoid signal conflicts, supporting efficient verification of heterogeneous designs.
[0078] Specifically, test cases are constructed based on the FIFO depth using a test case template file. These test cases include full-state write test cases, empty-state read test cases, and pointer wraparound test cases. In one specific embodiment, boundary condition test sequences are generated by dynamically constructing test sequences based on the FIFO depth using the test case template file. For example, a full-state write test... Figure 6 As shown.
[0079] Furthermore, the metastable propagation analysis unit simulates metastable events across clock domain paths by injecting clock phase offsets and frequency modulations; while the distributed scheduler allocates independent verification environments and isolates simulation resources for multiple FIFO instances. Therefore, specifically, this invention simulates the propagation path of metastable states in the synchronization chain through random clock phase offsets and frequency modulations, and performs timing visualization of cross-clock domain events based on the propagation path and waveform capture technology; it also allocates independent verification environments for each asynchronous FIFO memory instance based on the distributed scheduler and isolates simulation resources. Moreover, the metastable propagation analysis unit further includes a clock jitter injection module to randomize the phase difference and period of the read / write clocks during simulation; and a waveform capture trigger to automatically save cross-clock domain signal waveform segments when an assertion fails.
[0080] Step S15: Determine the coverage heatmap based on the coverage data generated from the test cases, and verify the completeness of the test cases based on the coverage data and the adjustment of the test incentives to obtain the fourth verification result; the coverage data includes row coverage, flip coverage and condition coverage.
[0081] In some technologies, the lack of coverage-based test optimization can lead to redundant tests or omissions of critical scenarios (such as uncovered pointer wrap-around or synchronization chain stress scenarios). Therefore, this invention performs coverage fusion analysis: it analyzes dynamically simulated line coverage, toggle coverage, and condition coverage to construct a coverage heatmap and identify uncovered code segments (such as pointer wrap-around logic and synchronizer reset paths). Then, based on the coverage data, it dynamically inserts directional tests (such as continuous backpressure tests) or constrained random stimuli to strengthen the verification of uncovered logic. For synchronization chain logic with low coverage, it automatically generates synchronizer stress test sequences (such as high-frequency clock switching and asynchronous reset interference). Finally, it designs an iterative verification mechanism that feeds back the coverage analysis results to the test sequence generation module, approximating the coverage convergence target through multiple rounds of verification iterations to achieve a quantitative evaluation of verification completeness. Specifically, an uncovered code segment (including pointer wrap-around logic and synchronization chain reset paths) is marked by a coverage heatmap generator; an adaptive test optimization engine inserts continuous backpressure tests or high-frequency clock switching stimuli based on the coverage gap. The adaptive test optimization engine further includes a constrained random stimulus generator for low coverage scenarios, which strengthens the verification of synchronization chain pressure scenarios; and an iterative verification controller that dynamically adjusts the simulation rounds according to the coverage convergence target.
[0082] Additionally, it's worth noting that in the process of dynamically inserting targeted tests (such as continuous backpressure tests) or constrained random stimuli based on coverage data to enhance the verification of uncovered logic, the correlation between MC / DC (Modified Condition / Decision Coverage) coverage and branch coverage can be analyzed in real time. This allows for dynamic adjustment of the weight allocation of constrained random stimuli, prioritizing the generation of test sequences covering low-coverage paths. Furthermore, neural networks can be combined to predict potential defect patterns in uncovered logic, automatically generating targeted test cases (such as scenarios combining high-frequency clock switching and asynchronous reset). Simultaneously, a syntax-aware synchronizer anomaly sequence generator has been developed, which can automatically construct test scenarios containing timing violations such as clock glitches and reset races. This achieves a closed-loop system from passive coverage statistics to proactive test strategy generation, significantly improving the verification efficiency of complex logic such as synchronization chains.
[0083] Step S16: Generate a verification report based on the detection results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous first-in-first-out memory.
[0084] In this embodiment of the invention, a standardized verification report will be output as follows: Figure 7As shown, the report includes detection results, first verification results, second verification results, third verification results, fourth verification results, and a coverage heatmap. This includes formal verification violation paths (such as missing Gray code encoding), dynamic simulation assertion trigger details (such as overflow operation timestamps), and coverage gap analysis. The output verification report supports rapid defect location and design remediation. For example, the structured violation report records violation paths such as missing Gray code and insufficient synchronization chain levels in formal verification. The HTML (Hyper Text Markup Language) report template uses the Jinja2 template engine to generate a visual report that links assertion violations with coverage gaps.
[0085] Furthermore, this invention automatically associates assertion failure events with key signals in the simulation waveform (such as full / empty flags and pointer synchronization chain states), assisting engineers in tracing the metastable propagation path. Assertion failure events simulated during testing are bound to waveform signals with corresponding timestamps, allowing for querying of assertion failure events based on waveform signals. The transition times of the full / empty flags in the FIFO memory are highlighted in the waveform viewer. For example, key signal annotation automatically marks the pointer synchronization chain state at the time of assertion failure in the Verdi waveform viewer. Figure 8 As shown, the waveform correlation analyzer automatically binds the assertion failure events of the dynamic simulation to the waveform signals with corresponding timestamps. Then, the waveform correlation analyzer uses key signal marking logic to highlight the full / empty flag transition times in the waveform viewer; and marks the uncertain states of the synchronization chain output signal within the metastable window.
[0086] Beneficial Effects: This invention achieves automatic identification and feature extraction of asynchronous first-in-first-out (FIFO) memory instances through abstract syntax tree parsing and fuzzy matching techniques, solving the inefficiency problem of traditional methods relying on manual annotation. A collaborative mechanism of formal verification and dynamic simulation covers all structural and functional risks. A coverage heatmap-driven adaptive feedback mechanism is constructed, achieving targeted reinforcement verification of uncovered logic through dynamic insertion of directional tests and constrained random stimuli, improving the convergence speed of verification completeness and significantly reducing the consumption of redundant test resources. The automated verification process reduces manual intervention, freeing up engineer resources for higher-order verification tasks.
[0087] Next, we will provide a detailed explanation of the specific asynchronous first-in-first-out (FIFO) memory verification method.
[0088] like Figure 9 As shown, the present invention proposes a full-process verification system for asynchronous FIFO, which includes: an RTL static pre-inspection module, a hybrid verification engine including a formal verification enhancement module and a dynamic simulation optimization module, a coverage-driven feedback module, and a verification report generation module.
[0089] Specifically, the RTL static preflight module verifies the legality of FIFO memory cell declarations and the clock domain binding relationship of read and write pointers through Abstract Syntax Tree (AST) parsing and fuzzy matching techniques; the hybrid verification engine integrates a formal verification enhancement module and a dynamic simulation optimization module. The formal verification enhancement module automatically generates formal assertions to verify synchronization chain hierarchy, Gray code encoding, and clock domain isolation, while the dynamic simulation optimization module constructs boundary condition test sequences and performs metastable propagation analysis; the coverage-driven feedback module parses row coverage, flip coverage, and conditional coverage data and dynamically adjusts test stimuli to optimize verification completeness; and the verification report generation module outputs a structured report containing formal violation paths, dynamic simulation assertion trigger events, and coverage heatmaps, and associates them with key waveform signals.
[0090] Among them, the RTL static pre-detection module is based on the storage cell legality verification logic of AST traversal to detect the consistency of bit width and depth parameters of register group or memory macro; the clock domain binding analysis driven by timing path tracing technology verifies the clock domain affiliation of the read and write pointer generation logic to ensure that the write pointer is driven by the write clock and the read pointer is driven by the read clock.
[0091] The formal verification enhancement module includes a synchronization chain-level verification unit, which verifies whether the read / write pointer synchronization chain is a two-stage synchronizer structure using automatically generated SystemVerilog assertions; a Gray code encoding verification unit, which uses a formal model to prove that the pointer signal has been converted to Gray code and satisfies the single-bit flip constraint before being transmitted across clock domains; and a clock domain isolation verification unit, which constructs a formal constraint model to verify that the clock domains of the read / write pointer generation logic are not cross-coupled. The synchronization chain-level verification unit further includes a synchronizer flip-flop level check assertion, which forces the number of flip-flops in the synchronization chain to equal the design specification definition; and a synchronization chain timing constraint verification, which checks the setup / hold time compliance of the synchronizer input and output signals.
[0092] In addition, the dynamic simulation optimization module includes a FIFO depth-based directional test sequence generator to construct full-state write, empty-state read, and pointer wrap-around test cases; a metastable propagation analysis unit to simulate metastable events across clock domain paths by injecting clock phase offset and frequency modulation; and a distributed scheduler to allocate independent verification environments and isolate simulation resources for multiple FIFO instances.
[0093] Finally, a structured report is generated: a standardized verification report is output, which includes formal verification violation paths (such as missing Gray code encoding), dynamic simulation assertion trigger details (such as overflow operation timestamps), and coverage gap analysis, supporting rapid defect location and design repair.
[0094] Beneficial effects: This invention achieves closed-loop management of asynchronous FIFO design risks through deep collaboration of static pre-inspection, formal verification, dynamic simulation and coverage feedback, significantly improving verification efficiency and pre-silicon reliability, and solving the technical bottlenecks of traditional methods in structural defect detection, extreme scenario coverage and multi-instance verification efficiency.
[0095] See Figure 10 As shown, an embodiment of the present invention provides an asynchronous first-in-first-out memory verification device, comprising:
[0096] The detection result acquisition module 11 is used to analyze the temporary register transfer language code of the first-in-first-out memory, and detect whether the declaration of the first-in-first-out memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications based on the analysis results, so as to obtain the corresponding detection results.
[0097] The first verification result acquisition module 12 is used to verify the clock domain attribution of the read and write pointer generation logic of the first-in-first-out memory using timing path tracing technology, and obtain the first verification result.
[0098] The second verification result acquisition module 13 is used to verify the synchronization chain level, Gray code encoding and clock domain isolation of the first-in-first-out memory according to formal assertions, so as to obtain the corresponding second verification result.
[0099] The third verification result acquisition module 14 is used to construct test cases based on the first-in-first-out memory depth, verify data integrity and error handling mechanism through test cases, and obtain the corresponding third verification result.
[0100] The fourth verification result acquisition module 15 is used to determine the coverage heatmap based on the coverage data generated based on the test cases, and to verify the completeness of the test cases based on the coverage data and the adjustment of the test incentives, so as to obtain the fourth verification result; the coverage data includes row coverage, flip coverage and condition coverage;
[0101] The verification report generation module 16 is used to generate a verification report based on the detection results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous first-in-first-out memory.
[0102] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.
[0103] Beneficial Effects: This invention achieves automatic identification and feature extraction of asynchronous first-in-first-out (FIFO) memory instances through abstract syntax tree parsing and fuzzy matching techniques, solving the inefficiency problem of traditional methods relying on manual annotation. A collaborative mechanism of formal verification and dynamic simulation covers all structural and functional risks. A coverage heatmap-driven adaptive feedback mechanism is constructed, achieving targeted reinforcement verification of uncovered logic through dynamic insertion of directional tests and constrained random stimuli, improving the convergence speed of verification completeness and significantly reducing the consumption of redundant test resources. The automated verification process reduces manual intervention, freeing up engineer resources for higher-order verification tasks.
[0104] Furthermore, embodiments of this application also disclose an electronic device, Figure 11 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the asynchronous first-in-first-out memory verification method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.
[0105] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0106] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0107] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the asynchronous first-in-first-out memory verification method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.
[0108] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned asynchronous first-in-first-out memory verification method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0109] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned asynchronous first-in-first-out memory verification method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0110] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0111] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0112] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0113] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0114] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for verifying an asynchronous first-in-first-out memory, characterized in that, include: The temporary register transfer language code of the first-in-first-out (FIFO) memory is analyzed. Based on the analysis results, the completeness of the declaration of the FIFO memory storage entity and the consistency of the bit width and depth parameters of the storage cell with the design specifications are checked to obtain the corresponding test results. The clock domain attribution of the read / write pointer generation logic of the first-in-first-out memory was verified using timing path tracing technology, and the first verification result was obtained. The synchronization chain hierarchy, Gray code encoding, and clock domain isolation of the first-in-first-out memory are verified according to formal assertions to obtain the corresponding second verification results; Test cases are constructed based on the first-in-first-out memory depth, and the data integrity and error handling mechanism are verified through the test cases to obtain the corresponding third verification results; A coverage heatmap is determined based on the coverage data generated from the test cases, and the completeness of the test cases is verified based on the coverage data and adjustments to the test stimuli to obtain a fourth verification result; the coverage data includes row coverage, flip coverage, and condition coverage; A verification report is generated based on the detection results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous first-in-first-out memory.
2. The asynchronous first-in-first-out memory verification method according to claim 1, characterized in that, The analysis of the register transfer language code of the first-in-first-out (FIFO) memory, based on the analysis results, checks whether the declaration of the FIFO memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications, to obtain the corresponding detection results, including: A hardware description language parser is constructed using a parser, and the parser is used to perform lexical and syntactic analysis on the language code passed in the register to generate an abstract syntax tree. The nodes of the abstract syntax tree are traversed to identify the target structure, which includes register array declarations, memory macro instantiations, and exception branches for missing memory entities. The target structure is used to determine whether the declaration of the first-in-first-out memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications, so as to obtain the corresponding detection results. During the lexical and syntactic analysis of the temporary register transmission language code, a signal naming rule library is constructed using a fuzzy matching algorithm. Based on the naming rule library, different names of the same code in the temporary register transmission language code are unified.
3. The asynchronous first-in-first-out memory verification method according to claim 1, characterized in that, The verification of the clock domain attribution of the read / write pointer generation logic of the first-in-first-out memory using timing path tracing technology, to obtain the first verification result, includes: Based on timing path tracing technology, static timing analysis is used to analyze the signal propagation path of the first-in-first-out memory to verify the clock domain affiliation of the read and write pointer generation logic of the first-in-first-out memory, and the first verification result is obtained.
4. The asynchronous first-in-first-out memory verification method according to claim 1, characterized in that, The verification of the synchronization chain hierarchy, Gray code encoding, and clock domain isolation of the first-in-first-out memory based on formal assertions to obtain the corresponding second verification result includes: Formal assertions based on pointer signals and synchronization chain structure are used to verify whether the read / write pointer synchronization chain is a two-stage synchronizer structure, whether the pointer signal has been converted to Gray code and satisfies the single-bit flip constraint before being transmitted across clock domains, and whether there is cross-coupling in the clock domain of the read / write pointer generation logic, so as to obtain the corresponding second verification results.
5. The asynchronous first-in-first-out memory verification method according to claim 1, characterized in that, The test cases constructed based on the first-in-first-out (FIFO) memory depth include: The test cases are constructed using a test case template file based on the first-in-first-out (FIFO) memory depth; the test cases include full-state write test cases, empty-state read test cases, and pointer wrap-around test cases.
6. The asynchronous first-in-first-out memory verification method according to claim 1, characterized in that, Also includes: By randomly shifting the clock phase and modulating the frequency, the propagation path of metastability in the synchronization chain is simulated, and the timing visualization of cross-clock domain events is performed based on the propagation path and waveform capture technology. The distributed scheduler allocates an independent verification environment for each asynchronous first-in-first-out memory instance and isolates simulation resources.
7. The asynchronous first-in-first-out memory verification method according to any one of claims 1 to 6, characterized in that, Also includes: The simulated assertion failure events during the test are bound to the waveform signals with corresponding timestamps so that the assertion failure events can be queried based on the waveform signals, and the full / empty flag transition times of the first-in-first-out memory are highlighted in the waveform viewer.
8. An asynchronous first-in-first-out (FIFO) memory verification device, characterized in that, include: The detection result acquisition module is used to analyze the temporary register transfer language code of the first-in-first-out memory, and detect whether the declaration of the first-in-first-out memory storage entity is complete and whether the bit width and depth parameters of the storage cell are consistent with the design specifications, so as to obtain the corresponding detection results. The first verification result acquisition module is used to verify the clock domain attribution of the read and write pointer generation logic of the first-in-first-out memory using timing path tracing technology, and obtain the first verification result. The second verification result acquisition module is used to verify the synchronization chain level, Gray code encoding and clock domain isolation of the first-in-first-out memory according to formal assertions, so as to obtain the corresponding second verification result. The third verification result acquisition module is used to construct test cases based on the depth of the first-in-first-out memory, and verify the data integrity and error handling mechanism through the test cases to obtain the corresponding third verification result. The fourth verification result acquisition module is used to determine a coverage heatmap based on the coverage data generated based on the test cases, and to verify the completeness of the test cases based on the coverage data and the adjustment of the test stimuli, so as to obtain the fourth verification result; the coverage data includes row coverage, flip coverage, and condition coverage; The verification report generation module is used to generate a verification report based on the detection results, the first verification result, the second verification result, the third verification result, the fourth verification result, and the coverage heatmap to complete the verification of the asynchronous first-in-first-out memory.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the asynchronous first-in-first-out memory verification method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the asynchronous first-in-first-out memory verification method as described in any one of claims 1 to 7.