Clock network optimization method, computer device and storage medium

Abstract

The present disclosure provides a clock network optimization method, a computer device and a storage medium. The method comprises: obtaining a chip design layout, determining a signal node set and a receiving endpoint set according to the chip design layout; establishing a connection between the signal node set and the receiving endpoint set, generating an initial connection result; in response to the initial connection result not meeting a set target, adjusting the connection of the initial connection result, determining whether to accept the adjustment through a set strategy, generating an intermediate connection result; and in response to the intermediate connection result meeting the set target, determining the intermediate connection result as an optimization result.

Description

Technical Field

[0001] This disclosure relates to the field of chip layout planning technology, and in particular to a clock network optimization method, computer equipment, and storage medium. Background Technology

[0002] Electronic Design Automation (EDA) refers to a design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, and physical design (including placement, routing, layout, design rule checking, etc.) of very large-scale integrated circuit (VLSI) chips.

[0003] In the design process, the clock network has become a key determinant of power consumption, timing, and area (PPA) in integrated circuits. The clock network allows for the determination of signal delays and skewnesses received by individual components within the chip, with optimization aiming to minimize clock delays and skewness. However, while existing optimization methods have achieved their objectives to some extent, they introduce excessive cloned components, resulting in significant area and power consumption overhead, and causing problems such as load balancing and wiring congestion, severely impacting the overall chip design performance.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, this disclosure proposes a clock network optimization method, computer device, and storage medium to solve or partially solve the above-mentioned problems.

[0006] In view of the above objectives, firstly, this disclosure provides a clock network optimization method, comprising:

[0007] Obtain the chip design layout, and determine the set of signal nodes and the set of receiving endpoints based on the chip design layout;

[0008] Establish a connection between the set of signal nodes and the set of receiving endpoints, and generate an initial connection result;

[0009] In response to the initial connection result not meeting the set target, the initial connection result is adjusted, and whether to accept the adjustment is determined by a set strategy to generate an intermediate connection result.

[0010] In response to the intermediate connection result meeting the set target, the intermediate connection result is determined as the optimized result.

[0011] In a second aspect, this disclosure provides a computer device including one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs including instructions for performing the method according to the first aspect.

[0012] Thirdly, this disclosure provides a non-volatile computer-readable storage medium containing a computer program that, when executed by one or more processors, causes the processors to perform the method described in the first aspect.

[0013] As can be seen from the above description, this disclosure provides a clock network optimization method, a computer device, and a storage medium. The method includes: acquiring a chip design layout; determining a set of signal nodes and a set of receiving endpoints based on the chip design layout; establishing connections between the set of signal nodes and the set of receiving endpoints to generate an initial connection result; adjusting the initial connection result in response to a predetermined target, determining whether to accept the adjustment through a predetermined strategy, and generating an intermediate connection result; and determining the intermediate connection result as an optimized result in response to a predetermined target. In setting up the clock network, this disclosure first establishes an initial connection after determining the signal node and receiving endpoint to be connected. Then, the connection effect is tested according to the set target requirements. If it does not meet the target, adjustments are made based on the currently established connection. During the adjustment process, as the receiving endpoint switches to the signal node, the corresponding parameters change accordingly, and the number of cloned devices in the connection also increases or decreases, thereby adjusting the number of components in the clock network. When the number of components is reduced to meet the requirements, the area and power consumption are reduced due to the reduced number of cloned components in the original optimization process. At the same time, the smaller number of cloned components further solves problems such as load balancing and wiring congestion, improving the chip design effect. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided in an embodiment of this disclosure is shown.

[0016] Figure 2 A schematic diagram of the basic structure of the EDA tool provided in an embodiment of this disclosure is shown.

[0017] Figure 3 A schematic diagram illustrating the basic execution flow of a computation command of an EDA tool provided in an embodiment of this disclosure is shown.

[0018] Figure 4a A schematic diagram of the structure of an unoptimized clock network provided in an embodiment of this disclosure is shown.

[0019] Figure 4b A schematic diagram of an optimized clock network provided in an embodiment of this disclosure is shown.

[0020] Figure 5 A flowchart illustrating an exemplary method provided in an embodiment of this disclosure is shown.

[0021] Figure 6a A schematic diagram illustrating the determination of the signal node set and the receiving endpoint set before optimization provided in an embodiment of this disclosure is shown.

[0022] Figure 6b A schematic diagram illustrating the connection based on the set of signal nodes and the set of receiving endpoints provided in the embodiments of this disclosure is shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this specification clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0024] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element, object, or method step preceding the term covers the element, object, or method step listed after the term and its equivalents, but does not exclude other elements, objects, or method steps. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] Figure 1A schematic diagram of the structure of a computer device 100 provided in an embodiment of this disclosure is shown. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected internally via the bus 110.

[0026] Processor 102 may be a central processing unit (CPU), image processor, neural network processor (NPU), microcontroller (MCU), programmable logic device, digital signal processor (DSP), application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may further include multiple sub-processors integrated as a single logic component, such as... Figure 1 As shown, processor 102 may include sub-processor a102a, sub-processor b102b, and sub-processor c102c, etc.

[0027] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as... Figure 1 As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of this disclosure) and data to be processed. The processor 102 may also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0028] Network interface 106 can be configured to provide communication with other external devices to computer device 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0029] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0030] Bus 110 can be configured to transfer information between various components of computer device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0031] It should be noted that although the above-described device only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this disclosure, and not necessarily all the components shown in the figures.

[0032] Figure 2 A schematic diagram of the basic structure of an EDA tool 200 according to an embodiment of the present disclosure is shown.

[0033] like Figure 2 As shown, the area above the dashed line represents the user interface; the area below the dashed line represents EDA tool 200. EDA tool 200 can be... Figure 1 The device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for placement and routing based on chip design. The EDA tool 200 may include a Tcl command module 204 (or a graphical / window interface module), various calculation modules (e.g., Place calculation module 206, Route calculation module 208, Optimization calculation module 210, etc.), and a database system 212. The user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command module 204 (or the graphical / window interface module).

[0034] The Tcl command module 204 primarily functions as a message or command transmission module. It can read instructions input by the user 202 into the simulation tool 200 and, based on the specific content of the instructions, allocate and transmit them to the corresponding computing modules for execution of specific tasks.

[0035] Depending on the computational task, the computational modules can be divided into, for example, Place computation module 206, Route computation module 208, and Optimization computation module 210. Place computation module 206 can calculate a reasonable placement for all components, Route computation module 208 can calculate a reasonable wiring connection method between the components, and Optimization computation module 210 can optimize the placement and wiring connection methods between the components. The computational processes of these modules can be performed, for example, Figure 1 The process is carried out in processor 102.

[0036] Database system 212 can be used to completely and comprehensively record and store all information (such as location, orientation, size, structure, wire connection method, etc.) of the simulated or designed chip. This information, for example, can be stored in... Figure 1 In memory 104.

[0037] Figure 3 The basic execution flow 300 of a computation command of an EDA tool 200 according to an embodiment of this disclosure is shown. For example... Figure 3 As shown, in step 302, user 202 can issue a command (e.g., the do_place command) to EDA tool 200 through the command interface or graphical user interface (GUI) provided by Tcl command module 204. Then, in step 304, Tcl command module 204 parses this command and distributes it to the corresponding calculation module (e.g., Place calculation module 206). In step 306, each calculation module performs its specific calculations. During this process, as shown in step 308, each calculation module needs to (frequently and repeatedly) retrieve data from database system 212 for calculations. After the calculations are completed, as shown in step 310, each calculation module can write the calculation results to database system 212 and return the results to Tcl command module 204. In step 312, Tcl command module 204 returns the calculation results to user 202 through the command interface or graphical user interface (GUI), and the processing of a calculation command by EDA tool 200 ends. In step 314, the user can evaluate the calculation results and then determine the next step.

[0038] As described in the background section, clock networks typically need to drive large-scale register flip-flops, with fan-out numbers often reaching tens of thousands or even millions. In some EDA tools, multi-level buffering, hierarchical topologies (such as H-trees, balanced trees, etc.) are commonly used to construct clock distribution networks to minimize clock latency and clock skew. Clock skew here refers to the difference in delay between clock signals arriving at different sink points. In high-performance chip design, except for specific requirements (useful skew), skew must be strictly controlled to ensure flip-flop synchronization and timing correctness.

[0039] In some embodiments, clock network optimization can also be performed using the Multi-Tap (multi-branch drive) method. The basic idea of ​​the Multi-Tap method is to introduce local drive through multiple "Tap points" in the early stages of clock tree synthesis, allowing clock signals to enter different regions of the chip in parallel from multiple locations. This shortens local wiring length, reduces latency, and balances the clock load across different regions. This method can improve the significant latency of long-distance transmission from a single clock source and shorten the construction depth of local subtrees, reducing latency differences between different regions.

[0040] like Figure 4a , Figure 4b As shown, where Figure 4a This represents a traditional or basic network structure without clock optimization. The timing relationships of each component are clearly defined in this structure. However, in this structure, the clock signal drives all registers and macrocells through a single tap driver, such as... Figure 4a In this network, clock signals for all components are transmitted through the "Tap point" in the upper left corner. Due to significant differences in the distance between different components and the Tap point, the clock signal arrival delay varies considerably between components, resulting in a large clock skew. Then, as... Figure 4b This is a schematic diagram illustrating the optimization of the Multi-Tap method. The Multi-Tap method introduces multiple parallel tap points and constructs an upper-level clock tree using methods such as H-trees, ensuring that clock signals arrive at the tap points synchronously. Then, by driving local cells through different tap points, it effectively reduces the difference in clock signal transmission path length and significantly reduces clock skew. However, from... Figure 4b As can be seen from this, although the Multi-Tap method can effectively optimize clock performance, its application also comes with significant costs. Figure 4a and Figure 4b Because of timing, the two components at the bottom of the diagram need to pass through an intermediate "clock gate" before receiving a signal. Initially, there is only one clock gate, and thus... Figure 4b In this process, a "clock gate" needs to be cloned to meet timing and component requirements. As a result, when the Multi-Tap method is applied to the actual chip, a large number of cloned components will be formed. For example, an area that originally had only 100 components may have 150 or even 200 components after the Multi-Tap method. The main problems caused by this include: (1) Area and power consumption overhead: Multi-Tap requires copying the original clock tree trunk and distributing it to different Tap points to share the load. This process introduces a large number of additional buffers and clock gates, resulting in a significant increase in network power consumption and area, which is particularly prominent in high-frequency and high-performance designs. (2) Load balancing problem: Due to the difference between the chip's floorplan and the standard cell placement, unreasonable Tap position planning may cause redundancy in the driving capability of local areas, while other areas still have insufficient driving and large delay, thus forming a timing bottleneck. (3) Routing congestion risk: Each Tap point needs to obtain a signal from the global clock tree and build its own local clock subtree. Additional global cabling resources and more local fan-out networks are required, which may cause congestion at critical cabling levels.

[0041] In view of this, this disclosure proposes a clock network optimization method. When setting up the clock network, after determining the signal nodes and receiving endpoints to be connected, an initial connection is established. Then, the connection effect is tested according to the set target requirements. If the target is not met, adjustments are made based on the currently established connection. During the adjustment process, as the receiving endpoint switches to the signal node, the corresponding parameters change accordingly, and the number of cloned devices in the connection increases or decreases, thereby adjusting the number of components in the clock network. When the number of components is reduced to meet the requirements, the area and power consumption are reduced due to the reduced number of cloned components in the original optimization process. Furthermore, the fewer cloned components further solve problems such as load balancing and wiring congestion, improving the chip design effect.

[0042] Figure 5 A flowchart illustrating an exemplary method 500 provided in an embodiment of this disclosure is shown. Method 500 can be... Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 This is part of the functionality of EDA tools 200. For example... Figure 5 As shown, the method 500 may further include the following steps.

[0043] Step 502: Obtain the chip design layout and determine the signal node set and the receiving endpoint set based on the chip design layout.

[0044] Generally, a chip design layout includes every layer of the chip's structure, specifically the transistor placement, wiring, traces, and inter-layer connections of vias, etc. Based on this chip design layout, chip manufacturing service providers can directly run and mass-produce the chips. Furthermore, the chip design layout itself is drawn step by step, with various optimizations accompanying it, ultimately completing the entire chip design layout. In the early stages of the chip design layout, it may only indicate the functional information of the layers, such as a certain layer being a wiring layer, another layer being an insulating layer, etc.; or it may only set up each functional component, indicating the location, size, and other information of each functional component. Then, using EDA tools, etc., step-by-step design and optimization are carried out, finally forming a complete version of the chip design layout. Here, the component (inst) can be a standard processing unit, module or hard core, input / output terminal, register, etc. in the chip.

[0045] In this step, since this embodiment optimizes and adjusts the clock network, the positions of each component and the initial timing connections between them may be marked on the chip design layout. For networks optimized using the Multi-Tap method, a clock tree is typically constructed to represent the timing relationships. This clock tree can include: Tap points: Components that branch off local drive signals from the master clock source or intermediate components to the EDA tool. Tap points can be chip input ports, buffer drivers, or other standard components (such as integrated clock gating (ICG)). Sinks: The final receiver of clock signals, typically registers, latches, or other clock-triggered functional modules. Trunk Nodes: Devices in the clock tree from the Tap point to the Sink, i.e., devices cloned during Tap allocation. Leaf Nets: Networks in the clock tree that ultimately connect to the Sink clock load. Trunk Nets: Networks in the clock tree that are not Leaf Nets. In this embodiment, the Tap point is called the signal node, the Sink point is called the receiving endpoint, and the set containing multiple Tap points is the signal node set, and the set containing multiple Sink points is the receiving endpoint set.

[0046] In a specific embodiment, a Leaf Net in the clock tree typically contains at least one Sink point. The Sink points in the receiver endpoint set can then be further divided using Leaf Nets to form at least one set of receiver endpoints. During clock network optimization, the above information is generally already configured and can be obtained by reading the chip design layout. In specific application scenarios, initial data information such as component connections and locations can be obtained from the DEF (Design Exchange File, physical information of the design library) and / or LEF (Library Exchange File, physical information of the technology library) files of the chip design layout.

[0047] Step 504: Establish the connection between the signal node set and the receiving endpoint set, and generate the initial connection result.

[0048] In this step, after determining the set of signal nodes and the set of receiving endpoints, initial connections can be established between the signal nodes and the receiving endpoints based on these two sets. During connection establishment, typically one receiving endpoint will connect to only one signal node, but one signal node can connect to more than one receiving endpoint. Therefore, the initial connection can be established by selecting the nearest signal node based on the location of each receiving endpoint, by connecting according to pre-defined connection relationships, or by connecting all receiving endpoints in the same group (Leaf Net) to a single signal node, etc., thus completing the initial connection and forming the initial connection result.

[0049] In some embodiments, considering issues such as latency and line length during layout, the initial connection can be made by selecting the shortest possible distance to minimize these factors. This distance can be the Manhattan distance between the signal node and the receiving endpoint, which represents the sum of the horizontal and vertical distances between two points in a two-dimensional (or multi-dimensional) coordinate system. For example, point A... With point B Manhattan distance is That is, in some embodiments, establishing a connection between the set of signal nodes and the set of receiving endpoints includes: for any receiving endpoint in the set of receiving endpoints, determining the signal node in the set of signal nodes that is closest to the receiving endpoint, and establishing a connection between the receiving endpoint and the signal node.

[0050] In different initial connection methods, for a set of (Leaf Net) receiving endpoints, it is inevitable that they will be connected to different signal nodes. Therefore, it is necessary to clone and copy other components on the connection line between the two points, resulting in a larger number of optimized components than the original number of components after the initial connection is completed. For example Figure 6a and Figure 6b As shown, in specific application scenarios, the design netlist, physical information, timing constraints, and other information can be read from the chip design layout, and then a clock tree data structure can be constructed. Further, a set of signal nodes and a set of receiving endpoints can be constructed, as shown in the diagram. Figure 6a As shown, other elements between the two are omitted, and the set of receiving endpoints can also be grouped according to the Leaf Net. Then, as... Figure 6b As shown, the initial allocation is performed, assigning each receiving endpoint to the signal node closest to its Manhattan distance. For example... Figure 6b As can be seen, Leaf Net 1 is divided into two parts, and Leaf Net 2 is divided into three parts, and correspondingly, the upstream components of them need to be copied.

[0051] Step 506: In response to the initial connection result not meeting the set target, the initial connection result is adjusted, and an intermediate connection result is generated by determining whether to accept the adjustment through a set strategy.

[0052] In this step, firstly, a target is set to evaluate the specific performance of the current clock network. This target may differ in different application scenarios and can be set according to the specific application scenario.

[0053] In some application scenarios, specific targets are set for clock skew, power consumption, and the number of components included. Specifically, let's assume the current set of signal nodes and tap points are: This represents all M pre-arranged, selectable Tap elements; the set of receiving endpoints and the set of Sink points are: Let N represent the N sink points that need to be allocated downstream of all tap points. Then, a set of binary decision variables can be used. To formalize the allocation operation, where... This indicates that the sink point will be... Assigned to Tap point , This indicates no connection. Typically, a Sink point can only be assigned to one Tap point, i.e. .

[0054] Next, regarding clock skew, in this scenario, we aim to minimize the clock skew, assuming a clock skew... ,in express Clock delay (Arrival Time: the time it takes for the clock signal to reach the Sink point). Typically, Tap points are evenly distributed across the upstream clock tree, and their design goal is to make the delay from the clock source to all Tap points as uniform as possible; therefore, all Tap points generally have the same clock delay. The clock delay from a Tap point to the Sink point is proportional to the routing length. Therefore, minimizing the clock skew is equivalent to minimizing the distance difference between all Sink points and their assigned Tap points. This distance difference can be measured using the bounding box of the coordinates of the Sink points driven by the Tap points, which ultimately simplifies to the clock skew distance. ,in Indicates the Tap point The bounding box area of ​​the physical coordinates of all assigned sink points.

[0055] Next, regarding power consumption, in this scenario, we also aim to minimize power consumption. Clock tree power consumption mainly includes dynamic switching power consumption and static power consumption, where dynamic switching power consumption is proportional to the total capacitance, i.e. .for This mainly includes the load capacitor. and connecting capacitors The input capacitance of all tap points and the input capacitors of all sink points It is fixed, i.e., the load capacitance. It is fixed, therefore minimize Equivalent to minimizing The optimization objective is directly transformed into minimizing the topological distance of the clock tree (i.e., the sum of the Manhattan distances from all sink points to their assigned tap points, denoted as...). On the other hand, static power consumption mainly comes from the leakage current of transistors, and its magnitude is proportional to the number of devices. Therefore, reducing the number of buffers and gating units can directly reduce the overall static power consumption. In other words, minimizing the number of components can also achieve the goal of minimizing static power consumption.

[0056] Finally, regarding the limitation on the number of components, when using the Multi-Tap method for clock performance optimization in the aforementioned embodiments, the allocation of Tap points means that the original clock tree needs to be cloned multiple times. For example, if the sink point of a certain group (Leaf Net) is assigned to 4 different Tap points, then the upstream clock backbone devices of that Net need to be copied at least 3 times. This process significantly increases the power consumption and area of ​​the clock tree. Obviously, the number of Leaf Nets is positively correlated with the number of device clones. Therefore, by controlling the number of sink points assigned to each group of receiver endpoints (Leaf Net), the scale of Tap allocation and the number of devices such as clock gating can be controlled. Thus, while achieving the target Skew, the degree of clock tree replication can be reasonably limited, achieving a controllable balance between power consumption, area, and performance. Specifically, assuming the number of components before optimization is... The number of components obtained in each optimization iteration is The target number of components is set as follows: ,in Therefore, it is possible to set For the goal.

[0057] Finally, considering the above objectives, it can be determined that the objective is a constrained mixed-integer nonlinear programming problem (MINLP), and its objective function can be expressed as follows, where, The score is indicated by connecting the dots. and These are weighting coefficients, which can be adjusted as needed.

[0058]

[0059] That is, in some embodiments, the set target includes at least target requirements for the connection score and the number of components; wherein the connection score corresponds to the topology distance obtained by converting the clock offset distance and the connection capacitance, and the number of components is used to count the number of components on the connection when the signal node set is connected to the receiving endpoint set.

[0060] After obtaining the initial connection results in step 504, their compliance with the set objective can be determined using a similar objective function as described above. If the set objective is directly met, the initial connection results are considered to have directly met the optimization requirements, and thus the optimization can be considered complete. The initial connection results are then output as the final optimization result. If the set objective is not met, the connection method can be adjusted based on the initial connection results to form a new connection result. The objective is then re-evaluated to determine if it is satisfied. If not, the adjustment continues, and this process is iterated. During this process, various setting strategies can be used to determine whether to accept the adjusted connection scheme. For example, heuristic optimization algorithms such as Simulated Annealing and Greedy Algorithms can be used to determine whether to accept the adjustment. Afterward, regardless of acceptance, the connection result output by the setting strategy is the intermediate connection result. That is, if the adjustment is accepted, the adjusted connection scheme is the intermediate connection result; if the adjustment is not accepted, the original connection scheme before adjustment is the intermediate connection result.

[0061] Various adjustment strategies can be employed to modify the connection method. For example, at least one receiving endpoint (Sink point) can be arbitrarily selected from the current connection result and reassigned from its original connected signal node (Tap point) to another Tap point; or at least two Sink points can be arbitrarily selected and their connected Tap points can be swapped; or for at least one group (Leaf Net) of receiving endpoints, the Sink points originally connected to the same Tap point can be adjusted to connect to another Tap point, and so on. In other embodiments, adjustments can also be made to Tap points, such as replacing the Sink point connected to a certain Tap point, or swapping two Tap points, etc. It can be seen that any scheme that provides a new connection result can be considered as a connection adjustment. Of course, when making adjustments, only one of the above methods can be executed, multiple methods can be used alternately during iteration, and multiple adjustments can be performed in a single iteration. Therefore, when making adjustments, the specific adjustment method for the connection scheme can be determined according to the specific scenario. Then, considering factors such as convergence speed, a scheme with fewer changes each time can be selected for adjustment. That is, in some embodiments, the connection adjustment of the initial connection result includes: randomly selecting at least one receiving endpoint and replacing the signal node connected to the at least one receiving endpoint; or randomly selecting at least two receiving endpoints and exchanging the signal nodes connected to the at least two receiving endpoints; or determining at least one group of receiving endpoints in the set of receiving endpoints and adjusting the receiving endpoints connected to the same signal node in the at least one group of receiving endpoints to connect to another signal node; wherein the grouping of the at least one group of receiving endpoints is determined according to the chip design layout. Here, "replacement" means replacing the signal node connected to the receiving endpoint with another one; "exchange" means swapping the signal nodes connected to two receiving endpoints; in a specific embodiment, a set of receiving endpoints refers to all receiving endpoints under a Leaf Net. Among these receiving endpoints, at least one receiving endpoint connected to the same signal node is selected, and its connected signal node is adjusted to another one. Of course, if there are multiple sets of receiving endpoints connected to the same signal node under a Leaf Net, one set can be selected for adjustment, or multiple sets can be selected.

[0062] In specific scenarios, through the above adjustments, each group of receiving endpoints within the original Leaf Net will be re-divided based on the existing Leaf Net, combined with... Figure 6a and Figure 6bThe original Leaf Net 1 corresponded to four receiving endpoints A, B, C, and D. After the initial connection, receiving endpoints A, B, and C were connected to signal node Tap0 (which can be called Root0), while receiving endpoint D was connected to road signal node Tap1. This divided the original set of receiving endpoints in Leaf Net 1 into two groups, requiring the cloning of the intermediate components needed for the original receiving endpoint D. In subsequent adjustments, if receiving endpoint C is connected to Tap2, the number of groups increases to three, further requiring the cloning of the intermediate components needed for the original receiving endpoint C. Compared to the two groups after the initial connection adjustment, the number of groups increases, and the number of components also increases accordingly. Furthermore, during iterative processes, with similar adjustments, the overall number of components will increase or decrease. As mentioned above, the initial Leaf Net partitioning is pre-defined in the chip design layout, and the Leaf Net can be read from the chip design layout. That is, in some embodiments, adjusting the connection result of the initial connection includes: determining at least one set of receiving endpoints based on the chip design layout, wherein the at least one set of receiving endpoints is divided based on the leaf node network of the chip design layout; and adjusting the number of components based on the adjustment of the number of groups of the at least one set of receiving endpoints during the adjustment process.

[0063] After the adjustment is completed, it is necessary to determine whether to accept the adjustment. Here, a condition for accepting the adjustment can be set. If the condition is met, the adjustment is accepted; if not, it is rejected, and the process continues or is repeated. This condition can be based on the aforementioned criteria, using connection scores and component counts as the judgment standards. For connection scores, the adjusted score can be set to be less than the original score or less than the target score. For component counts, the adjusted number of components can be set to be less than the target number or less than the original number. When the adjustment meets the requirements for both connection score and component count, the adjusted connection scheme is considered superior, and the adjustment is directly accepted. That is, in some embodiments, determining whether to accept the adjustment through a set strategy includes: determining whether to accept the adjustment based on a comparison of the connection scores and component counts before and after the adjustment.

[0064] Building upon this, this embodiment further selects an annealing strategy from various setting strategies to determine whether to accept adjustments. It can also use connection scores and component counts as judgment criteria. Similar to the previous embodiment, when both connection scores and component counts meet the conditions, the adjusted solution is considered superior, and the adjustment is directly accepted. However, unlike the previous embodiment, if the adjustment does not meet the aforementioned judgment conditions—that is, the connection score or component count does not meet the conditions—then the annealing strategy is applied probabilistically. Determine whether to accept the proposed adjustment, among which For the current temperature, the annealing strategy sets an initial temperature at the beginning, and then adjusts the temperature according to the iteration cycle. It will gradually decrease. and This compares the score of the connection after the adjustment to the score before the adjustment. It can be seen that as the number of iterations increases, the temperature... As the probability of accepting a solution that does not meet the conditions decreases, the probability of accepting the adjustment also decreases. That is, in some embodiments, determining whether to accept the adjustment includes: accepting the adjustment in response to the adjusted connection score being less than the original connection score, and the adjusted number of components being less than the original number of components or the adjusted number of components being less than a set target number; otherwise, determining the probability of accepting the adjustment based on the adjusted connection score, the original connection score, and the current temperature set by the set strategy, and determining whether to accept the adjustment based on the probability.

[0065] Step 508: In response to the intermediate connection result meeting the set target, the intermediate connection result is determined as the optimized result.

[0066] In this step, after obtaining the intermediate connection results, we re-evaluate whether the intermediate connection results meet the set target. If they do, we output the current intermediate connection results as the final optimization result.

[0067] If the set target is still not met, the aforementioned connection adjustment can be repeated. The intermediate connection result is used as input, adjusted, and a set strategy is used to determine whether the adjustment is accepted. A new intermediate connection result is then output, and the process of judging whether the intermediate connection result meets the set target continues. This iterative cycle continuously updates the intermediate connection result. Specifically, in some embodiments, after generating the intermediate connection result, the method further includes: in response to the intermediate connection result not meeting the set target, performing the connection adjustment on the intermediate connection result, determining whether to accept the adjustment using the set strategy, and iterating on the intermediate connection result.

[0068] Subsequently, during the iterative process of the intermediate connection results, if the set target cannot be met, a stopping condition can be set for the iteration to save resources. Then, after each intermediate connection result is obtained, before judging the set target based on the intermediate connection result, a judgment on whether the stopping condition is met can be made first. If the stopping condition is met, the judgment on the set target can be skipped, and the current intermediate connection result can be directly output as the optimization result. In some embodiments, the stopping conditions that can be set include: (1) in multiple consecutive iterations, the connection score and the number of components do not change significantly (i.e., in a set number of consecutive iterations, the change range of the connection score and the number of components is within a set threshold range); (2) the current temperature set in the setting strategy (e.g., annealing strategy). (3) The number of iterations reaches the set threshold temperature, etc. That is, in some embodiments, before the intermediate connection result meets the set target, the method further includes: in response to the change of the connection score and the number of components within a set range during a set number of consecutive iterations, or in response to the current temperature set by the set strategy decreasing to the set temperature, or in response to reaching the set number of iterations, determining the current intermediate connection result as the optimization result.

[0069] Finally, the optimized results can be output. They can be sent to downstream EDA processes for further processing, or the chip design layout can be adjusted directly based on the optimized results. Of course, the output methods for the optimized results can also include various methods, such as displaying the output on a corresponding device to provide feedback to the operator. In other embodiments, the output method for the optimized results is not limited to display; it can also be used to store, display, use, or further process the optimized results. The specific output method for the optimized results can be flexibly selected according to different application scenarios and implementation needs.

[0070] Specifically, for example, in the application scenario where the method of this embodiment is executed on a single device, the optimization results can be directly output on the display component (monitor, projector, etc.) of the current device, so that the operator of the current device can directly see the content of the optimization results on the display component.

[0071] For example, in application scenarios where the method of this embodiment is executed on a system composed of multiple devices, the optimization results can be sent to other preset devices within the system, i.e., synchronization terminals, as recipients, via any data communication method (wired connection, NFC, Bluetooth, Wi-Fi, cellular network, etc.), so that the synchronization terminals can perform subsequent processing. Optionally, the synchronization terminal can be a preset server, which is generally located in the cloud and serves as a data processing and storage center, capable of storing and distributing the optimization results; wherein, the recipients of the distribution are terminal devices, and the owners or operators of these terminal devices can be managers, designers, maintenance personnel, etc., at various stages of chip design.

[0072] For example, in the application scenario where the method of this embodiment is executed on a system composed of multiple devices, the optimization results can be directly sent to a preset terminal device through any data communication method. The terminal device can be one or more of the devices listed in the preceding paragraphs.

[0073] As can be seen from the above, the embodiments of this disclosure provide a clock network optimization method. The method includes: acquiring a chip design layout; determining a set of signal nodes and a set of receiving endpoints based on the chip design layout; establishing connections between the set of signal nodes and the set of receiving endpoints to generate initial connection results; in response to the initial connection results not meeting a set target, adjusting the connections of the initial connection results, determining whether to accept the adjustment through an annealing strategy, and generating intermediate connection results; in response to the intermediate connection results meeting the set target, determining the intermediate connection results as optimization results. In setting up the clock network, this disclosure first establishes an initial connection after determining the signal node and receiving endpoint to be connected. Then, the connection effect is tested according to the set target requirements. If it does not meet the target, adjustments are made based on the currently established connection. During the adjustment process, as the receiving endpoint switches to the signal node, the corresponding parameters change accordingly, and the number of cloned devices in the connection also increases or decreases, thereby adjusting the number of components in the clock network. When the number of components is reduced to meet the requirements, the area and power consumption are reduced due to the reduced number of cloned components in the original optimization process. At the same time, the smaller number of cloned components further solves problems such as load balancing and wiring congestion, improving the chip design effect.

[0074] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this disclosure embodiment can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0075] It should be noted that the above description describes specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0076] Based on the same inventive concept, corresponding to any of the above embodiments, this disclosure also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing the computer program stores computer instructions for causing the computer to perform the method 500 as described in any of the above embodiments.

[0077] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic tape / disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0078] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to perform the method 500 as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0079] Based on the same inventive concept, corresponding to the method 500 of any of the above embodiments, this disclosure also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform the method 500. Corresponding to the execution entity for each step in each embodiment of method 500, the processor executing the corresponding step may belong to the corresponding execution entity.

[0080] The computer program product of the above embodiments is used to cause the processor to execute the method 500 as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0081] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0082] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0083] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0084] This disclosure is intended to cover all such substitutions, modifications, and variations falling within the broad scope of the above embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A clock network optimization method, characterized in that, include: Obtain the chip design layout, and determine the set of signal nodes and the set of receiving endpoints based on the chip design layout; Establish a connection between the set of signal nodes and the set of receiving endpoints, and generate an initial connection result; In response to the initial connection result not meeting the set target, the initial connection result is adjusted, and an intermediate connection result is generated by determining whether to accept the adjustment through a set strategy. Specifically, the connection adjustment involves adjusting the connection relationship between the signal nodes in the signal node set and the receiving endpoints in the receiving endpoint set. The set target includes a limit on the number of components. The intermediate connection result determines the number of components by determining the increase or decrease of cloned devices before and after the adjustment. In response to the intermediate connection result meeting the set target, the intermediate connection result is determined as the optimized result.

2. The method according to claim 1, characterized in that, Establishing the connection between the signal node set and the receiving endpoint set includes: For any receiving endpoint in the set of receiving endpoints, determine the nearest signal node in the set of signal nodes, and establish a connection between the receiving endpoint and the signal node.

3. The method according to claim 1, characterized in that, The set target includes at least target requirements for connection score and number of components; wherein, the connection score corresponds to the clock offset distance and the topology distance obtained by the connection capacitance conversion, and the number of components is used to count the number of components on the connection when the signal node set is connected to the receiving endpoint set.

4. The method according to claim 3, characterized in that, The process of determining whether to accept adjustments by setting a strategy includes: Based on the comparison results of the connection scores and the number of components before and after the adjustment, it is determined whether to accept the adjustment.

5. The method according to claim 4, characterized in that, The process of determining whether to accept the adjustment includes: If the adjusted connection score is less than the original connection score, and the adjusted number of components is less than the original number of components, or the adjusted number of components is less than the set target number, then the adjustment is accepted. Conversely, based on the adjusted connection score, the connection score before adjustment, and the current temperature set by the set strategy, the probability of accepting the adjustment is determined, and whether to accept the adjustment is determined according to the probability.

6. The method according to claim 3, characterized in that, The connection adjustment of the initial connection result includes: At least one set of receiving endpoints is determined based on the chip design layout, and the at least one set of receiving endpoints is partitioned based on the leaf node network of the chip design layout; The number of components is adjusted based on the adjustment of the number of groups of the at least one set of receiving endpoints during the adjustment process.

7. The method according to claim 1, characterized in that, The connection adjustment of the initial connection result includes: Randomly select at least one receiving endpoint and replace the signal node connected to the at least one receiving endpoint; or Randomly select at least two receiving endpoints and exchange the signal nodes connected to the at least two receiving endpoints; or At least one set of receiving endpoints is determined in the set of receiving endpoints, and receiving endpoints in the at least one set of receiving endpoints that are connected to the same signal node are adjusted to connect to another signal node; wherein the grouping of the at least one set of receiving endpoints is determined according to the chip design layout.

8. The method according to claim 1, characterized in that, After generating the intermediate connection results, the method further includes: In response to the intermediate connection result not meeting the set target, the connection result is adjusted, and the set strategy determines whether to accept the adjustment, so as to iterate the intermediate connection result.

9. The method according to claim 8, characterized in that, Before the intermediate connection result meets the set target, the method further includes: In response to the changes in the connection score and the number of components being within a set range during a set number of iterations, or in response to the current temperature set by the set strategy decreasing to a set temperature, or in response to reaching a set number of iterations, the current intermediate connection result is determined as the optimization result; wherein the connection score corresponds to the clock offset distance and the topology distance obtained by converting the connection capacitance.

10. A computer device, characterized in that, It includes one or more processors, memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, the programs including instructions for performing the method according to any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium containing a computer program, characterized in that, When the computer program is executed by one or more processors, the processors perform the method of any one of claims 1 to 9.

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