Chip heat dissipation structure, design method thereof and chip packaging structure

Abstract

The invention provides a chip heat dissipation structure and a design method thereof, and a chip packaging structure, and the chip heat dissipation structure comprises a bare chip which comprises a substrate and an active device layer disposed on the surface of one side of the substrate; and the bionic micro-channel is arranged on the substrate and cools the active device layer through diversion cooling liquid, and the bionic micro-channel is in a vascular network shape. According to the structure, the active device layer can be directly cooled through heat conduction of the substrate, the flowing performance of the cooling liquid can be improved, the thermal resistance is reduced, the flowing range of the cooling liquid can be expanded, and the heat dissipation requirement of a high-power-density chip can be more sufficiently and efficiently met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a chip heat dissipation structure, a design method thereof and a chip packaging structure. BACKGROUND

[0002] With the continuous growth of the demand for chip computing power in society, the power density of chips has increased exponentially, which has brought severe challenges to the heat dissipation of chips. At present, the main heat dissipation way of chips is to set a heat sink in contact with the chip outside to absorb and dissipate the heat generated by the chip. However, in this heat dissipation way, the area of the liquid cooling plate of the heat sink cooling the chip is far away from the heat source on the chip, and is sandwiched by the chip packaging thermal resistance, the interface material thermal resistance and the heat sink substrate thermal resistance, etc., resulting in high overall thermal resistance of the heat sink and the heat dissipation efficiency cannot meet the heat dissipation demand of high-power chips. SUMMARY

[0003] Therefore, the present application provides a chip heat dissipation structure which can more fully and efficiently meet the heat dissipation demand of high-power density chips. In addition, the present application also provides a design method of the chip heat dissipation structure and a chip packaging structure.

[0004] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0005] A chip heat dissipation structure, comprising:

[0006] a die comprising a substrate and an active device layer arranged on one side surface of the substrate;

[0007] a bionic micro-channel arranged on the substrate and cooling the active device layer by flow guiding cooling liquid, and the bionic micro-channel is in the shape of a blood vessel network.

[0008] Optionally, in the chip heat dissipation structure, the bionic micro-channel comprises multi-stage micro-channels with different groove widths, and the distribution of the multi-stage micro-channels in different areas of the substrate corresponds to the power density distribution of different areas of the active device layer.

[0009] Optionally, in the chip heat dissipation structure, the distribution of the multi-stage micro-channels in different areas of the substrate comprises different extension lengths of different stage micro-channels, and / or different deployment densities of the multi-stage micro-channels.

[0010] Optionally, in the chip heat dissipation structure, the multi-stage micro-channels comprise a first-stage micro-channel, a second-stage micro-channel and a third-stage micro-channel with groove widths decreasing in turn.

[0011] The different regions of the active device layer include: a first region whose power density reaches 2 / 3 or more of the maximum power density of the active device layer; a second region whose power density reaches between 1 / 3 and 2 / 3 of the maximum power density of the active device layer; and a third region whose power density is less than 1 / 3 of the maximum power density of the active device layer.

[0012] In the first region, the extension length of the third-level microchannel is greater than the extension lengths of the first-level microchannel and the second-level microchannel; in the second region, the extension length of the second-level microchannel is greater than the extension lengths of the first-level microchannel and the third-level microchannel; and in the third region, the extension length of the first-level microchannel is greater than the extension lengths of the second-level microchannel and the third-level microchannel.

[0013] Optionally, in the above chip heat dissipation structure, in the first region, the deployment density K1 of the multi-level microchannel is 65% < K1 < 75%; in the second region, the deployment density K2 of the multi-level microchannel is 45% < K2 < 65%; and in the third region, the deployment density K3 of the multi-level microchannel is 35% < K3 < 45%.

[0014] Optionally, in the above chip heat dissipation structure, the groove width of the third-level microchannel is greater than 100 μm, the groove width of the second-level microchannel is 1.6-2 times the groove width of the third-level microchannel, and the groove width of the first-level microchannel is 3.2-4 times the groove width of the second-level microchannel.

[0015] Optionally, in the above chip heat dissipation structure, the groove width of the third-level microchannel is 125 μm-175 μm, the groove width of the second-level microchannel is 200 μm-350 μm, and the groove width of the first-level microchannel is 640 μm-1400 μm.

[0016] Optionally, in the above chip heat dissipation structure, the thickness of the substrate is 300 μm-500 μm.

[0017] In the thickness direction of the substrate, the depth of the first-level microchannel, the second-level microchannel and the third-level microchannel is 200 μm-300 μm.

[0018] Optionally, in the above chip heat dissipation structure, the connection part of any two levels of microchannels in different levels of microchannels is a circular arc structure, and the curvature radius of the circular arc structure is 1.5 times or more of the groove width of the microchannel with smaller groove width among the any two levels of microchannels.

[0019] Optionally, in the above chip heat dissipation structure, among the first-level microchannel, the second-level microchannel and the third-level microchannel, the spacing between adjacent other microchannels in the extension direction of any one of the microchannels is less than 12 times the groove width of the microchannel.

[0020] Optionally, in the chip heat dissipation structure, the microfluid channels of the same level are distributed at equal intervals in the first region, the second region and the third region.

[0021] Optionally, in the chip heat dissipation structure, the bionic microfluid channel is symmetrically arranged about two mutually perpendicular center lines of the substrate, and the outlet channel for leading out the cooling liquid in the bionic microfluid channel is perpendicular to a first center line of the two mutually perpendicular center lines.

[0022] Furthermore, the angle between the extension direction of the first-level microfluid channel and the second-level microfluid channel and the first center line is less than 60°, and the angle between the extension direction of the third-level microfluid channel and the first center line is less than 90°.

[0023] Optionally, in the chip heat dissipation structure, the surface of the substrate provided with the bionic microfluid channel is provided with an outlet channel for leading out the cooling liquid in the bionic microfluid channel, and the outlet channel is perpendicular to a first center line of two mutually perpendicular center lines of the substrate.

[0024] Furthermore, the die includes a liquid inlet structure, the liquid inlet structure is arranged on the side of the substrate provided with the bionic microfluid channel, and the liquid inlet structure forms a liquid inlet channel for leading in the cooling liquid to the bionic microfluid channel.

[0025] Optionally, in the chip heat dissipation structure, the bionic microfluid channel is formed on the side surface of the substrate away from the active device layer, and the liquid inlet structure includes:

[0026] a first liquid inlet layer, which is sealingly connected to the substrate and covers the bionic microfluid channel, and is provided with a liquid inlet hole in communication with the bionic microfluid channel;

[0027] a second liquid inlet layer, which is sealingly connected to the first liquid inlet layer and located on the side of the first liquid inlet layer away from the substrate, and is provided with a liquid inlet port in communication with the liquid inlet hole.

[0028] Optionally, in the chip heat dissipation structure, a plurality of layers of the bionic microfluid channel are arranged in the substrate, and the liquid inlet structure is a 3D manifold communicating each layer of the bionic microfluid channel.

[0029] A design method of a chip heat dissipation structure, which is applicable to the chip heat dissipation structure, and the method includes the following steps:

[0030] obtaining the power density of different regions of the active device layer;

[0031] obtaining the extension length relationship of the microfluid channels of different levels in the corresponding region according to the different power densities;

[0032] According to the power density and the extension length relationship, a deployment density of the biomimetic micro-channel in the corresponding area is obtained;

[0033] According to the power density, the extension length relationship and the deployment density, at least one of the following is obtained: a groove width of each level of micro-channel, a curvature radius of a connection part of any two levels of micro-channels, a spacing between two adjacent micro-channels connected to the same micro-channel, a spacing between equidistantly distributed same level micro-channels, and an included angle between extension directions of different levels of micro-channels connected to each other.

[0034] A chip packaging structure comprises:

[0035] a substrate;

[0036] a die disposed on the substrate and comprising a base and an active device layer disposed on a surface of the base facing the substrate;

[0037] a thermally conductive packaging shell connected to the substrate and covering the die;

[0038] a liquid cooling plate in thermally conductive contact or connection with the thermally conductive packaging shell;

[0039] a first biomimetic micro-channel formed in the thermally conductive packaging shell and / or the liquid cooling plate and cooling the active device layer by flow-guiding cooling liquid, and the first biomimetic micro-channel is in the shape of a blood vessel network.

[0040] Optionally, in the above chip packaging structure, a second biomimetic micro-channel is disposed on the base, the second biomimetic micro-channel cools the active device layer by flow-guiding cooling liquid, and the second biomimetic micro-channel is in the shape of a blood vessel network.

[0041] The chip heat dissipation structure provided in the present application processes a biomimetic micro-channel on the base of the die, i.e. the biomimetic micro-channel is disposed inside the die, so that the active device layer disposed on the base can be cooled more directly, fully and efficiently, and the biomimetic micro-channel is disposed in the shape of a blood vessel network, i.e. the shape and distribution mode of the biomimetic micro-channel are the same as the shape and distribution mode of the blood vessel network of animals and humans in the body, so that not only the active device layer can be cooled directly by the heat conduction of the base, but also the flow performance of the cooling liquid can be improved, the thermal resistance is reduced, and the flow range of the cooling liquid can be expanded, so that the heat dissipation demand of the high-power-density chip can be met more fully and efficiently. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only need to be drawn for the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings.

[0043] Figure 1 An exploded view of the chip heat dissipation structure provided in the embodiments of the present application;

[0044] Figure 2 A top view of the substrate provided with the bionic micro-channel;

[0045] Figure 3 A power density distribution diagram of the active device layer;

[0046] Figure 4 A schematic diagram of the bionic micro-channel and the active device layer being arranged in the local area of the bionic micro-channel and the local area of the active device layer;

[0047] Figure 5 A partial enlarged view of the bionic micro-channel;

[0048] Figure 6 A partial enlarged view of Figure 5 ;

[0049] Figure 7 A structural schematic diagram of the cooling liquid flowing in the liquid inlet structure;

[0050] Figure 8 A structural schematic diagram of the cooling liquid flowing in the bionic micro-channel and the lead-out channel;

[0051] Figure 9 A structural schematic diagram of the multilayer bionic micro-channel guiding the cooling liquid through the 3D manifold;

[0052] Figure 10 A simulation comparison diagram of the conventional straight channel and the bionic micro-channel;

[0053] Figure 11 A simulation effect diagram of the extreme heat dissipation capacity of the bionic micro-channel;

[0054] Figure 12 A design logic diagram of the chip heat dissipation structure provided in the embodiments of the present application;

[0055] Figure 13 A structural schematic diagram of the chip packaging structure provided in the embodiments of the present application.

[0056] In the above Figures 1-13 , the following is provided:

[0057] 1-die, 2-bionic microfluidic channel, 3-substrate, 4-thermally conductive package shell, 5-liquid cooling plate, 6-first bionic microfluidic channel;

[0058] 101-substrate, 102-active device layer, 103-second center line, 104-first center line, 105-lead-out channel, 106-liquid inlet structure;

[0059] 201-primary microfluidic channel, 202-secondary microfluidic channel, 203-tertiary microfluidic channel, 204-connection site,

[0060] 1061-first liquid inlet layer, 1062-liquid inlet hole, 1063-second liquid inlet layer, 1064-liquid inlet port. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0062] As Figures 1-11As shown, the embodiment of the present application provides a chip heat dissipation structure, which can improve the heat dissipation effect and efficiency of the chip, and can be applied to heterogeneous integrated packaging chips of high power density non-uniform heat sources, especially to AI chips and other scenes with high computing power demand, high power density and uneven heat source distribution. The chip heat dissipation structure mainly includes a die 1 (also known as a bare chip or DIE) and a bionic microchannel 2, and the die 1 further includes a substrate 101 and an active device layer 102 disposed on one side surface of the substrate 101. The active device layer 102, for example, is a MOS transistor layer, which is integrated on the surface of the substrate 101 through a chip preparation process. The bionic microchannel 2 is also disposed on the substrate 101 (i.e. integrated in the substrate 101 of the die 1), that is, the bionic microchannel 2 is disposed in the interior of the die 1. Since the active device layer 102 is disposed on one side surface of the substrate 101, the bionic microchannel 2 can be processed on the other side of the substrate 101. Optionally, the bionic microchannel 2 can be processed and formed on the substrate 101 of silicon material by etching process. The bionic microchannel 2 in the present application adopts a vascular network shape, that is, the shape and distribution mode of the bionic microchannel are the same as the shape and in-vivo distribution mode of the vascular network of animals and humans. Compared with the prior art of disposing a heat sink outside the die 1, the cooling liquid can flow through the bionic microchannel 2 to directly cool the active device layer 102 through the heat conduction of the substrate 101, thereby eliminating the influence of chip packaging thermal resistance, interface material thermal resistance and heat sink substrate thermal resistance, realizing near-junction effect, and more fully and efficiently meeting the heat dissipation demand of high power density chips. Moreover, the vascular network-shaped bionic microchannel can also improve the flow performance of the cooling liquid, reduce the thermal resistance, effectively reduce the junction temperature of the chip, improve the temperature uniformity and maximize the use of cooling resources, so that the cooling effect is further improved.

[0063] In optional embodiments, as shown in Figure 2 and Figure 5 The bionic microchannel 2 can include multiple microchannels with different groove widths, and the distribution of the multiple microchannels in different regions of the substrate 101 corresponds to the power density distribution of different regions of the active device layer 102. The bionic microchannel 2 is formed by etching or other operations on the substrate 101 to form grooves on the substrate 101, so the groove width is the flow channel width of the bionic microchannel 2. By including multiple microchannels with different groove widths (i.e. multiple microchannels), the cooling liquid can have multiple different flow performances, thereby meeting more diversified cooling demands, and the cooling effect can be more flexible and targeted for adjustment according to different heating conditions of the active device layer 102. Specifically, as shown in Figure 3As shown, the power density of different regions of the active device layer 102 is different, resulting in different heat generation of these regions, and the different heat generation results in different cooling capacity required by these regions to achieve the cooling requirement, and the cooling capacity is related to the distribution of the multi-stage micro-channel at the positions corresponding to these regions, so that the distribution of the multi-stage micro-channel at different regions of the substrate 101 corresponds to the distribution of the power density of different regions of the active device layer 102, so that different cooling capacity corresponding to different heat generation can be provided, so that each region of the entire active device layer 102 can be well cooled, and the uniformity of the entire active device layer 102 is also improved.

[0064] Further, the distribution of the multi-stage micro-channel at different regions of the substrate 101 includes that the extension lengths of different stages of micro-channels are different, and / or the deployment densities of the multi-stage micro-channels are different. Specifically, in the process of designing the bionic micro-channel 2, the region of the substrate 101 opposite to the active device layer 102 can be divided into a plurality of unit regions with equal areas, and the distribution of the multi-stage micro-channel in each unit region is determined in turn. Since the cooling capacity of the bionic micro-channel 2 in each unit region is mainly related to the extension length and the deployment density of the multi-stage micro-channel, the distribution is mainly designed for at least one of the two aspects. Among them, the different extension lengths of different stages of micro-channels refer to that the micro-channels of different levels (the classification standard of the level is the groove width of the micro-channel) in a unit region respectively have different extension lengths, and the extension length of the micro-channel of one level is greater than the extension length of the micro-channel of other levels (the extension length is the flow distance of the cooling liquid in a single level of micro-channel), that is, the micro-channels distributed in a unit region will be dominated by a certain level of micro-channel; the deployment density can be simply understood as the number of micro-channels set in a unit region. The more the number is, the greater the deployment density is. By increasing the deployment density of a certain level of micro-channel, more cooling liquid can flow in the micro-channel of the level, so that different unit regions have different cooling liquid flow performance and different cooling performance on the active device layer 102.

[0065] Optionally, the multi-stage micro-channel includes a first-stage micro-channel 201, a second-stage micro-channel 202 and a third-stage micro-channel 203 with groove widths decreasing in turn. By setting the three-stage micro-channel, the entire bionic micro-channel 2 can be more similar to the blood vessel network in animals and human bodies, so that the bionic micro-channel 2 has better cooling performance and cooling effect.

[0066] In the case that the extension length of the multi-stage micro-channel is arranged corresponding to the different power density areas of the active device layer 102, the different areas of the active device layer 102 are divided into: a first area, whose power density reaches 2 / 3 or above of the maximum power density of the active device layer 102; a second area, whose power density reaches between 1 / 3 and 2 / 3 of the maximum power density of the active device layer 102; and a third area, whose power density is less than 1 / 3 of the maximum power density of the active device layer 102. On this basis, in the first area, the extension length of the third-stage micro-channel 203 is greater than that of the first-stage micro-channel 201 and the second-stage micro-channel 202; in the second area, the extension length of the second-stage micro-channel 202 is greater than that of the first-stage micro-channel 201 and the third-stage micro-channel 203; and in the third area, the extension length of the first-stage micro-channel 201 is greater than that of the second-stage micro-channel 202 and the third-stage micro-channel 203. In the first area with higher power density, the multi-stage micro-channel mainly uses the third-stage micro-channel 203. Since the groove width of the third-stage micro-channel 203 is smaller, the flow of the cooling liquid in each third-stage micro-channel 203 is smaller, so that the cooling liquid has better fluidity, thereby absorbing the heat generated by the active device layer 102 in this area more fully in a more smooth flow process, so as to improve the cooling performance of the first area and achieve better cooling effect. In the second area with lower power density, the multi-stage micro-channel mainly uses the second-stage micro-channel 202. Since the groove width of the second-stage micro-channel 202 is between that of the third-stage micro-channel 203 and that of the first-stage micro-channel 201, the heat absorption capacity of the second-stage micro-channel 202 is also between that of the third-stage micro-channel 203 and that of the first-stage micro-channel 201, so that it can better match the heat generated by the active device layer 102 in the second area, on the basis of ensuring sufficient cooling of the second area, without wasting cooling resources, achieving energy saving optimization. In the third area with the lowest power density, since the heat generated is less, the multi-stage micro-channel mainly uses the first-stage micro-channel 201. Since the groove width of the first-stage micro-channel 201 is the largest, the flow of the cooling liquid therein is larger, which can also better achieve cooling of the third area.

[0067] Further, when the deployment density of the multi-stage microfluid channel is arranged corresponding to the different power density areas of the active device layer 102, in the first area, the deployment density K1 of the multi-stage microfluid channel is set to 65% < K1 < 75%; in the second area, the deployment density K2 of the multi-stage microfluid channel is set to 45% < K2 < 65%; and in the third area, the deployment density K3 of the multi-stage microfluid channel is set to 35% < K3 < 45%. Since the first area has a large amount of heat generation, the deployment density of the multi-stage microfluid channel in this area is the largest, and since the heat generation of the second area and the third area decreases in turn, the deployment density of the multi-stage microfluid channel in the second area and the third area decreases in turn. The percentage value of the deployment density refers to the percentage of the area occupied by the microfluid channel to the total area of the area. The selection of the above percentage value range can better match the heat and cooling capacity, that is, the multi-stage microfluid channel can cool the corresponding area well to meet the cooling requirements of the active device layer 102, while avoiding waste of cooling resources, and maximizing the use of cooling resources.

[0068] Specifically, based on the bionic geometry structure of the bionic microfluid channel 2 adopting a vascular network, the groove width relationship of the first-stage microfluid channel 201, the second-stage microfluid channel 202 and the third-stage microfluid channel 203 can be set as follows: the groove width of the third-stage microfluid channel 203 is greater than 100 μm, the groove width of the second-stage microfluid channel 202 is 1.6-2 times the groove width of the third-stage microfluid channel 203, and the groove width of the first-stage microfluid channel 201 is 3.2-4 times the groove width of the second-stage microfluid channel 202. By setting the groove width of the third-stage microfluid channel 203 to be greater than 100 μm, the bionic microfluid channel 2 provided by the present application can meet the industry standard (the industry standard requires that the impurity particle size in the cooling fluid be greater than 100 μm), and in order to further optimize the cooling effect, the groove width of the third-stage microfluid channel 203 is preferably 125 μm-175 μm, based on the above multiple relationship, the groove width of the second-stage microfluid channel 202 is preferably 200 μm-350 μm, and the groove width of the first-stage microfluid channel 201 is preferably 640 μm-1400 μm. By selecting the groove width value range, the flow guiding performance of the bionic microfluid channel 2 for the cooling liquid can be further optimized, so that the cooling liquid can more fully absorb the heat generated by the active device layer 102 in the bionic microfluid channel 2, and the cooling effect on the active device layer 102 is improved.

[0069] In an optional embodiment, the thickness of the substrate 101 can be set to 300 μm to 500 μm; and, in the thickness direction of the substrate 101, the depths of the primary microchannel 201, the secondary microchannel 202, and the tertiary microchannel 203 are all 200 μm to 300 μm. The biomimetic microchannel 2 is formed by machining grooves on the substrate 101. Therefore, based on the thickness of the substrate 101 being 300 μm to 500 μm, the depth of the biomimetic microchannel 2 can be set to 200 μm to 300 μm. This makes the thickness from the bottom of the groove of the biomimetic microchannel 2 to the surface of the active device layer 102 on the substrate 101 100 μm to 200 μm (preferably 100 μm), and also makes the depths of the primary microchannel 201, the secondary microchannel 202, and the tertiary microchannel 203 proportional to the thickness of the substrate 101, for example, when... When the thickness of the substrate 101 is 300 μm, the depth of the biomimetic microchannel 2 is 200 μm; when the thickness of the substrate 101 is 400 μm, the depth of the biomimetic microchannel 2 is 250 μm; and when the thickness of the substrate 101 is 500 μm, the depth of the biomimetic microchannel 2 is 350 μm. This ensures that the substrate 101 still has a certain thickness after the biomimetic microchannel 2 is fabricated to ensure that the substrate 101 meets the basic structural strength requirements. It also enables the substrate 101 to achieve timely and sufficient heat conduction between the biomimetic microchannel 2 and the active device layer 102. The reason why the depths of the primary microchannel 201, the secondary microchannel 202, and the tertiary microchannel 203 are chosen to be 200μm to 300μm is that, based on the above-mentioned groove width range, this depth range can form a suitable tooth width ratio (the tooth width ratio refers to the ratio of the depth of the microchannel to the groove width), thus avoiding an excessively large tooth width ratio that would reduce the structural strength of the biomimetic microchannel 2.

[0070] like Figure 6 As shown, in an optional embodiment, the connection point 204 between any two microchannels in different microchannel stages can also be an arc structure. The radius of curvature of this arc structure is more than 1.5 times the width of the smaller of the two microchannels. The connection point 204 between any two microchannels in different microchannel stages is the corner or bifurcation point of the biomimetic microchannel 2. In order to improve the smoothness of coolant flow and reduce flow resistance at this point, the two microchannels can adopt a high-curvature smooth transition design. That is, the two forks formed by the bifurcation (the forks are actually microchannels) form an arc structure, and the radius of curvature of this arc structure is set to more than 1.5 times the width of the smaller of the two forks, such as 1.5 times, 2 times, 2.5 times, etc. In this way, the cooling effect on the active device layer 102 can also be improved by improving the flow performance of the coolant.

[0071] In optional embodiments, in the primary microfluidic channel 201, the secondary microfluidic channel 202 and the tertiary microfluidic channel 203, and in any one of them, the spacing between the adjacent other one in the extension direction of this one is less than 12 times the slot width of this one, that is, as shown in Figure 5 the spacing between the two adjacent other microfluidic channels connected to this microfluidic channel in the extension direction of this microfluidic channel is L, and the value of L is less than 12 times the slot width W of this microfluidic channel, that is, L < 12W, which ensures that the spacing between any two adjacent microfluidic channels connected to the same microfluidic channel in the biomimetic microfluidic channel 2 is not too large, reduces the flow resistance of the biomimetic microfluidic channel 2, and makes the cooling liquid flow more smoothly. In addition, the spacing between any two adjacent microfluidic channels connected to the same microfluidic channel can also be limited by the above-mentioned correspondence between the deployment density and the power density to avoid the adverse effects of too many branches on the flow performance of the cooling liquid.

[0072] In optional embodiments, in the first region, the second region and the third region, the microfluidic channels of the same level can be further distributed at equal intervals, that is, in each unit region, the plurality of primary microfluidic channels 201 are distributed at equal intervals, the plurality of secondary microfluidic channels 202 are distributed at equal intervals, and / or the plurality of tertiary microfluidic channels 203 are distributed at equal intervals. This can further optimize the layout of the biomimetic microfluidic channel 2 and improve the cooling effect on the active device layer 102.

[0073] As shown in Figure 2 , the shape of the substrate 101 is generally rectangular, and it has two mutually perpendicular center lines. In order to reduce the design and processing difficulty of the biomimetic microfluidic channel 2, the biomimetic microfluidic channel 2 can be symmetrically arranged on the substrate 101 with respect to the two mutually perpendicular center lines of the substrate 101, that is, the biomimetic microfluidic channel 2 is arranged as a central symmetric structure with the center of the substrate 101 as the center of symmetry, and a discharge channel 105 is etched on the substrate 101 to guide the cooling liquid flowing through the biomimetic microfluidic channel 2 out of the substrate 101, while the inlet channel for introducing the cooling liquid into the biomimetic microfluidic channel 2 can be arranged at the middle part of the substrate 101 to introduce the cooling liquid into the biomimetic microfluidic channel 2 (as shown in Figure 8 , for example, the center part of the substrate 101 or the part coinciding with one of the center lines of the substrate 101, which is referred to as the second center line 103 (the other center line of the substrate 101 is referred to as the first center line 104) for ease of description. In this way, the cooling liquid flows in the biomimetic microchannel from the middle part of the substrate 101 to both sides of the second center line 103, as shown by the arrows in Figure 8 , the flow direction is macroscopically perpendicular to the second center line 103, that is, parallel to the first center line 104, and correspondingly, as shown in Figure 2 and Figure 8As shown, the outflow channel 105 is also arranged in parallel with the second center line 103 (or in other words, arranged perpendicularly to the first center line 104), and the outflow channel 105 is arranged in at least two, and the outflow channel 105 is arranged symmetrically about the second center line 103 on both side edges of the substrate 101, so that the cooling liquid can flow in the biomimetic microfluidic channel 2 in the direction of the first center line 104 on a macroscopic scale and finally enter the outflow channel 105.

[0074] On the basis of the above-mentioned arrangement of the biomimetic microfluidic channel 2 in a central symmetric structure, the angle between the extension direction of the first-level microfluidic channel 201 and the second-level microfluidic channel 202 and the first center line 104 is less than 60°, and the angle between the extension direction of the third-level microfluidic channel 203 and the first center line 104 is less than 90°. In this way, the extension direction of the first-level microfluidic channel 201, the second-level microfluidic channel 202 and the third-level microfluidic channel 203 is as close as possible to the extension direction of the first center line 104, so that the cooling liquid can flow more smoothly in the biomimetic microfluidic channel 2, and the cooling effect is improved.

[0075] In a specific example, as shown in the figure, Figure 4 The area power density is in the interval of more than two-thirds of the maximum power density, that is, the area is the first area, the multi-level microfluidic channel deployment density range is 65% to 75%, and the slot width requirements of the above-mentioned first-level microfluidic channel 201, second-level microfluidic channel 202 and third-level microfluidic channel 203 are adopted. Because the unit area of this area is small and the deployment density is high, only the second-level microfluidic channel 202 and the third-level microfluidic channel 203 are used. When designing the biomimetic microfluidic channel 2 corresponding to this area, the upstream microfluidic channel (this upstream microfluidic channel is the microfluidic channel in the other unit area adjacent to this area and closer to the second center line 103) and the unit area are connected at the starting point, the second-level microfluidic channel 202 is arranged, and due to the requirement of deployment density, when the maximum distance requirement (L < 12W) of adjacent microfluidic channels is not met, branching is required (that is, the deployment density of this area is high, and the maximum distance requirement of adjacent microfluidic channels is not triggered), the branching angle is less than 60°, the third-level microfluidic channel 203 is used between the branches of the second-level microfluidic channel 202 for branch and flow distribution, and the overall flow channel distribution is also uniform.

[0076] On the basis of the above-mentioned arrangement of the biomimetic microfluidic channel 2 in a central symmetric structure, the angle between the extension direction of the first-level microfluidic channel 201 and the second-level microfluidic channel 202 and the first center line 104 is less than 60°, and the angle between the extension direction of the third-level microfluidic channel 203 and the first center line 104 is less than 90°. In this way, the extension direction of the first-level microfluidic channel 201, the second-level microfluidic channel 202 and the third-level microfluidic channel 203 is as close as possible to the extension direction of the first center line 104, so that the cooling liquid can flow more smoothly in the biomimetic microfluidic channel 2, and the cooling effect is improved. Figure 1 and Figure 7As shown, the bare die 1 also includes a liquid inlet structure 106, which is disposed on one side of the substrate 101 where the biomimetic microchannel 2 is disposed, and the liquid inlet structure 106 forms an inlet channel for introducing coolant into the biomimetic microchannel 2. To cooperate with the biomimetic microchannel 2 located inside the die 1, a liquid inlet structure 106 is added to the die 1. This liquid inlet structure 106 is connected to the substrate 101 and is located on the side of the substrate 101 where the biomimetic microchannel 2 is located, that is, on the side of the substrate 101 opposite to the active device layer 102. When the biomimetic microchannel 2 is etched on the surface of the substrate 101, this liquid inlet structure 106 covers the groove-shaped biomimetic microchannel 2 to form a sealed structure with the biomimetic microchannel 2, ensuring the normal flow of coolant in the biomimetic microchannel 2. In addition, the liquid inlet structure 106 also forms an inlet channel for introducing coolant into the biomimetic microchannel 2, thereby forming a complete flow guiding structure in the die 1 consisting of a coolant inlet channel, a coolant cooling channel (i.e., biomimetic microchannel 2), and a coolant outlet channel 105, so that the die 1 has a self-heating function.

[0077] Specifically, such as Figure 1 As shown, the biomimetic microchannel 2 is formed on the side surface of the substrate 101 facing away from the active device layer 102, and the liquid inlet structure 106 specifically includes: a first liquid inlet layer 1061, which is sealed to the substrate 101 and covers the biomimetic microchannel 2, and has a liquid inlet hole 1062 communicating with the biomimetic microchannel 2; and a second liquid inlet layer 1063, which is sealed to the first liquid inlet layer 1061 and located on the side of the first liquid inlet layer 1061 facing away from the substrate 101, and has a liquid inlet 1064 communicating with the liquid inlet hole 1062. In this structure, the first liquid inlet layer 1061 is plate-shaped and can be a gallium nitride layer or a silicon carbide layer formed by chemical epitaxy. It covers the biomimetic microchannels 2 and is sealed to the substrate 101 (the connection is achieved by forming an integral structure through chemical epitaxy), thus creating a closed channel for the flow of coolant in the biomimetic microchannels 2. Liquid inlet holes 1062 formed on the first liquid inlet layer 1061 are used to guide the low-temperature coolant into the biomimetic microchannels 2. Figure 1 and Figure 8As shown, the liquid inlet hole 1062 can be a strip-shaped hole coinciding with the second center line 103, so that sufficient cooling liquid can enter the biomimetic microfluid channel 2 in the extension direction of the second center line 103, and then flow along the extension direction of the first center line 104 to the outlet channels 105 located on both sides of the second center line 103. The liquid inlet hole 1062 in this structure can improve the flow smoothness and efficiency of the cooling liquid, so that the cooling effect is improved. Alternatively, the liquid inlet hole 1062 can also be arranged in other ways, for example, the liquid inlet hole 1062 is a circular through hole arranged in alignment with the center of the substrate 101, and the cooling liquid enters the biomimetic microfluid channel 2 from the center of the substrate 101 and then diffuses and flows to the periphery in the biomimetic microfluid channel 2. Alternatively, the liquid inlet hole 1062 can be a plurality of circular through holes arranged along the second center line 103. The structure and forming method of the second liquid inlet layer 1063 can be the same as that of the first liquid inlet layer 1061, and the liquid inlet hole 1064 is arranged in communication with the liquid inlet hole 1062, as shown in Figure 1 and Figure 7 As shown, the liquid inlet hole 1064 can be a circular through hole arranged in alignment with the center of the substrate 101. Alternatively, the liquid inlet hole 1064 can be a circular through hole and arranged along the second center line 103. The liquid inlet hole 1062 and the liquid inlet hole 1064 can also be formed on the first liquid inlet layer 1061 and the second liquid inlet layer 1063, respectively, by etching process.

[0078] By arranging such a liquid inlet structure 106, as shown by the arrow in Figure 7 , the low-temperature cooling liquid can flow into the liquid inlet hole 1064 and pass through the second liquid inlet layer 1063 to enter the inside of the die 1. Then, the cooling liquid reaches the liquid inlet hole 1062, flows into the liquid inlet hole 1062 and passes through the first liquid inlet layer 1061 to enter the biomimetic microfluid channel 2, as shown in Figure 8 As shown, the liquid inlet hole 1062 is a strip-shaped hole, and the low-temperature cooling liquid can quickly fill the liquid inlet hole 1062 and quickly enter the biomimetic microfluid channel 2 due to its large cross-sectional size and low flow resistance. According to the flow resistance distribution characteristics formed by the geometric size of the biomimetic microfluid channel 2, the low-temperature cooling liquid can automatically fill the primary microfluid channel 201, the secondary microfluid channel 202 and the tertiary microfluid channel 203. The heat generated by the active device layer 102 during operation is conducted through the substrate 101 to the biomimetic microfluid channel 2 and absorbed by the cooling liquid in the biomimetic microfluid channel 2. The temperature of the cooling liquid rises, and the high-temperature cooling liquid flows out of the biomimetic microfluid channel 2 and enters the outlet channel 105, and then flows out of the die 1 through the outlet channel 105.

[0079] In other alternative embodiments, in addition to the above arrangement, other ways can also be used to arrange the biomimetic microfluid channel 2 inside the die 1, for example Figure 9As shown, multiple layers of biomimetic microchannels 2 are provided in the substrate 101, and the liquid inlet structure 106 is configured as a 3D manifold (not shown in the figure) connecting each layer of biomimetic microchannels 2. In this structure, in order to improve the cooling effect, multiple layers of biomimetic microchannels 2 can be stacked in the substrate 101 (each layer of biomimetic microchannels is the biomimetic microchannel 2 of the above structure), and a 3D manifold is used to replace the first liquid inlet layer 1061 and the second liquid inlet layer 1063 in the above embodiment. The 3D manifold connects all layers of biomimetic microchannels 2 to realize the introduction of coolant into the bare die 1 and the export of coolant from the bare die 1.

[0080] In summary, the chip heat dissipation structure provided in this application has the following advantages:

[0081] 1. Low thermal resistance: The biomimetic microchannel 2, which serves as the cooling end, and the active device layer 102, which serves as the heating end, are separated only by a substrate 101 with a thickness of 100μm to 200μm, resulting in a short distance and low thermal resistance.

[0082] II. Low resistance: The bifurcation section forms a high-radius arc structure with a smooth transition, which reduces corner resistance and achieves energy-saving effect;

[0083] 3. High turbulence: The use of multi-stage microchannels to divide and merge the flow increases the turbulence of the flow field and improves the convective heat transfer efficiency between the coolant and the biomimetic microchannel 2.

[0084] IV. Increased heat dissipation area: The biomimetic structure with a vascular network has a multi-level branch structure and a complex flow channel layout related to power density, which allows it to have a larger heat dissipation area compared to microchannels with conventional geometric shapes under the same space size constraints.

[0085] V. High design freedom: The biomimetic microchannel 2 can be flexibly deployed according to power density, without the limitations of conventional geometry;

[0086] VI. High temperature uniformity: The biomimetic microchannel 2 can accurately allocate cooling resources such as flow rate and pressure drop through a power density-dependent topology method, thereby reducing the temperature difference of the active device layer 102 and improving operational reliability.

[0087] VII. High heat dissipation efficiency:

[0088] like Figure 10 As shown, this application embodiment verifies conventional flat microchannels and biomimetic microchannels 2 with a vascular network structure using a hypothetical non-uniform heat source chip: the maximum allowable junction temperature of the active device layer 102 is 85°C, and the highest power density reaches 100W / cm² under the first operating condition. 2; under the same flow rate (0.2 LPM) and the same inlet temperature (40℃) of the cooling liquid, the maximum temperature of the active device layer 102 cooled by the biomimetic microchannel 2 is 11.4℃ lower than that of the active device layer 102 cooled by the conventional flat microchannel (74.8℃-63.4℃=11.4℃), the overall temperature difference (uniformity) of the active device layer 102 is 14.4℃ lower ((74.8℃-41.7℃)-(63.4℃-44.7℃)=14.4℃), and the flow resistance is 1.8 kPa lower, so it can be proved that the biomimetic microchannel 2 has stronger heat dissipation capacity and uniformity;

[0089] Eight, high limit heat dissipation capacity:

[0090] As shown in Figure 11 , the limit heat dissipation capacity of the biomimetic microchannel 2 in the form of a vascular network provided by the embodiment of the application is mainly used for dissipating heat of a future chip with ultra-high power density. The embodiment of the application verifies the biomimetic microchannel 2 in the form of a vascular network with a hypothetical non-uniform heat source chip. The maximum allowed junction temperature of the active device layer 102 is 85℃, and the maximum power density under the second working condition reaches 400W / cm 2 . The inlet temperature of the cooling liquid is 40℃, and the flow rate is 0.4 LPM. The maximum temperature of the active device layer 102 cooled by the biomimetic microchannel 2 is 84.8℃, which meets the established target requirements. The temperature difference of the active device layer 102 is 27.7℃ (84.8℃-57.1℃=27.7℃), and the total pressure drop of the cooling liquid is 71.1 kPa, which is within a reasonable range.

[0091] In addition, the embodiment of the application also provides a design method of a chip heat dissipation structure, which is suitable for the chip heat dissipation structure described above, as shown in Figure 12 , the method comprises the following steps:

[0092] Obtain the power density of different regions of the active device layer 102, and the power density distribution is as shown in Figure 3 ;

[0093] According to the different power densities, the extension length relationship of the different level microchannels in the corresponding region is obtained. Specifically, in the region where the power density reaches 2 / 3 or more of the maximum power density of the active device layer 102, the extension length of the third-level microchannel 203 is greater than that of the first-level microchannel 201 and the second-level microchannel 202; in the region where the power density reaches 1 / 3 to 2 / 3 of the maximum power density of the active device layer 102, the extension length of the second-level microchannel 202 is greater than that of the first-level microchannel 201 and the third-level microchannel 203; and in the region where the power density is less than 1 / 3 of the maximum power density of the active device layer 102, the extension length of the first-level microchannel 201 is greater than that of the second-level microchannel 202 and the third-level microchannel 203;

[0094] According to the different relationships between the power density and the extension length, the deployment density of the bionic micro-channel 2 in the corresponding area is obtained; specifically, in the area where the power density reaches 2 / 3 or more of the maximum power density of the active device layer 102, the deployment density K1 of the multi-stage micro-channel is 65% < K1 < 75%; in the area where the power density reaches between 1 / 3 and 2 / 3 of the maximum power density of the active device layer 102, the deployment density K2 of the multi-stage micro-channel is 45% < K2 < 65%; in the area where the power density is less than 1 / 3 of the maximum power density of the active device layer 102, the deployment density K3 of the multi-stage micro-channel is 35% < K3 < 45%.

[0095] According to the different relationships between the power density, the extension length, and the deployment density, at least one of the following is obtained: the slot width of each stage of the micro-channel, the curvature radius of the connection part 204 of any two stages of the micro-channel, the spacing between the adjacent two micro-channels connected to the same micro-channel, the spacing between the same stage micro-channels distributed at equal intervals, and the included angle between the extension directions of the different stages of the micro-channels connected to each other.

[0096] In addition, as shown in Figure 13 The chip packaging structure provided by the embodiment of the present application comprises: a substrate 3; a die 1 disposed on the substrate 3 and comprising a base 101 and an active device layer 102, the active device layer 102 being disposed on the surface of the base 101 facing the substrate 3; a heat-conducting packaging shell 4 made of metal and connected with the substrate 3 and covering the die 1; a liquid cooling plate 5 in heat-conducting contact or heat-conducting connection with the heat-conducting packaging shell 4; and a first bionic micro-channel 6 formed in the heat-conducting packaging shell 4 and / or the liquid cooling plate 5 and cooling the active device layer 102 by means of the flow-guiding cooling liquid, and the first bionic micro-channel 6 is in the form of a blood vessel network. That is, the chip packaging structure comprises the above-mentioned bionic micro-channel 2 (i.e. the first bionic micro-channel 6, the bionic micro-channel 2 is named as the first bionic micro-channel 6 in order to be distinguished from the second bionic micro-channel described below), and the first bionic micro-channel 6 is processed on the heat-conducting packaging shell 4 and / or the liquid cooling plate 5, for example by chemical etching or laser engraving, so that the heat dissipation of the die 1 can be more sufficient and efficient through the heat-conducting packaging shell 4 and / or the liquid cooling plate 5, and more heat dissipation scenarios can be applied, which can greatly enhance the heat dissipation effect of the die 1.

[0097] Further, in the chip packaging structure, a second bionic micro-channel can also be arranged on the substrate 101, the second bionic micro-channel cools the active device layer 102 through the flow guide cooling liquid, and the second bionic micro-channel is in the form of a blood vessel network. That is, on the basis of machining the first bionic micro-channel 6 on the heat-conducting packaging shell 4 and / or the liquid cooling plate 5, the bionic micro-channel is also machined in the interior of the die 1, that is, the second bionic micro-channel is arranged in the interior of the die 1 (the structures of the first bionic micro-channel 6 and the second bionic micro-channel 2 are the same as the structure of the bionic micro-channel 2 in the chip heat dissipation structure described above), so that the die 1 can be cooled by the second bionic micro-channel in the interior of the die 1 and the first bionic micro-channel 6 on the heat-conducting packaging shell 4 and / or the liquid cooling plate 5 at the same time, thereby making the cooling effect of the chip packaging structure on the die 1 more remarkable, and being able to meet the heat dissipation requirements of a higher power density chip.

[0098] On the basis of arranging the second bionic micro-channel in the die 1, since the structure of the second bionic micro-channel is the same as the structure of the bionic micro-channel 2 in the chip heat dissipation structure described above, other beneficial effects of the chip packaging structure brought by the second bionic micro-channel can be referred to the description of the chip heat dissipation structure, and will not be described herein.

[0099] The basic principle of the application is described above in combination with specific embodiments, but it should be pointed out that the advantages, advantages, effects and the like mentioned in the application are only examples and cannot be considered as the must-have of each embodiment of the application. In addition, the specific details disclosed above are only for the purpose of example and understanding, and are not limited to the application of the above specific details.

[0100] The block diagrams of the devices, apparatuses, equipment, systems involved in the application are only illustrative examples and are not intended to require or imply that the connection, arrangement and configuration shown in the block diagrams must be adopted. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged and configured in any way. Words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0101] It should also be noted that in the devices, equipment and methods of the application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombination should be considered as equivalent solutions of the application.

[0102] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the application. Thus, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0103] It should be understood that the limiting words "first", "second", "third", "fourth", "fifth" and "sixth" used in the embodiments description of the present application are only used for more clearly explaining the technical solutions, and cannot be used to limit the protection scope of the present application.

[0104] The above description has been presented for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the application to the forms disclosed herein. Although several example aspects and embodiments have been discussed above, those of ordinary skill in the art will appreciate a variety of modifications, alternatives, permutations, additions, and sub-combinations of the described aspects and embodiments.

Claims

1. A chip heat dissipation structure, characterized by comprising: Chip, comprising: a die including a substrate and an active device layer disposed on one side surface of the substrate; a biomimetic microfluidic channel disposed on the substrate and cooling the active device layer by conducting a cooling liquid, and the biomimetic microfluidic channel is in the form of a blood vessel network.

2. The chip heat dissipation structure according to claim 1, wherein The biomimetic microfluidic channel includes multi-stage microfluidic channels with different groove widths, and the distribution of the multi-stage microfluidic channels in different regions of the substrate corresponds to the power density distribution of different regions of the active device layer.

3. The chip heat dissipation structure according to claim 2, wherein, The distribution of the multi-stage microfluidic channels in different regions of the substrate includes different extension lengths of different-stage microfluidic channels and / or different deployment densities of the multi-stage microfluidic channels.

4. The chip heat dissipation structure according to claim 3, wherein The multi-stage microfluidic channels include first-stage, second-stage and third-stage microfluidic channels with groove widths decreasing in turn; The different regions of the active device layer include: a first region with a power density of 2 / 3 or more of the maximum power density of the active device layer; a second region with a power density between 1 / 3 and 2 / 3 of the maximum power density of the active device layer; and a third region with a power density less than 1 / 3 of the maximum power density of the active device layer; In the first region, the extension length of the third-stage microfluidic channel is greater than that of the first-stage and second-stage microfluidic channels; in the second region, the extension length of the second-stage microfluidic channel is greater than that of the first-stage and third-stage microfluidic channels; and in the third region, the extension length of the first-stage microfluidic channel is greater than that of the second-stage and third-stage microfluidic channels.

5. The chip heat dissipation structure according to claim 4, wherein In the first region, the deployment density K1 of the multi-stage microfluidic channels is 65% < K1 < 75%; in the second region, the deployment density K2 of the multi-stage microfluidic channels is 45% < K2 < 65%; and in the third region, the deployment density K3 of the multi-stage microfluidic channels is 35% < K3 < 45%.

6. The chip heat dissipation structure according to claim 4 or 5, wherein The groove width of the third-stage microfluidic channel is greater than 100 μm, the groove width of the second-stage microfluidic channel is 1.6-2 times the groove width of the third-stage microfluidic channel, and the groove width of the first-stage microfluidic channel is 3.2-4 times the groove width of the second-stage microfluidic channel.

7. The chip heat dissipation structure according to claim 6, wherein The groove width of the third-stage microfluidic channel is 125 μm-175 μm, the groove width of the second-stage microfluidic channel is 200 μm-350 μm, and the groove width of the first-stage microfluidic channel is 640 μm-1400 μm.

8. The chip heat dissipation structure according to claim 4 or 5, wherein The thickness of the substrate is 300 μm-500 μm; And in the thickness direction of the substrate, the depth of the first-stage, second-stage and third-stage microfluidic channels is 200 μm-300 μm.

9. The chip heat dissipation structure according to claim 4 or 5, wherein, The connection part of any two-stage microfluidic channels in different-stage microfluidic channels is in the form of a circular arc structure, and the curvature radius of the circular arc structure is 1.5 times or more the groove width of the microfluidic channel with smaller groove width.

10. The chip heat dissipation structure according to claim 4 or 5, wherein In the first-stage, second-stage and third-stage microfluidic channels, the spacing between adjacent other microfluidic channels in the extension direction of any one microfluidic channel is less than 12 times the groove width of the microfluidic channel.

11. The chip heat dissipation structure according to claim 5, wherein, In the first region, the second region and the third region, the microfluid channels of the same level are distributed at equal intervals.

12. The chip heat dissipation structure according to claim 4, wherein, The bionic microfluid channel is symmetrically arranged on the substrate with respect to two mutually perpendicular center lines of the substrate, and an outlet channel for leading out the cooling liquid in the bionic microfluid channel is perpendicular to a first center line of the two mutually perpendicular center lines. And, the angle between the extension direction of the first-level microfluid channel and the second-level microfluid channel and the first center line is less than 60°, and the angle between the extension direction of the third-level microfluid channel and the first center line is less than 90°.

13. The chip heat dissipation structure according to any one of claims 1-5 and 11 and 12, wherein, The surface of the substrate provided with the bionic microfluid channel is provided with an outlet channel for leading out the cooling liquid in the bionic microfluid channel, and the outlet channel is perpendicular to a first center line of two mutually perpendicular center lines of the substrate. And, the die includes a liquid inlet structure, which is arranged on the side of the substrate provided with the bionic microfluid channel, and forms an inlet channel for leading in the cooling liquid to the bionic microfluid channel.

14. The chip heat dissipation structure according to claim 13, wherein, The bionic microfluid channel is formed on the side surface of the substrate away from the active device layer, and the liquid inlet structure includes: a first liquid inlet layer, which is sealingly connected with the substrate and covers the bionic microfluid channel, and is provided with a liquid inlet hole in communication with the bionic microfluid channel; a second liquid inlet layer, which is sealingly connected with the first liquid inlet layer and located on the side of the first liquid inlet layer away from the substrate, and is provided with a liquid inlet port in communication with the liquid inlet hole.

15. The chip heat dissipation structure according to claim 13, wherein, The substrate is provided with multiple layers of the bionic microfluid channel, and the liquid inlet structure is a 3D manifold communicating each layer of the bionic microfluid channel.

16. A design method for a chip heat dissipation structure, characterized in that, The method is suitable for the chip heat dissipation structure of any one of claims 1-15, and the method comprises the following steps: obtaining the power density of different regions of the active device layer; obtaining the extension length relationship of the microfluid channels of different levels in the corresponding region according to the different power densities; obtaining the deployment density of the bionic microfluid channel in the corresponding region according to the different power densities and the different extension length relationships; obtaining at least one of the slot width of each level of microfluid channel, the curvature radius of the connection part of any two levels of microfluid channels, the spacing of the adjacent two microfluid channels connected to the same microfluid channel, the spacing between the microfluid channels of the same level distributed at equal intervals, and the angle between the extension directions of the microfluid channels of different levels connected to each other according to the different power densities, the different extension length relationships and the different deployment densities.

17. A chip package structure, comprising: comprise: a substrate; a die arranged on the substrate and comprising a substrate and an active device layer arranged on the surface of the substrate facing the substrate; a heat-conducting packaging shell connected with the substrate and covering the die; a liquid cooling plate in heat-conducting contact or heat-conducting connection with the heat-conducting packaging shell; a first bionic microfluid channel formed in the heat-conducting packaging shell and / or the liquid cooling plate and cooled by flowing cooling liquid to cool the active device layer, and the first bionic microfluid channel is in the shape of a blood vessel network.

18. The chip package structure of claim 17, wherein, The substrate is provided with a second bionic microfluid channel, the second bionic microfluid channel is cooled by flowing cooling liquid to cool the active device layer, and the second bionic microfluid channel is in the shape of a blood vessel network.

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