Clock oscillation circuit, key detection system and chip
By automatically starting and stopping the clock oscillator when the edge transition of the key status signal is detected, and by combining the counter and control unit to control the working state of the clock oscillator, the high power consumption problem caused by key signal glitches is solved, and a low power key detection system is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- EVEREST SEMICON CO LTD
- Filing Date
- 2025-09-09
- Publication Date
- 2026-06-09
Smart Images
Figure CN121150665B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a clock oscillation circuit, a key detection system, and a chip. Background Technology
[0002] When a button is pressed or released, there may be glitches. A glitch removal circuit is needed to process these glitches into an ideal switching signal. The glitch removal circuit requires a clock signal to operate, but the clock is usually off in the system standby mode. If the clock is always on, it will generate a lot of power consumption.
[0003] Therefore, to address the aforementioned technical problems, it is necessary to provide a clock oscillation circuit, a key detection system, and a chip. Summary of the Invention
[0004] The purpose of this invention is to provide a clock oscillation circuit, a key detection system, and a chip, which can reduce the power consumption of the key status detection circuit.
[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:
[0006] A clock oscillation circuit, the clock oscillation circuit comprising:
[0007] The trigger unit is used to generate an enable signal based on the button state signal;
[0008] A clock oscillator, connected to the trigger unit, is used to generate a clock signal based on the enable signal;
[0009] A counter, connected to the clock signal generation unit, is used to receive the clock signal and generate a count value based on the clock signal;
[0010] A control unit is connected between the trigger unit and the counter. The control unit is used to adjust the level of the enable signal based on the count value, and to control the clock oscillator to work continuously or be turned off.
[0011] In one or more embodiments of the present invention, in a first state, the control unit generates a clock hold signal to maintain the enable signal at a first level, and the clock oscillator continues to operate;
[0012] In the second state, the control unit simultaneously generates a reset signal and a clock hold signal, and the clock oscillator continues to operate;
[0013] In the third state, when the count value reaches the set value, the control unit stops generating the clock hold signal so that the enable signal switches to the second level, and the clock oscillator is turned off.
[0014] In one or more embodiments of the present invention, the triggering unit includes a logic unit, a first flip-flop, and a second flip-flop;
[0015] The first and second triggers are used to trigger based on any edge transition of the key state signal and output a trigger signal of the first level.
[0016] The input terminal of the logic unit is connected to the output terminal of the first flip-flop, the output terminal of the second flip-flop, and the control unit, and the output terminal is connected to the clock oscillator.
[0017] In one or more embodiments of the present invention, the logic unit includes an OR gate, the first flip-flop is used to trigger on the rising edge of the key state signal, the second flip-flop is used to trigger on the falling edge of the key state signal, the input of the OR gate is connected to the output of the first flip-flop, the output of the second flip-flop and the control unit, and the output is used to generate an enable signal.
[0018] In one or more embodiments of the present invention, the control unit is connected to the reset pin of the first flip-flop and the reset pin of the second flip-flop;
[0019] In the second state, when the counter starts counting but has not counted to the set value, the control unit generates a reset signal to reset the first and second flip-flops, and the triggering unit generates a first-level enable signal based on the clock hold signal.
[0020] Another specific embodiment of the present invention provides a key detection system, the key detection system including a deburring circuit and the clock oscillation circuit;
[0021] The clock oscillation circuit is used to automatically generate or turn off the clock signal based on the button status signal;
[0022] The de-glitching circuit is connected to the clock oscillation circuit and is used to perform de-glitching processing on the key status signal based on the clock signal to obtain the corresponding switch signal.
[0023] In one or more embodiments of the present invention, the counting range of the counter is greater than or equal to the period during which the de-ghosting circuit processes a key status signal.
[0024] In one or more embodiments of the present invention, the key detection system further includes a counting control circuit connected to the counter. The counting control circuit is used to generate a first control signal based on an interrupt wait signal. The first control signal is used to control the counter to pause counting or cancel pausing counting within a certain counting interval. The clock oscillator continuously generates a clock signal when the counter pauses counting.
[0025] In one or more embodiments of the present invention, the key detection system further includes an interrupt transmitter connected to the deburring circuit, which is used to generate an interrupt signal and an interrupt wait signal based on the switch signal.
[0026] A specific embodiment of the present invention provides a chip, the chip including the aforementioned key detection system.
[0027] Compared with the prior art, the clock oscillation circuit, key detection system and chip of the present invention start the clock oscillator by detecting the edge transition of the key status signal and realize the automatic shutdown of the clock oscillator. When there is no key status signal transition, it maintains a standby mode to reduce system power consumption. At the moment of the edge transition of the key status signal, the corresponding flip-flop is triggered to start the clock oscillation circuit and generate a clock signal. The circuit structure of the present invention is simple and the power consumption is very low, making it suitable for key status detection. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a circuit schematic diagram of a clock oscillation circuit in one embodiment of the present invention;
[0030] Figure 2 This is a schematic diagram of a key detection system according to an embodiment of the present invention. Detailed Implementation
[0031] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.
[0032] As described in the background section, ideally, the voltage level change of a mechanical button should be as follows: when pressed, the voltage level should instantly jump from high to low or from low to high; when released, the voltage level should instantly jump from low to high or from high to low. However, due to the physical structure of mechanical buttons, the internal metal contacts may bounce upon contact or separation, or the button contacts may oxidize. Poor conductivity during contact or bouncing can cause the voltage level to oscillate rapidly and irregularly between high and low multiple times within a short period (usually a few milliseconds to tens of milliseconds) before stabilizing to a final state. This unstable oscillating signal appears as if it has "gaps" on the waveform.
[0033] If a signal with glitches is directly input to a microcontroller unit (controller) or other digital circuit, the controller, which operates at extremely high speeds (capable of executing millions of instructions per second), will mistake this brief bouncing signal for multiple rapid key presses, leading to abnormal and unpredictable system behavior.
[0034] Therefore, we must use a glitching circuit to process the unstable signal into an ideal square wave signal, ensuring that each physical key press corresponds to only one valid logic level change. In digital integrated circuit design, the glitching circuit requires a constantly active clock, using a clock signal much faster than the jitter frequency to sample the key signal for glitching processing.
[0035] To address the aforementioned problems, this invention provides a clock oscillation circuit that automatically activates a clock oscillator by detecting changes in the state of a key, specifically comprising:
[0036] The trigger unit is used to generate an enable signal based on the button state signal;
[0037] A clock oscillator, connected to a trigger unit, is used to generate a clock signal based on an enable signal;
[0038] The counter, connected to the clock signal generation unit, is used to receive the clock signal and generate a count value based on the clock signal;
[0039] The control unit, connected between the trigger unit and the counter, is used to adjust the level of the enable signal based on the count value, and to control the clock oscillator to continue working or turn off.
[0040] In one embodiment, in the first state, the control unit generates a clock hold signal to maintain the enable signal at a first level, and the clock oscillator continues to operate;
[0041] In the second state, the control unit simultaneously generates a reset signal and a clock hold signal, and the clock oscillator continues to operate;
[0042] In the third state, when the count value reaches the set value, the control unit stops generating the clock hold signal so that the enable signal switches to the second level and the clock oscillator is turned off.
[0043] In one embodiment, the triggering unit includes a logic unit, a first flip-flop, and a second flip-flop. The first and second flip-flops are used to trigger based on arbitrary edge transitions of the key state signal and output a trigger signal of a first level. The input terminal of the logic unit is connected to the output terminal of the first flip-flop, the output terminal of the second flip-flop, and the control unit, and the output terminal is connected to a clock oscillator.
[0044] In one embodiment, the control unit is connected to the reset pin of the first flip-flop and the reset pin of the second flip-flop. In the second state, when the counter starts counting but has not counted to the set value, the control unit generates a reset signal to reset the first flip-flop and the second flip-flop. The triggering unit generates a first-level enable signal based on the clock hold signal.
[0045] Furthermore, the present invention also provides a key detection system, including a de-glitch circuit and a clock oscillation circuit, wherein the clock oscillation circuit is used to automatically generate or turn off a clock signal based on the key status signal, and the de-glitch circuit is connected to the clock oscillation circuit and is used to perform de-glitch processing on the key status signal based on the clock signal to obtain the corresponding switch signal.
[0046] In one embodiment, the key detection system further includes a counting control circuit connected to a counter. The counting control circuit generates a first control signal based on an interrupt wait signal. The first control signal is used to control the counter to pause or cancel counting within a certain counting interval. The clock oscillator continuously generates a clock signal when the counter pauses counting.
[0047] The present invention will be further described below with reference to specific embodiments.
[0048] Example 1:
[0049] like Figure 1 As shown, the clock oscillation circuit in this embodiment includes a trigger unit 10, a clock oscillator 20, a counter 30, and a control unit 40.
[0050] Specifically, the trigger unit 10 is used to generate an enable signal S2 based on the key state signal S1. In this embodiment, the trigger unit 10 includes a logic unit, a first flip-flop 11, and a second flip-flop 12. The first flip-flop 11 and the second flip-flop 12 are used to trigger based on any edge transition of the key state signal S1 and output a trigger signal of a first level. The input terminal of the logic unit is connected to the output terminals of the first flip-flop 11 and the second flip-flop 12, and to the control unit 40. The output terminal is connected to the clock oscillator 20.
[0051] Taking the first level as high level (1) and the second level as low level (0), the logic unit includes an OR gate for example. The first flip-flop 11 is used to trigger on the rising edge of the key state signal S1. After the first flip-flop 11 is triggered, the trigger signal output is high level. The second flip-flop 12 is used to trigger on the falling edge of the key state signal S1. After the second flip-flop 12 is triggered, the trigger signal output is low level.
[0052] When the button status signal S1 changes in any way (whether it is a rising edge or a falling edge), the trigger unit 10 will generate a high-level enable signal S2.
[0053] Clock oscillator 20 is connected to trigger unit 10 and is used to generate clock signal S3 based on enable signal S2. It is understood that clock oscillator 20 is well known in the prior art and therefore will not be described in detail here; any known or unknown clock oscillator 20 may be used without restriction. When enable signal S2 is high, clock oscillator 20 operates and generates clock signal S3; conversely, when enable signal S2 is low, clock oscillator 20 is turned off and no longer generates clock signal S3.
[0054] The counter 30 is connected to the clock signal S3 generation unit to receive the clock signal S3 and generate a count value based on the clock signal S3. Furthermore, in this embodiment, the counter 30 is configured with a preset counting interval, meaning that the counter 30 starts counting from 0 and stops counting when it reaches the set value.
[0055] The control unit 40 is connected between the trigger unit 10 and the counter 30, and the control unit 40 is connected to the reset pin of the first trigger 11 and the reset pin of the second trigger 12. The control unit 40 is used to adjust the level of the enable signal S2 based on the count value, and to control the clock oscillator 20 to work continuously or be turned off.
[0056] Specifically, in the first state, the counter 30 starts counting, and the control unit 40 generates a clock hold signal S4 based on the count value of the counter 30 (i.e., the count value changes from 0). The clock hold signal S4 is high. Based on the OR gate judgment logic, it can be known that the enable signal S2 is still maintained at a high level at this time, and the clock oscillator 20 continues to work.
[0057] In the second state, when counter 30 starts counting but has not reached the set value, control unit 40 simultaneously generates a reset signal S5 and a clock hold signal S4. Control unit 40 generates reset signal S5 to reset either the first trigger 11 or the second trigger 12. It is understood that if the trigger is not reset (restoring the trigger to its initial state) and the reset is not released in time (allowing the trigger to re-detect the next key press) before the clock oscillator is turned off after the trigger is activated, it will affect the trigger's next activation. Clock hold signal S4 ensures that the clock oscillator 20 remains operational during trigger reset and after reset release, allowing the counter to continue counting to the set value.
[0058] In the third state, when the count value reaches the set value (i.e., the set counting interval is reached), the control unit 40 stops generating the clock hold signal S4 based on the count value so that the enable signal S2 switches to a low level, the clock oscillator 20 is turned off, and the counter 30 stops counting.
[0059] In this embodiment, the clock oscillation circuit achieves automatic start and stop through a simple circuit structure. The clock oscillation circuit can be started based on any transition edge of the button status signal S1, and it can be turned off without any additional signal, thus reducing power consumption.
[0060] Example 2:
[0061] like Figure 2 As shown, this embodiment provides a key detection system, which includes a deburring circuit 200, a counting control circuit 400, an interrupt transmitter 300, and a clock oscillation circuit 100 as in Embodiment 1.
[0062] Referring to Embodiment 1, the clock oscillation circuit 100 is used to automatically generate or turn off the clock signal S3 based on the key status signal S1. The de-glitch circuit 200 is connected to the clock oscillation circuit 100 and is used to perform de-glitch processing on the key status signal S1 based on the clock signal S3 to obtain the corresponding switch signal. It is understood that the de-glitch circuit 200 is well known in the prior art, and therefore will not be described in detail here. Any known or unknown de-glitch circuit 200 can be used without restriction.
[0063] It is understood that in this embodiment, the counting range of the counter 30 is greater than or equal to the period during which the de-glitch circuit 200 processes one key status signal S1. That is, after the de-glitch circuit 200 finishes processing one key status signal S1, the clock oscillation circuit 100 can be automatically turned off without the need for additional control signals to control the clock oscillation circuit 100.
[0064] Interrupt transmitter 300 is connected to de-glitch circuit 200 and is used to generate interrupt signal and interrupt wait signal based on switch signal.
[0065] The counting control circuit 400 is connected to the counter 30 and is used to generate a first control signal based on an interrupt wait signal. The first control signal is used to control the counter 30 to pause or cancel counting within a certain counting interval. The clock oscillator 20 continuously generates a clock signal S3 when the counter 30 pauses counting. It can be understood that when the interrupt transmitter confirms that a key press has been detected and an interrupt needs to be sent, it first generates an interrupt wait signal to instruct the counting control circuit 400 to control the counter 30 to pause counting, preventing the clock oscillator from stopping due to an excessively long interrupt transmission time. After the interrupt transmission is completed, the interrupt wait signal is released, and the counter resumes counting until it reaches the set value, at which point the clock oscillator automatically shuts down.
[0066] Understandably, after the de-glitch circuit 200 processes the key state signal S1 and generates a corresponding switch signal, confirming a key state change (e.g., pressed or released), the event corresponding to this switch signal requires processing by the upper-level controller 500 (e.g., MCU). At this time, the interrupt transmitter 300 parses the switch signal and generates an interrupt signal. After the interrupt signal is issued, the interrupt transmitter 300 generates an interrupt wait signal. The controller 500 starts processing the corresponding event based on the interrupt signal. The counting control circuit 400 generates a first control signal based on the interrupt wait signal, thereby controlling the counter 30 to pause counting. This is to ensure that during event processing, the clock oscillator 20 does not stop working because the counter 30 has counted to the set value. The key detection system remains in its current state during event processing until the interrupt event is processed. Then, the counting control circuit 400 controls the counter 30 to continue counting from the count value before the pause until the set value is reached.
[0067] If the de-glitch circuit 200 does not generate a corresponding switch signal after processing the button status signal S1, that is, the button status signal S1 is an abnormal glitch, then the counter 30 continues to count normally.
[0068] This invention also provides a chip, including the above-described button detection system.
[0069] This invention provides a clock oscillation circuit that can be automatically started and stopped. When there is no transition of the key status signal S1, it maintains a standby mode to reduce system power consumption. The transition of the edge of the key status signal S1 triggers the corresponding flip-flop to start the clock oscillation circuit and generate a clock signal S3. The de-glitch circuit processes the key status signal S1 based on the clock signal S3 to obtain the corresponding switch signal, and automatically shuts down the clock oscillation circuit after the processing is completed.
[0070] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0071] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A clock oscillation circuit, characterized in that, The clock oscillation circuit includes: The trigger unit is used to generate an enable signal based on the button state signal; A clock oscillator, connected to the trigger unit, is used to generate a clock signal based on the enable signal; A counter, connected to the clock signal generation unit, is used to receive the clock signal and generate a count value based on the clock signal; A control unit is connected between the trigger unit and the counter. The control unit is used to adjust the level of the enable signal based on the count value, and to control the clock oscillator to work continuously or be turned off. In the first state, the control unit generates a clock hold signal, the trigger unit maintains the enable signal at a first level based on the clock hold signal, and the clock oscillator continues to operate; In the second state, the control unit simultaneously generates a reset signal and a clock hold signal. The trigger unit performs a reset based on the reset signal and maintains the enable signal at a first level based on the clock hold signal. The clock oscillator continues to operate. In the third state, when the count value reaches the set value, the control unit stops generating the clock hold signal so that the enable signal switches to the second level, and the clock oscillator is turned off.
2. The clock oscillation circuit according to claim 1, characterized in that, The triggering unit includes a logic unit, a first trigger, and a second trigger; The first and second triggers are used to trigger based on any edge transition of the key state signal and output a trigger signal of the first level. The input terminal of the logic unit is connected to the output terminal of the first flip-flop, the output terminal of the second flip-flop, and the control unit, and the output terminal is connected to the clock oscillator.
3. The clock oscillation circuit according to claim 2, characterized in that, The logic unit includes an OR gate, the first flip-flop is triggered on the rising edge of the key status signal, the second flip-flop is triggered on the falling edge of the key status signal, the input of the OR gate is connected to the output of the first flip-flop, the output of the second flip-flop and the control unit, and the output is used to generate an enable signal.
4. The clock oscillation circuit according to claim 2, characterized in that, The control unit is connected to the reset pin of the first flip-flop and the reset pin of the second flip-flop; In the second state, when the counter starts counting but has not counted to the set value, the control unit generates a reset signal to reset the first and second flip-flops, and the triggering unit generates a first-level enable signal based on the clock hold signal.
5. A key detection system, characterized in that, The key detection system includes a deburring circuit and a clock oscillation circuit as described in any one of claims 1 to 4; The clock oscillation circuit is used to automatically generate or turn off the clock signal based on the button status signal; The de-glitching circuit is connected to the clock oscillation circuit and is used to perform de-glitching processing on the key status signal based on the clock signal to obtain the corresponding switch signal.
6. The key detection system according to claim 5, characterized in that, The counting range of the counter is greater than or equal to the period during which the de-ghosting circuit processes a key status signal.
7. The key detection system according to claim 5, characterized in that, The key detection system also includes an interrupt transmitter, which is connected to the deburring circuit and is used to generate an interrupt signal and an interrupt wait signal based on the switch signal.
8. The key detection system according to claim 7, characterized in that, The key detection system further includes a counting control circuit connected to the counter. The counting control circuit generates a first control signal based on the interrupt wait signal. The first control signal controls the counter to pause or cancel counting within a certain counting interval. The clock oscillator continuously generates a clock signal when the counter pauses counting.
9. A chip, characterized in that, The chip includes a key detection system as described in any one of claims 5 to 8.