Electronic device

Abstract

The invention provides an electronic device. The electronic device includes a sensing pixel. The sensing pixel comprises a photosensitive element, a first transistor, a second transistor and a third transistor. A control terminal of the first transistor is electrically connected to a read signal line. The control end of the second transistor is electrically connected to the photosensitive element. A first terminal of the second transistor is electrically connected to a first voltage. The second end of the second transistor is electrically connected to the first end of the first transistor. A third terminal of the second transistor is electrically connected to a second voltage. The first end of the third transistor is electrically connected to a reset voltage. The second end of the third transistor is electrically connected to the photosensitive element. The control end of the third transistor is electrically connected to a reset signal line. The electronic device can provide stable circuit operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an apparatus, and more particularly to an electronic apparatus. BACKGROUND

[0002] For a conventional active pixel sensor, during a read period, a kink effect can occur in a transistor of a source follower or a current source, and thus an unexpected voltage change can occur in a data signal of a sensing result, so as to cause a distortion of the sensing result read by a back-end circuit. SUMMARY

[0003] An electronic apparatus of the present disclosure includes a sensing pixel. The sensing pixel includes a photosensitive element, a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor is electrically connected to a read signal line. The second terminal of the first transistor is electrically connected to a data line. The second transistor includes a first terminal, a second terminal, a third terminal, and a control terminal. The control terminal of the second transistor is electrically connected to the photosensitive element. The first terminal of the second transistor is electrically connected to a first voltage. The second terminal of the second transistor is electrically connected to the first terminal of the first transistor. The third terminal of the second transistor is electrically connected to a second voltage. The third transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is electrically connected to a reset voltage. The second terminal of the third transistor is electrically connected to the photosensitive element. The control terminal of the third transistor is electrically connected to a reset signal line.

[0004] An electronic apparatus of the present disclosure includes a current source circuit. The current source circuit includes an active load transistor. The active load transistor includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the active load transistor is electrically connected to a sensing pixel through a data line. The second terminal of the active load transistor is electrically connected to a third voltage. The third terminal of the active load transistor is electrically connected to a fourth voltage.

[0005] Based on the above, according to the electronic apparatus of the present disclosure, the electronic apparatus can provide stable circuit operation.

[0006] In order to make the above content more clear and easy to understand, the following will be combined with the drawings to explain several embodiments in detail. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A schematic diagram of an electronic apparatus of an embodiment of the present disclosure;

[0008] Figure 2A A schematic diagram of a sensing pixel of an embodiment of the present disclosure;

[0009] Figure 2B A timing diagram of a sensing pixel of an embodiment of the present disclosure;

[0010] Figure 3 A cross-sectional view of a transistor structure according to an embodiment of the present disclosure;

[0011] Figure 4 A current-voltage (IV) characteristic of a transistor according to an embodiment of the present disclosure;

[0012] Figure 5 A schematic view of a sensing pixel according to another embodiment of the present disclosure;

[0013] Figure 6 A cross-sectional view of a transistor structure according to another embodiment of the present disclosure;

[0014] Figure 7 A schematic view of a current source circuit according to an embodiment of the present disclosure;

[0015] Figure 8 A schematic view of a current source circuit according to an embodiment of the present disclosure.

[0016] BRIEF DESCRIPTION OF DRAWINGS

[0017] 100: electronic device

[0018] 101: active region

[0019] 102: peripheral region

[0020] 110: pixel array

[0021] 120: peripheral circuit

[0022] 200, 500, PC(1,1) - PC(m,n): sensing pixel

[0023] 300, 600: transistor structure

[0024] 301, 302, 303, 304, 601, 602, 603, 604: via

[0025] 310, 610: buffer layer

[0026] 320, 620: first insulating layer

[0027] 330, 630: semiconductor layer

[0028] 331, 631: current channel

[0029] 340, 640: second insulating layer

[0030] 350, 650: third insulating layer

[0031] 351, 651: connection electrode

[0032] 361, 661: second gate electrode

[0033] 362, 363, 662, 663, 665: electrode

[0034] 364, 664: first gate electrode

[0035] 370, 670: substrate

[0036] 400: dotted line

[0037] 401-403: current-voltage (IV) characteristic curve

[0038] 700, 800, CS, CS_1, CS_n: current source circuit

[0039] Amp_1-Amp_n: amplifier circuit

[0040] BE: node

[0041] C: capacitor

[0042] D1, D2: direction

[0043] DAL, DAL_1-DAL_n: data line

[0044] DAS, DAS_1-DAS_n: data signal

[0045] PD: light sensing element

[0046] RDL, RDL_1-RDL_m: read signal line

[0047] RDS, RDS_1-RDS_m: read control signal

[0048] RL, RL_1-RL_m: reset signal line

[0049] RS, RS_1-RS_m: reset signal

[0050] Sal_1, Sal_2: active load control signal

[0051] T1: first transistor

[0052] T2: second transistor

[0053] T3: third transistor

[0054] Tal_1, Tal_2: active load transistor

[0055] VDD: first voltage

[0056] Vs: second voltage

[0057] VSS: third voltage

[0058] Vsal: fourth voltage

[0059] Va1, Va2: fixed voltage

[0060] Vbias: bias voltage

[0061] Ics: constant current

[0062] t0, t1, t2, t3: time

[0063] Pr: reset period

[0064] Pe: exposure period

[0065] Ps: scanning period DETAILED DESCRIPTION

[0066] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0067] Throughout this specification and the claims that follow, certain terms can be used for ease of reference which have meanings commonly understood by those of ordinary skill in the art. However, unless specifically defined herein, no term is intended to be limited to a specific property or characteristic. In addition, it is to be noted that the use of particular terms to describe certain embodiments should not be considered limiting and other terms can be substituted therefor.

[0068] In some embodiments of the present disclosure, the terms such as "coupled", "connected", etc. with respect to the connection or junction can refer to two structures being in direct contact, or can also refer to two structures not being in direct contact, with other structures being disposed between the two structures. In addition, the term "coupled" can include any direct and indirect electrical connection means. The ordinal numbers such as "first", "second", etc. used in the specification and claims are used to modify the components, and do not inherently mean and represent any previous ordinal number of the components, nor represent the order or sequence of the components in the manufacturing method. The use of the ordinal numbers is only used to make the components with a certain name distinguishable from another component with the same name. The same words can not be used in the claims and the specification, and thus the first member in the specification can be the second member in the claims. It should be understood that the following embodiments can be replaced, reorganized, and mixed with the technical features in different embodiments without departing from the spirit of the present disclosure.

[0069] Figure 1 FIG. 1 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. Referring to FIG. 1, an electronic device 100 includes a pixel array 110 and a peripheral circuit 120. Figure 1 In an embodiment of the present disclosure, the pixel array 110 includes a plurality of sensing pixels PC(1,1)~PC(m,n) arranged in an array, where m and n are positive integers. Each row of the sensing pixels PC(1,1)~PC(m,n) is electrically connected to a corresponding one of a plurality of read signal lines RDL_1~RDL_m to receive a corresponding one of a plurality of read control signals RDS_1~RDS_m. Each row of the sensing pixels PC(1,1)~PC(m,n) is also electrically connected to a corresponding one of a plurality of reset signal lines RL_1~RL_m to receive a corresponding one of a plurality of reset signals RS_1~RS_m. Each column of the sensing pixels PC(1,1)~PC(m,n) is electrically connected to a corresponding one of a plurality of data lines DAL_1~DAL_n to output a corresponding one of a plurality of data signals DAS_1~DAS_n.

[0070] In an embodiment of the present disclosure, the peripheral circuit 120 includes a plurality of amplifier circuits Amp_1~Amp_n and a plurality of current source circuits CS_1~CS_n. Each of the amplifier circuits Amp_1~Amp_n is electrically connected to a corresponding one of the data lines DAL_1~DAL_n to read out a corresponding one of the data signals DAS_1~DAS_n. Each of the current source circuits CS_1~CS_n is electrically connected to a corresponding one of the data lines DAL_1~DAL_n to provide a constant current.

[0071] In an embodiment of the present disclosure, the electronic device 100 can be an image sensing device, such as a voltage-programmed active pixel sensor (APS). In an embodiment of the present disclosure, the image sensing device can be, for example, an X-ray image sensor, an invisible light image sensor, a fingerprint sensor, or a photo sensor. In some embodiments, the sensing pixels PC(1,1)~PC(m,n) can be used to sense X-rays, invisible light, or visible light. In an embodiment of the present disclosure, the pixel array 110 and the peripheral circuit 120 can be disposed on the same substrate (e.g., a glass substrate, such as the substrate 370 shown in FIG. 3, or a silicon substrate, such as the substrate 470 shown in FIG. 4). Figure 3 Figure 6 ​The substrate 670) is shown, but the disclosure is not limited thereto. In an embodiment of the disclosure, the pixel array 110 can be disposed in the active region 101 of the substrate, and the peripheral circuit 120 can be disposed in the peripheral region 102 of the substrate. In some embodiments, the sensing pixels and the current source circuit can be disposed on the same substrate. The substrate 370 can include the active region 101 and the peripheral region 102 adjacent to the active region 101. The sensing pixels can be disposed on the substrate of the active region 101, and the current source circuit can be disposed on the substrate of the peripheral region 102.

[0072] Figure 2A A schematic diagram of a sensing pixel of an embodiment of the disclosure. Referring to FIG. 4, a sensing pixel PC(1,1) of the pixel array 110 is shown. The sensing pixel PC(1,1) includes a photosensitive element PD, a capacitor C, a first transistor T1, a second transistor T2, and a third transistor T3. The photosensitive element PD includes a cathode terminal and an anode terminal. The cathode terminal of the photosensitive element PD is electrically connected to the second terminal of the second transistor T2 and the second terminal of the third transistor T3. The anode terminal of the photosensitive element PD is electrically connected to a bias voltage Vbias. The photosensitive element PD can be a photodiode. The capacitor C includes a first terminal and a second terminal. The first terminal of the capacitor C is electrically connected to the second terminal of the second transistor T2 and the second terminal of the third transistor T3. The second terminal of the capacitor C is electrically connected to the bias voltage Vbias. The capacitor C can include a photodiode capacitor. The first transistor T1 includes a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor T1 is electrically connected to a read signal line RDL to receive a read control signal RDS. The first terminal of the first transistor T1 is electrically connected to the second transistor T2. The second terminal of the first transistor T1 is electrically connected to a data line DAL to output a data signal DAS. The second transistor T2 includes a first terminal, a second terminal, a third terminal, and a control terminal. The control terminal of the second transistor T2 is electrically connected to the photosensitive element PD via a node BE. The first terminal of the second transistor T2 is electrically connected to a first voltage VDD (i.e., an operating voltage or an operation voltage). The second terminal of the second transistor T2 is electrically connected to the first terminal of the first transistor T1. The second terminal of the second transistor T2 has a second voltage Vs. The third terminal of the second transistor T2 is electrically connected to the second terminal of the second transistor T2 to receive the second voltage Vs. The third transistor T3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor T3 is electrically connected to a reset voltage Vrst. The second terminal of the third transistor T3 is electrically connected to the photosensitive element PD via the node BE. The control terminal of the third transistor T3 is electrically connected to a reset signal line RL to receive a reset signal RS. Figure 2A , Figure 1 The circuit architecture of each of the sensing pixels PC(1,1)~PC(m,n) can be implemented as Figure 2A The circuit architecture of the sensing pixel 200. In an embodiment of the disclosure, the sensing pixel 200 includes a photosensitive element PD, a capacitor C, a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 includes a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor T1 is electrically connected to a read signal line RDL to receive a read control signal RDS. The first terminal of the first transistor T1 is electrically connected to the second transistor T2. The second terminal of the first transistor T1 is electrically connected to a data line DAL to output a data signal DAS. The second transistor T2 includes a first terminal, a second terminal, a third terminal, and a control terminal. The control terminal of the second transistor T2 is electrically connected to the photosensitive element PD via a node BE. The first terminal of the second transistor T2 is electrically connected to a first voltage VDD (i.e., an operating voltage or an operation voltage). The second terminal of the second transistor T2 is electrically connected to the first terminal of the first transistor T1. The second terminal of the second transistor T2 has a second voltage Vs. The third terminal of the second transistor T2 is electrically connected to the second terminal of the second transistor T2 to receive the second voltage Vs. The third transistor T3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor T3 is electrically connected to a reset voltage Vrst. The second terminal of the third transistor T3 is electrically connected to the photosensitive element PD via the node BE. The control terminal of the third transistor T3 is electrically connected to a reset signal line RL to receive a reset signal RS. The cathode terminal of the photosensitive element PD is electrically connected to the control terminal of the second transistor T2 and the second terminal of the third transistor T3. The anode terminal of the photosensitive element PD is electrically connected to a bias voltage Vbias. The photosensitive element PD can be a photodiode. The first terminal of the capacitor C is electrically connected to the control terminal of the second transistor T2 and the second terminal of the third transistor T3. The second terminal of the capacitor C is electrically connected to the bias voltage Vbias. The capacitor C can include a photodiode capacitor.

[0073] In an embodiment of the present disclosure, the first transistor T1, the second transistor T2 and the third transistor T3 can be N-type transistors. The first terminal of the transistor can be a drain terminal. The second terminal of the transistor can be a source terminal. The control terminal of the transistor can be a gate terminal. The third terminal of the transistor can be another gate terminal. In an embodiment of the present disclosure, when the second transistor T2 operates in the saturation mode (saturation region), there is a voltage difference between the first terminal (i.e., the drain terminal) of the second transistor T2 and the second terminal (i.e., the source terminal) of the second transistor T2, so that the first voltage VDD is different from the second voltage Vs, and the first voltage VDD is higher than the second voltage Vs (i.e., VDD > Vs).

[0074] And, please refer to Figure 2A Since the second transistor T2 operates in the saturation mode and the second transistor T2 is an N-type transistor, the threshold voltage of the second transistor T2 is positive, the second voltage Vs of the second terminal of the second transistor T2 and the voltage of the third terminal of the second transistor T2 are lower than the voltage of the control terminal (i.e., the gate terminal) of the second transistor T2, and the first voltage VDD of the first terminal of the second transistor T2 is higher than the voltage of the control terminal of the second transistor T2, and the first voltage VDD of the first terminal of the second transistor T2 is higher than the voltage of the control terminal of the second transistor T2 (i.e., the voltage of node BE) minus the threshold voltage of the second transistor T2. That is, when the second transistor T2 operates in the saturation mode, since the voltage of the control terminal (i.e., the gate terminal) of the second transistor T2 is higher than the third terminal (i.e., the other gate terminal) of the second transistor T2, an electric field is generated between the control terminal (i.e., the gate terminal) and the third terminal (i.e., the other gate terminal) of the second transistor T2. Therefore, since the direction of the electric field between the control terminal (i.e., the gate terminal) of the second transistor T2 and the third terminal (i.e., the gate terminal) of the second transistor T2 is perpendicular to the direction of the current from the first terminal of the second transistor T2 to the second terminal of the second transistor T2, the warpage effect of the second transistor T2 can be effectively improved.

[0075] Figure 2B Timing diagram of the sensing pixel of an embodiment of the present disclosure. Please refer to Figure 2A and Figure 2BIn an embodiment of the present disclosure, during a reset period Pr from time t0 to time t1, the first transistor T1 can be turned off by the read control signal RDS having a low level, and the third transistor T3 can be turned on by the reset signal RS having a high level. Thus, the voltage of the cathode terminal of the photosensitive element PD (i.e., the voltage of the node BE) is reset to the reset voltage Vrst. Then, during an exposure period Pe from time t1 to time t2, the first transistor T1 can be turned off by the read control signal RDS having a low level, and the third transistor T3 can be turned off by the reset signal RS having a low level. The photosensitive element PD can be operated to perform an exposure operation, and the photosensitive element PD can provide a photo current according to a sensing result of the photosensitive element PD to the node BE to generate a voltage drop AVBE at the node BE. Thus, the voltage of the node BE can be reduced from the reset voltage Vrst to a voltage of the reset voltage Vrst minus the voltage drop AVBE (i.e., = Vrst - AVBE).

[0076] Then, during a scan period Ps (or a data readout period) from time t2 to time t3, the first transistor T1 can be turned on by the read control signal RDS having a high level, and the third transistor T3 can be turned off (i.e., turned off) by the reset signal RS having a low level. The constant current Ics flows from the current source circuit CS via the data line DAL, the second transistor T2, and the first transistor T1. Thus, since the voltage between the drain terminal and the source terminal of the second transistor T2 (i.e., a voltage equal to the first voltage VDD minus the second voltage Vs) is higher than the voltage between the gate terminal of the second transistor T2 and the source terminal of the second transistor T2 minus the threshold voltage of the second transistor T2 (i.e., a voltage equal to the voltage of the node BE minus the second voltage Vs minus the threshold voltage (Vth)), the transistor T2 operates in a saturation mode. According to the saturation mode transistor formula, the voltage of the second terminal of the second transistor T2 is the voltage of the control terminal of the second transistor T2 (i.e., the voltage of the node BE) minus the threshold voltage (Vth) of the second transistor T2, and minus the voltage drop AVBE (i.e., = VBE - Vth - AVBE). (ie ), where Ics is a constant current value, L is the length of the second transistor T2, W is the width of the second transistor T2, μ is the mobility parameter of the second transistor T2, and Cox is the insulator capacitance per unit area of the gate of the second transistor T2. In this regard, the voltage at the first end of the second transistor T2 is higher than the voltage at the control end of the second transistor T2 minus the threshold voltage of the second transistor T2, and the voltage at the control end of the second transistor T2 is higher than the voltage at the second end of the second transistor T2. In other words, the second voltage Vs at the second end of the second transistor T2 is lower than the voltage at the control end of the second transistor T2 (i.e. the voltage at node BE) minus the threshold voltage (Vth) of the second transistor. ΔVBE-Vth), and thus the second voltage Vs is lower than the voltage at the control end of the second transistor T2. Therefore, the second transistor T2 can read the sensing result of the photosensitive element PD as a source follower amplifier, and output the second voltage Vs at the second end of the second transistor T2 (i.e. the voltage at node BE) to the third transistor T3. The parameters in the equation are the same as or similar to the definitions described above.

[0077] However, in one embodiment of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 can be P-type transistors. When the second transistor T2 is a P-type transistor, the first end of the second transistor T2 can be electrically connected to the source end of the second voltage Vs, and the second end of the second transistor T2 can be electrically connected to the drain end of the second voltage Vs. In one embodiment of the present disclosure, when the second transistor T2 is a P-type transistor and operates in the saturation mode, there is a voltage difference between the first end (i.e. the source end) of the second transistor T2 and the second end (i.e. the drain end) of the second transistor T2, and the voltage at the first end (i.e. the source end) of the second transistor T2 is higher than the voltage at the second end (i.e. the drain end) of the second transistor T2, so that the second voltage Vs is higher than the third voltage VSS (i.e. Vs>VSS).

[0078] Figure 3 A cross-sectional view of the structure of a transistor of one embodiment of the present disclosure. Referring to Figure 2A and Figure 3 , the structure of the second transistor T2 can be implemented as the structure of the transistor structure 300. The transistor structure 300 is a double-gate transistor structure. In one embodiment of the present disclosure, the transistor structure 300 includes a substrate 370, a buffer layer 310, a first insulating layer 320, a semiconductor layer 330, a second insulating layer 340, and a third insulating layer 350. A sensing pixel (e.g. the sensing pixel 200 of Figure 2A is disposed on the substrate 370. The second transistor T2 of the sensing pixel includes a first gate electrode 364, the semiconductor layer 330, the first insulating layer 320, a second gate electrode 361, and the second insulating layer 340.

[0079] In an embodiment of the present disclosure, the first gate electrode 364 is disposed on the buffer layer 310. The first insulating layer 320 covers the first gate electrode 364. The semiconductor layer 330 is disposed on the first insulating layer 320. The second insulating layer 340 is disposed on the semiconductor layer 330. The second transistor T2 of the sensing pixel further includes the connection electrode 351, the electrode 362, and the electrode 363. The second gate electrode 361 and the connection electrode 351 are disposed on the second insulating layer 340. The third insulating layer 350 covers the second gate electrode 361. The electrode 362 and the electrode 363 are disposed on the third insulating layer 350.

[0080] The electrode 362 is electrically connected to the connection electrode 351 through the via hole 301 disposed in the third insulating layer 350, and the connection electrode 351 is electrically connected to the first gate electrode 364 through the via hole 302 disposed in the first insulating layer 320. The layer 330 and the second insulating layer 340. The electrode 362 is also electrically connected to the semiconductor layer 330 through the via hole 303 disposed in the second insulating layer 340 and the third insulating layer 350. The electrode 363 is also electrically connected to the semiconductor layer 330 through the via hole 304 formed in the second insulating layer 340 and the third insulating layer 350. It should be noted that, in the top view, the projection of the first gate electrode 364 on the substrate 370 overlaps with the projection of the second gate electrode 361 on the substrate 370.

[0081] In an embodiment of the present disclosure, the first end (i.e., the drain end) of the second transistor T2 is electrically connected to the electrode 363. The second end (i.e., the source end) and the third end (i.e., the other gate end) of the second transistor T2 are electrically connected to the electrode 362, so that the third end (i.e., the other gate end) of the second transistor T2 is electrically connected to the second end (i.e., the source end) of the second transistor T2 through the electrode 362 to receive the second voltage Vs of the second end (i.e., the source end) of the second transistor T2. The control end (i.e., the gate end) of the second transistor T2 is electrically connected to the second gate electrode 361.

[0082] In an embodiment of the present disclosure, when the second transistor T2 operates in the saturation mode, a voltage difference is formed between the electrode 362 and the electrode 363 to form the current channel 331 in the semiconductor layer 330 for providing a current path between the electrode 362 and the electrode 363. That is, the current flows from the first end of the second transistor T2 to the second end of the second transistor T2. Since the current flows from the first end of the second transistor T2 to the second end of the second transistor T2, a corresponding lateral electric field Eh (in the direction Dl) is generated, and the lateral electric field Eh is increased with the collision ionization phenomenon in the current channel 331, so as to correspondingly change and increase the current flowing from the first end of the second transistor T2 to the second end of the second transistor T2, so as to cause the data signal DAS to be distorted (i.e., the warping effect).

[0083] Therefore, in this embodiment, the second transistor T2 utilizes the first gate electrode 364 and the second gate electrode 361 to generate a vertical electric field Ev (along the D2 direction) to improve the Kink effect. Specifically, since the first gate electrode 364 receives the second voltage Vs, a voltage difference is formed between the second gate electrode 361 and the first gate electrode 364, and a vertical electric field Ev is formed between the first gate electrode 364 and the second gate electrode 364. That is, the vertical electric field Ev can shield part of the transverse electric field Eh in the current channel 331, thereby effectively dispersing part of the transverse electric field Eh in the current channel 331. In other words, the occurrence rate of impact ionization in the current channel 331 can be effectively reduced. Thus, as Figure 4 As shown, this can effectively improve the warpage effect of the second transistor T2.

[0084] Figure 4 This is a schematic diagram of the current-voltage (IV) characteristics of a transistor according to an embodiment of this disclosure. (See reference...) Figure 4 The current-voltage (IV) characteristic curves 401-403 of the transistor correspond to the linear region and the saturation region, respectively, divided by the dashed line 400. Curve 403 corresponds to a transistor with a higher gate-source voltage Vgs, and curve 401 corresponds to a transistor with a lower voltage Vgs. When the voltage Vds (drain-source voltage) is low, in the linear region, the current Ids of transistor T2 increases linearly with increasing voltage Vds. However, as the voltage Vds gradually increases further, the increase in current Ids of transistor T2 decreases and gradually saturates (saturation region). Even in the saturation region, the increase in current Ids of transistor T2 cannot saturate it if the collisional ionization phenomenon in the current path of the transverse electric field is not improved, and the current Ids of transistor T2 can continue to increase with increasing voltage Vds (i.e., warping effect). According to some embodiments, in the saturation region, the current Ids of transistor T2 remains almost constant as the voltage Vds increases. In other words, as the voltage Vds increases, the current Ids of transistor T2 does not change significantly. Therefore, the warpage effect can be mitigated. For any voltage Vgs (i.e., the voltage between the gate and source terminals) of the second transistor T2, in the saturation region, as the voltage Vds (i.e., the voltage between the drain and source terminals) of the second transistor T2 increases, the second transistor T2 can output a stable current Ids (i.e., current flows from the drain terminal to the source terminal of the second transistor T2).

[0085] Figure 5 This is a schematic diagram of a sensing pixel according to another embodiment of this disclosure. (See reference...) Figure 5 , Figure 1The circuit architecture of each of the sensing pixels PC(1,1)~PC(m,n) can be implemented as Figure 5 The circuit architecture of the sensing pixel 500. In an embodiment of the present disclosure, the sensing pixel 500 includes a photosensitive element PD, a capacitor C, a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 includes a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor T1 is electrically connected to a read signal line RDL to receive a read control signal RDS. The first terminal of the first transistor T1 is electrically connected to the second transistor T2. The second terminal of the first transistor T1 is electrically connected to a data line DAL to output a data signal DAS. The second transistor T2 includes a first terminal, a second terminal, a third terminal, and a control terminal. The control terminal of the second transistor T2 is electrically connected to the photosensitive element PD. The first terminal of the second transistor T2 is electrically connected to a first voltage VDD. The second terminal of the second transistor T2 is electrically connected to the first terminal of the first transistor T1. The third terminal of the second transistor T2 is electrically connected to a fixed voltage Va1. The third transistor T3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor T3 is electrically connected to a reset voltage Vrst. The second terminal of the third transistor T3 is electrically connected to the photosensitive element PD. The control terminal of the third transistor T3 is electrically connected to a reset signal line RL to receive a reset signal RS. The cathode terminal of the photosensitive element PD is electrically connected to the control terminal of the second transistor T2 and the second terminal of the third transistor T3. The anode terminal of the photosensitive element PD is electrically connected to a bias voltage Vbias. The photosensitive element PD can be a photodiode. The first terminal of the capacitor C is electrically connected to the control terminal of the second transistor T2 and the second terminal of the third transistor T3. The second terminal of the capacitor C is electrically connected to the bias voltage Vbias. The capacitor C can include a photodiode capacitor.

[0086] In an embodiment of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 can be N-type transistors. The first terminal of the above-mentioned transistors can be a drain terminal. The second terminal of the above-mentioned transistors can be a source terminal. The control terminal of the above-mentioned transistors can be a gate terminal. The third terminal of the above-mentioned transistors can be another gate terminal. In an embodiment of the present disclosure, when the second transistor T2 operates in a saturation mode, there is a voltage difference between the first terminal (i.e., the drain terminal) of the second transistor T2 and the second terminal (i.e., the source terminal) of the second transistor T2. In an embodiment of the present disclosure, the fixed voltage Va1 can be designed to be lower than the voltage of the control terminal of the second transistor T2 and the first voltage VDD. That is, the first voltage VDD is higher than the fixed voltage Va1 (i.e., VDD> Va1). However, in an embodiment of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 can be P-type transistors.

[0087] In addition, please refer to Figure 5Since the second transistor T2 operates in saturation mode and is an N-type transistor, its threshold voltage is positive. The voltage at its second terminal (source) and third terminal (fixed voltage Va1) is lower than the voltage at its control terminal (gate). Furthermore, the first voltage VDD at the first terminal of the second transistor T2 is higher than the voltage at the control terminal (node ​​BE) minus its threshold voltage. In other words, when the second transistor T2 operates in saturation mode, an electric field is generated between its control terminal (gate) and third terminal (another gate) due to the voltage at the control terminal. The third terminal (gate) of the second transistor T2 has a higher voltage than its fixed voltage Va1. Therefore, since the electric field direction between the control terminal (i.e., the gate terminal) and the third terminal (i.e., the other gate terminal) of the second transistor T2 is perpendicular to the current direction flowing from the first terminal to the second terminal of the second transistor T2, the warpage effect of the second transistor T2 can be effectively improved.

[0088] In one embodiment of this disclosure, the sensing pixel 500 may also be in accordance with Figure 2B The timing diagram is used for operation. Therefore, during the scan period Ps (or data readout period) from time t2 to time t3, the second transistor T2 can operate as a source follower amplifier to read out the sensing result of the photosensitive element PD and output the corresponding data signal DAS, which is the voltage at the second terminal of the second transistor T2 minus a voltage (i.e., The parameters in the equation are the same as or similar to those defined above.

[0089] Figure 6 A cross-sectional view of a transistor provided for another embodiment of this disclosure. (See also...) Figure 5 as well as Figure 6 The semiconductor structure of the second transistor T2 can be implemented as the semiconductor structure of transistor structure 600. Transistor structure 600 is a dual-gate transistor structure. In one embodiment disclosed herein, transistor structure 600 includes a substrate 670, a buffer layer 610, a first insulating layer 620, a semiconductor layer 630, a second insulating layer 640, and a third insulating layer 650. Sensing pixels (e.g. Figure 5 The sensing pixel 500 is disposed on the substrate 670. The second transistor T2 of the sensing pixel includes a first gate electrode 664, a semiconductor layer 630, a first insulating layer 620, a second gate electrode 661, and a second insulating layer 640.

[0090] In an embodiment of the present disclosure, the first gate electrode 664 is disposed on the buffer layer 610. The first insulating layer 620 covers the first gate electrode 664. The semiconductor layer 630 is disposed on the first insulating layer 620. The second insulating layer 640 is disposed on the semiconductor layer 630. The second transistor T2 of the sensing pixel further includes the connecting electrode 651, the electrode 662, the electrode 663, and the electrode 665. The second gate electrode 661 and the connecting electrode 651 are disposed on the second insulating layer 640. The third insulating layer 650 covers the second gate electrode 661. The electrode 662, the electrode 663, and the electrode 665 are disposed on the third insulating layer 650.

[0091] Reference Figure 6 The electrode 665 is electrically connected to the connecting electrode 651 through the via hole 601 disposed in the third insulating layer 650, and the connecting electrode 651 is electrically connected to the first gate electrode 664 through the via hole 602 disposed in the third insulating layer 650. The electrode 662 is electrically connected to the semiconductor layer 630 through the via hole 603 disposed in the second insulating layer 640 and the third insulating layer 650. The electrode 663 is also electrically connected to the semiconductor layer 630 through the via hole 604 disposed in the second insulating layer 640 and the third insulating layer 650. It is noted that, in the top view, the projection of the first gate electrode 664 on the substrate 670 overlaps with the projection of the second gate electrode 661 on the substrate 670.

[0092] In an embodiment of the present disclosure, the first end (i.e., the drain end) of the second transistor T2 is electrically connected to the electrode 663. The second end (i.e., the source end) of the second transistor T2 is electrically connected to the electrode 662. The third end (i.e., the other gate end) of the second transistor T2 is electrically connected to the electrode 665 to receive the fixed voltage Va1. The control end (i.e., the gate end) of the second transistor T2 is electrically connected to the second gate electrode 661.

[0093] In an embodiment of the present disclosure, when the second transistor T2 operates in the saturation mode, a voltage difference is formed between the electrode 662 and the electrode 663 to form the current channel 631 in the semiconductor layer 630 for providing a current path between the electrode 662 and the electrode 663. That is, the current flows from the first end of the second transistor T2 to the second end of the second transistor T2. As the current flows from the first end of the second transistor T2 to the second end of the second transistor T2, a lateral electric field Eh (in the direction Dl) is correspondingly generated, and the lateral electric field Eh is increased with the collision ionization phenomenon in the current channel 631 to correspondingly change and increase the current flowing from the first end of the second transistor T2 to the second end of the second transistor T2 (i.e., the Kink effect).

[0094] Therefore, in this embodiment, the second transistor T2 utilizes a vertical electric field Ev (along direction D2) generated between the first gate electrode 664 and the second gate electrode 661 to improve the Kink effect. Specifically, since the first gate electrode 664 receives a fixed voltage Va1 from the electrode 665, a voltage difference is formed between the second gate electrode 661 and the first gate electrode 664, thus creating a vertical electric field Ev between them. In other words, the vertical electric field Ev can shield part of the lateral electric field Eh in the current channel 631, effectively dispersing some of the lateral electric field Eh in the current channel 631. In other words, the occurrence rate of impact ionization in the current channel 631 can be effectively reduced. Accordingly, as... Figure 4 As shown, this can effectively improve the warpage effect of the second transistor T2.

[0095] Therefore, as Figure 4 As shown, with the warpage effect improved, for any voltage Vgs (i.e., the voltage between the gate and source terminals) of the second transistor T2, as the voltage Vds (i.e., the voltage between the drain and source terminals) of the second transistor T2 increases, the second transistor T2 can output a stable current Ids (i.e., the current flows from the drain terminal to the source terminal of the second transistor T2).

[0096] Figure 7 This is a schematic diagram of a current source circuit according to an embodiment of this disclosure. (See reference...) Figure 7 , Figure 1 The circuit architecture of each of the current source circuits CS_1 to CS_n can be implemented as follows: Figure 7 The circuit architecture of the current source circuit 700 is disclosed. In one embodiment, the current source circuit 700 includes an active load transistor Tal_1. The active load transistor Tal_1 includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the active load transistor Tal_1 is electrically connected to the sensing pixel PC (e.g., PC) via the data line DAL. Figure 1 The sensing pixels PC(1,1) to PC(m,n) are in one column. The second terminal of the active load transistor Tal_1 is electrically connected to the third voltage VSS (i.e., the operating voltage). The third terminal of the active load transistor Tal_1 is electrically connected to the second terminal of the active load transistor Tal_1 to receive the fourth voltage Vsal (i.e., the voltage at the second terminal of the active load transistor Tal_1). That is, the fourth voltage Vsal is equal to the third voltage VSS. The control terminal of the active load transistor Tal_1 receives the active load control signal Sal_1.

[0097] In an embodiment of the present disclosure, the active load transistor Tal_1 can be an N-type transistor. The first terminal of the active load transistor Tal_1 can be a drain terminal. The second terminal of the active load transistor Tal_1 can be a source terminal. The control terminal of the active load transistor Tal_1 can be a gate terminal. The third terminal of the active load transistor can be another gate terminal. However, in an embodiment of the present disclosure, the active load transistor Tal_1 can be a P-type transistor.

[0098] In particular, in an embodiment of the present disclosure, during the data readout of the sensing pixel PC, the active load transistor Tal_1 can be operated in the saturation mode according to the active load control signal Sal_1 having a high level, such that a constant current Ics is formed between the first terminal of the active load transistor Tal_1 and the second terminal of the active load transistor Tal_1 (i.e. the current Ids flowing from the first terminal to the second terminal of the active load transistor Tal_1). The constant current Ics flows from the first terminal of the active load transistor Tal_1 to the second terminal of the active load transistor Tal_1. Therefore, the data signal DAS of the sensing result of the sensing pixel PC can be effectively read out from the data signal line DAL to the corresponding amplifier circuit. The first terminal of the active load transistor Tal_1 is electrically connected to the data line DAL to receive the data signal DAS. In addition, when the active load transistor Tal_1 is operated in the saturation mode and the active load transistor Tal_1 is an N-type transistor, the threshold voltage of the active load transistor Tal_1 is positive, and the fourth voltage Vsal is lower than the voltage of the control terminal of the active load transistor Tal_1, and the voltage of the data signal DAS of the first terminal of the active load transistor Tal_1 is higher than the voltage of the control terminal of the active load transistor Tal_1 minus the threshold voltage of the active load transistor Tal_1.

[0099] In an embodiment of the present disclosure, the semiconductor structure of the active load transistor Tal_1 can also be implemented as the semiconductor structure of the transistor structure 300 of Figure 3 Therefore, the warpage effect of the active load transistor Tal_1 can be effectively improved, as shown in Figure 4 Figure 4 The current-voltage (IV) characteristic curves 401-403 can also be applicable to the active load transistor Tal_1 of the current source circuit 700 of Figure 7 Figure 4 ​​As shown, with the warpage effect improved, for any voltage Vgs (i.e., the voltage between the gate and source terminals) of the active load transistor Tal_1, as the voltage Vds (i.e., the voltage between the drain and source terminals) of the active load transistor Tal_1 increases, the active load transistor Tal_1 can output a stable constant current Ics (i.e., the current Ids flows from the drain of the active load transistor Tal_1 to the source terminal), thereby effectively stabilizing the operation of the active load transistor Tal_1 as a source follower amplifier, and effectively stabilizing the data signal DAS transmitted on the data line DAL.

[0100] Figure 8 This is a schematic diagram of a current source circuit according to an embodiment of this disclosure. (See reference...) Figure 8 , Figure 1 The circuit architecture of each of the current source circuits CS_1 to CS_n can be implemented as follows: Figure 8 The circuit architecture of the current source circuit 800 is disclosed. In one embodiment, the current source circuit 800 includes an active load transistor Tal_2. The active load transistor Tal_2 includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the active load transistor Tal_2 is electrically connected to the sensing pixel PC (e.g., PC) via the data line DAL. Figure 1 The sensing pixels PC(1,1) to PC(m,n) form a column. The second terminal of the active load transistor Tal_2 is electrically connected to a third voltage VSS. The third terminal of the active load transistor Tal_2 is electrically connected to a fixed voltage Va2, such that the fixed voltage Va2 can be provided to the first gate electrode of the active load transistor Tal_2 (e.g., this gate electrode has the same function as the first gate electrode 364 or the first gate electrode 664). The control terminal of the active load transistor Tal_2 receives the active load control signal Sal_2.

[0101] In an embodiment of the present disclosure, the active load transistor Tal_2 can be an N-type transistor. The first terminal of the active load transistor Tal_2 can be a drain terminal. The second terminal of the active load transistor Tal_2 can be a source terminal. The control terminal of the active load transistor Tal_2 can be a gate terminal. The third terminal of the active load transistor can be another gate terminal. In an embodiment of the present disclosure, when the active load transistor Tal_2 operates in the saturation mode, there is a voltage difference between the first terminal (i.e., the drain terminal) and the second terminal (i.e., the source terminal) of the active load transistor Tal_2. The voltage of the first terminal (i.e., the drain terminal) of the active load transistor Tal_2 is higher than the voltage of the second terminal (i.e., the source terminal) of the active load transistor Tal_2. In an embodiment of the present disclosure, the fixed voltage Va2 can be designed to be equal to or different from the third voltage VSS, and the fixed voltage Va2 can be designed to be lower than the voltage of the control terminal of the active load transistor Tal_2. That is, the fixed voltage Va2 can be equal to or different from the third voltage VSS, and lower than the voltage of the control terminal of the active load transistor Tal_2. However, in an embodiment of the present disclosure, the active load transistor Tal_2 can be a P-type transistor.

[0102] In addition, when the active load transistor Tal_2 operates in the saturation mode, a voltage of the active load transistor Tal_2 generates an electric field between the control terminal (i.e., the gate terminal) and the third terminal (i.e., the other gate terminal) of the active load transistor Tal_2. Therefore, since the direction of the electric field between the control terminal (i.e., the gate terminal) of the active load transistor Tal_2 and the third terminal (i.e., the other gate terminal) of the active load transistor Tal_2 is perpendicular to the direction of the current flowing from the first terminal to the second terminal of the active load transistor Tal_2, the warpage effect of the active load transistor Tal_2 can be effectively improved.

[0103] Specifically, in an embodiment of the present disclosure, during the data readout of the sensing pixel PC, the active load transistor Tal_2 can operate in the saturation mode according to the active load control signal Sal_2 having a high level, so that a constant current Ics (i.e., the current Ids flowing from the first terminal to the second terminal of the active load transistor Tal_2) is formed between the first terminal of the active load transistor Tal_2 and the second terminal of the active load transistor Tal_2. The constant current Ics flows from the first terminal of the active load transistor Tal_2 to the second terminal of the active load transistor Tal_2. Therefore, the data signal DAS of the sensing result of the sensing pixel PC can be effectively read out from the data signal line DAL to the corresponding amplifier circuit.

[0104] In an embodiment of the present disclosure, the semiconductor structure of the active load transistor Tal_2 can also be implemented as Figure 6of the transistor structure 600. Thus, the warping effect of the active load transistor Tal_2 can be effectively improved, as shown in Figure 4 . Figure 4 The current-voltage (IV) characteristic curves 401-403 of the active load transistor Tal_2 of the current source circuit 800 can also be applicable to Figure 8 the active load transistor Tal_2 of the current source circuit 800. As shown in Figure 4 improving the warping effect, for any voltage Vgs (i.e., the voltage between the gate terminal and the source terminal) of the active load transistor Tal_2, as the voltage Vds (i.e., the voltage between the drain terminal and the source terminal) of the active load transistor Tal_2 rises, the active load transistor Tal_2 can output a stable constant current Ics (i.e., the current Ids flowing from the drain terminal to the source terminal of the active load transistor Tal_2), so as to effectively stabilize the operation of the active load transistor Tal_2 as a source-follower amplifier, and effectively stabilize the data signal DAS transmitted on the data line DAL.

[0105] It is noted that, referring to Figure 1 in an embodiment of the present disclosure, at least one of the sensing pixels PC(1,1)-PC(m,n) of the pixel array 110 of the electronic device 100 can be implemented as the sensing pixel 200 of Figure 2A or the sensing pixel 500 of Figure 5 , and at least one of the current source circuits CS_1-CS_n of the peripheral circuit 120 of the electronic device 100 does not necessarily have to be implemented as the current source circuit 700 of Figure 7 or the current source circuit 800 of Figure 8 . At least one of the current source circuits CS_1-CS_n of the peripheral circuit 120 of the electronic device 100 can be implemented as a general current source circuit. In another embodiment of the present disclosure, at least one of the sensing pixels PC(1,1)-PC(m,n) of the pixel array 110 of the electronic device 100 can be implemented as the sensing pixel 200 of Figure 2A or the sensing pixel 500 of Figure 5 . In another embodiment of the present disclosure, at least one of the current source circuits CS_1-CS_n of the peripheral circuit 120 of the electronic device 100 can be implemented as the current source circuit 700 of Figure 7 or the current source circuit 800 of Figure 8 , and at least one of the sensing pixels PC(1,1)-PC(m,n) of the pixel array 110 of the electronic device 100 does not necessarily have to be implemented as the sensing pixel 200 of Figure 2A or the sensing pixel 500 of Figure 5 Figure 7 Figure 8 Figure 2A Figure 5 . At least one of the sensing pixels PC(1,1)-PC(m,n) of the pixel array 110 of the electronic device 100 can be implemented as a general sensing pixel.

[0106] In summary, the electronic device of the present disclosure can apply the transistor of the dual-gate transistor structure to the source-follower amplifier of the sensing pixel or the current source of the readout circuit, so that the warpage effect of the transistor in the source-follower amplifier or the current source of the readout circuit can be effectively improved. Therefore, the electronic device of the present disclosure can provide stable circuit operation.

[0107] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An electronic device, characterized in that, Includes sensing pixels, wherein the sensing pixels include: Photosensitive element; A first transistor includes a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first transistor is electrically connected to a read signal line, and the second terminal of the first transistor is electrically connected to a data line. A second transistor includes a first terminal, a second terminal, a third terminal, and a control terminal, wherein the control terminal of the second transistor is electrically connected to the photosensitive element, the first terminal of the second transistor is electrically connected to a first voltage, the second terminal of the second transistor is electrically connected to the first terminal of the first transistor, and the third terminal of the second transistor is electrically connected to a second voltage; and The third transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is electrically connected to a reset voltage, the second terminal of the third transistor is electrically connected to the photosensitive element, and the control terminal of the third transistor is electrically connected to a reset signal line.

2. The electronic device according to claim 1, characterized in that, The second terminal of the second transistor has the second voltage, and the third terminal of the second transistor is electrically connected to the second terminal of the second transistor to receive the second voltage.

3. The electronic device according to claim 1, characterized in that, When the second transistor operates in saturation mode and is an N-type transistor, the threshold voltage of the second transistor is positive, the second voltage is lower than the voltage at the control terminal of the second transistor, and the first voltage at the first terminal of the second transistor is higher than the voltage at the control terminal of the second transistor minus the threshold voltage of the second transistor.

4. The electronic device according to claim 1, characterized in that, Also includes: substrate; as well as The sensing pixels are disposed on the substrate. The second transistor of the sensing pixel includes: The first gate electrode is electrically connected to the third terminal of the second transistor; Semiconductor layer; A first insulating layer is disposed between the first gate electrode and the semiconductor layer; The second gate electrode is electrically connected to the control terminal of the second transistor; and A second insulating layer is disposed between the second gate electrode and the semiconductor layer, wherein the projection of the first gate electrode on the substrate overlaps with the projection of the second gate electrode on the substrate.

5. The electronic device according to claim 4, characterized in that, When the second transistor operates in saturation mode, a vertical electric field is formed between the first gate electrode and the second gate electrode.

6. The electronic device according to claim 1, characterized in that, The second voltage is a fixed voltage.

7. The electronic device according to claim 1, characterized in that, The first voltage is different from the second voltage.

8. The electronic device according to claim 1, characterized in that, The second transistor is an N-type transistor, and the first voltage is higher than the second voltage.

9. The electronic device according to claim 1, characterized in that, The second transistor is a P-type transistor, and the first voltage is lower than the second voltage.

10. The electronic device according to claim 1, characterized in that, It also includes a current source circuit, wherein the current source circuit includes: An active load transistor includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the active load transistor is electrically connected to the sensing pixel via the data line. The second terminal of the active load transistor is electrically connected to a third voltage. The third terminal of the active load transistor is electrically connected to a fourth voltage. The control terminal of the active load transistor is electrically connected to an active load control signal.

11. The electronic device according to claim 10, characterized in that, The third terminal of the active load transistor is electrically connected to the second terminal of the active load transistor.

12. The electronic device according to claim 10, characterized in that, The fourth voltage is a fixed voltage.

13. The electronic device according to claim 10, characterized in that, The third voltage is equal to the fourth voltage.

14. The electronic device according to claim 10, characterized in that, Also includes Substrate; and The sensing pixels are disposed on the substrate. The current source circuit is disposed on the substrate.

15. The electronic device according to claim 14, characterized in that, The substrate includes an active region and a peripheral region. The sensing pixel is disposed in the active region of the substrate, and the current source circuit is disposed in the peripheral region of the substrate.

16. An electronic device, characterized in that, Includes a current source circuit, wherein the current source circuit includes: An active load transistor includes a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the active load transistor is electrically connected to a sensing pixel via a data line, the second terminal of the active load transistor is electrically connected to a third voltage, the third terminal of the active load transistor is electrically connected to a fourth voltage, and the control terminal of the active load transistor is electrically connected to an active load control signal.

17. The electronic device according to claim 16, characterized in that, The third terminal of the active load transistor is electrically connected to the second terminal of the active load transistor.

18. The electronic device according to claim 16, characterized in that, When the active load transistor operates in saturation mode and is an N-type transistor, the threshold voltage of the active load transistor is positive, the fourth voltage is lower than the voltage at the control terminal of the active load transistor, and the voltage at the first terminal of the active load transistor is higher than the voltage at the control terminal of the active load transistor minus the threshold voltage of the active load transistor.

19. The electronic device according to claim 16, characterized in that, The fourth voltage is a fixed voltage.

20. The electronic device according to claim 16, characterized in that, The third voltage is equal to the fourth voltage.

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