Clamping field effect transistor, layout structure, chip, clamping circuit and equipment

Abstract

The invention discloses a clamping field effect transistor, a layout structure, a chip, a clamping circuit and equipment, and belongs to the technical field of circuits. The clamping field effect transistor comprises a first field effect transistor and a second field effect transistor which are arranged side by side along a first direction, and each field effect transistor comprises a substrate, and a source electrode, a grid electrode and a drain electrode which are positioned on one side of the substrate and are distributed along the first direction; projections of contacts of the source electrode and the drain electrode in the first direction and projections of the contacts of the source electrode and the drain electrode in the second direction are arranged at intervals, and the second direction is perpendicular to the first direction; at least one of the first field effect transistor or the second field effect transistor is provided with an avoiding area, and the avoiding area is used for configuring a contact of the substrate, so that the contact of the substrate is located in the avoiding area. The contact of the source electrode and the contact of the drain electrode are staggered, and the contact of the substrate is configured in the avoiding region, so that the distance between the source electrode and the drain electrode is increased, and the maintaining voltage of the transistor is improved on the premise that the area of the transistor is not increased.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a clamping field-effect transistor, layout structure, chip, clamping circuit and device. Background Technology

[0002] In the field of circuit technology, there are various types of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). MOSFETs are used to discharge current in circuits or devices, but there are situations where the holding voltage of a MOSFET is lower than the supply voltage of the circuit or device, leading to…

[0003] If a MOSFET remains in the ON state for an extended period, signals in a circuit or device will flow to ground through the MOSFET, causing the circuit or device to fail. MOSFETs include, but are not limited to, NMOS (N-Metal-Oxide-Semiconductor) or PMOS (P-Metal-Oxide-Semiconductor).

[0004] In related technologies, the holding voltage of a MOSFET is increased by increasing the distance between its gate and drain. However, this increased distance leads to a larger MOSFET area, resulting in wasted space in the circuit or device. Summary of the Invention

[0005] This application provides a clamping field-effect transistor, layout structure, chip, clamping circuit, and device, which can increase the holding voltage of the transistor without increasing the transistor area. The technical solution is as follows:

[0006] In a first aspect, a clamping field-effect transistor is provided, the clamping field-effect transistor being applied to a clamping circuit, the clamping field-effect transistor comprising a first field-effect transistor and a second field-effect transistor arranged side by side along a first direction;

[0007] Both the first field-effect transistor and the second field-effect transistor include a substrate and a source, a gate, and a drain located on one side of the substrate and distributed along the first direction. The projections of the contacts of the source and the drain in the first direction and in the second direction are arranged at intervals, and the second direction is perpendicular to the first direction.

[0008] The first electrode of the target field-effect transistor has a first clearance region for configuring contacts of a substrate, at least a portion of the contacts of the substrate being located in the first clearance region, the first electrode being the source or drain of the target field-effect transistor, and the target field-effect transistor being at least one of the first field-effect transistor or the second field-effect transistor.

[0009] In one possible implementation, the first electrode has a plurality of first clearance areas located on both sides of the contact of the first electrode in the second direction.

[0010] In one possible implementation, the first pole has at least one first clearance area located between two contacts of the first pole in the second direction.

[0011] In one possible implementation, the first electrode has a plurality of first clearance areas, which are distributed intersectingly with the contact points of the first electrode in the second direction.

[0012] In one possible implementation, the contact of each first pole is located between two first clearance zones, or each first clearance zone is located between two contacts of the first pole.

[0013] In one possible implementation, the second electrode of the target field-effect transistor has a second clearance region, a portion of the substrate contacts are located in the first clearance region, and another portion of the substrate contacts are located in the second clearance region. The second electrode is the source or drain of the target field-effect transistor, and the second electrode is different from the first electrode.

[0014] In a second aspect, a transistor layout structure is provided, the layout structure including: a drain region for configuring a drain, a source region for configuring a source, a gate region for configuring a gate, and a substrate region for configuring a substrate, wherein the drain region, the source region, and the gate region are all located on one side of the substrate region and distributed along a first direction;

[0015] The drain region includes a drain sub-region, which is used to configure the contacts of the drain.

[0016] The source region includes a source sub-region, which is used to configure the contacts of the source. The contacts of the source and the contacts of the drain are arranged at intervals in the projection of the source and the contacts of the drain in the first direction, and are arranged at intervals in the projection of the source and the contacts of the drain in the second direction, which is perpendicular to the first direction.

[0017] At least one of the drain region or the source region further includes a clearance sub-region for configuring contacts of the substrate.

[0018] In one possible implementation, the drain region includes at least one drain sub-region and a plurality of drain avoidance sub-regions; wherein the plurality of drain avoidance sub-regions are located on both sides of the at least one drain sub-region in the second direction.

[0019] In one possible implementation, the drain region includes a plurality of drain sub-regions and at least one drain avoidance sub-region; wherein the at least one drain avoidance sub-region is located between two drain sub-regions in the second direction.

[0020] In one possible implementation, the drain region includes multiple drain sub-regions and multiple drain avoidance sub-regions; wherein the multiple drain sub-regions and multiple drain avoidance sub-regions are distributed intersectingly in the second direction.

[0021] In one possible implementation, each of the plurality of drain sub-regions is located between two drain avoidance sub-regions; or, each of the plurality of drain avoidance sub-regions is located between two drain regions.

[0022] In one possible implementation, the source region includes at least one source sub-region and a plurality of source avoidance sub-regions; wherein the plurality of source avoidance sub-regions are located on both sides of the at least one source sub-region in the second direction.

[0023] In one possible implementation, the source region includes a plurality of source sub-regions and at least one source avoidance sub-region; wherein the at least one source avoidance sub-region is located between two source sub-regions in the second direction.

[0024] In one possible implementation, the source pole region includes multiple source pole sub-regions and multiple source pole avoidance sub-regions; wherein the multiple source pole sub-regions and multiple source pole avoidance sub-regions are distributed intersectingly in the second direction.

[0025] In one possible implementation, each of the plurality of source pole regions is located between two source pole avoidance sub-regions; or, each of the plurality of source pole avoidance sub-regions is located between two source pole regions.

[0026] Thirdly, a chip is provided, the chip comprising the clamping field-effect transistor described in any of the first aspects above.

[0027] Fourthly, a clamping circuit is provided, the clamping circuit including any of the clamping field-effect transistors described in the first aspect above, the clamping field-effect transistor being used to discharge current in the clamping circuit.

[0028] Fifthly, an electrostatic discharge device is provided, which includes the aforementioned clamping circuit.

[0029] The technical solution provided in this application has at least the following beneficial effects:

[0030] In the technical solution provided in this application, the source and drain contacts are spaced apart in both the projections in the first direction and the projections in the second direction, thereby achieving mutual offset between the source and drain contacts and increasing the distance between the source and drain. This allows for an increase in the transistor's holding voltage without increasing the transistor area. Furthermore, compared to methods that place substrate contacts around the source or drain, the substrate contacts in this application are located in the region where the source or drain is located, thus reducing the area occupied by the substrate contacts and further reducing the transistor area. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a clamping circuit provided by related technologies;

[0033] Figure 2 This is a schematic diagram of the layout structure of a transistor in related technologies;

[0034] Figure 3 This is a schematic diagram of another transistor layout in related technologies;

[0035] Figure 4 This is a schematic diagram of an NMOS structure in related technologies;

[0036] Figure 5 This is a schematic diagram of the layout structure of a transistor provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the structure of a clamping field-effect transistor provided in an embodiment of this application;

[0038] Figure 7 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0039] Figure 8 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0040] Figure 9 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0041] Figure 10 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0042] Figure 11 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0043] Figure 12 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0044] Figure 13 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0045] Figure 14 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0046] Figure 15 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0047] Figure 16 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0048] Figure 17 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0049] Figure 18 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0050] Figure 19 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0051] Figure 20 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0052] Figure 21 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0053] Figure 22 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0054] Figure 23 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0055] Figure 24 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0056] Figure 25 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0057] Figure 26 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0058] Figure 27 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0059] Figure 28 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0060] Figure 29 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0061] Figure 30 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0062] Figure 31 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0063] Figure 32 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0064] Figure 33 This is a schematic diagram of another transistor layout structure provided in an embodiment of this application;

[0065] Figure 34 This is a schematic diagram of another clamping field-effect transistor provided in an embodiment of this application;

[0066] Figure 35 This is a schematic diagram of the sustaining voltage of a transistor provided in an embodiment of this application. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0068] It should be noted that the terms "first," "second," etc., used in the specification of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0069] In the field of circuit technology, MOSFETs are used to discharge current in circuits or devices to protect them from adverse conditions such as overcurrent or ESD (Electro-Static Discharge). In the overall ESD protection of an integrated circuit (IC), in addition to the ESD protection circuits around each input or output pad, an effective ESD clamping circuit between VDD (Voltage Drain) and VSS (Voltage Source) needs to be designed. For example... Figure 1 One clamping circuit provided in the related technology is an RC (Resistor Capacitor)-INV (Inverter)-NMOS CLAMP circuit. The RC-INV-NMOS primarily relies on the NMOS channel and the parasitic NPN junctions at the source, substrate, and drain to discharge amplified current, thereby clamping the port voltage. However, in practical applications, the MOSFET's holding voltage may be lower than the circuit or device's power supply voltage.

[0070] For example, in a CLAMP NMOS (clamped NMOS), an excessively low sustaining voltage can cause the NMOS to turn on unexpectedly due to interference signals at the input / output ports, and remain in a low-impedance conduction state because the sustaining voltage is lower than the supply voltage. This prolonged conduction state causes signals in the circuit or device to flow directly to ground (VSS) through the NMOS instead of following the normal processing path, resulting in the circuit or device malfunctioning.

[0071] See Figure 2 The diagram shown is a schematic representation of a transistor layout structure in the related technology. Figure 2This includes a gate region 101 for configuring the gate, a drain region 102 for configuring the drain, a source region 103 for configuring the source, and a substrate region 104 for configuring the substrate. Taking an NMOS layout as an example, the gate is used to control the NMOS switch, i.e., the flow of current in the NMOS. The drain is the port where current flows in, and the source is the port where current flows out. The substrate and source are connected to the negative terminal of the power supply, and the drain is connected to the positive terminal of the power supply. Furthermore, the drain, source, gate, and substrate include multiple contacts.

[0072] In related technologies, based on Figure 2 The schematic diagram of the transistor layout shown illustrates... Figure 3 The diagram shows a schematic layout of a transistor. Figure 3 It also includes a gate region 101 for configuring the gate, a drain region 102 for configuring the drain, a source region 103 for configuring the source, and a substrate region 104 for configuring the substrate. Figure 2 and Figure 3 The substrate regions 104 shown are all used to configure substrate contacts (as indicated by the squares in substrate regions 104). From Figure 2 and Figure 3 As can be seen from the substrate region 104 shown, the substrate region 104 is disposed around the gate region 101, the drain region 102, and the source region 103. Since the substrate region 104 is used to set the substrate contacts, the substrate contacts are disposed around the periphery of the transistor layout structure. Furthermore, compared to... Figure 2 , Figure 3 The distance between the drain region 102 and the gate region 101 is increased, which increases the distance between the drain and the gate, thereby increasing the sustaining voltage of the NMOS. See [link to relevant documentation]. Figure 4 The diagram shown is a schematic of an NMOS structure. Figure 4 The method shown is equivalent to adding a resistor R to the drain terminal, thereby increasing the on-resistance of the NMOS and thus increasing the holding voltage of the NMOS.

[0073] In related technologies, increasing the distance between the gate and drain in an NMOS transistor improves its sustaining voltage. However, because a larger gap is required between the gate and drain to ensure the sustaining voltage, the NMOS area increases significantly. In integrated circuit design, an excessively large area increases manufacturing costs and affects the overall circuit layout and performance.

[0074] This application provides a transistor layout structure that allows the corresponding MOSFET to increase its holding voltage without increasing the transistor area. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the layout structure of a transistor provided in an embodiment of this application. Figure 5 The transistor layout shown includes a drain region 402 for configuring the drain, a source region 403 for configuring the source, a gate region 401 for configuring the gate, and a substrate region for configuring the substrate. The drain region 402, the source region 403, and the gate region 401 are all located on one side of the substrate region and distributed along a first direction.

[0075] like Figure 5 As shown, the drain region 402 includes a drain sub-region 4021, which is used to configure the drain contacts; the source region 403 includes a source sub-region 4031, which is used to configure the source contacts. Figure 5 The example only uses two drain regions 4021 and three source regions 4031, but it is not limited to this. It is sufficient to arrange the source contacts and drain contacts at a distance from each other in the first direction, and the source contacts and drain contacts at a distance from each other in the second direction, wherein the second direction is perpendicular to the first direction.

[0076] Because the source contacts and drain contacts are arranged with their projections spaced apart in the first direction and with their projections spaced apart in the second direction, the source contacts and drain contacts are staggered, increasing the distance between the source and drain. This increases the distance between the gate and drain, thereby improving the holding voltage of the transistor without increasing the transistor area.

[0077] Furthermore, in the layout structure provided in this application embodiment, at least one of the drain region 402 or the source region 403 further includes a clearance sub-region, which is used to configure the substrate contacts. This application embodiment does not limit the number of clearance sub-regions provided in the drain region 402 or the source region 403, nor does it limit the total number of clearance sub-regions; they can be configured based on the usage requirements of the substrate contacts. By setting the substrate contacts in the clearance sub-regions provided in the drain region 402 and / or the source region 403, compared to... Figure 2 or Figure 3 As shown in the method of setting substrate contacts in the peripheral substrate region 104, the layout structure provided in this application embodiment can save more transistor area, thereby increasing the transistor's holding voltage without increasing the transistor area.

[0078] In the embodiments of this application, such as Figure 5 The layout shown corresponds to a clamped field-effect transistor, which includes two field-effect transistors arranged side-by-side along the same direction. Figure 5The drain region 402, source region 403, gate region 401, and substrate region shown are all symmetrically arranged, which helps to balance current flow and improve device performance. Furthermore, the two symmetrically arranged field-effect transistors share the same structural principle. Figure 5 The explanation will be based on the example of the structure of one of two symmetrically arranged field-effect transistors.

[0079] Based on the above Figure 5 The transistor layout shown in this application embodiment also provides a clamping field-effect transistor (FET), which is applied to a clamping circuit. The clamping FET includes a first FET and a second FET arranged side-by-side along a first direction; both the first and second FETs include a substrate and source, gate, and drain located on one side of the substrate and distributed along the first direction. Figure 6 As shown, the first field-effect transistor has a source 511, a drain 521 and a gate 531 distributed along a first direction on one side of the substrate 54, and the second field-effect transistor has a source 521, a drain 522 and a gate 532 distributed along the first direction on the other side of the substrate 54.

[0080] In the embodiments of this application, whether it is the first field-effect transistor or the second field-effect transistor, the source contact ( Figure 6 Not shown in the image, please refer to the image. Figure 5 The location of the source sub-region 4031 shown (for configuring the source contacts) and the drain contacts ( Figure 6 Not shown in the image, please refer to the image. Figure 5 The location of the drain sub-region 4021 (shown for configuring the drain contacts) is arranged at intervals in both the projection in the first direction and the projection in the second direction, with the second direction perpendicular to the first direction. Because the source and drain contacts are arranged at intervals in both the projection in the first direction and the projection in the second direction, the source and drain contacts are staggered, increasing the distance between the source and drain. This increases the distance between the gate and drain, thereby improving the transistor's holding voltage without increasing the transistor area.

[0081] Furthermore, in the clamped field-effect transistor provided in this application embodiment, the first electrode of the target field-effect transistor has a first clearance region. The first clearance region is used to configure the contacts of the substrate, and at least a portion of the contacts of the substrate are located in the first clearance region. The first electrode is the source or drain of the target field-effect transistor, and the target field-effect transistor is at least one of a first field-effect transistor or a second field-effect transistor. That is, at least one of the drain or source of the target field-effect transistor has a first clearance region. This application embodiment does not limit the number of first clearance regions. Since the first clearance region can be used to configure the contacts of the substrate, the number of first clearance regions can be determined based on the number of contacts required by the substrate.

[0082] Based on the above transistor layout structure and clamped field-effect transistor, for ease of understanding, the following layout structures will be used as examples to illustrate the transistor layout structure and the corresponding clamped field-effect transistor.

[0083] In the first layout structure provided in the embodiments of this application, the drain region includes at least one drain sub-region and multiple drain avoidance sub-regions; wherein, the multiple drain avoidance sub-regions are located on both sides of at least one drain sub-region in the second direction.

[0084] like Figure 5 As shown, taking the drain region 402, which includes two drain sub-regions 4021 and two drain avoidance sub-regions 4022, as an example, the two drain sub-regions 4021 are located between the two drain avoidance sub-regions 4022, that is, the two drain avoidance sub-regions 4022 are located on both sides of the two drain sub-regions 4021 in the second direction.

[0085] This application does not limit the number of drain sub-regions and drain avoidance sub-regions. Figure 5 The quantities shown are not intended to limit this application. For example, Figure 5 The drain region 4021 shown can be one or more, ensuring that the source contacts and the drain contacts disposed in the drain region 4021 are arranged with a projection interval in the first direction, and that the source contacts and the drain contacts are arranged with a projection interval in the second direction. Optionally, Figure 5 The drain avoidance sub-region 4022 shown can also be two or more, and it does not need to be set symmetrically. That is, the number of drain avoidance sub-regions 4022 located on both sides of the drain sub-region 4021 can be different, as long as the drain avoidance sub-regions 4022 are located on both sides of all drain sub-regions 4021 in the second direction.

[0086] For the first layout structure described above, in the clamped field-effect transistor corresponding to the first layout structure provided in the embodiments of this application, the first electrode has multiple first clearance regions, and the multiple first clearance regions are located on both sides of the contact of the first electrode in the second direction. Taking the first electrode as the drain of the target field-effect transistor and the first clearance region as the drain clearance region as an example, as follows... Figure 6 The clamped field-effect transistor shown, in its structure, with two drain clearance regions at the drain, has substrate contacts 541 and 542 located within the drain clearance region 5210, compared to... Figure 2 or Figure 3 Compared to the method of setting substrate contacts in the peripheral substrate region 104 as shown, the transistor provided in this application embodiment has a smaller area.

[0087] This application does not limit the number of drain avoidance regions in its embodiments. Figure 6 The number of drain clearance regions 5210 shown is not intended to limit this application. Optionally, Figure 6 The drain clearance area 5210 shown can also be two or more, and does not need to be symmetrically arranged, that is, located at the drain contact ( Figure 6 Not shown in the image, please refer to the following: Figure 5 The number of drain clearance areas on both sides of the location of the drain electrode region 4021 shown can be different, as long as the drain clearance area 5210 is located on both sides of the contact of all drain electrodes in the second direction.

[0088] The second layout structure, in the layout structure provided in the embodiments of this application, includes a drain region comprising a plurality of drain sub-regions and at least one drain avoidance sub-region; wherein, at least one drain avoidance sub-region is located between two drain sub-regions in a second direction.

[0089] like Figure 7 In the layout structure shown, the drain region 402 includes two drain sub-regions 4021 and one drain avoidance sub-region 4022, with the drain avoidance sub-region 4022 located between the two drain sub-regions 4021 in the second direction.

[0090] This application does not limit the number of drain sub-regions 4021 and drain avoidance sub-regions 4022 in its embodiments. Figure 7 The quantities shown are not intended to limit this application. For example, Figure 7 The drain region 4021 shown can also be two or more, ensuring that the source contacts in the source region 4031 and the drain contacts in the drain region 4021 are arranged with a projection interval in the first direction, and that the source contacts and drain contacts are arranged with a projection interval in the second direction. Optionally, Figure 7The drain avoidance sub-region 4022 shown can also be one or more, as long as the drain avoidance sub-region 4022 is located between two drain sub-regions 4021 in the second direction, that is, the drain sub-region 4021 is located on both sides of the drain avoidance sub-region 4022.

[0091] Corresponding to the second layout structure, in the clamped field-effect transistor provided in this application embodiment, the first electrode has at least one first clearance region, and the at least one first clearance region is located between the two contacts of the first electrode in the second direction. Taking the first electrode as the drain of the target field-effect transistor and the first clearance region as the drain clearance region as an example, as follows... Figure 8 The clamped field-effect transistor shown has a drain clearance region 5210 at its drain terminal, which is located in the second direction between the two contacts of the drain terminal. Figure 8 Not shown in the image, see reference. Figure 7 The location of the drain pole region 4021 shown is between (e.g., the location of the drain pole region 4021). Figure 8 The substrate contact 543 shown is located between the two contacts of the drain electrode (reference). Figure 7 (The relationship between the locations of the drain avoidance sub-region 4022 and the two drain sub-regions 4021 is shown).

[0092] This application does not limit the number of drain avoidance regions in its embodiments. Figure 8 The number of drain clearance regions 5210 shown is not intended to limit this application; alternatively, Figure 8 The drain clearance area 5210 shown can also be two or more, as long as the drain clearance area 5210 is located between the two contacts of the drain in the second direction.

[0093] The third layout structure, in the layout structure provided in the embodiments of this application, includes multiple drain sub-regions and multiple drain avoidance sub-regions; wherein, the multiple drain sub-regions and multiple drain avoidance sub-regions are distributed crosswise in the second direction.

[0094] The embodiments of this application do not limit the manner in which the multiple drain sub-regions and multiple drain avoidance sub-regions are distributed in a cross direction, including but not limited to a first cross distribution method or a second cross distribution method. For example, in the first cross distribution method, each drain sub-region in the multiple drain sub-regions is located between two drain avoidance sub-regions; optionally, in the second cross distribution method, each drain avoidance sub-region in the multiple drain avoidance sub-regions is located between two drain regions.

[0095] Taking the first cross-distribution method as an example, such as Figure 9 As shown, the drain region 402 includes two drain sub-regions 4021 and three drain avoidance sub-regions 4022; wherein the two drain sub-regions 4021 and the three drain avoidance sub-regions 4022 are distributed crosswise in the second direction. Figure 9 The explanation will be based on the example of each of the two drain sub-regions 4021 being located between the two drain avoidance sub-regions 4022.

[0096] This application does not limit the number of drain sub-regions and drain avoidance sub-regions. Figure 9 The quantities shown are not intended to limit this application. For example, Figure 9 The drain region 4021 shown can also be two or more, ensuring that the source contacts in the source region 4031 and the drain contacts in the drain region 4021 are arranged with a projection interval in the first direction, and that the source contacts and drain contacts are arranged with a projection interval in the second direction. Optionally, Figure 9 The drain avoidance sub-region 4022 shown can also be three or more, as long as the drain avoidance sub-region 4022 and the drain sub-region 4021 are distributed in an overlapping manner in the second direction.

[0097] Taking the second cross-distribution method as an example, such as Figure 11 As shown, the drain region 402 includes three drain sub-regions 4021 and two drain avoidance sub-regions 4022; wherein the three drain sub-regions 4021 and the two drain avoidance sub-regions 4022 are distributed in a cross direction in the second direction. Figure 11 The explanation will be based on the example of each of the two drain avoidance sub-regions 4022 being located between the two drain sub-regions 4021.

[0098] This application does not limit the number of drain sub-regions and drain avoidance sub-regions. Figure 11 The quantities shown are not intended to limit this application. For example, Figure 11 The drain region 4021 shown can also be three or more, ensuring that the source contacts in the source region 4031 and the drain contacts in the drain region 4021 are arranged with a projection interval in the first direction, and that the source contacts and drain contacts are arranged with a projection interval in the second direction. Optionally, Figure 11 The drain avoidance sub-region 4022 shown can also be two or more, as long as the drain avoidance sub-region 4022 and the drain sub-region 4021 are distributed intersectingly in the second direction, and each drain avoidance sub-region 4022 is located between two drain sub-regions 4021.

[0099] For the third layout structure, in the clamped field-effect transistor provided in this application embodiment, the first electrode has multiple first clearance regions, and the contacts of the multiple first clearance regions and the first electrode are distributed crosswise in the second direction. The way in which the multiple first clearance regions and the contacts of the first electrode are distributed crosswise in the second direction includes, but is not limited to, each contact of the first electrode being located between two first clearance regions, or each first clearance region being located between two contacts of the first electrode.

[0100] Taking the first electrode as the drain of the target field-effect transistor and the first clearance region as the drain clearance region as an example, regarding the first crossover distribution method in the third layout structure, and... Figure 9 The layout structure shown corresponds to the clamping field-effect transistors as follows: Figure 10 As shown, the drain has three drain clearance regions 5210, and the contacts of each drain ( Figure 10 Not shown in the image, please refer to the following: Figure 9 The two drain regions 4021 shown are located between the two drain avoidance regions 5210. Figure 10 Taking the contacts of the three substrates as examples, namely substrate contacts 541, 542, and 543, substrate contacts 541, 542, and 543 are located in the drain avoidance region 5210, compared to Figure 2 or Figure 3 Compared to the method of setting substrate contacts in the peripheral substrate region 104 as shown, the transistor provided in this application embodiment has a smaller area.

[0101] This application does not limit the number of drain avoidance regions in its embodiments. Figure 10 The number of drain clearance regions 5210 shown is not intended to limit this application. For example, Figure 10 The number of drain clearance regions 5210 shown can also be three or more, as long as the contacts of the drain clearance regions 5210 and the first electrode are distributed crosswise in the second direction, and the contacts of each drain electrode are located between two drain clearance regions, that is, the contacts of each drain electrode are located between the contacts of the two substrates (see reference). Figure 9 (The relationship between the drain sub-region 4021 and the drain avoidance sub-region 4022 is shown).

[0102] Regarding the second cross-distribution pattern in the third type of map structure, and Figure 11 The layout structure shown corresponds to the clamping field-effect transistors as follows: Figure 12 As shown, the drain electrode has two drain clearance areas 5210, each drain clearance area 5210 being located at the contact point of the two drain electrodes. Figure 12 Not shown in the image, please refer to the following: Figure 11 The location is between the drain pole region 4021 shown in the diagram. Figure 11Taking the contacts of the two substrates as examples, namely substrate contacts 5211 and 5212, substrate contacts 5211 and 5212 are located in the drain avoidance region 5210, compared to Figure 2 or Figure 3 Compared to the method of setting substrate contacts in the peripheral substrate region 104 as shown, the transistor provided in this application embodiment has a smaller area.

[0103] This application does not limit the number of drain avoidance regions in its embodiments. Figure 12 The number of drain clearance regions 5210 shown is not intended to limit this application. For example, Figure 12 The number of drain clearance regions 5210 shown can also be two or more, as long as the contacts of the drain clearance regions 5210 and the first electrode are distributed intersectingly in the second direction, and each drain clearance region 5210 is located between the contacts of two drain electrodes, that is, the contacts of each substrate are located between the contacts of two drain electrodes (see reference). Figure 11 (The positional relationship between the drain sub-region 4021 and the drain avoidance sub-region 4022 is shown).

[0104] The fourth layout structure, in the layout structure provided in the embodiments of this application, the source pole region includes at least one source pole sub-region and multiple source pole avoidance sub-regions; wherein, the multiple source pole avoidance sub-regions are located on both sides of at least one source pole sub-region in the second direction.

[0105] like Figure 13 As shown, taking the source region 403 as an example, which includes two source sub-regions 4031 and two source avoidance sub-regions 4032, the two source sub-regions 4031 are located between the two source avoidance sub-regions 4032, that is, the two source avoidance sub-regions 4032 are located on both sides of the two source sub-regions 4031 in the second direction.

[0106] This application does not limit the number of source pole regions and source pole avoidance regions in its embodiments. Figure 13 The quantities shown are not intended to limit this application. For example, Figure 13 The source region 4031 shown can be one or more, ensuring that the contacts of the drain electrode in the drain region 4021 and the contacts of the source electrode in the source region 4031 are arranged with a projection interval in the first direction, and that the contacts of the source electrode and the contacts of the drain electrode are arranged with a projection interval in the second direction. Optionally, Figure 13 The source pole avoidance sub-region 4032 shown can also be two or more, and it does not need to be set symmetrically. That is, the number of source pole avoidance sub-regions 4032 located on both sides of the source pole sub-region 4031 can be different, as long as the source pole avoidance sub-regions 4032 are located on both sides of all source pole sub-regions 4031 in the second direction.

[0107] For the fourth layout structure, in the clamped field-effect transistor corresponding to the fourth layout structure provided in the embodiments of this application, the first electrode has multiple first clearance regions, and the multiple first clearance regions are located on both sides of the contact of the first electrode in the second direction. Taking the first electrode as the source of the target field-effect transistor and the first clearance region as the source clearance region as an example, as follows... Figure 14 The clamped field-effect transistor shown has the following structure: taking a source electrode with two source clearance regions 5110 as an example, the substrate contacts 5111 and 5112 are located in the source clearance regions 5110, and the source clearance regions 5110 are located in the second direction at the source contacts ( Figure 14 Not shown in the image, see reference. Figure 13 On either side of the location of the two source pole regions 4031. Compared to Figure 2 or Figure 3 Compared to the method of setting substrate contacts in the peripheral substrate region 104 as shown, the transistor provided in this application embodiment has a smaller area.

[0108] This application does not limit the number of source avoidance regions in its embodiments. Figure 14 The number of source avoidance zones 5110 shown is not intended to limit this application; alternatively, Figure 14 The source avoidance area 5110 shown can also be two or more, and does not need to be symmetrically arranged. That is, the number of source avoidance areas 5110 located on both sides of the source contact can be different, as long as the source avoidance areas 5110 are located on both sides of all source contacts in the second direction (see Figure 13 (The positional relationship between source pole region 4031 and source pole avoidance region 4032 is shown).

[0109] The fifth layout structure, in the layout structure provided in the embodiments of this application, the source pole region includes multiple source pole sub-regions and at least one source pole avoidance sub-region; wherein, at least one source pole avoidance sub-region is located between two source pole sub-regions in the second direction.

[0110] like Figure 15 In the layout structure shown, the source region 403 includes two source sub-regions 4031 and one source avoidance sub-region 4032; wherein, the source avoidance sub-region 4032 is located between the two source sub-regions 4031 in the second direction.

[0111] This application does not limit the number of source pole regions and source pole avoidance regions in its embodiments. Figure 15 The quantities shown are not intended to limit this application. For example, Figure 15The source region 4031 shown can be two or more, and can be non-symmetrically arranged, as long as the contact of the drain electrode in the drain region 4021 and the contact of the source electrode in the source region 4031 are arranged with a projection interval in the first direction, and the contacts of the source electrode and the contact of the drain electrode are arranged with a projection interval in the second direction. Optionally, Figure 15 The source pole avoidance sub-region 4032 shown can also be more than one, as long as the source pole avoidance sub-region 4032 is located between two source pole sub-regions 4031 in the second direction, that is, the source pole sub-region 4031 is located on both sides of the source pole avoidance sub-region 4032.

[0112] For the fifth layout structure, in the clamped field-effect transistor provided in this application embodiment, the first electrode has at least one first clearance region, and the at least one first clearance region is located between the two contacts of the first electrode in the second direction. Taking the first electrode as the source of the target field-effect transistor and the first clearance region as the source clearance region as an example, as follows... Figure 16 The clamped field-effect transistor shown has a source clearance region 5110 at its source, which is located at the two contacts of the source in the second direction. Figure 16 Not shown in the image, see reference. Figure 15 The location of the source avoidance sub-region 4302 shown is between (e.g., the location of the source avoidance sub-region 4302). Figure 16 The substrate contact 5113 shown is located between the two contacts of the source electrode (reference). Figure 15 (The positional relationship between source pole region 4031 and source pole avoidance region 4032 is shown).

[0113] This application does not limit the number of source avoidance regions in its embodiments. Figure 16 The number of source avoidance zones 5110 shown is not intended to limit this application; alternatively, Figure 16 The source avoidance area 5110 shown can also be two or more, as long as the source avoidance area 5110 is located between the two contacts of the source in the second direction.

[0114] The sixth layout structure, in the layout structure provided in the embodiments of this application, the source pole region includes multiple source pole sub-regions and multiple source pole avoidance sub-regions; wherein, the multiple source pole sub-regions and multiple source pole avoidance sub-regions are distributed crosswise in the second direction.

[0115] The embodiments of this application do not limit the manner in which the multiple source pole regions and multiple source pole avoidance sub-regions are interleaved in the second direction, but include, but are not limited to, a third interleaved distribution or a fourth interleaved distribution. For example, in the third interleaved distribution, each source pole avoidance sub-region in the multiple source pole avoidance sub-regions is located between two source pole regions; alternatively, in the fourth interleaved distribution, each source pole region in the multiple source pole regions is located between two source pole avoidance sub-regions.

[0116] Taking the third cross distribution as an example, such as Figure 17 As shown, the source region 403 includes three source sub-regions 4031 and two source avoidance sub-regions 4032; wherein, the three source sub-regions 4031 and the two source avoidance sub-regions 4032 are distributed intersectingly in the second direction. Figure 17 As shown, each of the multiple source avoidance sub-regions 4032 is located between two source sub-regions 4031.

[0117] This application does not limit the number of source pole regions and source pole avoidance regions in its embodiments. Figure 17 The quantities shown are not intended to limit this application. For example, Figure 17 The source region 4031 shown can also be three or more, ensuring that the contacts of the drain electrode in the drain region 4021 and the contacts of the source electrode in the source region 4031 are arranged with a projection interval in the first direction, and that the contacts of the source electrode and the contacts of the drain electrode are arranged with a projection interval in the second direction. Optionally, Figure 17 The source pole avoidance sub-region 4032 shown can also be two or more, as long as the source pole avoidance sub-region 4032 and the source pole sub-region 4031 are intersected in the second direction, and each source pole avoidance sub-region 4032 is located between two source pole sub-regions 4031.

[0118] The sixth type of map structure, besides such as Figure 17 In addition to the methods shown, it is also possible to... Figure 19 The layout structure shown is still based on the example of the source pole including three source pole sub-regions 4031 and two source pole avoidance sub-regions 4032, with each source pole avoidance sub-region 4032 located between two source pole sub-regions 4031.

[0119] Taking the fourth cross distribution as an example, such as Figure 21 As shown, the source region 403 includes three source avoidance sub-regions 4032 and two source sub-regions 4031; wherein, the three source avoidance sub-regions 4032 and the two source sub-regions 4031 are distributed intersectingly in the second direction. Figure 21 The explanation will be based on the example of each of the two source pole regions 4031 being located between two source pole avoidance regions 4032.

[0120] This application does not limit the number of source pole regions and source pole avoidance regions in its embodiments. Figure 21 The number of source pole sub-regions 4031 and source pole avoidance sub-regions 4032 shown is not intended to limit this application. For example, Figure 21 The source region 4031 shown can also be two or more, ensuring that the contacts of the drain electrode in the drain region 4021 and the contacts of the source electrode in the source region 4031 are arranged with a projection interval in the first direction, and that the contacts of the source electrode and the contacts of the drain electrode are arranged with a projection interval in the second direction. Optionally, Figure 21 The source pole avoidance sub-region 4032 shown can also be three or more, as long as the source pole avoidance sub-region 4032 and the source pole sub-region 4031 are intersected in the second direction, and each source pole sub-region 4031 is located between two source pole avoidance sub-regions 4032.

[0121] For the sixth layout structure, in the clamped field-effect transistor provided in this application embodiment, the first electrode has multiple first clearance regions, and the contacts of the multiple first clearance regions and the first electrode are distributed crosswise in the second direction. The way in which the multiple first clearance regions and the contacts of the first electrode are distributed crosswise in the second direction includes, but is not limited to, each contact of the first electrode being located between two first clearance regions, or each first clearance region being located between two contacts of the first electrode.

[0122] Taking the first electrode as the source of the target field-effect transistor and the first clearance region as the source clearance region as an example, regarding the third cross-distribution method in the sixth layout structure, and... Figure 17 The layout structure shown corresponds to the clamping field-effect transistors as follows: Figure 18 As shown, the source electrode has two source electrode clearance regions 5110, each source electrode clearance region 5110 being located at the contact point of the two source electrodes ( Figure 18 Not shown in the image, please refer to the following: Figure 17 The location of the source pole region 4031 shown can be referenced. Figure 17 The positional relationship between source pole region 4031 and source pole avoidance region 4032 is shown. Regarding the third cross-distribution mode in the sixth layout structure, and... Figure 19 The layout structure shown corresponds to the clamping field-effect transistors as follows: Figure 20 As shown, the source electrode has two source electrode clearance regions 5110, each source electrode clearance region 5110 being located at the contact point of the two source electrodes ( Figure 20 Not shown in the image, please refer to the following: Figure 19 The location of the source pole region 4031 shown can be referenced. Figure 19 The positional relationship between the source pole region 4031 and the source pole avoidance region 4032 is shown.

[0123] Figure 18 and Figure 20 Taking the contacts of the two substrates as examples, namely substrate contacts 5111 and 5112, substrate contacts 5111 and 5112 are located in the source avoidance region 5110, compared to Figure 2 or Figure 3 Compared to the method of setting substrate contacts in the peripheral substrate region 104 as shown, the transistor provided in this application embodiment has a smaller area.

[0124] This application does not limit the number of source avoidance regions in its embodiments. Figure 18 and Figure 20 The number of source avoidance regions 5110 shown is not intended to limit this application. For example, Figure 18 and Figure 20 The number of source avoidance regions 5110 shown can also be two or more, as long as the contacts of the source avoidance regions 5110 and the source electrodes are distributed crosswise in the second direction, and each source avoidance region 5110 is located between the contacts of two source electrodes, that is, the contacts of each substrate are located between the contacts of two source electrodes. (Refer to [reference needed]). Figure 17 or Figure 19 The positional relationship between the source pole region 4031 and the source pole avoidance region 4032 is shown.

[0125] Taking the first electrode as the source of the target field-effect transistor and the first clearance region as the source clearance region as an example, regarding the fourth cross-distribution method in the sixth layout structure, and... Figure 21 The layout structure shown corresponds to the clamping field-effect transistors as follows: Figure 22 As shown, the source electrode has three source electrode clearance regions 5110, and the contact of each source electrode ( Figure 22 Not shown in the image, please refer to the following: Figure 21 The location of the source pole region 4031 shown is situated between the two source pole avoidance zones 5110, which can be referenced. Figure 21 The positional relationship between the source pole region 4031 and the source pole avoidance region 4032 is shown.

[0126] Figure 22 Taking the contacts of the three substrates as examples, namely substrate contacts 5111, 5112, and 5113, the substrate contacts 5111, 5112, and 5113 are located in the source avoidance region 5110, compared to Figure 2 or Figure 3 Compared to the method of setting substrate contacts in the peripheral substrate region 104 as shown, the transistor provided in this application embodiment has a smaller area.

[0127] This application does not limit the number of source avoidance regions in its embodiments. Figure 22 The number of source clearance regions 5110 shown is not intended to limit this application. For example, Figure 22The number of source avoidance regions 5110 shown can also be three or more, as long as the contacts of the source avoidance regions 5110 and the source are distributed crosswise in the second direction, and the contacts of each source are located between two source avoidance regions 5110, that is, the contacts of each source are located between the contacts of the two substrates. (Refer to [reference needed]). Figure 21 The positional relationship between the source pole region 4031 and the source pole avoidance region 4032 is shown.

[0128] In one possible implementation, in addition to the first clearance region being present at the first electrode of the target field-effect transistor, the target field-effect transistor provided in this application may also have a second clearance region at its second electrode, with a portion of the substrate contacts located in the first clearance region and another portion of the substrate contacts located in the second clearance region. The second electrode is either the source or drain of the target field-effect transistor, and it differs from the first electrode. If the first electrode is the source of the target field-effect transistor, then the second electrode is the drain; conversely, if the first electrode is the drain, then the second electrode is the source. The target field-effect transistor can be either a first field-effect transistor or a second field-effect transistor.

[0129] For the case where the source of the target field-effect transistor has a source avoidance region and the drain has a drain avoidance region, the setting method of the drain avoidance region can refer to the setting method of the drain avoidance sub-region in any of the first to third layout structures mentioned above, or refer to the setting method of the drain avoidance region in the structure of the field-effect transistor corresponding to any of the first to third layout structures. The setting method of the source avoidance region can refer to the setting method of the source avoidance sub-region in any of the fourth to sixth layout structures mentioned above, or refer to the setting method of the source avoidance region in the structure of the field-effect transistor corresponding to any of the fourth to sixth layout structures. In other words, the setting method of the drain avoidance sub-region in any of the first to third layout structures can be combined with the setting method of the source avoidance sub-region in any of the fourth to sixth layout structures, ensuring that the projections of the source contacts and the drain contacts in the first direction and the second direction are arranged at intervals.

[0130] To facilitate understanding, the following examples will be used to illustrate the layout structures from the seventh to the twelfth type and their corresponding transistor structures.

[0131] The seventh layout structure includes a drain region comprising at least one drain sub-region and multiple drain avoidance sub-regions, with the multiple drain avoidance sub-regions located on either side of the at least one drain sub-region in a second direction. The source region comprises multiple source sub-regions and multiple source avoidance sub-regions, which are interleaved in a second direction, with each source avoidance sub-region located between two source sub-regions.

[0132] This seventh type of map structure can be as follows: Figure 23 As shown, the seventh layout structure provided in this application embodiment is a combination of the drain avoidance sub-region in the first layout structure and the source avoidance sub-region in the third cross distribution mode of the sixth layout structure, that is... Figure 5 The drain avoidance sub-region 4022 shown is Figure 17 The combination of source pole avoidance sub-region 4032 shown. Figure 23 The number of source avoidance sub-regions 4032 and drain avoidance sub-regions 4022 is shown as an example, but is not limited thereto. The number of drain avoidance sub-regions 4022 and source avoidance sub-regions 4032 can also be two or more, as long as the projections of the source contacts and drain contacts in the first direction and the projections in the second direction are arranged at intervals.

[0133] In the clamped field-effect transistor corresponding to the seventh layout structure provided in this application embodiment, taking one of the first electrode and the second electrode as the drain of the target field-effect transistor and the other as the source of the target field-effect transistor, and taking one of the first clearance region and the second clearance region as the drain clearance region and the other as the source clearance region as an example, multiple drain clearance regions are located on both sides of the drain contact in the second direction, and each of the multiple source clearance regions is located between the two contacts of the source.

[0134] The clamping field-effect transistor corresponding to the seventh layout structure is as follows: Figure 24 The diagram shows a combination of the drain clearance region in a clamped field-effect transistor corresponding to the first layout structure and the source clearance region in a clamped field-effect transistor corresponding to the third cross-distribution method in the sixth layout structure. Figure 6 The drain clearance area 5210 shown is... Figure 18 The combination of source pole avoidance zone 5110 shown. Figure 24 The number of source avoidance region 5110 and drain avoidance region 5210 is shown as an example, but is not limited thereto. The number of drain avoidance region 5210 and source avoidance region 5110 can also be two or more, as long as the projections of the source contact and the drain contact in the first direction and the projections in the second direction are arranged at intervals.

[0135] The eighth layout structure includes a drain region comprising multiple drain sub-regions and at least one drain-avoiding sub-region, with the at least one drain-avoiding sub-region located between two drain sub-regions in the second direction. The source region comprises multiple source sub-regions and multiple source-avoiding sub-regions, which are interleaved in the second direction, with each source-avoiding sub-region located between two source sub-regions.

[0136] This eighth type of map structure can be as follows: Figure 25 As shown, the eighth layout structure provided in this application embodiment is a combination of the drain avoidance sub-region in the second layout structure and the source avoidance sub-region in the third cross distribution mode of the sixth layout structure, that is... Figure 7 The drain avoidance sub-region 4022 shown is Figure 17 The combination of source pole avoidance sub-region 4032 shown. Figure 25 The number of source avoidance sub-regions 4022 and drain avoidance sub-regions 4032 is shown as an example, but is not limited thereto. The number of drain avoidance sub-regions 4022 and source avoidance sub-regions 4032 can also be two or more, as long as the projections of the source contacts and drain contacts in the first direction and the projections in the second direction are arranged at intervals.

[0137] In the clamped field-effect transistor corresponding to the eighth layout structure provided in this application embodiment, taking one of the first electrode and the second electrode as the drain of the target field-effect transistor and the other as the source of the target field-effect transistor, and taking one of the first clearance region and the second clearance region as the drain clearance region and the other as the source clearance region as an example, at least one drain clearance region is located between the two contacts of the drain in the second direction, and each of the multiple source clearance regions is located between the two contacts of the source.

[0138] The clamping field-effect transistor corresponding to the eighth layout structure is as follows: Figure 26 The diagram shows a combination of the drain clearance region in a clamped field-effect transistor corresponding to the second layout structure and the source clearance region in a clamped field-effect transistor corresponding to the third cross-distribution method in the sixth layout structure. Figure 8 The drain clearance area 5210 shown is... Figure 18 The combination of source pole avoidance zone 5110 shown. Figure 26 The number of source avoidance region 5110 and drain avoidance region 5210 is shown as an example, but is not limited thereto. The number of drain avoidance region 5210 and source avoidance region 5110 can also be two or more, as long as the projections of the source contact and the drain contact in the first direction and the projections in the second direction are arranged at intervals.

[0139] The ninth layout structure includes multiple drain sub-regions and multiple drain avoidance sub-regions in the drain region. These drain sub-regions and drain avoidance sub-regions are interleaved in the second direction, with each drain sub-region located between two drain avoidance sub-regions. Similarly, the source region includes multiple source sub-regions and multiple source avoidance sub-regions, which are also interleaved in the second direction, with each source avoidance sub-region located between two source sub-regions.

[0140] This ninth type of map structure can be as follows: Figure 27 As shown, the ninth layout structure provided in this application embodiment is a combination of the drain avoidance sub-region in the first cross-distribution mode of the third layout structure and the source avoidance sub-region in the third cross-distribution mode of the sixth layout structure, that is... Figure 9 The drain avoidance sub-region 4022 shown is Figure 17 The combination of source pole avoidance sub-region 4032 shown. Figure 27 The number of source avoidance sub-regions 4032 and drain avoidance sub-regions 4022 is shown as an example, but is not limited thereto. The number of drain avoidance sub-regions 4022 and source avoidance sub-regions 4032 can also be two or more, as long as the projections of the source contacts and drain contacts in the first direction and the projections in the second direction are arranged at intervals.

[0141] In the clamped field-effect transistor corresponding to the ninth layout structure provided in this application embodiment, taking one of the first electrode and the second electrode as the drain of the target field-effect transistor and the other as the source of the target field-effect transistor, and taking one of the first clearance region and the second clearance region as the drain clearance region and the other as the source clearance region as an example, the contact of each drain electrode is located between the two drain clearance regions in the second direction, and each of the multiple source clearance regions is located between the two contacts of the source electrode.

[0142] The clamping field-effect transistor corresponding to the ninth layout structure is as follows: Figure 28 The diagram shows a combination of the drain avoidance region in a clamped field-effect transistor corresponding to the first cross-distribution method of the third layout structure and the source avoidance region in a clamped field-effect transistor corresponding to the third cross-distribution method of the sixth layout structure. Figure 10 The drain clearance area 5210 shown is... Figure 18 The combination of source pole avoidance zone 5110 shown. Figure 28The number of source avoidance region 5110 and drain avoidance region 5210 is shown as an example, but is not limited thereto. The number of drain avoidance region 5210 and source avoidance region 5110 can also be two or more, as long as the projections of the source contact and the drain contact in the first direction and the projections in the second direction are arranged at intervals.

[0143] The tenth layout structure includes a drain region comprising multiple drain sub-regions and multiple drain avoidance sub-regions, which are interleaved in a second direction. The interleaving arrangement is such that each drain avoidance sub-region is located between two drain sub-regions. The source region comprises multiple source sub-regions and at least one source avoidance sub-region, which is located between two source sub-regions in a second direction.

[0144] This tenth type of map structure can be as follows: Figure 29 As shown, the tenth layout structure provided in this application embodiment is a combination of the drain avoidance sub-region in the second cross distribution mode of the third layout structure and the source avoidance sub-region in the fifth layout structure, that is... Figure 11 The drain avoidance sub-region 4022 shown is Figure 15 The combination of source pole avoidance sub-region 4032 shown. Figure 29 The number of source avoidance sub-regions 4032 and drain avoidance sub-regions 4022 is shown as an example, but is not limited thereto. The number of drain avoidance sub-regions 4022 and source avoidance sub-regions 4032 can also be two or more, as long as the projections of the source contacts and drain contacts in the first direction and the projections in the second direction are arranged at intervals.

[0145] In the clamped field-effect transistor corresponding to the tenth layout structure provided in the embodiments of this application, taking one of the first electrode and the second electrode as the drain of the target field-effect transistor and the other as the source of the target field-effect transistor, and taking one of the first clearance region and the second clearance region as the drain clearance region and the other as the source clearance region as an example, each drain clearance region is located between the contacts of the two drain electrodes in the second direction, and at least one source clearance region is located between the two contacts of the source electrode.

[0146] The clamping field-effect transistor corresponding to the tenth layout structure is as follows: Figure 30 The diagram shows a combination of the drain clearance region in a clamped field-effect transistor corresponding to the second cross-distribution method of the third layout structure and the source clearance region in a clamped field-effect transistor corresponding to the fifth layout structure. Figure 12 The drain clearance area 5210 shown is... Figure 16 The combination of source pole avoidance zone 5110 shown. Figure 30The number of source avoidance region 5110 and drain avoidance region 5210 is shown as an example, but is not limited thereto. The number of drain avoidance region 5210 and source avoidance region 5110 can also be two or more, as long as the projections of the source contact and the drain contact in the first direction and the projections in the second direction are arranged at intervals.

[0147] The eleventh layout structure includes a drain region comprising multiple drain sub-regions and multiple drain avoidance sub-regions. These drain sub-regions and drain avoidance sub-regions are interleaved in the second direction, with each drain avoidance sub-region located between two drain sub-regions. The source has multiple source avoidance regions, located on either side of the source contact in the second direction.

[0148] The eleventh type of map structure can be as follows: Figure 31 As shown, the eleventh layout structure provided in this application embodiment is a combination of the drain avoidance sub-region in the second cross-distribution mode of the third layout structure and the source avoidance sub-region in the fourth layout structure, that is... Figure 11 The drain avoidance sub-region 4022 shown is Figure 13 The combination of source pole avoidance sub-region 4032 shown. Figure 31 The number of source avoidance sub-regions 4032 and drain avoidance sub-regions 4022 is shown as an example, but is not limited thereto. The number of drain avoidance sub-regions 4022 and source avoidance sub-regions 4032 can also be two or more, as long as the projections of the source contacts and drain contacts in the first direction and the projections in the second direction are arranged at intervals.

[0149] In the clamped field-effect transistor corresponding to the eleventh layout structure provided in this application embodiment, taking one of the first electrode and the second electrode as the drain of the target field-effect transistor and the other as the source of the target field-effect transistor, and taking one of the first clearance region and the second clearance region as the drain clearance region and the other as the source clearance region as an example, each drain clearance region is located between the contacts of the two drain electrodes in the second direction, and multiple source clearance regions are located on both sides of the contacts of the source electrodes.

[0150] The clamping field-effect transistor corresponding to the eleventh layout structure is as follows: Figure 32 The diagram shows a combination of the drain clearance region in a clamped field-effect transistor corresponding to the second cross-distribution method of the third layout structure and the source clearance region in a clamped field-effect transistor corresponding to the fourth layout structure. Figure 12 The drain clearance area 5210 shown is... Figure 14 The combination of source pole avoidance zone 5110 shown. Figure 32The number of source avoidance region 5110 and drain avoidance region 5210 is shown as an example, but is not limited thereto. The number of drain avoidance region 5210 and source avoidance region 5110 can also be two or more, as long as the projections of the source contact and the drain contact in the first direction and the projections in the second direction are arranged at intervals.

[0151] The twelfth layout structure includes a drain region comprising multiple drain sub-regions and multiple drain avoidance sub-regions. These drain sub-regions and drain avoidance sub-regions are interleaved in a second direction, with each drain avoidance sub-region located between two drain sub-regions. Similarly, the source region comprises multiple source sub-regions and multiple source avoidance sub-regions. These source sub-regions and source avoidance sub-regions are interleaved in a second direction, with each source sub-region located between two source avoidance sub-regions.

[0152] This twelfth type of map structure can be as follows: Figure 33 As shown, the twelfth layout structure provided in this application embodiment is a combination of the drain avoidance sub-region in the second cross distribution mode of the third layout structure and the source avoidance sub-region in the second quad cross distribution mode of the sixth layout structure, that is... Figure 11 The drain avoidance sub-region 4022 shown is Figure 21 The combination of source pole avoidance sub-region 4032 shown. Figure 33 The number of source avoidance sub-regions 4032 and drain avoidance sub-regions 4022 is shown as an example, but is not limited thereto. The number of drain avoidance sub-regions 4022 and source avoidance sub-regions 4032 can also be two or more, as long as the projections of the source contacts and drain contacts in the first direction and the projections in the second direction are arranged at intervals.

[0153] In the clamped field-effect transistor corresponding to the twelfth layout structure provided in the embodiments of this application, taking one of the first electrode and the second electrode as the drain of the target field-effect transistor and the other as the source of the target field-effect transistor, and taking one of the first clearance region and the second clearance region as the drain clearance region and the other as the source clearance region as an example, each drain clearance region is located between the contacts of the two drain electrodes in the second direction, and each source electrode contact is located between the two source clearance regions.

[0154] The clamping field-effect transistor corresponding to the twelfth layout structure is as follows: Figure 34 The diagram shows a combination of the drain clearance region in a clamped field-effect transistor corresponding to the second cross-distribution method of the third layout structure and the source clearance region in a clamped field-effect transistor corresponding to the fourth cross-distribution method of the sixth layout structure. Figure 12 The drain clearance area 5210 shown is... Figure 22The combination of source pole avoidance zone 5110 shown. Figure 34 The number of source avoidance region 5110 and drain avoidance region 5210 is shown as an example, but is not limited thereto. The number of drain avoidance region 5210 and source avoidance region 5110 can also be two or more, as long as the projections of the source contact and the drain contact in the first direction and the projections in the second direction are arranged at intervals.

[0155] In the above Figures 23-34 In the layout or transistor structure shown, since both the source and drain have clearance areas for arranging substrate contacts, the space of the substrate contact area is increased, making the substrate area more uniform and improving the discharge capability.

[0156] Exemplarily, the layout structure of the transistor provided in the embodiments of this application, and Figure 1 as well as Figure 2 Compared to the transistor layout shown, different transistors have different holding voltages; see [reference needed]. Figure 35 The diagram shows the sustaining voltage of a transistor. V indicates voltage, I indicates current, core BV / Vt is the circuit breakdown voltage, VDD is the power supply voltage, and ESD spec (3kV~2A) indicates the ESD discharge specification voltage and current. It2 is the ESD operating current. During ESD discharge, It2 must meet certain rules (e.g., greater than 2A at 3kV) and less than core BV (core Vt1) to prevent internal circuit conduction during ESD discharge. Figure 35 (A) in the middle is Figure 1 The transistor shown has a sustaining voltage Vh that is below the supply voltage. Figure 35 (B) in the middle is Figure 2 The transistor shown corresponds to a sustaining voltage Vh, which is above the supply voltage, but... Figure 2 The transistor shown has a relatively large area. Figure 35 In the example, (C) represents the sustaining voltage Vh corresponding to the transistor shown in the embodiment of this application. The sustaining voltage Vh is above the power supply voltage, and the transistor has a small area. Figure 35 (D) in the middle is related to Figure 35 The comparison diagrams of (A), (B), and (C) in the figure, Vh1 corresponds to Figure 2 Vh2 corresponds to Figure 3 Vh3 corresponds to the embodiment of this application, and the voltage gradually increases from Vh1, Vh2 to Vh3.

[0157] It should be noted that the transistor layout structure provided in this application is applicable not only to NMOS but also to PMOS.

[0158] In summary, the transistor layout structure provided in this application increases the distance between the source and drain by staggering the source contacts and drain contacts, thereby improving the transistor's sustaining voltage without increasing the transistor area. Furthermore, by inserting the substrate region between the source and drain regions, the transistor area is further reduced. Because the source region has an interdigitated structure, the recessed structures between adjacent source sub-regions are periodically arranged, i.e., the substrate region is periodically arranged, thereby improving the transistor's uniform triggering capability.

[0159] This application provides a clamping circuit, which includes any of the clamping field-effect transistors provided in this application. The clamping field-effect transistor is used to discharge the current in the clamping circuit.

[0160] This application provides a chip that includes any of the clamped field-effect transistors provided in the embodiments of this application. This application does not limit the type of device using this chip; for example, the device can be a terminal or a server. The terminal can be a PC (Personal Computer), mobile phone, smartphone, PDA (Personal Digital Assistant), wearable device, PPC (Pocket PC), tablet computer, smart car system, smart TV, smart speaker, etc. The server can be a single server, a server cluster consisting of multiple servers, or a cloud computing service center.

[0161] This application provides an electrostatic discharge device, which includes the clamping circuit provided in the above-described embodiment.

[0162] It should be understood that "multiple" as used in this article refers to two or more.

[0163] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A clamping field-effect transistor, characterized in that, The clamping field-effect transistor is used in a clamping circuit, and the clamping field-effect transistor includes a first field-effect transistor and a second field-effect transistor arranged side by side along a first direction. Both the first field-effect transistor and the second field-effect transistor include a substrate and a source, a gate, and a drain located on one side of the substrate and distributed along the first direction. The projections of the contacts of the source and the drain in the first direction and in the second direction are arranged at intervals, and the second direction is perpendicular to the first direction. The first electrode of the target field-effect transistor has a first clearance region for configuring contacts of the substrate. At least a portion of the contacts of the substrate are located in the first clearance region. The first electrode is the source or drain of the target field-effect transistor. The target field-effect transistor is at least one of the first field-effect transistor or the second field-effect transistor.

2. The clamping field-effect transistor according to claim 1, characterized in that, The first electrode has a plurality of first clearance areas, which are located on both sides of the contact of the first electrode in the second direction.

3. The clamping field-effect transistor according to claim 1, characterized in that, The first electrode has at least one first clearance area, which is located between two contacts of the first electrode in the second direction.

4. The clamping field-effect transistor according to claim 1, characterized in that, The first electrode has a plurality of first clearance areas, and the plurality of first clearance areas and the contact points of the first electrode are distributed intersectingly in the second direction.

5. The clamping field-effect transistor according to claim 4, characterized in that, The contact of each first pole is located between two first clearance zones, or each first clearance zone is located between two contacts of the first pole.

6. The clamping field-effect transistor according to any one of claims 1-5, characterized in that, The second electrode of the target field-effect transistor has a second clearance region, a portion of the contacts of the substrate are located in the first clearance region, and another portion of the contacts of the substrate are located in the second clearance region. The second electrode is the source or drain of the target field-effect transistor, and the second electrode is different from the first electrode.

7. A transistor layout structure, characterized in that, The layout structure includes: a drain region for configuring a drain, a source region for configuring a source, a gate region for configuring a gate, and a substrate region for configuring a substrate, wherein the drain region, the source region, and the gate region are all located on one side of the substrate region and distributed along a first direction; The drain region includes a drain sub-region, which is used to configure the contacts of the drain. The source region includes a source sub-region, which is used to configure the contacts of the source. The contacts of the source and the contacts of the drain are arranged at intervals in the projection of the source and the contacts of the drain in the first direction, and are arranged at intervals in the projection of the source and the contacts of the drain in the second direction, which is perpendicular to the first direction. At least one of the drain region or the source region further includes a clearance sub-region for configuring contacts of the substrate.

8. The layout structure according to claim 7, characterized in that, The drain region includes at least one drain sub-region and multiple drain avoidance sub-regions; The plurality of drain avoidance sub-regions are located on both sides of the at least one drain sub-region in the second direction.

9. The layout structure according to claim 7, characterized in that, The drain region includes multiple drain sub-regions and at least one drain avoidance sub-region; Wherein, the at least one drain avoidance sub-region is located between two drain sub-regions in the second direction.

10. The layout structure according to claim 7, characterized in that, The drain region includes multiple drain sub-regions and multiple drain avoidance sub-regions; The plurality of drain sub-regions and the plurality of drain avoidance sub-regions are distributed in a cross pattern in the second direction.

11. The layout structure according to claim 10, characterized in that, Each of the plurality of drain sub-regions is located between two drain avoidance sub-regions; Alternatively, each of the plurality of drain avoidance sub-regions is located between two drain sub-regions.

12. The layout structure according to any one of claims 7-11, characterized in that, The source region includes at least one source sub-region and multiple source avoidance sub-regions; The plurality of source pole avoidance sub-regions are located on both sides of the at least one source pole sub-region in the second direction.

13. The layout structure according to any one of claims 7-11, characterized in that, The source region includes multiple source sub-regions and at least one source avoidance sub-region; Wherein, the at least one source pole avoidance sub-region is located between two source pole sub-regions in the second direction.

14. The layout structure according to any one of claims 7-11, characterized in that, The source region includes multiple source sub-regions and multiple source avoidance sub-regions; The plurality of source pole regions and the plurality of source pole avoidance regions are distributed intersectingly in the second direction.

15. The layout structure according to claim 14, characterized in that, Each of the plurality of source pole regions is located between two source pole avoidance regions; Alternatively, each of the plurality of source-avoiding sub-regions is located between two source-avoiding sub-regions.

16. A chip, characterized in that, The chip includes a clamping field-effect transistor as described in any one of claims 1-6.

17. A clamping circuit, characterized in that, The clamping circuit includes a clamping field-effect transistor as described in any one of claims 1-6, the clamping field-effect transistor being used to discharge current in the clamping circuit.

18. An electrostatic discharge device, characterized in that, The electrostatic discharge device includes the clamping circuit as described in claim 17.

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