High-voltage large-current SiC MOSFET chip and preparation process thereof

Abstract

The invention discloses a high-voltage large-current SiC MOSFET chip and a preparation process thereof, and relates to the technical field of electronic components. The chip comprises a substrate layer located at the bottommost layer, a double-gradient multi-buffer layer is formed on the upper surface of the substrate layer, an N-drift region is formed on the upper surface of the double-gradient multi-buffer layer, and a current expansion layer which is provided with a boss and used for gradient doping is formed on the upper surface of the N-drift region. The cellular regions are formed on the two sides of a boss of the gradient doping current expansion layer and comprise two cellular units which are symmetrically distributed left and right, each cellular unit comprises a P + base region, a P + region and an N + source region are formed on the P + base region, the gate structure is located on the upper surface of the boss, a gate is connected with the two N + source regions, and the gate is connected with the two N + source regions. The source electrodes are located on the two sides of the grid electrode and connected with the N + source region and the P + region on one side respectively, and the grid electrode is not connected with the source electrodes. The device has the advantages of being excellent in electrical performance, high in reliability, efficient in thermal management, good in consistency and the like.

Description

Technical Field

[0001] This invention relates to the field of electronic components technology, and in particular to a high-voltage, high-current SiC MOSFET chip and its fabrication process. Background Technology

[0002] With the rapid development of the new energy industry, the performance requirements of core components in power electronic systems are constantly increasing. Traditional silicon-based power devices, due to their narrow bandgap, low breakdown electric field, and other defects such as high on-resistance, poor high-temperature resistance, and low energy conversion efficiency, are difficult to meet the application requirements of high-voltage and high-current scenarios. For example, in the field of DC charging piles, the system conversion efficiency caused by silicon-based IGBTs is usually below 95%, and their large size and high heat dissipation costs limit the miniaturization and high efficiency development of charging piles.

[0003] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses advantages such as a large bandgap, high breakdown electric field, and high thermal conductivity. MOSFET devices based on SiC exhibit significant advantages in high-voltage, high-current, and high-temperature applications, making them a core alternative to silicon-based devices. Currently, 1200V-class SiC MOSFETs are gradually being applied in DC charging piles, SVG, and other fields. However, existing technologies still face the following key challenges:

[0004] Uneven electric field distribution and insufficient breakdown reliability: Existing SiC MOSFETs often employ uniform doping or single-gradient doping designs for their buffer layers. This leads to the electric field concentrating at the interfaces between the substrate and the buffer layer, and between the buffer layer and the drift region, during device operation. Excessively high local electric field peaks can easily trigger early breakdown, reducing the device's breakdown voltage reliability. For example, the peak electric field of a traditional single-buffer layer structure can reach over 1.8 MV / cm, far exceeding the material's safety threshold, resulting in a large breakdown voltage fluctuation range.

[0005] The challenge of balancing specific on-resistance and gate oxide reliability: To reduce specific on-resistance, existing technologies often increase the doping concentration of the current spreading layer or reduce the thickness of the drift region. However, high doping concentration leads to an enhanced electric field near the gate oxide, exacerbating the generation of gate oxide interface states. Meanwhile, traditional gate oxides often use a single SiO2 material, whose density of states at the SiC interface is as high as 1×10⁻⁶. 12 ~5×10 12 cm -2 eV -1 This results in low channel migration rates (typically below 100cm). 2 It has a low density ( / V·s) and is prone to gate oxide breakdown under high pressure or high temperature, resulting in poor reliability.

[0006] Weak surge protection: In applications such as DC charging piles, surge currents are generated when the system starts up or stops or the load changes suddenly. The current spread layer design of existing SiC MOSFETs is unreasonable, which causes the current to concentrate near the source bonding line, resulting in a sudden increase in local temperature and easy failures such as source metal melting and gate-source short circuit. In addition, the lack of an effective high-temperature protection structure on the device surface further exacerbates the risk of failure under surge impact.

[0007] Low thermal management efficiency: SiC MOSFETs generate a large amount of Joule heat when operating at high current. Existing heat sinks are mostly made of copper or aluminum, with a thermal conductivity of only 380-420 W·m. -1 ·K -1 Low heat dissipation efficiency leads to excessively high junction temperatures, which not only reduces device performance but also shortens its lifespan. Although diamond has extremely high thermal conductivity, the interfacial bonding between diamond and metal electrodes is poor, resulting in high thermal resistance and hindering practical applications.

[0008] Poor consistency of fabrication process: The existing annealing process after ion implantation lacks real-time monitoring methods, and the activation rate of doped ions fluctuates greatly, resulting in large dispersion of device parameters; at the same time, the deposition process of the gate dielectric layer (such as CVD) is difficult to precisely control the thickness and uniformity, which further reduces the yield of the device. Summary of the Invention

[0009] The technical problem to be solved by the present invention is how to provide a high-voltage, high-current SiC MOSFET chip with excellent electrical performance, high reliability, efficient thermal management and good consistency, and its fabrication process.

[0010] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a high-voltage, high-current SiC MOSFET chip, the chip comprising a substrate layer at the bottom layer, a double-gradient multi-buffer layer formed on the upper surface of the substrate layer, and an N-type multi-buffer layer formed on the upper surface of the double-gradient multi-buffer layer. - Drift region, the N - A gradient-doped current-spreading layer with protrusions is formed on the upper surface of the drift region. Cell regions are formed on both sides of the protrusions in the gradient-doped current-spreading layer, comprising two symmetrically distributed cell units. Each cell unit includes a P... + The base region, the P + A P is formed on the base region + Region and an N + In the source region, the gate structure is located on the upper surface of the boss, and the gate is connected to two N-type nodes. + The source region is connected, with the source located on both sides of the gate and connected to the N-terminal on one side. + Source region and P +The region is connected, and the gate is not connected to the source; the drain is located on the lower surface of the substrate, and the composite heat sink is attached to the bottom of the drain; the high-temperature barrier layer covers the drained portion between the source and the gate.

[0011] The beneficial effects of adopting the above technical solution are as follows: 1) Excellent electrical performance: device breakdown voltage ≥1250V, rated current ≥125A, conduction resistance ≤14mΩ, switching loss reduced by 30-40%, meeting the needs of high voltage and high current scenarios such as DC charging piles and SVG;

[0012] 2) High reliability: Gate oxide interface state density ≤ 5 × 10 11 cm -2 eV -1 Gate oxide breakdown field strength ≥10MV / cm, surge current withstand capability ≥250A (10ms), and device lifetime at 150℃ increased to 1×10 5 h or more;

[0013] 3) High-efficiency thermal management: Composite heat sink thermal conductivity ≥600W·m -1 ·K -1 The junction temperature of the device is ≤120℃ under rated current, and the heat dissipation efficiency is improved by more than 50%.

[0014] 4) Good fabrication consistency: Through in-situ monitored annealing, precise ALD deposition and other processes, the device parameter dispersion is ≤3%, and the yield is improved to over 90%;

[0015] 5) Controllable cost: It adopts mature CVD, ALD and other process equipment, without the need for special customized equipment, and reduces the total life cycle cost of the device by improving yield and reliability. Attached Figure Description

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0017] Figure 1 This is a schematic diagram of the chip structure described in an embodiment of the present invention;

[0018] Figure 2 This is a flowchart of the process described in the embodiments of the present invention;

[0019] The structure includes: 1. Substrate layer; 2. Dual-gradient multi-buffer layer; 3. N-drift region; 4. Current spread layer; 5. Cell region; 51. P+ region; 52. N+ source region; 53. P+ base region; 6. Gate structure; 7. Source; 8. Drain; 9. Composite heat sink; 10. High-temperature barrier layer. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0022] like Figure 1 As shown, this embodiment of the invention discloses a high-voltage, high-current SiC MOSFET chip. The chip includes a substrate layer 1 at the bottom layer, and the substrate layer 1 is an N-type substrate. + Type 4H-SiC substrate, crystal orientation is <0001> The doping concentration is 1×10 19 ~5×10 19 cm -3 The substrate has a thickness of 300–400 μm and a surface roughness ≤0.5 nm. A dual-gradient multi-buffer layer 2 is formed on the upper surface of the substrate 1. Further, the dual-gradient multi-buffer layer 2 comprises 3–5 layers extending from the substrate to N. - The buffer sublayers are stacked sequentially in the drift region direction. The doping concentration of each buffer sublayer increases linearly along the depth direction, and the concentration gradient coefficients of adjacent buffer sublayers are different. The concentration gradient coefficient is the rate of change of doping concentration with depth.

[0023] The total thickness of the dual-gradient multi-buffer layer 2 is 2–3 μm. Each buffer sublayer is N-type doped with nitrogen as the dopant. The initial doping concentration of the first buffer sublayer closest to the substrate is 1 × 10⁻⁶. 17 ~5×10 17 cm -3 The termination doping concentration is 5×10 17 ~1×10 17 cm -3 The termination doping concentration of the last buffer sublayer closest to the drift region is 1×10⁻⁶. 18 ~2×10 18 cm -3 .

[0024] The upper surface of the dual-gradient multi-buffer layer 2 is formed with N - Drift region 3, the N -A gradient-doped current spreading layer 4 with protrusions is formed on the upper surface of the drift region 3. Cell regions 5 are formed on both sides of the protrusions in the gradient-doped current spreading layer, comprising two symmetrically distributed cell units. Each cell unit includes a P... + Base region 53, the P + A P is formed on base region 53. + Zone 51 and an N + Source region 52, gate structure 6 is located on the upper surface of the boss, and gate 6 is connected to two N-type nodes. + The source region 52 is connected, and the source electrode 7 is located on both sides of the gate structure 6 and is connected to the N on one side respectively. + Source region 52 and P + Region 51 is connected, and the gate is not connected to the source 7;

[0025] Furthermore, the P + Region 51 was formed by Al ion implantation at an energy of 50–80 keV and an implantation dose of 1 × 10⁻⁶. 13 ~5×10 13 cm -2 The junction depth is 0.5–0.8 μm; the N + Source region 52 was formed by N ion implantation at an energy of 20–40 keV and an implantation dose of 1 × 10⁻⁶. 15 ~5×10 15 cm -2 The junction depth is 0.1–0.3 μm.

[0026] Furthermore, the gate structure 6 includes an interface passivation layer, a stacked gate dielectric layer, and a polysilicon gate, arranged sequentially from bottom to top. The interface passivation layer is a Si3N4 layer with a thickness of 3nm-8nm. The stacked gate dielectric layer is an Al2O3 / SiO2 / HfO2 three-layer composite structure, wherein the Al2O3 layer is close to the gradient doped current extension layer with a thickness of 4nm-8nm, the SiO2 layer is a transition layer with a thickness of 8nm-12nm, and the HfO2 layer is the top dielectric with a thickness of 12nm-20nm.

[0027] The drain electrode 8 is located on the lower surface of the substrate layer 1, and the composite heat sink 9 is attached below the drain electrode 8; the high-temperature resistant barrier layer 10 covers the drained portion between the source electrode 7 and the gate electrode 6. The composite heat sink 9 comprises a diamond base layer, a graphene nitride transition layer, and a metal particle filling layer stacked sequentially. The diamond base layer has a thickness of 50–100 μm and a thermal conductivity ≥1500 W·m. -1 ·K -1The nitrided graphene transition layer has a thickness of 5 nm to 10 nm and is grown on the surface of the diamond substrate by chemical vapor deposition. The metal particle filling layer is a composite layer formed by dispersing copper or silver particles in an organic binder, with a particle size of 50 to 200 nm, a filling volume fraction of 15% to 30%, and a thickness of 20 to 50 μm.

[0028] like Figure 2 As shown in the figure, this invention also discloses a fabrication process for a high-voltage, high-current SiC MOSFET chip, including the following steps:

[0029] S1, Substrate pretreatment:

[0030] Select N + The 4H-SiC substrate was sequentially ultrasonically cleaned with acetone for 15-20 min, ultrasonically cleaned with ethanol for 15-20 min, and rinsed with deionized water for 5-10 min. Then it was placed in RCA cleaning solution and immersed at 70-80℃ for 20-30 min to remove surface organic contaminants and metal impurities, forming an oxide layer with a thickness of 20-30 nm. After cooling, it was ready for use.

[0031] S2, dual-gradient multi-buffered layer growth:

[0032] A dual-gradient multi-buffer layer is grown on the pretreated substrate surface using a multi-step chemical vapor deposition (CVD) method, specifically including:

[0033] S21: Place the substrate in the CVD reaction chamber and evacuate to a pressure ≤1×10⁻⁶. -5 Pa, heat to 1500-1550℃, and introduce H2 gas for reduction treatment for 30-40 min, with an H2 flow rate of 50-100 sccm;

[0034] S22: Growth of the first buffer sublayer: Maintain the temperature at 1500-1550℃, introduce SiH4 gas at a flow rate of 10-20 sccm and NH3 gas at an initial flow rate of 5-10 sccm, which increases linearly with the growth time to 10-15 sccm, and the growth time is 30-40 min, forming a first buffer sublayer with a thickness of 0.6-0.8 μm, whose doping concentration increases linearly with depth.

[0035] S23: Sequentially grow the remaining buffer sublayers: Adjust the initial flow rate and flow rate increase rate of NH3 gas so that the concentration gradient coefficient of each buffer sublayer is different from the previous layer. Maintain the growth temperature at 1500-1550℃, the growth time of each layer is 20-30 min, and the total thickness reaches 2-3 μm to obtain a dual-gradient multi-buffer layer.

[0036] Furthermore, in step S2, the substrate support stage of the multi-step CVD reaction chamber is made of graphite material and coated with SiC coating to prevent the substrate from sticking to the support stage.

[0037] S3, epitaxial growth in the drift region:

[0038] N is grown on the surface of a dual-gradient multi-buffered layer using CVD. - The drift region was grown at a temperature of 1550–1600℃, a pressure of 50–100 mbar, a SiH3 flow rate of 20–30 sccm, an NH3 flow rate of 2–5 sccm, and a growth time of 2–3 h, forming a thickness of 8–12 μm and a doping concentration of 8 × 10⁻⁶. 15 ~1.2×10 18 cm -3 The drift zone;

[0039] S4, Fabrication of the gradient-doped current-spreading layer:

[0040] The gradient-doped current-extending layer is prepared by ion implantation combined with in-situ annealing, specifically including:

[0041] S41, Photoresist is coated on the surface of the drift region, and the current extension layer region is defined by photolithography;

[0042] S42 employs multi-energy stepwise N-ion implantation, with implantation energies of 10 keV, 20 keV, and 30 keV, corresponding to implantation doses of 5 × 10⁻⁶ kilovolts. 14 cm -2 3×10 14 cm -2 2×10 14 cm -2 This results in a gradient distribution of doping concentration that decreases exponentially;

[0043] S43 employs an in-situ Raman spectroscopy-monitored annealing process: the sample is placed in a rapid thermal annealing furnace with a heating rate of 50–100 °C / min, heated to 1600–1800 °C, and held for 30–60 min. The activation rate of N ions is monitored in real time using Raman spectroscopy. Annealing is stopped when the activation rate is ≥95%. After cooling, the photoresist is removed to obtain a gradient-doped current-extended layer. The characteristic peak monitored by Raman spectroscopy is the characteristic peak wavenumber of N ions in 4H-SiC at 796 cm⁻¹. -1 The activation rate is calculated by the change in the intensity of the characteristic peak.

[0044] S5, Cellular Production:

[0045] S51, P + Region fabrication: Photoresist is coated on the surface of the gradient doped current spreading layer, and photolithography is used to define P... +The base region pattern was created using Al ion implantation at an energy of 50–80 keV and a dose of 1 × 10⁻⁶. 13 ~5×10 13 cm -2 After implantation, annealing at 1700–1750℃ for 40–50 min activates Al ions, which are then placed in P... + Base region formation P + district;

[0046] S52, N + Source region preparation: in P + The base region surface is coated with photoresist, and photolithography defines N. + Source region pattern, using N ion implantation, implantation energy 20–40 keV, dose 1 × 10⁻⁶ 15 ~5×10 15 cm -2 After injection, annealing at 1650–1700℃ for 30–40 min activates N ions, which then react with P. + Base region forms N + Source region;

[0047] S6, Gate structure fabrication:

[0048] S61, Interfacial passivation layer deposition: Si3N4 interfacial passivation layer was deposited on the cell region and the surface of the gradient doped current extension layer by plasma-enhanced chemical vapor deposition (PECVD). The deposition temperature was 300-350℃, the pressure was 50-100Pa, the SiH4 flow rate was 10-15sccm, the NH3 flow rate was 20-30sccm, the deposition time was 10-15min, and the thickness was 3-8nm.

[0049] S62, Fabrication of the stacked gate dielectric layer: Al2O3 layer, SiO2 layer and HfO2 layer were deposited sequentially using atomic layer deposition (ALD) method:

[0050] Al2O3 layer: Trimethylaluminum (TMA) and H2O were used as precursors. The deposition temperature was 250–300℃, the pulse time was 0.1–0.2 s for TMA and 0.1–0.2 s for H2O, the purge time was 5–10 s, and the deposition thickness was 4–8 nm.

[0051] SiO2 layer: using tetraethoxysilane (TEOS) and O2 as precursors, deposition temperature 300-350℃, RF power 100-150W, deposition thickness 8-12nm;

[0052] HfO2 layer: using four-hafnium TDMAH and H2O as precursors, deposition temperature 250–300℃, pulse time TDMAH 0.2–0.3s, H2O 0.1–0.2s, purge time 5–10s, deposition thickness 12–20nm; during ALD deposition, the precursor pulse and purge time of each cycle are monitored in real time by a quartz crystal microbalance (QCM) to ensure that the thickness deviation of each dielectric layer is ≤5%;

[0053] S63, Polysilicon gate fabrication: A polysilicon layer is deposited by CVD at a deposition temperature of 600-650℃, a SiH4 flow rate of 20-30 sccm, and a deposition thickness of 150-200 nm. Then, photoresist is coated, and the gate pattern is defined by photolithography. The polysilicon layer and the stacked gate dielectric layer are etched by reactive ion etching (RIE) to obtain the polysilicon gate.

[0054] S7, metallization preparation:

[0055] S71, Source electrode fabrication: Ti, Ni, and Au layers were sequentially deposited using electron beam evaporation, with a deposition vacuum degree ≤5×10⁻⁶. -4 Pa, Ti layer deposition rate 0.5-1 nm / s, Ni layer 1-2 nm / s, Au layer 2-3 nm / s, then alloying treatment at 400-450℃ for 30-40 min to form the front electrode;

[0056] S72, Backside thinning and drain electrode preparation: The sample is flipped over and the backside of the substrate is thinned to a thickness of 100-150 μm using a diamond grinding wheel. Then, Ti layer, Ni layer and Ag layer are deposited sequentially. The deposition process is the same as that of the source electrode. The alloying temperature is 350-400℃ and the time is 20-30 min to form the drain electrode.

[0057] S8, Preparation and bonding of nitrided graphene / diamond composite heat sink:

[0058] S81, diamond substrate preparation: diamond sheets with a thickness of 50-100 μm were prepared by high temperature and high pressure method, and the surface was polished to a roughness of ≤0.2 nm;

[0059] S82, Graphene Nitride Transition Layer Growth: Graphene nitride was grown on the surface of a diamond substrate using plasma-enhanced CVD at a growth temperature of 800–900℃, a pressure of 10–20 Pa, a CH4 flow rate of 5–10 sccm and an N2 flow rate of 20–30 sccm, a radio frequency power of 200–300 W, and a growth time of 30–40 min, forming a graphene nitride transition layer with a thickness of 5–10 nm.

[0060] S83, Preparation of metal particle filling layer: Mix copper or silver particles with polyimide binder, coat the mixture onto the surface of nitrided graphene transition layer with a coating thickness of 20-50 μm, and cure at 200-250℃ for 1-2 h to obtain nitrided graphene / diamond composite heat sink.

[0061] S84, Heat sink bonding: Coat the drain surface with thermally conductive silver paste, bond the metal particle filling layer of the nitrided graphene / diamond composite heat sink with the thermally conductive silver paste, and cure under pressure of 5-10 MPa at 150-200℃ for 30-60 minutes to complete the heat sink bonding.

[0062] S9, High-Temperature Barrier Layer Coating: Tungsten particles, nano-Al2O3 particles, and polyetheretherketone powder are mixed in a specific ratio, and N-methylpyrrolidone (NMP) solvent is added. The mixture is stirred to form a uniform slurry, which is then coated onto the exposed surfaces of the front electrode and gate structure using a spin-coating method. The coating speed is 3000–5000 rpm, and the coating time is 30–60 s. The slurry is then cured at 300–350℃ for 2–3 h to form a high-temperature barrier layer with a thickness of 1–3 μm, resulting in a high-voltage, high-current SiC MOSFET chip. The solid content of the high-temperature barrier layer slurry is 40–60 wt%, and the viscosity is 500–1000 cP to ensure coating uniformity.

[0063] In this application, a multi-step CVD method is used for the dual-gradient multi-buffer layer. By precisely controlling the initial flow rate and flow rate increase rate of NH3 gas in each step, buffer sublayers with different concentration gradient coefficients are grown. For example, when growing the first buffer sublayer, the NH3 flow rate increases linearly from 5 sccm to 10 sccm, and when growing the second buffer sublayer, the NH3 flow rate increases linearly from 10 sccm to 20 sccm, ensuring the gradient coefficient of each layer is differentiated. Simultaneously, a graphite support stage (coated with SiC) is used to prevent substrate adhesion and improve the uniformity of the buffer layers.

[0064] The gradient doped current extension layer employs stepwise N-ion implantation at three energies of 10keV, 20keV, and 30keV to form an exponentially decaying concentration distribution. During annealing, the activation rate of N-ions (characteristic peak at 796 cm⁻¹) is monitored in real time using Raman spectroscopy. -1 (Regarding the intensity change), annealing is stopped when the activation rate is ≥95% to avoid crystal damage caused by over-annealing. This process reduces the fluctuation range of ion activation rate from ±5% to ±2%, significantly reducing the dispersion of device parameters.

[0065] The stacked gate dielectric is deposited using the ALD method, consisting of Al2O3, SiO2, and HfO2 layers. The growth rate of each layer is monitored in real-time using a QCM to ensure thickness deviation is ≤5%. For example, during Al2O3 layer deposition, the pulse duration of TMA and H2O is controlled at 0.1–0.2 s, and the purge time is 5–10 s to avoid precursor residue. During SiO2 layer deposition, TEOS and O2 are used as precursors, with an RF power of 100–150 W to improve film density.

[0066] The composite heat sink is fabricated using a diamond base layer prepared by a high-temperature, high-pressure method, followed by CVD growth of a graphene nitride transition layer, and then coating with a metal particle filler layer. Thermally conductive silver paste is used for bonding, and the mixture is cured at 150–200℃ and 5–10 MPa pressure to ensure good interfacial contact and reduce the interfacial thermal resistance to 5 × 10⁻⁶. -5 m 2 • Below K / W.

[0067] In the high-temperature resistant barrier layer, tungsten particles, nano-Al2O3 and polyetheretherketone are mixed in a certain proportion to prepare a slurry with a solid content of 40-60 wt% and a viscosity of 500-1000 cP. A spin-coating speed of 3000-5000 rpm is used to ensure uniform coating. The curing process is carried out by raising the temperature in stages (100℃ / 1h→200℃ / 1h→300℃ / 1h) to avoid the generation of bubbles and improve the density of the barrier layer.

Claims

1. A high voltage, high current SiC MOSFET chip, characterized by: The chip comprises a substrate layer (1) at the bottom, the upper surface of the substrate layer (1) is formed with a double gradient multi-buffer layer (2), the upper surface of the double gradient multi-buffer layer (2) is formed with an N - drift region (3), the upper surface of the N - drift region (3) is formed with a gradient-doped current spreading layer (4) with a boss, a cell region (5) is formed on both sides of the boss of the gradient-doped current spreading layer, and each cell unit comprises a P + base region (53), the P + base region (53) is formed with a P + region (51) and an N + source region (52), a gate structure (6) is located on the upper surface of the boss, the gate (6) is connected with the two N + source regions (52), and a source electrode (7) is located on both sides of the gate structure (6) and is connected with the N + source region (52) and the P + region (51) on one side, and the gate is not connected with the source electrode (7); a drain electrode (8) is located on the lower surface of the substrate layer (1), a composite heat sink (9) is attached below the drain electrode (8), and a high-temperature-resistant barrier layer (10) covers the leaked part between the source electrode (7) and the gate (6).

2. The high-voltage high-current SiC MOSFET chip of claim 1, wherein: The double-gradient multi-buffer layer (2) includes 3-5 buffer sub-layers stacked in sequence along the substrate layer to N - The buffer sub-layers are stacked in sequence along the drift region direction, the doping concentration of each buffer sub-layer increases linearly along the depth direction, and the concentration gradient coefficients of adjacent buffer sub-layers are different, the concentration gradient coefficient being a change rate of the doping concentration with the depth.

3. The high-voltage high-current SiC MOSFET chip of claim 1, wherein: The gate structure (6) comprises, from bottom to top, an interface passivation layer, a stacked gate dielectric layer and a polysilicon gate, the interface passivation layer is a Si3N4 layer with a thickness of 3-8 nm; the stacked gate dielectric layer is a three-layer composite structure of Al2O3 / SiO2 / HfO2, wherein the Al2O3 layer is close to the gradient-doped current spreading layer with a thickness of 4-8 nm, the SiO2 layer is a transition layer with a thickness of 8-12 nm, and the HfO2 layer is a top dielectric layer with a thickness of 12-20 nm.

4. The high-voltage high-current SiC MOSFET chip of claim 1, wherein: The composite heat sink (9) comprises a diamond base layer, a nitrogenated graphene transition layer and a metal particle filling layer which are stacked in sequence, the diamond base layer has a thickness of 50-100 μm and a thermal conductivity of ≥1500 W·m -1 ·K -1 The nitrogenated graphene transition layer has a thickness of 5-10 nm and is grown on the surface of the diamond base layer by chemical vapor deposition; and the metal particle filling layer is a composite layer formed by dispersing copper particles or silver particles in an organic binder, the particle size is 50-200 nm, the filling volume fraction is 15-30%, and the thickness is 20-50 μm.

5. The high-voltage high-current SiC MOSFET chip of claim 1, wherein: The substrate layer (1) is N + type 4H-SiC substrate, crystal orientation <0001>, doping concentration thickness 300-400 μm, surface roughness ≤0.5 nm.

6. The high-voltage high-current SiC MOSFET chip of claim 1, wherein: The total thickness of the dual-gradient multi-buffer layer (2) is 2-3 μm. Each buffer sublayer is N-type doped with nitrogen as the doping element. The initial doping concentration of the first buffer sublayer closest to the substrate is 1×10⁻⁶. 17 ~5×10 17 cm -3 The termination doping concentration is 5×10 17 ~1×10 17 cm -3 The termination doping concentration of the last buffer sublayer closest to the drift region is 1×10⁻⁶. 18 ~2×10 18 cm -3 .

7. The high-voltage high-current SiC MOSFET chip of claim 1, wherein: The P + The region (51) is formed by Al ion implantation with an implantation energy of 50-80 keV and an implantation dose of 1 x 10 13 ~ 5 x 10 13 cm -2 , and a junction depth of 0.5-0.8 μm; the N + The source region (52) is formed by N ion implantation with an implantation energy of 20-40 keV and an implantation dose of 1 x 10 15 ~ 5 x 10 15 cm -2 , and a junction depth of 0.1-0.3 μm.

8. A process for producing a high-voltage large-current SiC MOSFET chip according to any one of claims 1 to 7, characterized by, comprising the following steps: S1, substrate pretreatment; S2, double-gradient multi-buffer layer growth: using a multi-step chemical vapor deposition (CVD) method to grow a double-gradient multi-buffer layer on the surface of the pretreated substrate; S3, drift region epitaxial growth: N-type drift region is grown by CVD method on the double gradient multi-buffer layer surface - type drift region; S4, preparation of the gradient-doped current spreading layer: using ion implantation combined with in-situ annealing to prepare the gradient-doped current spreading layer; S5, cell region fabrication: in P + base region fabrication P + region and N + source region; S6, gate structure preparation; S7, metallization preparation: source electrode preparation and back thinning and drain electrode preparation; S8, preparation and bonding of graphene / diamond composite heat sink; S9, high-temperature-resistant barrier layer coating.

9. The fabrication process of high-voltage high-current SiC MOSFET chips according to claim 8, wherein: In step S2, the substrate support table of the multi-step CVD reaction chamber is made of graphite material, and the surface is coated with a SiC coating to prevent the substrate from sticking to the support table.

10. The process for preparing a high-voltage high-current SiC MOSFET chip according to claim 8, wherein: In step S9, the solid content of the high-temperature-resistant barrier layer slurry is 40-60 wt%, and the viscosity is 500-1000 cP, ensuring uniformity of coating.

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