Backside illumination image sensor fabrication method and backside illumination image sensor

Abstract

The present disclosure relates to a back-illuminated image sensor preparation method and a back-illuminated image sensor, and relates to the technical field of integrated circuits, comprising: providing a substrate, the substrate comprising a plurality of trench isolation portions spaced along a first direction; after forming a first layer on the back of the substrate, forming a plurality of first light-sensitive portions spaced along the first direction, extending along a second direction close to the substrate into the first layer; after forming a second layer covering the plurality of first light-sensitive portions, forming a plurality of second light-sensitive portions spaced along the first direction, extending along the second direction through the second layer, and extending into the first light-sensitive portions; after forming a third layer covering the plurality of second light-sensitive portions, forming a plurality of isolation columns spaced along the first direction, extending along the second direction through the third layer, the second layer, the first layer, and extending into the plurality of trench isolation portions. At least the electron concentration of the photosensitive area can be increased, and the photosensitive performance of the BSI image sensor can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a back-illuminated image sensor manufacturing method and a back-illuminated image sensor. BACKGROUND

[0002] A back-illuminated (BSI) image sensor is a type of image sensor, and has better performance than a front-illuminated image sensor in low light conditions.

[0003] However, the photosensitive performance of the BSI image sensor manufactured by the existing BSI image sensor manufacturing method cannot meet the actual demand, and therefore, how to improve the photosensitive performance of the BSI image sensor has become one of the technical problems that need to be solved at present. SUMMARY

[0004] Therefore, it is necessary to provide a back-illuminated image sensor manufacturing method and a back-illuminated image sensor to solve the technical problem of insufficient photosensitive performance of the BSI image sensor in the prior art.

[0005] In a first aspect, the present disclosure provides a back-illuminated image sensor manufacturing method, comprising:

[0006] providing a substrate, the substrate comprising a plurality of trench isolation portions spaced apart along a first direction, forming a first layer after forming a first layer on the back surface of the substrate, forming a plurality of first light-sensitive portions spaced apart along the first direction, extending along a second direction close to the substrate into the first layer;

[0007] forming a second layer covering the plurality of first light-sensitive portions, forming a plurality of second light-sensitive portions spaced apart along the first direction, extending along the second direction through the second layer, and extending into the first light-sensitive portion;

[0008] forming a third layer covering the plurality of second light-sensitive portions, forming a plurality of isolation columns spaced apart along the first direction, extending along the second direction through the third layer, the second layer, and the first layer, and extending into the plurality of trench isolation portions; the first layer, the second layer, and the third layer each comprise a target semiconductor layer; the first light-sensitive portion, the second light-sensitive portion, and the target semiconductor layer each comprise a different fifth main group element.

[0009] The backside illumination image sensor manufacturing method in the above embodiment forms a plurality of groove isolation portions spaced along a first direction in the substrate, and the first direction can be parallel to the back surface of the substrate; after forming the first stack including the target semiconductor layer on the back surface of the substrate, a plurality of first light sensitive portions spaced along the first direction and extending along a second direction close to the substrate into the first stack are formed, so that the target semiconductor layer of the first stack covers the bottom of the first light sensitive portion; after forming a second stack covering the plurality of first light sensitive portions, a plurality of second light sensitive portions spaced along the first direction and penetrating the second stack along the second direction and extending into the first light sensitive portion are formed, so that the target semiconductor layer of the second stack circumferentially surrounds the second light sensitive portion, and the top of the first light sensitive portion circumferentially surrounds and covers the bottom of the second light sensitive portion; after forming a third stack covering the plurality of second light sensitive portions, a plurality of isolation columns spaced along the first direction and penetrating the third stack, the second stack, the first stack along the second direction and extending to the top surface of the plurality of groove isolation portions are formed, so that the target semiconductor layer of the third stack covers and circumferentially surrounds the top of the second light sensitive portion, and the light sensitive stacks including the first light sensitive portion, the second light sensitive portion, the first stack covering the first light sensitive portion, the second stack surrounding the second light sensitive portion, and the third stack covering the second light sensitive portion are isolated by the isolation columns along the first direction. The first light sensitive portion, the second light sensitive portion, and the target semiconductor layer in the light sensitive stack respectively include different fifth main group elements. The light sensitive stack doped with different fifth main group elements generates a concentration gradient in the interior thereof after being excited by light. The transmission path of the photo-generated carrier is optimized by using the difference, the recombination rate in the diffusion process is reduced, and the quantum efficiency of the light sensitive stack based on the structure is effectively improved under the joint action of the two. In addition, the atomic mass of the fifth main group element is higher than that of silicon, and the mobility is low in epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing different doped fifth main group elements in multiple times can improve the uniformity of the doping concentration in the pixel area.

[0010] Further, the isolation columns and the groove isolation portions can jointly constitute target isolation portions, which can effectively avoid signal crosstalk between the light sensitive stacks adjacent along the first direction; and in the process of manufacturing the isolation columns, a plurality of light sensitive stacks spaced along the first direction are simultaneously manufactured, which effectively reduces the complexity and cost of the manufacturing process.

[0011] In some embodiments, the first light sensitive portion circumferentially surrounds and covers the bottom of the second light sensitive portion; and the third stack circumferentially surrounds and covers the top of the second light sensitive portion.

[0012] In some embodiments, the top surface of the groove isolation portion is located within the bottom surface of the isolation column.

[0013] In some embodiments, the first light sensitive portion includes a SiP layer; the second light sensitive portion includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

[0014] In some embodiments, the first stack includes a first target semiconductor layer, a first dielectric layer stacked along the second direction; the target semiconductor layer covers the plurality of first light-sensitive parts, and a top surface of the target semiconductor layer is higher than top surfaces of the plurality of first light-sensitive parts.

[0015] In some embodiments, after the plurality of isolation columns are formed, the method further includes: self-aligning the plurality of isolation columns to form a plurality of grids located directly above the plurality of isolation columns; and forming a filter between grids adjacent along the first direction.

[0016] In a second aspect, the present disclosure provides a back-illuminated image sensor prepared by the method for preparing a back-illuminated image sensor according to any one of the preceding embodiments, the back-illuminated image sensor including a substrate, a first stack, a plurality of first light-sensitive parts, a second stack, a plurality of second light-sensitive parts, a third stack, and a plurality of isolation columns; the substrate includes a plurality of trench isolation portions spaced apart along a first direction; the first stack is located on a back surface of the substrate; the plurality of first light-sensitive parts are spaced apart along the first direction and extend into the first stack along a second direction close to the substrate; the second stack covers the plurality of first light-sensitive parts; the plurality of second light-sensitive parts are spaced apart along the first direction, extend through the second stack along the second direction, and extend into the first light-sensitive parts; the third stack covers the plurality of second light-sensitive parts; and the plurality of isolation columns are spaced apart along the first direction, extend through the third stack, the second stack, the first stack along the second direction, and extend into the plurality of trench isolation portions.

[0017] In some embodiments, the first light-sensitive part circumferentially surrounds and covers a bottom portion of the second light-sensitive part; the third stack circumferentially surrounds and covers a top portion of the second light-sensitive part; and a top surface of the trench isolation portion is located within a bottom surface of the isolation column.

[0018] In some embodiments, the first stack, the second stack, and the third stack each include a target semiconductor layer; and the first light-sensitive part, the second light-sensitive part, and the target semiconductor layer each include a different fifth main group element.

[0019] In some embodiments, the first light-sensitive part includes a SiP layer; the second light-sensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

[0020] The method for preparing a back-illuminated image sensor and the back-illuminated image sensor according to the embodiments of the present disclosure have the following unexpected technical effects:

[0021] The target semiconductor layer of the first stack covers the bottom of the first light-sensitive part; after forming the second stack covering the plurality of first light-sensitive parts, a plurality of second light-sensitive parts are formed, which are distributed along the first direction at intervals, penetrate the second stack along the second direction, and extend into the first light-sensitive part, so that the target semiconductor layer of the second stack circumferentially surrounds the second light-sensitive part, and the top of the first light-sensitive part circumferentially surrounds and covers the bottom of the second light-sensitive part; after forming the third stack covering the plurality of second light-sensitive parts, a plurality of isolation columns are formed, which are distributed along the first direction at intervals, penetrate the third stack, the second stack, and the first stack along the second direction, and extend to the top surface of the plurality of trench isolation parts, so that the target semiconductor layer of the third stack covers and circumferentially surrounds the top of the second light-sensitive part, and the light-sensitive stacks including the first light-sensitive part, the second light-sensitive part, the first stack covering the first light-sensitive part, the second stack surrounding the second light-sensitive part, and the third stack covering the second light-sensitive part are isolated by the isolation columns along the first direction. The first light-sensitive part, the second light-sensitive part, and the target semiconductor layer in the light-sensitive stack each include a different fifth main group element. The light-sensitive stack doped with different fifth main group elements generates a concentration gradient in the interior thereof after being excited by light. The difference is used to optimize the transport path of photo-generated carriers, reduce the recombination rate in the diffusion process, and effectively improve the quantum efficiency of the light-sensitive stack based on the structure under the joint action of the two. In addition, the atomic mass of the fifth main group element is higher than that of silicon, and the mobility is low in epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing different doped fifth main group elements in multiple times can improve the uniformity of the doping concentration in the pixel area.

[0022] Further, the isolation columns and the trench isolation parts can jointly constitute target isolation parts, which can effectively avoid signal crosstalk between the light-sensitive stacks adjacent along the first direction; and in the process of preparing the isolation columns, a plurality of light-sensitive stacks distributed along the first direction at intervals are prepared at the same time, which effectively reduces the complexity and cost of the preparation process. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creating laborious work.

[0024] Figure 1 A flowchart of a back-illuminated image sensor preparation method provided in an embodiment;

[0025] Figure 2 A longitudinal cross-sectional structure schematic diagram of a semiconductor structure obtained after forming the first stack on the substrate in step S10 of the back-illuminated image sensor preparation method provided in an embodiment;

[0026] Figure 3 FIG. 10 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a first recess on a substrate in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0027] Figure 4 FIG. 11 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a first light-sensitive portion on a substrate in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0028] Figure 5 FIG. 12 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a second stack in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0029] Figure 6 FIG. 13 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a second recess in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0030] Figure 7 FIG. 14 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a second light-sensitive portion in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0031] Figure 8 FIG. 15 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a third stack in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0032] Figure 9 FIG. 16 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming an isolation column in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0033] Figure 10 FIG. 17 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a grid in a method of manufacturing a back-illuminated image sensor according to an embodiment;

[0034] Figure 11 FIG. 18 is a schematic view of a longitudinal cross-sectional structure of a semiconductor structure after forming a filter in a method of manufacturing a back-illuminated image sensor according to an embodiment.

[0035] BRIEF DESCRIPTION OF THE DRAWINGS

[0036] 10, substrate; 10a, back surface; 101, trench isolation; 102, etching stop layer; 103, interlayer dielectric layer; 21, first target semiconductor layer; 22, first dielectric layer; 20, first stack; 31, first recess; 32, first sacrificial layer; 30, first photosensitive part; 41, second target semiconductor layer; 42, second dielectric layer; 40, second stack; 51, second recess; 52, second sacrificial layer; 50, second photosensitive part; 61, third target semiconductor layer; 62, third dielectric layer; 60, third stack; 70, spacer; 80, grating; 81, first grating material layer; 82, second grating material layer; 83, third grating material layer; 90, optical filter. DETAILED DESCRIPTION

[0037] For the purpose of promoting an understanding of the disclosure, the disclosure will now be described more fully with reference to the associated drawings. The preferred embodiments of the disclosure are shown in the drawings. However, the disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0039] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0040] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections but are not intended to limit the scope of the present disclosure. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0041] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

[0043] In embodiments of the present disclosure, a direction parallel to the substrate surface, for example, is a first direction, and a direction away from the substrate surface (a thickness direction of the substrate) is a second direction, for example, in the case of neglecting the substrate surface flatness. In embodiments of the present disclosure, the first direction can be an ox direction, and the second direction can be an oz direction.

[0044] Reference is made to Figure 1 In some embodiments, a back-illuminated image sensor manufacturing method is provided, comprising:

[0045] Step S10: providing a substrate, the substrate comprising a plurality of trench isolation portions spaced apart along a first direction, forming a first stack on a back surface of the substrate, and then forming a plurality of first photosensitive portions spaced apart along the first direction and extending along a second direction close to the substrate into the first stack;

[0046] Step S20: forming a second stack covering the plurality of first photosensitive portions, and then forming a plurality of second photosensitive portions spaced apart along the first direction and extending along the second direction through the second stack and into the first photosensitive portions;

[0047] Step S30: forming a third stack covering the plurality of second photosensitive portions, and then forming a plurality of isolation columns spaced apart along the first direction and extending along the second direction through the third stack, the second stack, the first stack, and into the plurality of trench isolation portions; the first stack, the second stack, and the third stack each comprising a target semiconductor layer; the first photosensitive portions, the second photosensitive portions, and the target semiconductor layer each comprising a different fifth main group element.

[0048] By way of example, reference continues to Figure 1The plurality of groove isolation portions are formed in the substrate and are spaced apart along a first direction, which can be parallel to the back surface of the substrate. After forming the first stack including the target semiconductor layer on the back surface of the substrate, a plurality of first photosensitive portions are formed, which are spaced apart along the first direction and extend into the first stack along a second direction close to the substrate, so that the target semiconductor layer of the first stack covers the bottom of the first photosensitive portion. After forming a second stack covering the plurality of first photosensitive portions, a plurality of second photosensitive portions are formed, which are spaced apart along the first direction and extend through the second stack along the second direction and into the first photosensitive portion, so that the target semiconductor layer of the second stack circumferentially surrounds the second photosensitive portion, and the top of the first photosensitive portion circumferentially surrounds and covers the bottom of the second photosensitive portion. After forming a third stack covering the plurality of second photosensitive portions, a plurality of isolation columns are formed, which are spaced apart along the first direction and extend through the third stack, the second stack, the first stack, and the plurality of groove isolation portions along the second direction, so that the target semiconductor layer of the third stack covers and circumferentially surrounds the top of the second photosensitive portion, and the photosensitive stacks including the first photosensitive portion, the second photosensitive portion, the first stack covering the first photosensitive portion, the second stack circumferentially surrounding the second photosensitive portion, and the third stack covering the second photosensitive portion are isolated by the isolation columns along the first direction. The first photosensitive portion, the second photosensitive portion, and the target semiconductor layer in the photosensitive stack each include a different fifth main group element. The photosensitive stack doped with different fifth main group elements generates a concentration gradient in the interior thereof after being excited by light. The difference optimizes the transport path of the photo-generated carriers, reduces the recombination rate in the diffusion process, and effectively improves the quantum efficiency of the photosensitive stack based on the structure. In addition, the atomic mass of the fifth main group element is higher than that of silicon, and the mobility is low in epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing different doped fifth main group elements in multiple times can improve the uniformity of the doping concentration in the pixel area.

[0049] Further, the isolation columns and the groove isolation portions can jointly constitute target isolation portions, which can effectively avoid signal crosstalk between the photosensitive stacks adjacent along the first direction. In addition, in the process of preparing the isolation columns, the plurality of photosensitive stacks spaced apart along the first direction are prepared at the same time, which effectively reduces the complexity and cost of the preparation process.

[0050] For reference Figure 2 In some embodiments, the substrate 10 includes a plurality of groove isolation portions 101 spaced apart along a first direction, for example, the ox direction. The material of the groove isolation portion 101 can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or the like or a combination thereof.

[0051] For example, please continue to refer to Figure 2The trench isolation part 101 can be used to isolate electrons and light energy. The shape of the longitudinal section (the section parallel to the zox plane) of the trench isolation part 101 can include a right trapezoid, an inverted trapezoid, a rectangle, etc., or can also be a combination of a right trapezoid, an inverted trapezoid, a rectangle, etc. The present disclosure does not make specific limitations on the shape, material, and size of the trench isolation part 101, and can isolate electrons, light energy, doping ions, etc. In addition, the present embodiment also does not make specific limitations on the spacing between adjacent trench isolation parts 101, and can be set according to actual needs.

[0052] By way of example, please continue to refer to Figure 2 The substrate 10 can be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0053] By way of example, please continue to refer to Figure 2 The P-type ions, for example, boron ions, can be implanted into the substrate 10 by ion implantation to form a P-type substrate.

[0054] Please continue to refer to Figure 2 In some embodiments, the front surface of the trench isolation part 101 is covered with an etching stop layer 102, and the side of the etching stop layer 102 away from the trench isolation part 101 includes an interlayer dielectric layer 103.

[0055] By way of example, please continue to refer to Figure 2 After the etching stop layer 102 is formed, metal is deposited to form a partial connection structure, and the interlayer dielectric layer 103 is formed thereon. When the etching stop layer 102 is multi-layered, other process problems caused by cracks in a single layer can be avoided, and / or the metal connection structure can be ineffective. The interlayer dielectric layer 103 can be a silicon oxide layer or other dielectric material layer. In addition, a metal interconnection structure can be formed on the interlayer dielectric layer 103 as a metal connection part of the device.

[0056] Of course, the present embodiment only represents one way, as long as the metal interconnection structure can be reasonably formed, and the thickness of the etching stop layer 102 and the interlayer dielectric layer 103 is not limited, and can be adjusted according to specific process requirements.

[0057] Please continue to refer to Figure 2 In some embodiments, after forming the shallow trench isolation (STI) in the substrate 10, and filling the dielectric material in the STI, the trench isolation portion 101 can be formed. Then, the substrate 10 can be flipped, and the back surface of the substrate 10 can be thinned and planarized to expose the back surface of the trench isolation portion 101. In order to form the PN junction between the P-type substrate and the N-type photosensitive layer.

[0058] For example, please continue to refer to Figure 2 The first target semiconductor layer 21 can be epitaxially grown on the back surface 10a of the substrate 10. The thickness of the first target semiconductor layer 21 can be 50-60 nm. For example, the thickness of the first target semiconductor layer 21 can be 50 nm, 55 nm, or 60 nm, etc. The first target semiconductor layer 21 can include a SiAs layer, which is used to represent a silicon material doped with arsenic (As).

[0059] For example, please continue to refer to Figure 2 After forming the first target semiconductor layer 21 on the back surface 10a of the substrate 10 by using the selective epitaxial growth process, a first dielectric layer 22 can be formed on the top surface of the first target semiconductor layer 21. The first target semiconductor layer 21 and the first dielectric layer 22 can be used to jointly constitute a first layer stack 20. The first dielectric layer 22 can be used to protect the first target semiconductor layer 21 from being damaged in subsequent etching or grinding processes.

[0060] For example, please continue to refer to Figure 3 The thickness of the first dielectric layer 22 can be 1-2 nm. For example, the thickness of the first dielectric layer 22 can be 1 nm, 1.5 nm, or 2 nm, etc. The material of the first dielectric layer 22 can include silicon oxide.

[0061] Please refer to Figure 4 In some embodiments, after forming the first patterned photoresist layer (not shown) on the top surface of the first layer stack 20, the first patterned photoresist layer can include an opening pattern for defining the shape, position, and size of the first recess 31. Based on the first patterned photoresist layer, the first layer stack 20 can be etched to form a plurality of first recesses 31 spaced apart along a first direction in the first layer stack 20. The first layer stack 20 between the first recesses 31 adjacent along the first direction can be used to constitute a first sacrificial layer 32.

[0062] Please refer to Figure 5 In some embodiments, the first photosensitive portion 30 can be formed in the first recess 31 by using the selective epitaxial growth process. The first photosensitive portion 30 can fill the first recess 31, and the top surface of the first photosensitive portion 30 can be higher than the top surface of the first dielectric layer 22. The first photosensitive portion 30 can include a SiP layer, which is used to represent a silicon material doped with phosphorus (P).

[0063] Referring to Figure 5 In some embodiments, a selective epitaxial growth process can be employed to form a second target semiconductor layer 41 covering the first photosensitive portion 30 and the first sacrificial layer 32, the top surface of the second target semiconductor layer 41 being higher than the top surface of the first photosensitive portion 30. The material of the second target semiconductor layer 41 can be the same as that of the first target semiconductor layer 21.

[0064] For example, still referring to Figure 5 The second target semiconductor layer 41 can include a SiAs layer, which is used to represent a silicon material doped with arsenic (As).

[0065] For example, still referring to Figure 5 A second dielectric layer 42 is formed on the top surface of the second target semiconductor layer 41, the thickness of the second dielectric layer 42 being less than that of the second target semiconductor layer 41. The second target semiconductor layer 41 and the second dielectric layer 42 are used to jointly constitute a second stack 40. The second dielectric layer 42 is used to protect the second target semiconductor layer 41 from being damaged in subsequent etching or grinding processes.

[0066] For example, still referring to Figure 6 The material of the second dielectric layer 42 can include silicon oxide.

[0067] Referring to Figure 7 In some embodiments, after a second patterned photoresist layer (not shown) is formed on the top surface of the second stack 40, the second patterned photoresist layer includes an opening pattern for defining the shape, position and size of the second recess 51, the second stack 40 is etched based on the second patterned photoresist layer, and a plurality of second recesses 51 are formed in the second stack 40 and spaced apart along the first direction. The second stack 40 between the second recesses 51 adjacent along the first direction is used to constitute a second sacrificial layer 52.

[0068] Referring to Figure 8 In some embodiments, a selective epitaxial growth process can be employed to form a second photosensitive portion 50 in the second recess 51, the second photosensitive portion 50 filling the second recess 51, and the top surface of the second photosensitive portion 50 being higher than the top surface of the second dielectric layer 42. The second photosensitive portion 50 can include a SiSb layer, which is used to represent a silicon material doped with antimony (Sb).

[0069] Referring to Figure 8 In some embodiments, a selective epitaxial growth process can be employed to form a third target semiconductor layer 61 covering the second photosensitive portion 50 and the second sacrificial layer 52, the top surface of the third target semiconductor layer 61 being higher than the top surface of the second photosensitive portion 50. The material of the third target semiconductor layer 61 can be the same as that of the second target semiconductor layer 41.

[0070] By way of example, please continue to refer to Figure 8 The third target semiconductor layer 61 can include a SiAs layer, which is used to characterize a silicon material doped with arsenic (As).

[0071] By way of example, please continue to refer to Figure 8 A third dielectric layer 62 is formed on the top surface of the third target semiconductor layer 61, and the thickness of the third dielectric layer 62 is less than the thickness of the third target semiconductor layer 61. The third target semiconductor layer 61 and the third dielectric layer 62 are used to jointly constitute a third stack 60.

[0072] By way of example, please continue to refer to Figure 8 The material of the third dielectric layer 62 can include silicon oxide. In the subsequent etching process of removing the second sacrificial layer 52 and the first sacrificial layer 32, the third dielectric layer 62 can protect the third target semiconductor layer 61 from being damaged by etching.

[0073] Please continue to refer to Figure 9 In some embodiments, the first light-sensitive part 30 includes a SiP layer; the second light-sensitive part 50 includes a SiSb layer; and the target semiconductor layer includes a SiAs layer. The light-sensitive stack doped with different pentavalent elements can also generate a concentration gradient inside after being excited by light. By utilizing this difference, the transmission path of the photo-generated carriers is optimized, and the recombination rate in the diffusion process is reduced. Under the joint action of the above two, the quantum efficiency of the light-sensitive stack based on this structure is effectively improved.

[0074] By way of example, the N-type light-sensitive stack can form a PN junction of a photodiode with a P-type substrate. Please refer to Figure 9 In some embodiments, after the third dielectric layer 62 is formed, a third patterned photoresist layer (not shown) can be formed on the top surface of the third dielectric layer 62, and the third patterned photoresist layer includes an opening pattern for defining the shape, position and size of the isolation column 70. Based on the third patterned photoresist layer, the third stack 60 is etched, and the second sacrificial layer 52 and the first sacrificial layer 32 are removed, thereby obtaining a plurality of isolation grooves (not shown) spaced apart along the first direction. The isolation grooves expose the top surface of the trench isolation part 101.

[0075] Please continue to refer to Figure 10 In some embodiments, a deposition process can be used to fill the isolation material in the plurality of isolation grooves, and then the top surface of the isolation material is planarized to obtain the isolation column 70, whose top surface is flush with the top surface of the third dielectric layer 62.

[0076] Please refer to Figure 10- Figure 11In some embodiments, after forming the isolation column 70, a grid material stack (not shown) covering the top surface of the isolation column 70 and the top surface of the third dielectric layer 62 can be formed, which includes a first grid material layer 81, a second grid material layer 82, and a third grid material layer 83 stacked in sequence along a second direction away from the substrate. The material of the first grid material layer 81 can include HfO2. The material of the second grid material layer 82 can include TiN. The material of the third grid material layer 83 can include Al.

[0077] Please continue to refer to Figure 10- Figure 11 In some embodiments, after forming the grid material stack, a fourth patterned photoresist layer (not shown) can be formed on the top surface of the grid material stack, which includes an opening pattern for defining the shape, position, and size of the optical filter 90. The grid 80 can be formed by etching the grid material stack based on the fourth patterned photoresist layer directly above the isolation column 70.

[0078] Please continue to refer to Figure 11 In some embodiments, after forming the grid 80, further comprising:

[0079] The optical filter 90 is formed between the grids 80 adjacent to each other along the first direction, for example, the ox direction.

[0080] For example, please continue to refer to Figure 11 The optical filter 90 includes, but is not limited to, a red optical filter, a yellow optical filter, a blue optical filter, etc., and the three kinds of optical filters are arranged adjacent to each other as a pixel group. Among them, the red optical filter transmits red light waves, the yellow optical filter transmits yellow light waves, and the blue optical filter transmits blue light waves.

[0081] Please continue to refer to Figure 11 In some embodiments, a back-illuminated image sensor is provided, which is prepared by the back-illuminated image sensor preparation method in any of the preceding embodiments. The back-illuminated image sensor includes a substrate 10, a first stack 20, a plurality of first light-sensitive parts 30, a second stack 40, a plurality of second light-sensitive parts 50, a third stack 60, and a plurality of isolation columns 70. The substrate 10 includes a plurality of trench isolation parts 101 spaced apart along a first direction. The first stack 20 is located on the back surface 10a of the substrate 10. The plurality of first light-sensitive parts 30 are spaced apart along the first direction and extend into the first stack 20 along a second direction close to the substrate 10. The second stack 40 covers the plurality of first light-sensitive parts 30. The plurality of second light-sensitive parts 50 are spaced apart along the first direction and extend into the first light-sensitive part 30 along the second direction and penetrate the second stack 40. The third stack 60 covers the plurality of second light-sensitive parts 50. The plurality of isolation columns 70 are spaced apart along the first direction and extend to the top surface of the plurality of trench isolation parts 101 along the second direction and penetrate the third stack 60, the second stack 40, and the first stack 20.

[0082] Please continue to refer to Figure 11 In some embodiments, the first light-sensitive part 30 circumferentially surrounds and covers the bottom of the second light-sensitive part 50; the third stack 60 circumferentially surrounds and covers the top of the second light-sensitive part 50; the top surface of the trench isolation part 101 is located within the bottom surface of the isolation column 70.

[0083] Please continue to refer to Figure 11 In some embodiments, the first stack 20, the second stack 40 and the third stack 60 all include target semiconductor layers; the first light-sensitive part 30, the second light-sensitive part 50 and the target semiconductor layers respectively include different fifth main group elements. The fifth main group elements include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi).

[0084] Please continue to refer to Figure 11 In some embodiments, the target semiconductor layers include a first target semiconductor layer 21, a second target semiconductor layer 41 and a third target semiconductor layer 61. The first stack 20 includes the first target semiconductor layer 21 and the first dielectric layer 22 stacked in a second direction away from the substrate; the second stack 40 includes the second target semiconductor layer 41 and the second dielectric layer 42 stacked in the second direction away from the substrate; the third stack 60 includes the third target semiconductor layer 61 and the third dielectric layer 62 stacked in the second direction away from the substrate. The first target semiconductor layer 21, the second target semiconductor layer 41 and the third target semiconductor layer 61 all include SiAs layers, and the SiAs layers are used to characterize silicon materials doped with arsenic (As).

[0085] Please continue to refer to Figure 1- Figure 11 In some embodiments, the first light-sensitive part 30 includes a SiP layer; the second light-sensitive part 50 includes a SiSb layer; and the target semiconductor layers include SiAs layers.

[0086] Please continue to refer to Figure 1 The back-illuminated image sensor preparation method and the back-illuminated image sensor in the embodiments of the present disclosure include the following unexpected technical effects:

[0087] The target semiconductor layer of the first stack 20 covers the bottom of the first light-sensitive part 30; after forming the second stack 40 covering the plurality of first light-sensitive parts 30, a plurality of second light-sensitive parts 50 are formed, which are distributed along the first direction, penetrate the second stack 40 along the second direction, and extend into the first light-sensitive part 30, so that the target semiconductor layer of the second stack 40 circumferentially surrounds the second light-sensitive part 50, and the top of the first light-sensitive part 30 circumferentially surrounds and covers the bottom of the second light-sensitive part 50; after forming the third stack 60 covering the plurality of second light-sensitive parts 50, a plurality of isolation columns 70 are formed, which are distributed along the first direction, penetrate the third stack 60, the second stack 40, and the first stack 20 along the second direction, and extend to the top surface of the plurality of trench isolation parts 101, so that the target semiconductor layer of the third stack 60 covers and circumferentially surrounds the top of the second light-sensitive part 50, and the light-sensitive stacks including the first light-sensitive part 30, the second light-sensitive part 50, the first stack 20 covering the first light-sensitive part 30, the second stack 40 surrounding the second light-sensitive part 50, and the third stack 60 covering the second light-sensitive part 50 are isolated by the isolation column 70 along the first direction. The first light-sensitive part 30, the second light-sensitive part 50, and the target semiconductor layer in the light-sensitive stack respectively include different fifth main group elements. The light-sensitive stack doped with different fifth main group elements generates a concentration gradient in the interior thereof after being excited by light. The difference is used to optimize the transport path of the photo-generated carriers, reduce the recombination rate in the diffusion process, and effectively improve the quantum efficiency of the light-sensitive stack based on the structure. In addition, the atomic mass of the fifth main group element is higher than that of silicon, and the mobility is low in epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing different doped fifth main group elements in multiple times can improve the uniformity of the doping concentration in the pixel area.

[0088] Further, the isolation column 70 and the trench isolation part 101 can jointly constitute a target isolation part, which can effectively avoid signal crosstalk between the light-sensitive stacks adjacent along the first direction; and in the process of preparing the isolation column 70, a plurality of light-sensitive stacks distributed along the first direction are prepared at the same time, which effectively reduces the complexity and cost of the preparation process.

[0089] It should be understood that, although Figure 1 the steps in the flowchart diagram are shown in the order indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, ​ at least part of the steps in the flowchart diagram can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0090] The technical features of the above-mentioned embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features of the above-mentioned embodiments are described, however, as long as the combination of the technical features does not result in a contradiction, it should be considered as falling within the scope of the present disclosure.

[0091] The above-mentioned embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, include: A substrate is provided, the substrate including a plurality of trench isolation portions spaced apart along a first direction; After forming a first stack on the back side of the substrate, the first stack includes a first target semiconductor layer and a first dielectric layer stacked along a second direction away from the substrate; a plurality of first photosensitive portions are formed that are spaced apart along the first direction, penetrate the first dielectric layer along a second direction close to the substrate, and extend into the first target semiconductor layer; the bottom surface of the columnar plurality of first photosensitive portions is higher than the bottom surface of the first target semiconductor layer, and the top surface is higher than the top surface of the first dielectric layer; After forming a second stack covering the plurality of first photosensitive portions, the second stack includes a second target semiconductor layer and a second dielectric layer stacked along a second direction away from the substrate; a plurality of second photosensitive portions are formed that are spaced apart along the first direction, penetrate the second stack along the second direction, and extend into the first photosensitive portions; the top surface of the columnar plurality of second photosensitive portions is higher than the top surface of the second dielectric layer; After forming a third stack covering the plurality of second photosensitive portions, the third stack includes a third target semiconductor layer and a third dielectric layer stacked along a second direction away from the substrate; and a plurality of isolation pillars are formed that are spaced apart along the first direction, penetrate the third stack, the second stack, and the first stack along the second direction, and extend to the plurality of trench isolation portions. The target semiconductor layer includes a first target semiconductor layer, a second target semiconductor layer, and a third target semiconductor layer; the first photosensitive part, the second photosensitive part, and the target semiconductor layer each include different Group 5 elements; The third target semiconductor layer circumferentially surrounds and covers the top of the second photosensitive part.

2. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The first photosensitive part surrounds and covers the bottom of the second photosensitive part in a circumferential direction.

3. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The top surface of the trench isolation section is located inside the bottom surface of the isolation column.

4. The method for fabricating a back-illuminated image sensor according to any one of claims 1-3, characterized in that, The first photosensitive part includes a SiP layer; the second photosensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

5. The method for fabricating a back-illuminated image sensor according to any one of claims 1-3, characterized in that, Includes at least one of the following features: The material of the first dielectric layer includes silicon oxide; The material of the second dielectric layer includes silicon oxide; The material of the third dielectric layer includes silicon oxide.

6. The method for fabricating a back-illuminated image sensor according to any one of claims 1-3, characterized in that, After forming the plurality of isolation pillars, the method further includes: Self-aligning with the plurality of isolation posts to form a plurality of grids located directly above the plurality of isolation posts; A filter is formed between adjacent grids along the first direction.

7. A back-illuminated image sensor, characterized in that, The back-illuminated image sensor is fabricated using the method described in any one of claims 1-6, wherein the back-illuminated image sensor comprises: A substrate, wherein the substrate includes a plurality of trench isolation portions spaced apart along a first direction; A first stack is located on the back side of the substrate; the first stack includes a first target semiconductor layer and a first dielectric layer stacked along a second direction away from the substrate; A plurality of first photosensitive portions are spaced apart along the first direction, penetrate the first dielectric layer along a second direction close to the substrate, and extend into the first target semiconductor layer; the bottom surface of the columnar plurality of first photosensitive portions is higher than the bottom surface of the first target semiconductor layer, and the top surface is higher than the top surface of the first dielectric layer; A second stacked layer covers the plurality of first photosensitive portions; the second stacked layer includes a second target semiconductor layer and a second dielectric layer stacked along a second direction away from the substrate; A plurality of second photosensitive portions are spaced apart along the first direction, penetrate the second stack along the second direction, and extend into the first photosensitive portion; the top surface of the columnar plurality of second photosensitive portions is higher than the top surface of the second dielectric layer; A third stacked layer covers the plurality of second photosensitive portions; the third stacked layer includes a third target semiconductor layer and a third dielectric layer stacked along a second direction away from the substrate; the third target semiconductor layer circumferentially surrounds and covers the top of the second photosensitive portions; Multiple isolation pillars are spaced apart along the first direction, penetrate the third stack, the second stack, and the first stack along the second direction, and extend to the multiple trench isolation portions; the target semiconductor layer includes the first target semiconductor layer, the second target semiconductor layer, and the third target semiconductor layer; the first photosensitive portion, the second photosensitive portion, and the target semiconductor layer each include different Group 5 elements.

8. The back-illuminated image sensor according to claim 7, characterized in that, The first photosensitive part circumferentially surrounds and covers the bottom of the second photosensitive part; The top surface of the trench isolation section is located inside the bottom surface of the isolation column.

9. The back-illuminated image sensor according to claim 7 or 8, characterized in that, Includes at least one of the following features: The material of the first dielectric layer includes silicon oxide; The material of the second dielectric layer includes silicon oxide; The material of the third dielectric layer includes silicon oxide.

10. The back-illuminated image sensor according to claim 9, characterized in that, The first photosensitive part includes a SiP layer; the second photosensitive part includes a SiSb layer; and the target semiconductor layer includes a SiAs layer.

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